1 /*-
2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 #include "opt_rss.h"
29 #include "opt_ratelimit.h"
30
31 #include <linux/interrupt.h>
32 #include <linux/module.h>
33 #include <dev/mlx5/port.h>
34 #include <dev/mlx5/mlx5_ifc.h>
35 #include <dev/mlx5/mlx5_fpga/core.h>
36 #include <dev/mlx5/mlx5_core/mlx5_core.h>
37 #include <dev/mlx5/mlx5_core/eswitch.h>
38
39 #ifdef RSS
40 #include <net/rss_config.h>
41 #include <netinet/in_rss.h>
42 #endif
43
44 enum {
45 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
46 MLX5_EQE_OWNER_INIT_VAL = 0x1,
47 };
48
49 enum {
50 MLX5_NUM_SPARE_EQE = 0x80,
51 MLX5_NUM_ASYNC_EQE = 0x100,
52 MLX5_NUM_CMD_EQE = 32,
53 };
54
55 enum {
56 MLX5_EQ_DOORBEL_OFFSET = 0x40,
57 };
58
59 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
60 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
61 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
62 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
63 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
64 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
65 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
66 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
67 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
68 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
69 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
70 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT) | \
71 (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE))
72
73 struct map_eq_in {
74 u64 mask;
75 u32 reserved;
76 u32 unmap_eqn;
77 };
78
79 struct cre_des_eq {
80 u8 reserved[15];
81 u8 eqn;
82 };
83
84 /*Function prototype*/
85 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
86 struct mlx5_eqe *eqe);
87 static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev,
88 struct mlx5_eqe *eqe);
89
mlx5_cmd_destroy_eq(struct mlx5_core_dev * dev,u8 eqn)90 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
91 {
92 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0};
93 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
94
95 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
96 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
97
98 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
99 }
100
get_eqe(struct mlx5_eq * eq,u32 entry)101 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
102 {
103 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
104 }
105
next_eqe_sw(struct mlx5_eq * eq)106 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
107 {
108 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
109
110 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
111 }
112
eqe_type_str(u8 type)113 static const char *eqe_type_str(u8 type)
114 {
115 switch (type) {
116 case MLX5_EVENT_TYPE_COMP:
117 return "MLX5_EVENT_TYPE_COMP";
118 case MLX5_EVENT_TYPE_PATH_MIG:
119 return "MLX5_EVENT_TYPE_PATH_MIG";
120 case MLX5_EVENT_TYPE_COMM_EST:
121 return "MLX5_EVENT_TYPE_COMM_EST";
122 case MLX5_EVENT_TYPE_SQ_DRAINED:
123 return "MLX5_EVENT_TYPE_SQ_DRAINED";
124 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
125 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
126 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
127 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
128 case MLX5_EVENT_TYPE_CQ_ERROR:
129 return "MLX5_EVENT_TYPE_CQ_ERROR";
130 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
131 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
132 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
133 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
134 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
135 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
136 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
137 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
138 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
139 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
140 case MLX5_EVENT_TYPE_INTERNAL_ERROR:
141 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
142 case MLX5_EVENT_TYPE_PORT_CHANGE:
143 return "MLX5_EVENT_TYPE_PORT_CHANGE";
144 case MLX5_EVENT_TYPE_GPIO_EVENT:
145 return "MLX5_EVENT_TYPE_GPIO_EVENT";
146 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
147 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
148 case MLX5_EVENT_TYPE_TEMP_WARN_EVENT:
149 return "MLX5_EVENT_TYPE_TEMP_WARN_EVENT";
150 case MLX5_EVENT_TYPE_REMOTE_CONFIG:
151 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
152 case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
153 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
154 case MLX5_EVENT_TYPE_STALL_EVENT:
155 return "MLX5_EVENT_TYPE_STALL_EVENT";
156 case MLX5_EVENT_TYPE_CMD:
157 return "MLX5_EVENT_TYPE_CMD";
158 case MLX5_EVENT_TYPE_PAGE_REQUEST:
159 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
160 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
161 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
162 case MLX5_EVENT_TYPE_FPGA_ERROR:
163 return "MLX5_EVENT_TYPE_FPGA_ERROR";
164 case MLX5_EVENT_TYPE_FPGA_QP_ERROR:
165 return "MLX5_EVENT_TYPE_FPGA_QP_ERROR";
166 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT:
167 return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT";
168 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT:
169 return "MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT";
170 default:
171 return "Unrecognized event";
172 }
173 }
174
port_subtype_event(u8 subtype)175 static enum mlx5_dev_event port_subtype_event(u8 subtype)
176 {
177 switch (subtype) {
178 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
179 return MLX5_DEV_EVENT_PORT_DOWN;
180 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
181 return MLX5_DEV_EVENT_PORT_UP;
182 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
183 return MLX5_DEV_EVENT_PORT_INITIALIZED;
184 case MLX5_PORT_CHANGE_SUBTYPE_LID:
185 return MLX5_DEV_EVENT_LID_CHANGE;
186 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
187 return MLX5_DEV_EVENT_PKEY_CHANGE;
188 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
189 return MLX5_DEV_EVENT_GUID_CHANGE;
190 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
191 return MLX5_DEV_EVENT_CLIENT_REREG;
192 }
193 return -1;
194 }
195
dcbx_subevent(u8 subtype)196 static enum mlx5_dev_event dcbx_subevent(u8 subtype)
197 {
198 switch (subtype) {
199 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX:
200 return MLX5_DEV_EVENT_ERROR_STATE_DCBX;
201 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE:
202 return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE;
203 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE:
204 return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE;
205 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE:
206 return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE;
207 }
208 return -1;
209 }
210
eq_update_ci(struct mlx5_eq * eq,int arm)211 static void eq_update_ci(struct mlx5_eq *eq, int arm)
212 {
213 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
214 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
215 __raw_writel((__force u32) cpu_to_be32(val), addr);
216 /* We still want ordering, just not swabbing, so add a barrier */
217 mb();
218 }
219
220 static void
mlx5_temp_warning_event(struct mlx5_core_dev * dev,struct mlx5_eqe * eqe)221 mlx5_temp_warning_event(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe)
222 {
223
224 mlx5_core_warn(dev,
225 "High temperature on sensors with bit set %#jx %#jx\n",
226 (uintmax_t)be64_to_cpu(eqe->data.temp_warning.sensor_warning_msb),
227 (uintmax_t)be64_to_cpu(eqe->data.temp_warning.sensor_warning_lsb));
228 }
229
mlx5_eq_int(struct mlx5_core_dev * dev,struct mlx5_eq * eq)230 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
231 {
232 struct mlx5_eqe *eqe;
233 int eqes_found = 0;
234 int set_ci = 0;
235 u32 cqn;
236 u32 rsn;
237 u8 port;
238
239 while ((eqe = next_eqe_sw(eq))) {
240 /*
241 * Make sure we read EQ entry contents after we've
242 * checked the ownership bit.
243 */
244 atomic_thread_fence_acq();
245
246 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
247 eq->eqn, eqe_type_str(eqe->type));
248 switch (eqe->type) {
249 case MLX5_EVENT_TYPE_COMP:
250 mlx5_cq_completion(dev, eqe);
251 break;
252
253 case MLX5_EVENT_TYPE_PATH_MIG:
254 case MLX5_EVENT_TYPE_COMM_EST:
255 case MLX5_EVENT_TYPE_SQ_DRAINED:
256 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
257 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
258 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
259 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
260 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
261 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
262 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
263 eqe_type_str(eqe->type), eqe->type, rsn);
264 mlx5_rsc_event(dev, rsn, eqe->type);
265 break;
266
267 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
268 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
269 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
270 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
271 eqe_type_str(eqe->type), eqe->type, rsn);
272 mlx5_srq_event(dev, rsn, eqe->type);
273 break;
274
275 case MLX5_EVENT_TYPE_CMD:
276 if (dev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
277 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector),
278 MLX5_CMD_MODE_EVENTS);
279 }
280 break;
281
282 case MLX5_EVENT_TYPE_PORT_CHANGE:
283 port = (eqe->data.port.port >> 4) & 0xf;
284 switch (eqe->sub_type) {
285 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
286 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
287 case MLX5_PORT_CHANGE_SUBTYPE_LID:
288 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
289 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
290 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
291 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
292 if (dev->event)
293 dev->event(dev, port_subtype_event(eqe->sub_type),
294 (unsigned long)port);
295 break;
296 default:
297 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
298 port, eqe->sub_type);
299 }
300 break;
301
302 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT:
303 port = (eqe->data.port.port >> 4) & 0xf;
304 switch (eqe->sub_type) {
305 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX:
306 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE:
307 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE:
308 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE:
309 if (dev->event)
310 dev->event(dev,
311 dcbx_subevent(eqe->sub_type),
312 0);
313 break;
314 default:
315 mlx5_core_warn(dev,
316 "dcbx event with unrecognized subtype: port %d, sub_type %d\n",
317 port, eqe->sub_type);
318 }
319 break;
320
321 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT:
322 mlx5_port_general_notification_event(dev, eqe);
323 break;
324
325 case MLX5_EVENT_TYPE_CQ_ERROR:
326 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
327 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
328 cqn, eqe->data.cq_err.syndrome);
329 mlx5_cq_event(dev, cqn, eqe->type);
330 break;
331
332 case MLX5_EVENT_TYPE_PAGE_REQUEST:
333 {
334 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
335 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
336
337 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
338 func_id, npages);
339 mlx5_core_req_pages_handler(dev, func_id, npages);
340 }
341 break;
342
343 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
344 mlx5_port_module_event(dev, eqe);
345 break;
346
347 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
348 {
349 struct mlx5_eqe_vport_change *vc_eqe =
350 &eqe->data.vport_change;
351 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
352
353 if (dev->event)
354 dev->event(dev,
355 MLX5_DEV_EVENT_VPORT_CHANGE,
356 (unsigned long)vport_num);
357 }
358 if (dev->priv.eswitch != NULL)
359 mlx5_eswitch_vport_event(dev->priv.eswitch,
360 eqe);
361 break;
362
363 case MLX5_EVENT_TYPE_FPGA_ERROR:
364 case MLX5_EVENT_TYPE_FPGA_QP_ERROR:
365 mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);
366 break;
367 case MLX5_EVENT_TYPE_TEMP_WARN_EVENT:
368 mlx5_temp_warning_event(dev, eqe);
369 break;
370
371 default:
372 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
373 eqe->type, eq->eqn);
374 break;
375 }
376
377 ++eq->cons_index;
378 eqes_found = 1;
379 ++set_ci;
380
381 /* The HCA will think the queue has overflowed if we
382 * don't tell it we've been processing events. We
383 * create our EQs with MLX5_NUM_SPARE_EQE extra
384 * entries, so we must update our consumer index at
385 * least that often.
386 */
387 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
388 eq_update_ci(eq, 0);
389 set_ci = 0;
390 }
391 }
392
393 eq_update_ci(eq, 1);
394
395 return eqes_found;
396 }
397
mlx5_msix_handler(int irq,void * eq_ptr)398 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
399 {
400 struct mlx5_eq *eq = eq_ptr;
401 struct mlx5_core_dev *dev = eq->dev;
402
403 /* check if IRQs are not disabled */
404 if (likely(dev->priv.disable_irqs == 0))
405 mlx5_eq_int(dev, eq);
406
407 /* MSI-X vectors always belong to us */
408 return IRQ_HANDLED;
409 }
410
init_eq_buf(struct mlx5_eq * eq)411 static void init_eq_buf(struct mlx5_eq *eq)
412 {
413 struct mlx5_eqe *eqe;
414 int i;
415
416 for (i = 0; i < eq->nent; i++) {
417 eqe = get_eqe(eq, i);
418 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
419 }
420 }
421
mlx5_create_map_eq(struct mlx5_core_dev * dev,struct mlx5_eq * eq,u8 vecidx,int nent,u64 mask)422 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
423 int nent, u64 mask)
424 {
425 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
426 struct mlx5_priv *priv = &dev->priv;
427 __be64 *pas;
428 void *eqc;
429 int inlen;
430 u32 *in;
431 int err;
432
433 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
434 eq->cons_index = 0;
435 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE,
436 &eq->buf);
437 if (err)
438 return err;
439
440 init_eq_buf(eq);
441
442 inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
443 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
444 in = mlx5_vzalloc(inlen);
445 if (!in) {
446 err = -ENOMEM;
447 goto err_buf;
448 }
449
450 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
451 mlx5_fill_page_array(&eq->buf, pas);
452
453 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
454 MLX5_SET64(create_eq_in, in, event_bitmask, mask);
455
456 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
457 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
458 MLX5_SET(eqc, eqc, uar_page, priv->uar->index);
459 MLX5_SET(eqc, eqc, intr, vecidx);
460 MLX5_SET(eqc, eqc, log_page_size,
461 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
462
463 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
464 if (err)
465 goto err_in;
466
467 eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
468 eq->irqn = vecidx;
469 eq->dev = dev;
470 eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
471 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0,
472 "mlx5_core", eq);
473 if (err)
474 goto err_eq;
475 #ifdef RSS
476 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) {
477 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE;
478 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector,
479 rss_getcpu(bucket % rss_getnumbuckets()));
480 if (err)
481 goto err_irq;
482 }
483 #else
484 if (0)
485 goto err_irq;
486 #endif
487
488
489 /* EQs are created in ARMED state
490 */
491 eq_update_ci(eq, 1);
492
493 kvfree(in);
494 return 0;
495
496 err_irq:
497 free_irq(priv->msix_arr[vecidx].vector, eq);
498
499 err_eq:
500 mlx5_cmd_destroy_eq(dev, eq->eqn);
501
502 err_in:
503 kvfree(in);
504
505 err_buf:
506 mlx5_buf_free(dev, &eq->buf);
507 return err;
508 }
509 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
510
mlx5_destroy_unmap_eq(struct mlx5_core_dev * dev,struct mlx5_eq * eq)511 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
512 {
513 int err;
514
515 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq);
516 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
517 if (err)
518 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
519 eq->eqn);
520 mlx5_buf_free(dev, &eq->buf);
521
522 return err;
523 }
524 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
525
mlx5_eq_init(struct mlx5_core_dev * dev)526 int mlx5_eq_init(struct mlx5_core_dev *dev)
527 {
528 int err;
529
530 spin_lock_init(&dev->priv.eq_table.lock);
531
532 err = 0;
533
534 return err;
535 }
536
537
mlx5_eq_cleanup(struct mlx5_core_dev * dev)538 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
539 {
540 }
541
mlx5_start_eqs(struct mlx5_core_dev * dev)542 int mlx5_start_eqs(struct mlx5_core_dev *dev)
543 {
544 struct mlx5_eq_table *table = &dev->priv.eq_table;
545 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
546 int err;
547
548 if (MLX5_CAP_GEN(dev, port_module_event))
549 async_event_mask |= (1ull <<
550 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT);
551
552 if (MLX5_CAP_GEN(dev, nic_vport_change_event))
553 async_event_mask |= (1ull <<
554 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
555
556 if (MLX5_CAP_GEN(dev, dcbx))
557 async_event_mask |= (1ull <<
558 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT);
559
560 if (MLX5_CAP_GEN(dev, fpga))
561 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) |
562 (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR);
563
564 if (MLX5_CAP_GEN(dev, temp_warn_event))
565 async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT);
566
567 if (MLX5_CAP_GEN(dev, general_notification_event)) {
568 async_event_mask |= (1ull <<
569 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT);
570 }
571
572 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
573 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD);
574 if (err) {
575 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
576 return err;
577 }
578
579 mlx5_cmd_use_events(dev);
580
581 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
582 MLX5_NUM_ASYNC_EQE, async_event_mask);
583 if (err) {
584 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
585 goto err1;
586 }
587
588 err = mlx5_create_map_eq(dev, &table->pages_eq,
589 MLX5_EQ_VEC_PAGES,
590 /* TODO: sriov max_vf + */ 1,
591 1 << MLX5_EVENT_TYPE_PAGE_REQUEST);
592 if (err) {
593 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
594 goto err2;
595 }
596
597 return err;
598
599 err2:
600 mlx5_destroy_unmap_eq(dev, &table->async_eq);
601
602 err1:
603 mlx5_cmd_use_polling(dev);
604 mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
605 return err;
606 }
607
mlx5_stop_eqs(struct mlx5_core_dev * dev)608 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
609 {
610 struct mlx5_eq_table *table = &dev->priv.eq_table;
611 int err;
612
613 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
614 if (err)
615 return err;
616
617 mlx5_destroy_unmap_eq(dev, &table->async_eq);
618 mlx5_cmd_use_polling(dev);
619
620 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
621 if (err)
622 mlx5_cmd_use_events(dev);
623
624 return err;
625 }
626
mlx5_core_eq_query(struct mlx5_core_dev * dev,struct mlx5_eq * eq,u32 * out,int outlen)627 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
628 u32 *out, int outlen)
629 {
630 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
631
632 memset(out, 0, outlen);
633 MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ);
634 MLX5_SET(query_eq_in, in, eq_number, eq->eqn);
635
636 return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
637 }
638 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);
639
mlx5_port_module_event_error_type_to_string(u8 error_type)640 static const char *mlx5_port_module_event_error_type_to_string(u8 error_type)
641 {
642 switch (error_type) {
643 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED:
644 return "Power budget exceeded";
645 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE:
646 return "Long Range for non MLNX cable";
647 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK:
648 return "Bus stuck(I2C or data shorted)";
649 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT:
650 return "No EEPROM/retry timeout";
651 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST:
652 return "Enforce part number list";
653 case MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE:
654 return "Unknown identifier";
655 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE:
656 return "High Temperature";
657 case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED:
658 return "Bad or shorted cable/module";
659 case MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED:
660 return "PMD type is not enabled";
661 case MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE:
662 return "Laster_TEC_failure";
663 case MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT:
664 return "High_current";
665 case MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE:
666 return "High_voltage";
667 case MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED:
668 return "pcie_system_power_slot_Exceeded";
669 case MLX5_MODULE_EVENT_ERROR_HIGH_POWER:
670 return "High_power";
671 case MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT:
672 return "Module_state_machine_fault";
673 default:
674 return "Unknown error type";
675 }
676 }
677
mlx5_query_module_status(struct mlx5_core_dev * dev,int module_num)678 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num)
679 {
680 if (module_num < 0 || module_num >= MLX5_MAX_PORTS)
681 return 0; /* undefined */
682 return dev->module_status[module_num];
683 }
684
mlx5_port_module_event(struct mlx5_core_dev * dev,struct mlx5_eqe * eqe)685 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
686 struct mlx5_eqe *eqe)
687 {
688 unsigned int module_num;
689 unsigned int module_status;
690 unsigned int error_type;
691 struct mlx5_eqe_port_module_event *module_event_eqe;
692
693 module_event_eqe = &eqe->data.port_module_event;
694
695 module_num = (unsigned int)module_event_eqe->module;
696 module_status = (unsigned int)module_event_eqe->module_status &
697 PORT_MODULE_EVENT_MODULE_STATUS_MASK;
698 error_type = (unsigned int)module_event_eqe->error_type &
699 PORT_MODULE_EVENT_ERROR_TYPE_MASK;
700
701 if (module_status < MLX5_MODULE_STATUS_NUM)
702 dev->priv.pme_stats.status_counters[module_status]++;
703 switch (module_status) {
704 case MLX5_MODULE_STATUS_PLUGGED_ENABLED:
705 mlx5_core_info(dev,
706 "Module %u, status: plugged and enabled\n",
707 module_num);
708 break;
709
710 case MLX5_MODULE_STATUS_UNPLUGGED:
711 mlx5_core_info(dev,
712 "Module %u, status: unplugged\n", module_num);
713 break;
714
715 case MLX5_MODULE_STATUS_ERROR:
716 mlx5_core_err(dev,
717 "Module %u, status: error, %s (%d)\n",
718 module_num,
719 mlx5_port_module_event_error_type_to_string(error_type),
720 error_type);
721 if (error_type < MLX5_MODULE_EVENT_ERROR_NUM)
722 dev->priv.pme_stats.error_counters[error_type]++;
723 break;
724
725 default:
726 mlx5_core_info(dev,
727 "Module %u, unknown status %d\n", module_num, module_status);
728 }
729 /* store module status */
730 if (module_num < MLX5_MAX_PORTS)
731 dev->module_status[module_num] = module_status;
732 }
733
mlx5_port_general_notification_event(struct mlx5_core_dev * dev,struct mlx5_eqe * eqe)734 static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev,
735 struct mlx5_eqe *eqe)
736 {
737 u8 port = (eqe->data.port.port >> 4) & 0xf;
738 u32 rqn;
739 struct mlx5_eqe_general_notification_event *general_event;
740
741 switch (eqe->sub_type) {
742 case MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT:
743 general_event = &eqe->data.general_notifications;
744 rqn = be32_to_cpu(general_event->rq_user_index_delay_drop) &
745 0xffffff;
746 break;
747 case MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT:
748 mlx5_trigger_health_watchdog(dev);
749 break;
750 default:
751 mlx5_core_warn(dev,
752 "general event with unrecognized subtype: port %d, sub_type %d\n",
753 port, eqe->sub_type);
754 break;
755 }
756 }
757
758 void
mlx5_disable_interrupts(struct mlx5_core_dev * dev)759 mlx5_disable_interrupts(struct mlx5_core_dev *dev)
760 {
761 int nvec = dev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE;
762 int x;
763
764 for (x = 0; x != nvec; x++)
765 disable_irq(dev->priv.msix_arr[x].vector);
766 }
767
768 void
mlx5_poll_interrupts(struct mlx5_core_dev * dev)769 mlx5_poll_interrupts(struct mlx5_core_dev *dev)
770 {
771 struct mlx5_eq *eq;
772
773 if (unlikely(dev->priv.disable_irqs != 0))
774 return;
775
776 mlx5_eq_int(dev, &dev->priv.eq_table.cmd_eq);
777 mlx5_eq_int(dev, &dev->priv.eq_table.async_eq);
778 mlx5_eq_int(dev, &dev->priv.eq_table.pages_eq);
779
780 list_for_each_entry(eq, &dev->priv.eq_table.comp_eqs_list, list)
781 mlx5_eq_int(dev, eq);
782 }
783