1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 1997, Stefan Esser <[email protected]>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 *
30 */
31
32 #ifndef _PCIVAR_H_
33 #define _PCIVAR_H_
34
35 #include <sys/queue.h>
36 #include <sys/eventhandler.h>
37
38 /* some PCI bus constants */
39 #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
40 #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
41 #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
42
43 typedef uint64_t pci_addr_t;
44
45 /* Config registers for PCI-PCI and PCI-Cardbus bridges. */
46 struct pcicfg_bridge {
47 uint8_t br_seclat;
48 uint8_t br_subbus;
49 uint8_t br_secbus;
50 uint8_t br_pribus;
51 uint16_t br_control;
52 };
53
54 /* Interesting values for PCI power management */
55 struct pcicfg_pp {
56 uint16_t pp_cap; /* PCI power management capabilities */
57 uint8_t pp_status; /* conf. space addr. of PM control/status reg */
58 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */
59 uint8_t pp_data; /* conf. space addr. of PM data reg */
60 };
61
62 struct pci_map {
63 pci_addr_t pm_value; /* Raw BAR value */
64 pci_addr_t pm_size;
65 uint16_t pm_reg;
66 STAILQ_ENTRY(pci_map) pm_link;
67 };
68
69 struct vpd_readonly {
70 char keyword[2];
71 char *value;
72 int len;
73 };
74
75 struct vpd_write {
76 char keyword[2];
77 char *value;
78 int start;
79 int len;
80 };
81
82 struct pcicfg_vpd {
83 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
84 char vpd_cached;
85 char *vpd_ident; /* string identifier */
86 int vpd_rocnt;
87 struct vpd_readonly *vpd_ros;
88 int vpd_wcnt;
89 struct vpd_write *vpd_w;
90 };
91
92 /* Interesting values for PCI MSI */
93 struct pcicfg_msi {
94 uint16_t msi_ctrl; /* Message Control */
95 uint8_t msi_location; /* Offset of MSI capability registers. */
96 uint8_t msi_msgnum; /* Number of messages */
97 int msi_alloc; /* Number of allocated messages. */
98 uint64_t msi_addr; /* Contents of address register. */
99 uint16_t msi_data; /* Contents of data register. */
100 u_int msi_handlers;
101 };
102
103 /* Interesting values for PCI MSI-X */
104 struct msix_vector {
105 uint64_t mv_address; /* Contents of address register. */
106 uint32_t mv_data; /* Contents of data register. */
107 int mv_irq;
108 };
109
110 struct msix_table_entry {
111 u_int mte_vector; /* 1-based index into msix_vectors array. */
112 u_int mte_handlers;
113 };
114
115 struct pcicfg_msix {
116 uint16_t msix_ctrl; /* Message Control */
117 uint16_t msix_msgnum; /* Number of messages */
118 uint8_t msix_location; /* Offset of MSI-X capability registers. */
119 uint8_t msix_table_bar; /* BAR containing vector table. */
120 uint8_t msix_pba_bar; /* BAR containing PBA. */
121 uint32_t msix_table_offset;
122 uint32_t msix_pba_offset;
123 int msix_alloc; /* Number of allocated vectors. */
124 int msix_table_len; /* Length of virtual table. */
125 struct msix_table_entry *msix_table; /* Virtual table. */
126 struct msix_vector *msix_vectors; /* Array of allocated vectors. */
127 struct resource *msix_table_res; /* Resource containing vector table. */
128 struct resource *msix_pba_res; /* Resource containing PBA. */
129 };
130
131 /* Interesting values for HyperTransport */
132 struct pcicfg_ht {
133 uint8_t ht_slave; /* Non-zero if device is an HT slave. */
134 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
135 uint16_t ht_msictrl; /* MSI mapping control */
136 uint64_t ht_msiaddr; /* MSI mapping base address */
137 };
138
139 /* Interesting values for PCI-express */
140 struct pcicfg_pcie {
141 uint8_t pcie_location; /* Offset of PCI-e capability registers. */
142 uint8_t pcie_type; /* Device type. */
143 uint16_t pcie_flags; /* Device capabilities register. */
144 uint16_t pcie_device_ctl; /* Device control register. */
145 uint16_t pcie_link_ctl; /* Link control register. */
146 uint16_t pcie_slot_ctl; /* Slot control register. */
147 uint16_t pcie_root_ctl; /* Root control register. */
148 uint16_t pcie_device_ctl2; /* Second device control register. */
149 uint16_t pcie_link_ctl2; /* Second link control register. */
150 uint16_t pcie_slot_ctl2; /* Second slot control register. */
151 };
152
153 struct pcicfg_pcix {
154 uint16_t pcix_command;
155 uint8_t pcix_location; /* Offset of PCI-X capability registers. */
156 };
157
158 struct pcicfg_vf {
159 int index;
160 };
161
162 struct pci_ea_entry {
163 int eae_bei;
164 uint32_t eae_flags;
165 uint64_t eae_base;
166 uint64_t eae_max_offset;
167 uint32_t eae_cfg_offset;
168 STAILQ_ENTRY(pci_ea_entry) eae_link;
169 };
170
171 struct pcicfg_ea {
172 int ea_location; /* Structure offset in Configuration Header */
173 STAILQ_HEAD(, pci_ea_entry) ea_entries; /* EA entries */
174 };
175
176 #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */
177
178 /* config header information common to all header types */
179 typedef struct pcicfg {
180 device_t dev; /* device which owns this */
181
182 STAILQ_HEAD(, pci_map) maps; /* BARs */
183
184 uint16_t subvendor; /* card vendor ID */
185 uint16_t subdevice; /* card device ID, assigned by card vendor */
186 uint16_t vendor; /* chip vendor ID */
187 uint16_t device; /* chip device ID, assigned by chip vendor */
188
189 uint16_t cmdreg; /* disable/enable chip and PCI options */
190 uint16_t statreg; /* supported PCI features and error state */
191
192 uint8_t baseclass; /* chip PCI class */
193 uint8_t subclass; /* chip PCI subclass */
194 uint8_t progif; /* chip PCI programming interface */
195 uint8_t revid; /* chip revision ID */
196
197 uint8_t hdrtype; /* chip config header type */
198 uint8_t cachelnsz; /* cache line size in 4byte units */
199 uint8_t intpin; /* PCI interrupt pin */
200 uint8_t intline; /* interrupt line (IRQ for PC arch) */
201
202 uint8_t mingnt; /* min. useful bus grant time in 250ns units */
203 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
204 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
205
206 uint8_t mfdev; /* multi-function device (from hdrtype reg) */
207 uint8_t nummaps; /* actual number of PCI maps used */
208
209 uint32_t domain; /* PCI domain */
210 uint8_t bus; /* config space bus address */
211 uint8_t slot; /* config space slot address */
212 uint8_t func; /* config space function number */
213
214 uint32_t flags; /* flags defined above */
215
216 struct pcicfg_bridge bridge; /* Bridges */
217 struct pcicfg_pp pp; /* Power management */
218 struct pcicfg_vpd vpd; /* Vital product data */
219 struct pcicfg_msi msi; /* PCI MSI */
220 struct pcicfg_msix msix; /* PCI MSI-X */
221 struct pcicfg_ht ht; /* HyperTransport */
222 struct pcicfg_pcie pcie; /* PCI Express */
223 struct pcicfg_pcix pcix; /* PCI-X */
224 struct pcicfg_iov *iov; /* SR-IOV */
225 struct pcicfg_vf vf; /* SR-IOV Virtual Function */
226 struct pcicfg_ea ea; /* Enhanced Allocation */
227 } pcicfgregs;
228
229 /* additional type 1 device config header information (PCI to PCI bridge) */
230
231 typedef struct {
232 pci_addr_t pmembase; /* base address of prefetchable memory */
233 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
234 uint32_t membase; /* base address of memory window */
235 uint32_t memlimit; /* topmost address of memory window */
236 uint32_t iobase; /* base address of port window */
237 uint32_t iolimit; /* topmost address of port window */
238 uint16_t secstat; /* secondary bus status register */
239 uint16_t bridgectl; /* bridge control register */
240 uint8_t seclat; /* CardBus latency timer */
241 } pcih1cfgregs;
242
243 /* additional type 2 device config header information (CardBus bridge) */
244
245 typedef struct {
246 uint32_t membase0; /* base address of memory window */
247 uint32_t memlimit0; /* topmost address of memory window */
248 uint32_t membase1; /* base address of memory window */
249 uint32_t memlimit1; /* topmost address of memory window */
250 uint32_t iobase0; /* base address of port window */
251 uint32_t iolimit0; /* topmost address of port window */
252 uint32_t iobase1; /* base address of port window */
253 uint32_t iolimit1; /* topmost address of port window */
254 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
255 uint16_t secstat; /* secondary bus status register */
256 uint16_t bridgectl; /* bridge control register */
257 uint8_t seclat; /* CardBus latency timer */
258 } pcih2cfgregs;
259
260 extern uint32_t pci_numdevs;
261
262 struct pci_device_table {
263 #if BYTE_ORDER == LITTLE_ENDIAN
264 uint16_t
265 match_flag_vendor:1,
266 match_flag_device:1,
267 match_flag_subvendor:1,
268 match_flag_subdevice:1,
269 match_flag_class:1,
270 match_flag_subclass:1,
271 match_flag_revid:1,
272 match_flag_unused:9;
273 #else
274 uint16_t
275 match_flag_unused:9,
276 match_flag_revid:1,
277 match_flag_subclass:1,
278 match_flag_class:1,
279 match_flag_subdevice:1,
280 match_flag_subvendor:1,
281 match_flag_device:1,
282 match_flag_vendor:1;
283 #endif
284 uint16_t vendor;
285 uint16_t device;
286 uint16_t subvendor;
287 uint16_t subdevice;
288 uint16_t class_id;
289 uint16_t subclass;
290 uint16_t revid;
291 uint16_t unused;
292 uintptr_t driver_data;
293 char *descr;
294 };
295
296 #define PCI_DEV(v, d) \
297 .match_flag_vendor = 1, .vendor = (v), \
298 .match_flag_device = 1, .device = (d)
299 #define PCI_SUBDEV(sv, sd) \
300 .match_flag_subvendor = 1, .subvendor = (sv), \
301 .match_flag_subdevice = 1, .subdevice = (sd)
302 #define PCI_CLASS(x) \
303 .match_flag_class = 1, .class_id = (x)
304 #define PCI_SUBCLASS(x) \
305 .match_flag_subclass = 1, .subclass = (x)
306 #define PCI_REVID(x) \
307 .match_flag_revid = 1, .revid = (x)
308 #define PCI_DESCR(x) \
309 .descr = (x)
310 #define PCI_PNP_STR \
311 "M16:mask;U16:vendor;U16:device;U16:subvendor;U16:subdevice;" \
312 "U16:class;U16:subclass;U16:revid;"
313 #define PCI_PNP_INFO(table) \
314 MODULE_PNP_INFO(PCI_PNP_STR, pci, table, table, \
315 sizeof(table) / sizeof(table[0]))
316
317 const struct pci_device_table *pci_match_device(device_t child,
318 const struct pci_device_table *id, size_t nelt);
319 #define PCI_MATCH(child, table) \
320 pci_match_device(child, (table), nitems(table));
321
322 /* Only if the prerequisites are present */
323 #if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
324 struct pci_devinfo {
325 STAILQ_ENTRY(pci_devinfo) pci_links;
326 struct resource_list resources;
327 pcicfgregs cfg;
328 struct pci_conf conf;
329 };
330 #endif
331
332 #ifdef _SYS_BUS_H_
333
334 #include "pci_if.h"
335
336 enum pci_device_ivars {
337 PCI_IVAR_SUBVENDOR,
338 PCI_IVAR_SUBDEVICE,
339 PCI_IVAR_VENDOR,
340 PCI_IVAR_DEVICE,
341 PCI_IVAR_DEVID,
342 PCI_IVAR_CLASS,
343 PCI_IVAR_SUBCLASS,
344 PCI_IVAR_PROGIF,
345 PCI_IVAR_REVID,
346 PCI_IVAR_INTPIN,
347 PCI_IVAR_IRQ,
348 PCI_IVAR_DOMAIN,
349 PCI_IVAR_BUS,
350 PCI_IVAR_SLOT,
351 PCI_IVAR_FUNCTION,
352 PCI_IVAR_ETHADDR,
353 PCI_IVAR_CMDREG,
354 PCI_IVAR_CACHELNSZ,
355 PCI_IVAR_MINGNT,
356 PCI_IVAR_MAXLAT,
357 PCI_IVAR_LATTIMER
358 };
359
360 /*
361 * Simplified accessors for pci devices
362 */
363 #define PCI_ACCESSOR(var, ivar, type) \
364 __BUS_ACCESSOR(pci, var, PCI, ivar, type)
365
PCI_ACCESSOR(subvendor,SUBVENDOR,uint16_t)366 PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
367 PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
368 PCI_ACCESSOR(vendor, VENDOR, uint16_t)
369 PCI_ACCESSOR(device, DEVICE, uint16_t)
370 PCI_ACCESSOR(devid, DEVID, uint32_t)
371 PCI_ACCESSOR(class, CLASS, uint8_t)
372 PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
373 PCI_ACCESSOR(progif, PROGIF, uint8_t)
374 PCI_ACCESSOR(revid, REVID, uint8_t)
375 PCI_ACCESSOR(intpin, INTPIN, uint8_t)
376 PCI_ACCESSOR(irq, IRQ, uint8_t)
377 PCI_ACCESSOR(domain, DOMAIN, uint32_t)
378 PCI_ACCESSOR(bus, BUS, uint8_t)
379 PCI_ACCESSOR(slot, SLOT, uint8_t)
380 PCI_ACCESSOR(function, FUNCTION, uint8_t)
381 PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
382 PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
383 PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
384 PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
385 PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
386 PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
387
388 #undef PCI_ACCESSOR
389
390 /*
391 * Operations on configuration space.
392 */
393 static __inline uint32_t
394 pci_read_config(device_t dev, int reg, int width)
395 {
396 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
397 }
398
399 static __inline void
pci_write_config(device_t dev,int reg,uint32_t val,int width)400 pci_write_config(device_t dev, int reg, uint32_t val, int width)
401 {
402 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
403 }
404
405 /*
406 * Ivars for pci bridges.
407 */
408
409 /*typedef enum pci_device_ivars pcib_device_ivars;*/
410 enum pcib_device_ivars {
411 PCIB_IVAR_DOMAIN,
412 PCIB_IVAR_BUS
413 };
414
415 #define PCIB_ACCESSOR(var, ivar, type) \
416 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
417
PCIB_ACCESSOR(domain,DOMAIN,uint32_t)418 PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
419 PCIB_ACCESSOR(bus, BUS, uint32_t)
420
421 #undef PCIB_ACCESSOR
422
423 /*
424 * PCI interrupt validation. Invalid interrupt values such as 0 or 128
425 * on i386 or other platforms should be mapped out in the MD pcireadconf
426 * code and not here, since the only MI invalid IRQ is 255.
427 */
428 #define PCI_INVALID_IRQ 255
429 #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
430
431 /*
432 * Convenience functions.
433 *
434 * These should be used in preference to manually manipulating
435 * configuration space.
436 */
437 static __inline int
438 pci_enable_busmaster(device_t dev)
439 {
440 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
441 }
442
443 static __inline int
pci_disable_busmaster(device_t dev)444 pci_disable_busmaster(device_t dev)
445 {
446 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
447 }
448
449 static __inline int
pci_enable_io(device_t dev,int space)450 pci_enable_io(device_t dev, int space)
451 {
452 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
453 }
454
455 static __inline int
pci_disable_io(device_t dev,int space)456 pci_disable_io(device_t dev, int space)
457 {
458 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
459 }
460
461 static __inline int
pci_get_vpd_ident(device_t dev,const char ** identptr)462 pci_get_vpd_ident(device_t dev, const char **identptr)
463 {
464 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
465 }
466
467 static __inline int
pci_get_vpd_readonly(device_t dev,const char * kw,const char ** vptr)468 pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
469 {
470 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
471 }
472
473 /*
474 * Check if the address range falls within the VGA defined address range(s)
475 */
476 static __inline int
pci_is_vga_ioport_range(rman_res_t start,rman_res_t end)477 pci_is_vga_ioport_range(rman_res_t start, rman_res_t end)
478 {
479
480 return (((start >= 0x3b0 && end <= 0x3bb) ||
481 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
482 }
483
484 static __inline int
pci_is_vga_memory_range(rman_res_t start,rman_res_t end)485 pci_is_vga_memory_range(rman_res_t start, rman_res_t end)
486 {
487
488 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
489 }
490
491 /*
492 * PCI power states are as defined by ACPI:
493 *
494 * D0 State in which device is on and running. It is receiving full
495 * power from the system and delivering full functionality to the user.
496 * D1 Class-specific low-power state in which device context may or may not
497 * be lost. Buses in D1 cannot do anything to the bus that would force
498 * devices on that bus to lose context.
499 * D2 Class-specific low-power state in which device context may or may
500 * not be lost. Attains greater power savings than D1. Buses in D2
501 * can cause devices on that bus to lose some context. Devices in D2
502 * must be prepared for the bus to be in D2 or higher.
503 * D3 State in which the device is off and not running. Device context is
504 * lost. Power can be removed from the device.
505 */
506 #define PCI_POWERSTATE_D0 0
507 #define PCI_POWERSTATE_D1 1
508 #define PCI_POWERSTATE_D2 2
509 #define PCI_POWERSTATE_D3 3
510 #define PCI_POWERSTATE_UNKNOWN -1
511
512 static __inline int
pci_set_powerstate(device_t dev,int state)513 pci_set_powerstate(device_t dev, int state)
514 {
515 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
516 }
517
518 static __inline int
pci_get_powerstate(device_t dev)519 pci_get_powerstate(device_t dev)
520 {
521 return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
522 }
523
524 static __inline int
pci_find_cap(device_t dev,int capability,int * capreg)525 pci_find_cap(device_t dev, int capability, int *capreg)
526 {
527 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
528 }
529
530 static __inline int
pci_find_next_cap(device_t dev,int capability,int start,int * capreg)531 pci_find_next_cap(device_t dev, int capability, int start, int *capreg)
532 {
533 return (PCI_FIND_NEXT_CAP(device_get_parent(dev), dev, capability, start,
534 capreg));
535 }
536
537 static __inline int
pci_find_extcap(device_t dev,int capability,int * capreg)538 pci_find_extcap(device_t dev, int capability, int *capreg)
539 {
540 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
541 }
542
543 static __inline int
pci_find_next_extcap(device_t dev,int capability,int start,int * capreg)544 pci_find_next_extcap(device_t dev, int capability, int start, int *capreg)
545 {
546 return (PCI_FIND_NEXT_EXTCAP(device_get_parent(dev), dev, capability,
547 start, capreg));
548 }
549
550 static __inline int
pci_find_htcap(device_t dev,int capability,int * capreg)551 pci_find_htcap(device_t dev, int capability, int *capreg)
552 {
553 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
554 }
555
556 static __inline int
pci_find_next_htcap(device_t dev,int capability,int start,int * capreg)557 pci_find_next_htcap(device_t dev, int capability, int start, int *capreg)
558 {
559 return (PCI_FIND_NEXT_HTCAP(device_get_parent(dev), dev, capability,
560 start, capreg));
561 }
562
563 static __inline int
pci_alloc_msi(device_t dev,int * count)564 pci_alloc_msi(device_t dev, int *count)
565 {
566 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
567 }
568
569 static __inline int
pci_alloc_msix(device_t dev,int * count)570 pci_alloc_msix(device_t dev, int *count)
571 {
572 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
573 }
574
575 static __inline void
pci_enable_msi(device_t dev,uint64_t address,uint16_t data)576 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
577 {
578 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data);
579 }
580
581 static __inline void
pci_enable_msix(device_t dev,u_int index,uint64_t address,uint32_t data)582 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
583 {
584 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data);
585 }
586
587 static __inline void
pci_disable_msi(device_t dev)588 pci_disable_msi(device_t dev)
589 {
590 PCI_DISABLE_MSI(device_get_parent(dev), dev);
591 }
592
593 static __inline int
pci_remap_msix(device_t dev,int count,const u_int * vectors)594 pci_remap_msix(device_t dev, int count, const u_int *vectors)
595 {
596 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
597 }
598
599 static __inline int
pci_release_msi(device_t dev)600 pci_release_msi(device_t dev)
601 {
602 return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
603 }
604
605 static __inline int
pci_msi_count(device_t dev)606 pci_msi_count(device_t dev)
607 {
608 return (PCI_MSI_COUNT(device_get_parent(dev), dev));
609 }
610
611 static __inline int
pci_msix_count(device_t dev)612 pci_msix_count(device_t dev)
613 {
614 return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
615 }
616
617 static __inline int
pci_msix_pba_bar(device_t dev)618 pci_msix_pba_bar(device_t dev)
619 {
620 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev));
621 }
622
623 static __inline int
pci_msix_table_bar(device_t dev)624 pci_msix_table_bar(device_t dev)
625 {
626 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev));
627 }
628
629 static __inline int
pci_get_id(device_t dev,enum pci_id_type type,uintptr_t * id)630 pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id)
631 {
632 return (PCI_GET_ID(device_get_parent(dev), dev, type, id));
633 }
634
635 /*
636 * This is the deprecated interface, there is no way to tell the difference
637 * between a failure and a valid value that happens to be the same as the
638 * failure value.
639 */
640 static __inline uint16_t
pci_get_rid(device_t dev)641 pci_get_rid(device_t dev)
642 {
643 uintptr_t rid;
644
645 if (pci_get_id(dev, PCI_ID_RID, &rid) != 0)
646 return (0);
647
648 return (rid);
649 }
650
651 static __inline void
pci_child_added(device_t dev)652 pci_child_added(device_t dev)
653 {
654
655 return (PCI_CHILD_ADDED(device_get_parent(dev), dev));
656 }
657
658 device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
659 device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
660 device_t pci_find_device(uint16_t, uint16_t);
661 device_t pci_find_class(uint8_t class, uint8_t subclass);
662
663 /* Can be used by drivers to manage the MSI-X table. */
664 int pci_pending_msix(device_t dev, u_int index);
665
666 int pci_msi_device_blacklisted(device_t dev);
667 int pci_msix_device_blacklisted(device_t dev);
668
669 void pci_ht_map_msi(device_t dev, uint64_t addr);
670
671 device_t pci_find_pcie_root_port(device_t dev);
672 int pci_get_max_payload(device_t dev);
673 int pci_get_max_read_req(device_t dev);
674 void pci_restore_state(device_t dev);
675 void pci_save_state(device_t dev);
676 int pci_set_max_read_req(device_t dev, int size);
677 int pci_power_reset(device_t dev);
678 uint32_t pcie_read_config(device_t dev, int reg, int width);
679 void pcie_write_config(device_t dev, int reg, uint32_t value, int width);
680 uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
681 uint32_t value, int width);
682 bool pcie_flr(device_t dev, u_int max_delay, bool force);
683 int pcie_get_max_completion_timeout(device_t dev);
684 bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay);
685 int pcie_link_reset(device_t port, int pcie_location);
686
687 void pci_print_faulted_dev(void);
688
689 #ifdef BUS_SPACE_MAXADDR
690 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
691 #define PCI_DMA_BOUNDARY 0x100000000
692 #else
693 #define PCI_DMA_BOUNDARY 0
694 #endif
695 #endif
696
697 #endif /* _SYS_BUS_H_ */
698
699 /*
700 * cdev switch for control device, initialised in generic PCI code
701 */
702 extern struct cdevsw pcicdev;
703
704 /*
705 * List of all PCI devices, generation count for the list.
706 */
707 STAILQ_HEAD(devlist, pci_devinfo);
708
709 extern struct devlist pci_devq;
710 extern uint32_t pci_generation;
711
712 struct pci_map *pci_find_bar(device_t dev, int reg);
713 int pci_bar_enabled(device_t dev, struct pci_map *pm);
714 struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev);
715
716 #define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000
717 #define VGA_PCI_BIOS_SHADOW_SIZE 131072
718
719 int vga_pci_is_boot_display(device_t dev);
720 void * vga_pci_map_bios(device_t dev, size_t *size);
721 void vga_pci_unmap_bios(device_t dev, void *bios);
722 int vga_pci_repost(device_t dev);
723
724 /**
725 * Global eventhandlers invoked when PCI devices are added or removed
726 * from the system.
727 */
728 typedef void (*pci_event_fn)(void *arg, device_t dev);
729 EVENTHANDLER_DECLARE(pci_add_device, pci_event_fn);
730 EVENTHANDLER_DECLARE(pci_delete_device, pci_event_fn);
731
732 #endif /* _PCIVAR_H_ */
733