1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
5 * Copyright (C) 2009-2015 Semihalf
6 * Copyright (C) 2015 Stormshield
7 * All rights reserved.
8 *
9 * Developed by Semihalf.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. Neither the name of MARVELL nor the names of contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36 #ifdef HAVE_KERNEL_OPTION_HEADERS
37 #include "opt_device_polling.h"
38 #endif
39
40 #include <sys/cdefs.h>
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/endian.h>
44 #include <sys/mbuf.h>
45 #include <sys/lock.h>
46 #include <sys/mutex.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/socket.h>
50 #include <sys/sysctl.h>
51
52 #include <net/ethernet.h>
53 #include <net/bpf.h>
54 #include <net/if.h>
55 #include <net/if_arp.h>
56 #include <net/if_dl.h>
57 #include <net/if_media.h>
58 #include <net/if_types.h>
59 #include <net/if_vlan_var.h>
60
61 #include <netinet/in_systm.h>
62 #include <netinet/in.h>
63 #include <netinet/ip.h>
64
65 #include <sys/sockio.h>
66 #include <sys/bus.h>
67 #include <machine/bus.h>
68 #include <sys/rman.h>
69 #include <machine/resource.h>
70
71 #include <dev/mii/mii.h>
72 #include <dev/mii/miivar.h>
73
74 #include <dev/fdt/fdt_common.h>
75 #include <dev/ofw/ofw_bus.h>
76 #include <dev/ofw/ofw_bus_subr.h>
77 #include <dev/mdio/mdio.h>
78
79 #include <dev/mge/if_mgevar.h>
80 #include <arm/mv/mvreg.h>
81 #include <arm/mv/mvvar.h>
82
83 #include "miibus_if.h"
84 #include "mdio_if.h"
85
86 #define MGE_DELAY(x) pause("SMI access sleep", (x) / tick_sbt)
87
88 static int mge_probe(device_t dev);
89 static int mge_attach(device_t dev);
90 static int mge_detach(device_t dev);
91 static int mge_shutdown(device_t dev);
92 static int mge_suspend(device_t dev);
93 static int mge_resume(device_t dev);
94
95 static int mge_miibus_readreg(device_t dev, int phy, int reg);
96 static int mge_miibus_writereg(device_t dev, int phy, int reg, int value);
97
98 static int mge_mdio_readreg(device_t dev, int phy, int reg);
99 static int mge_mdio_writereg(device_t dev, int phy, int reg, int value);
100
101 static int mge_ifmedia_upd(if_t ifp);
102 static void mge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr);
103
104 static void mge_init(void *arg);
105 static void mge_init_locked(void *arg);
106 static void mge_start(if_t ifp);
107 static void mge_start_locked(if_t ifp);
108 static void mge_watchdog(struct mge_softc *sc);
109 static int mge_ioctl(if_t ifp, u_long command, caddr_t data);
110
111 static uint32_t mge_tfut_ipg(uint32_t val, int ver);
112 static uint32_t mge_rx_ipg(uint32_t val, int ver);
113 static void mge_ver_params(struct mge_softc *sc);
114
115 static void mge_intrs_ctrl(struct mge_softc *sc, int enable);
116 static void mge_intr_rxtx(void *arg);
117 static void mge_intr_rx(void *arg);
118 static void mge_intr_rx_check(struct mge_softc *sc, uint32_t int_cause,
119 uint32_t int_cause_ext);
120 static int mge_intr_rx_locked(struct mge_softc *sc, int count);
121 static void mge_intr_tx(void *arg);
122 static void mge_intr_tx_locked(struct mge_softc *sc);
123 static void mge_intr_misc(void *arg);
124 static void mge_intr_sum(void *arg);
125 static void mge_intr_err(void *arg);
126 static void mge_stop(struct mge_softc *sc);
127 static void mge_tick(void *msc);
128 static uint32_t mge_set_port_serial_control(uint32_t media);
129 static void mge_get_mac_address(struct mge_softc *sc, uint8_t *addr);
130 static void mge_set_mac_address(struct mge_softc *sc);
131 static void mge_set_ucast_address(struct mge_softc *sc, uint8_t last_byte,
132 uint8_t queue);
133 static void mge_set_prom_mode(struct mge_softc *sc, uint8_t queue);
134 static int mge_allocate_dma(struct mge_softc *sc);
135 static int mge_alloc_desc_dma(struct mge_softc *sc,
136 struct mge_desc_wrapper* desc_tab, uint32_t size,
137 bus_dma_tag_t *buffer_tag);
138 static int mge_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
139 struct mbuf **mbufp, bus_addr_t *paddr);
140 static void mge_get_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg,
141 int error);
142 static void mge_free_dma(struct mge_softc *sc);
143 static void mge_free_desc(struct mge_softc *sc, struct mge_desc_wrapper* tab,
144 uint32_t size, bus_dma_tag_t buffer_tag, uint8_t free_mbufs);
145 static void mge_offload_process_frame(if_t ifp, struct mbuf *frame,
146 uint32_t status, uint16_t bufsize);
147 static void mge_offload_setup_descriptor(struct mge_softc *sc,
148 struct mge_desc_wrapper *dw);
149 static uint8_t mge_crc8(uint8_t *data, int size);
150 static void mge_setup_multicast(struct mge_softc *sc);
151 static void mge_set_rxic(struct mge_softc *sc);
152 static void mge_set_txic(struct mge_softc *sc);
153 static void mge_add_sysctls(struct mge_softc *sc);
154 static int mge_sysctl_ic(SYSCTL_HANDLER_ARGS);
155
156 static device_method_t mge_methods[] = {
157 /* Device interface */
158 DEVMETHOD(device_probe, mge_probe),
159 DEVMETHOD(device_attach, mge_attach),
160 DEVMETHOD(device_detach, mge_detach),
161 DEVMETHOD(device_shutdown, mge_shutdown),
162 DEVMETHOD(device_suspend, mge_suspend),
163 DEVMETHOD(device_resume, mge_resume),
164 /* MII interface */
165 DEVMETHOD(miibus_readreg, mge_miibus_readreg),
166 DEVMETHOD(miibus_writereg, mge_miibus_writereg),
167 /* MDIO interface */
168 DEVMETHOD(mdio_readreg, mge_mdio_readreg),
169 DEVMETHOD(mdio_writereg, mge_mdio_writereg),
170 { 0, 0 }
171 };
172
173 DEFINE_CLASS_0(mge, mge_driver, mge_methods, sizeof(struct mge_softc));
174
175 static int switch_attached = 0;
176
177 DRIVER_MODULE(mge, simplebus, mge_driver, 0, 0);
178 DRIVER_MODULE(miibus, mge, miibus_driver, 0, 0);
179 DRIVER_MODULE(mdio, mge, mdio_driver, 0, 0);
180 MODULE_DEPEND(mge, ether, 1, 1, 1);
181 MODULE_DEPEND(mge, miibus, 1, 1, 1);
182 MODULE_DEPEND(mge, mdio, 1, 1, 1);
183
184 static struct resource_spec res_spec[] = {
185 { SYS_RES_MEMORY, 0, RF_ACTIVE },
186 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
187 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE },
188 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_SHAREABLE },
189 { -1, 0 }
190 };
191
192 static struct {
193 driver_intr_t *handler;
194 char * description;
195 } mge_intrs[MGE_INTR_COUNT + 1] = {
196 { mge_intr_rxtx,"GbE aggregated interrupt" },
197 { mge_intr_rx, "GbE receive interrupt" },
198 { mge_intr_tx, "GbE transmit interrupt" },
199 { mge_intr_misc,"GbE misc interrupt" },
200 { mge_intr_sum, "GbE summary interrupt" },
201 { mge_intr_err, "GbE error interrupt" },
202 };
203
204 /* SMI access interlock */
205 static struct sx sx_smi;
206
207 static uint32_t
mv_read_ge_smi(device_t dev,int phy,int reg)208 mv_read_ge_smi(device_t dev, int phy, int reg)
209 {
210 uint32_t timeout;
211 uint32_t ret;
212 struct mge_softc *sc;
213
214 sc = device_get_softc(dev);
215 KASSERT(sc != NULL, ("NULL softc ptr!"));
216 timeout = MGE_SMI_WRITE_RETRIES;
217
218 MGE_SMI_LOCK();
219 while (--timeout &&
220 (MGE_READ(sc, MGE_REG_SMI) & MGE_SMI_BUSY))
221 MGE_DELAY(MGE_SMI_WRITE_DELAY);
222
223 if (timeout == 0) {
224 device_printf(dev, "SMI write timeout.\n");
225 ret = ~0U;
226 goto out;
227 }
228
229 MGE_WRITE(sc, MGE_REG_SMI, MGE_SMI_MASK &
230 (MGE_SMI_READ | (reg << 21) | (phy << 16)));
231
232 /* Wait till finished. */
233 timeout = MGE_SMI_WRITE_RETRIES;
234 while (--timeout &&
235 !((MGE_READ(sc, MGE_REG_SMI) & MGE_SMI_READVALID)))
236 MGE_DELAY(MGE_SMI_WRITE_DELAY);
237
238 if (timeout == 0) {
239 device_printf(dev, "SMI write validation timeout.\n");
240 ret = ~0U;
241 goto out;
242 }
243
244 /* Wait for the data to update in the SMI register */
245 MGE_DELAY(MGE_SMI_DELAY);
246 ret = MGE_READ(sc, MGE_REG_SMI) & MGE_SMI_DATA_MASK;
247
248 out:
249 MGE_SMI_UNLOCK();
250 return (ret);
251
252 }
253
254 static void
mv_write_ge_smi(device_t dev,int phy,int reg,uint32_t value)255 mv_write_ge_smi(device_t dev, int phy, int reg, uint32_t value)
256 {
257 uint32_t timeout;
258 struct mge_softc *sc;
259
260 sc = device_get_softc(dev);
261 KASSERT(sc != NULL, ("NULL softc ptr!"));
262
263 MGE_SMI_LOCK();
264 timeout = MGE_SMI_READ_RETRIES;
265 while (--timeout &&
266 (MGE_READ(sc, MGE_REG_SMI) & MGE_SMI_BUSY))
267 MGE_DELAY(MGE_SMI_READ_DELAY);
268
269 if (timeout == 0) {
270 device_printf(dev, "SMI read timeout.\n");
271 goto out;
272 }
273
274 MGE_WRITE(sc, MGE_REG_SMI, MGE_SMI_MASK &
275 (MGE_SMI_WRITE | (reg << 21) | (phy << 16) |
276 (value & MGE_SMI_DATA_MASK)));
277
278 out:
279 MGE_SMI_UNLOCK();
280 }
281
282 static int
mv_read_ext_phy(device_t dev,int phy,int reg)283 mv_read_ext_phy(device_t dev, int phy, int reg)
284 {
285 uint32_t retries;
286 struct mge_softc *sc;
287 uint32_t ret;
288
289 sc = device_get_softc(dev);
290
291 MGE_SMI_LOCK();
292 MGE_WRITE(sc->phy_sc, MGE_REG_SMI, MGE_SMI_MASK &
293 (MGE_SMI_READ | (reg << 21) | (phy << 16)));
294
295 retries = MGE_SMI_READ_RETRIES;
296 while (--retries &&
297 !(MGE_READ(sc->phy_sc, MGE_REG_SMI) & MGE_SMI_READVALID))
298 DELAY(MGE_SMI_READ_DELAY);
299
300 if (retries == 0)
301 device_printf(dev, "Timeout while reading from PHY\n");
302
303 ret = MGE_READ(sc->phy_sc, MGE_REG_SMI) & MGE_SMI_DATA_MASK;
304 MGE_SMI_UNLOCK();
305
306 return (ret);
307 }
308
309 static void
mv_write_ext_phy(device_t dev,int phy,int reg,int value)310 mv_write_ext_phy(device_t dev, int phy, int reg, int value)
311 {
312 uint32_t retries;
313 struct mge_softc *sc;
314
315 sc = device_get_softc(dev);
316
317 MGE_SMI_LOCK();
318 MGE_WRITE(sc->phy_sc, MGE_REG_SMI, MGE_SMI_MASK &
319 (MGE_SMI_WRITE | (reg << 21) | (phy << 16) |
320 (value & MGE_SMI_DATA_MASK)));
321
322 retries = MGE_SMI_WRITE_RETRIES;
323 while (--retries && MGE_READ(sc->phy_sc, MGE_REG_SMI) & MGE_SMI_BUSY)
324 DELAY(MGE_SMI_WRITE_DELAY);
325
326 if (retries == 0)
327 device_printf(dev, "Timeout while writing to PHY\n");
328 MGE_SMI_UNLOCK();
329 }
330
331 static void
mge_get_mac_address(struct mge_softc * sc,uint8_t * addr)332 mge_get_mac_address(struct mge_softc *sc, uint8_t *addr)
333 {
334 uint32_t mac_l, mac_h;
335 uint8_t lmac[6];
336 int i, valid;
337
338 /*
339 * Retrieve hw address from the device tree.
340 */
341 i = OF_getprop(sc->node, "local-mac-address", (void *)lmac, 6);
342 if (i == 6) {
343 valid = 0;
344 for (i = 0; i < 6; i++)
345 if (lmac[i] != 0) {
346 valid = 1;
347 break;
348 }
349
350 if (valid) {
351 bcopy(lmac, addr, 6);
352 return;
353 }
354 }
355
356 /*
357 * Fall back -- use the currently programmed address.
358 */
359 mac_l = MGE_READ(sc, MGE_MAC_ADDR_L);
360 mac_h = MGE_READ(sc, MGE_MAC_ADDR_H);
361
362 addr[0] = (mac_h & 0xff000000) >> 24;
363 addr[1] = (mac_h & 0x00ff0000) >> 16;
364 addr[2] = (mac_h & 0x0000ff00) >> 8;
365 addr[3] = (mac_h & 0x000000ff);
366 addr[4] = (mac_l & 0x0000ff00) >> 8;
367 addr[5] = (mac_l & 0x000000ff);
368 }
369
370 static uint32_t
mge_tfut_ipg(uint32_t val,int ver)371 mge_tfut_ipg(uint32_t val, int ver)
372 {
373
374 switch (ver) {
375 case 1:
376 return ((val & 0x3fff) << 4);
377 case 2:
378 default:
379 return ((val & 0xffff) << 4);
380 }
381 }
382
383 static uint32_t
mge_rx_ipg(uint32_t val,int ver)384 mge_rx_ipg(uint32_t val, int ver)
385 {
386
387 switch (ver) {
388 case 1:
389 return ((val & 0x3fff) << 8);
390 case 2:
391 default:
392 return (((val & 0x8000) << 10) | ((val & 0x7fff) << 7));
393 }
394 }
395
396 static void
mge_ver_params(struct mge_softc * sc)397 mge_ver_params(struct mge_softc *sc)
398 {
399 uint32_t d, r;
400
401 soc_id(&d, &r);
402 if (d == MV_DEV_88F6281 || d == MV_DEV_88F6781 ||
403 d == MV_DEV_88F6282 ||
404 d == MV_DEV_MV78100 ||
405 d == MV_DEV_MV78100_Z0 ||
406 (d & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY) {
407 sc->mge_ver = 2;
408 sc->mge_mtu = 0x4e8;
409 sc->mge_tfut_ipg_max = 0xFFFF;
410 sc->mge_rx_ipg_max = 0xFFFF;
411 sc->mge_tx_arb_cfg = 0xFC0000FF;
412 sc->mge_tx_tok_cfg = 0xFFFF7FFF;
413 sc->mge_tx_tok_cnt = 0x3FFFFFFF;
414 } else {
415 sc->mge_ver = 1;
416 sc->mge_mtu = 0x458;
417 sc->mge_tfut_ipg_max = 0x3FFF;
418 sc->mge_rx_ipg_max = 0x3FFF;
419 sc->mge_tx_arb_cfg = 0x000000FF;
420 sc->mge_tx_tok_cfg = 0x3FFFFFFF;
421 sc->mge_tx_tok_cnt = 0x3FFFFFFF;
422 }
423 if (d == MV_DEV_88RC8180)
424 sc->mge_intr_cnt = 1;
425 else
426 sc->mge_intr_cnt = 2;
427
428 if (d == MV_DEV_MV78160 || d == MV_DEV_MV78260 || d == MV_DEV_MV78460)
429 sc->mge_hw_csum = 0;
430 else
431 sc->mge_hw_csum = 1;
432 }
433
434 static void
mge_set_mac_address(struct mge_softc * sc)435 mge_set_mac_address(struct mge_softc *sc)
436 {
437 char *if_mac;
438 uint32_t mac_l, mac_h;
439
440 MGE_GLOBAL_LOCK_ASSERT(sc);
441
442 if_mac = (char *)if_getlladdr(sc->ifp);
443
444 mac_l = (if_mac[4] << 8) | (if_mac[5]);
445 mac_h = (if_mac[0] << 24)| (if_mac[1] << 16) |
446 (if_mac[2] << 8) | (if_mac[3] << 0);
447
448 MGE_WRITE(sc, MGE_MAC_ADDR_L, mac_l);
449 MGE_WRITE(sc, MGE_MAC_ADDR_H, mac_h);
450
451 mge_set_ucast_address(sc, if_mac[5], MGE_RX_DEFAULT_QUEUE);
452 }
453
454 static void
mge_set_ucast_address(struct mge_softc * sc,uint8_t last_byte,uint8_t queue)455 mge_set_ucast_address(struct mge_softc *sc, uint8_t last_byte, uint8_t queue)
456 {
457 uint32_t reg_idx, reg_off, reg_val, i;
458
459 last_byte &= 0xf;
460 reg_idx = last_byte / MGE_UCAST_REG_NUMBER;
461 reg_off = (last_byte % MGE_UCAST_REG_NUMBER) * 8;
462 reg_val = (1 | (queue << 1)) << reg_off;
463
464 for (i = 0; i < MGE_UCAST_REG_NUMBER; i++) {
465 if ( i == reg_idx)
466 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val);
467 else
468 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), 0);
469 }
470 }
471
472 static void
mge_set_prom_mode(struct mge_softc * sc,uint8_t queue)473 mge_set_prom_mode(struct mge_softc *sc, uint8_t queue)
474 {
475 uint32_t port_config;
476 uint32_t reg_val, i;
477
478 /* Enable or disable promiscuous mode as needed */
479 if (if_getflags(sc->ifp) & IFF_PROMISC) {
480 port_config = MGE_READ(sc, MGE_PORT_CONFIG);
481 port_config |= PORT_CONFIG_UPM;
482 MGE_WRITE(sc, MGE_PORT_CONFIG, port_config);
483
484 reg_val = ((1 | (queue << 1)) | (1 | (queue << 1)) << 8 |
485 (1 | (queue << 1)) << 16 | (1 | (queue << 1)) << 24);
486
487 for (i = 0; i < MGE_MCAST_REG_NUMBER; i++) {
488 MGE_WRITE(sc, MGE_DA_FILTER_SPEC_MCAST(i), reg_val);
489 MGE_WRITE(sc, MGE_DA_FILTER_OTH_MCAST(i), reg_val);
490 }
491
492 for (i = 0; i < MGE_UCAST_REG_NUMBER; i++)
493 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), reg_val);
494
495 } else {
496 port_config = MGE_READ(sc, MGE_PORT_CONFIG);
497 port_config &= ~PORT_CONFIG_UPM;
498 MGE_WRITE(sc, MGE_PORT_CONFIG, port_config);
499
500 for (i = 0; i < MGE_MCAST_REG_NUMBER; i++) {
501 MGE_WRITE(sc, MGE_DA_FILTER_SPEC_MCAST(i), 0);
502 MGE_WRITE(sc, MGE_DA_FILTER_OTH_MCAST(i), 0);
503 }
504
505 mge_set_mac_address(sc);
506 }
507 }
508
509 static void
mge_get_dma_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)510 mge_get_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
511 {
512 u_int32_t *paddr;
513
514 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
515 paddr = arg;
516
517 *paddr = segs->ds_addr;
518 }
519
520 static int
mge_new_rxbuf(bus_dma_tag_t tag,bus_dmamap_t map,struct mbuf ** mbufp,bus_addr_t * paddr)521 mge_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
522 bus_addr_t *paddr)
523 {
524 struct mbuf *new_mbuf;
525 bus_dma_segment_t seg[1];
526 int error;
527 int nsegs;
528
529 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
530
531 new_mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
532 if (new_mbuf == NULL)
533 return (ENOBUFS);
534 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
535
536 if (*mbufp) {
537 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
538 bus_dmamap_unload(tag, map);
539 }
540
541 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
542 BUS_DMA_NOWAIT);
543 KASSERT(nsegs == 1, ("Too many segments returned!"));
544 if (nsegs != 1 || error)
545 panic("mge_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
546
547 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
548
549 (*mbufp) = new_mbuf;
550 (*paddr) = seg->ds_addr;
551 return (0);
552 }
553
554 static int
mge_alloc_desc_dma(struct mge_softc * sc,struct mge_desc_wrapper * tab,uint32_t size,bus_dma_tag_t * buffer_tag)555 mge_alloc_desc_dma(struct mge_softc *sc, struct mge_desc_wrapper* tab,
556 uint32_t size, bus_dma_tag_t *buffer_tag)
557 {
558 struct mge_desc_wrapper *dw;
559 bus_addr_t desc_paddr;
560 int i, error;
561
562 desc_paddr = 0;
563 for (i = size - 1; i >= 0; i--) {
564 dw = &(tab[i]);
565 error = bus_dmamem_alloc(sc->mge_desc_dtag,
566 (void**)&(dw->mge_desc),
567 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
568 &(dw->desc_dmap));
569
570 if (error) {
571 if_printf(sc->ifp, "failed to allocate DMA memory\n");
572 dw->mge_desc = NULL;
573 return (ENXIO);
574 }
575
576 error = bus_dmamap_load(sc->mge_desc_dtag, dw->desc_dmap,
577 dw->mge_desc, sizeof(struct mge_desc), mge_get_dma_addr,
578 &(dw->mge_desc_paddr), BUS_DMA_NOWAIT);
579
580 if (error) {
581 if_printf(sc->ifp, "can't load descriptor\n");
582 bus_dmamem_free(sc->mge_desc_dtag, dw->mge_desc,
583 dw->desc_dmap);
584 dw->mge_desc = NULL;
585 return (ENXIO);
586 }
587
588 /* Chain descriptors */
589 dw->mge_desc->next_desc = desc_paddr;
590 desc_paddr = dw->mge_desc_paddr;
591 }
592 tab[size - 1].mge_desc->next_desc = desc_paddr;
593
594 /* Allocate a busdma tag for mbufs. */
595 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent */
596 1, 0, /* alignment, boundary */
597 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
598 BUS_SPACE_MAXADDR, /* highaddr */
599 NULL, NULL, /* filtfunc, filtfuncarg */
600 MCLBYTES, 1, /* maxsize, nsegments */
601 MCLBYTES, 0, /* maxsegsz, flags */
602 NULL, NULL, /* lockfunc, lockfuncarg */
603 buffer_tag); /* dmat */
604 if (error) {
605 if_printf(sc->ifp, "failed to create busdma tag for mbufs\n");
606 return (ENXIO);
607 }
608
609 /* Create TX busdma maps */
610 for (i = 0; i < size; i++) {
611 dw = &(tab[i]);
612 error = bus_dmamap_create(*buffer_tag, 0, &dw->buffer_dmap);
613 if (error) {
614 if_printf(sc->ifp, "failed to create map for mbuf\n");
615 return (ENXIO);
616 }
617
618 dw->buffer = (struct mbuf*)NULL;
619 dw->mge_desc->buffer = (bus_addr_t)NULL;
620 }
621
622 return (0);
623 }
624
625 static int
mge_allocate_dma(struct mge_softc * sc)626 mge_allocate_dma(struct mge_softc *sc)
627 {
628 struct mge_desc_wrapper *dw;
629 int i;
630
631 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
632 bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent */
633 16, 0, /* alignment, boundary */
634 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
635 BUS_SPACE_MAXADDR, /* highaddr */
636 NULL, NULL, /* filtfunc, filtfuncarg */
637 sizeof(struct mge_desc), 1, /* maxsize, nsegments */
638 sizeof(struct mge_desc), 0, /* maxsegsz, flags */
639 NULL, NULL, /* lockfunc, lockfuncarg */
640 &sc->mge_desc_dtag); /* dmat */
641
642
643 mge_alloc_desc_dma(sc, sc->mge_tx_desc, MGE_TX_DESC_NUM,
644 &sc->mge_tx_dtag);
645 mge_alloc_desc_dma(sc, sc->mge_rx_desc, MGE_RX_DESC_NUM,
646 &sc->mge_rx_dtag);
647
648 for (i = 0; i < MGE_RX_DESC_NUM; i++) {
649 dw = &(sc->mge_rx_desc[i]);
650 mge_new_rxbuf(sc->mge_rx_dtag, dw->buffer_dmap, &dw->buffer,
651 &dw->mge_desc->buffer);
652 }
653
654 sc->tx_desc_start = sc->mge_tx_desc[0].mge_desc_paddr;
655 sc->rx_desc_start = sc->mge_rx_desc[0].mge_desc_paddr;
656
657 return (0);
658 }
659
660 static void
mge_free_desc(struct mge_softc * sc,struct mge_desc_wrapper * tab,uint32_t size,bus_dma_tag_t buffer_tag,uint8_t free_mbufs)661 mge_free_desc(struct mge_softc *sc, struct mge_desc_wrapper* tab,
662 uint32_t size, bus_dma_tag_t buffer_tag, uint8_t free_mbufs)
663 {
664 struct mge_desc_wrapper *dw;
665 int i;
666
667 for (i = 0; i < size; i++) {
668 /* Free RX mbuf */
669 dw = &(tab[i]);
670
671 if (dw->buffer_dmap) {
672 if (free_mbufs) {
673 bus_dmamap_sync(buffer_tag, dw->buffer_dmap,
674 BUS_DMASYNC_POSTREAD);
675 bus_dmamap_unload(buffer_tag, dw->buffer_dmap);
676 }
677 bus_dmamap_destroy(buffer_tag, dw->buffer_dmap);
678 if (free_mbufs)
679 m_freem(dw->buffer);
680 }
681 /* Free RX descriptors */
682 if (dw->desc_dmap) {
683 bus_dmamap_sync(sc->mge_desc_dtag, dw->desc_dmap,
684 BUS_DMASYNC_POSTREAD);
685 bus_dmamap_unload(sc->mge_desc_dtag, dw->desc_dmap);
686 bus_dmamem_free(sc->mge_desc_dtag, dw->mge_desc,
687 dw->desc_dmap);
688 }
689 }
690 }
691
692 static void
mge_free_dma(struct mge_softc * sc)693 mge_free_dma(struct mge_softc *sc)
694 {
695
696 /* Free descriptors and mbufs */
697 mge_free_desc(sc, sc->mge_rx_desc, MGE_RX_DESC_NUM, sc->mge_rx_dtag, 1);
698 mge_free_desc(sc, sc->mge_tx_desc, MGE_TX_DESC_NUM, sc->mge_tx_dtag, 0);
699
700 /* Destroy mbuf dma tag */
701 bus_dma_tag_destroy(sc->mge_tx_dtag);
702 bus_dma_tag_destroy(sc->mge_rx_dtag);
703 /* Destroy descriptors tag */
704 bus_dma_tag_destroy(sc->mge_desc_dtag);
705 }
706
707 static void
mge_reinit_rx(struct mge_softc * sc)708 mge_reinit_rx(struct mge_softc *sc)
709 {
710 struct mge_desc_wrapper *dw;
711 int i;
712
713 MGE_RECEIVE_LOCK_ASSERT(sc);
714
715 mge_free_desc(sc, sc->mge_rx_desc, MGE_RX_DESC_NUM, sc->mge_rx_dtag, 1);
716
717 mge_alloc_desc_dma(sc, sc->mge_rx_desc, MGE_RX_DESC_NUM,
718 &sc->mge_rx_dtag);
719
720 for (i = 0; i < MGE_RX_DESC_NUM; i++) {
721 dw = &(sc->mge_rx_desc[i]);
722 mge_new_rxbuf(sc->mge_rx_dtag, dw->buffer_dmap, &dw->buffer,
723 &dw->mge_desc->buffer);
724 }
725
726 sc->rx_desc_start = sc->mge_rx_desc[0].mge_desc_paddr;
727 sc->rx_desc_curr = 0;
728
729 MGE_WRITE(sc, MGE_RX_CUR_DESC_PTR(MGE_RX_DEFAULT_QUEUE),
730 sc->rx_desc_start);
731
732 /* Enable RX queue */
733 MGE_WRITE(sc, MGE_RX_QUEUE_CMD, MGE_ENABLE_RXQ(MGE_RX_DEFAULT_QUEUE));
734 }
735
736 #ifdef DEVICE_POLLING
737 static poll_handler_t mge_poll;
738
739 static int
mge_poll(if_t ifp,enum poll_cmd cmd,int count)740 mge_poll(if_t ifp, enum poll_cmd cmd, int count)
741 {
742 struct mge_softc *sc = if_getsoftc(ifp);
743 uint32_t int_cause, int_cause_ext;
744 int rx_npkts = 0;
745
746 MGE_RECEIVE_LOCK(sc);
747
748 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
749 MGE_RECEIVE_UNLOCK(sc);
750 return (rx_npkts);
751 }
752
753 if (cmd == POLL_AND_CHECK_STATUS) {
754 int_cause = MGE_READ(sc, MGE_PORT_INT_CAUSE);
755 int_cause_ext = MGE_READ(sc, MGE_PORT_INT_CAUSE_EXT);
756
757 /* Check for resource error */
758 if (int_cause & MGE_PORT_INT_RXERRQ0)
759 mge_reinit_rx(sc);
760
761 if (int_cause || int_cause_ext) {
762 MGE_WRITE(sc, MGE_PORT_INT_CAUSE, ~int_cause);
763 MGE_WRITE(sc, MGE_PORT_INT_CAUSE_EXT, ~int_cause_ext);
764 }
765 }
766
767
768 rx_npkts = mge_intr_rx_locked(sc, count);
769
770 MGE_RECEIVE_UNLOCK(sc);
771 MGE_TRANSMIT_LOCK(sc);
772 mge_intr_tx_locked(sc);
773 MGE_TRANSMIT_UNLOCK(sc);
774 return (rx_npkts);
775 }
776 #endif /* DEVICE_POLLING */
777
778 static int
mge_attach(device_t dev)779 mge_attach(device_t dev)
780 {
781 struct mge_softc *sc;
782 struct mii_softc *miisc;
783 if_t ifp;
784 uint8_t hwaddr[ETHER_ADDR_LEN];
785 int i, error, phy;
786
787 sc = device_get_softc(dev);
788 sc->dev = dev;
789 sc->node = ofw_bus_get_node(dev);
790 phy = 0;
791
792 if (fdt_get_phyaddr(sc->node, sc->dev, &phy, (void **)&sc->phy_sc) == 0) {
793 device_printf(dev, "PHY%i attached, phy_sc points to %s\n", phy,
794 device_get_nameunit(sc->phy_sc->dev));
795 sc->phy_attached = 1;
796 } else {
797 device_printf(dev, "PHY not attached.\n");
798 sc->phy_attached = 0;
799 sc->phy_sc = sc;
800 }
801
802 if (fdt_find_compatible(sc->node, "mrvl,sw", 1) != 0) {
803 device_printf(dev, "Switch attached.\n");
804 sc->switch_attached = 1;
805 /* additional variable available across instances */
806 switch_attached = 1;
807 } else {
808 sc->switch_attached = 0;
809 }
810
811 if (device_get_unit(dev) == 0) {
812 sx_init(&sx_smi, "mge_tick() SMI access threads interlock");
813 }
814
815 /* Set chip version-dependent parameters */
816 mge_ver_params(sc);
817
818 /* Initialize mutexes */
819 mtx_init(&sc->transmit_lock, device_get_nameunit(dev), "mge TX lock",
820 MTX_DEF);
821 mtx_init(&sc->receive_lock, device_get_nameunit(dev), "mge RX lock",
822 MTX_DEF);
823
824 /* Allocate IO and IRQ resources */
825 error = bus_alloc_resources(dev, res_spec, sc->res);
826 if (error) {
827 device_printf(dev, "could not allocate resources\n");
828 mge_detach(dev);
829 return (ENXIO);
830 }
831
832 /* Allocate DMA, buffers, buffer descriptors */
833 error = mge_allocate_dma(sc);
834 if (error) {
835 mge_detach(dev);
836 return (ENXIO);
837 }
838
839 sc->tx_desc_curr = 0;
840 sc->rx_desc_curr = 0;
841 sc->tx_desc_used_idx = 0;
842 sc->tx_desc_used_count = 0;
843
844 /* Configure defaults for interrupts coalescing */
845 sc->rx_ic_time = 768;
846 sc->tx_ic_time = 768;
847 mge_add_sysctls(sc);
848
849 /* Allocate network interface */
850 ifp = sc->ifp = if_alloc(IFT_ETHER);
851 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
852 if_setsoftc(ifp, sc);
853 if_setflags(ifp, IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST);
854 if_setcapabilities(ifp, IFCAP_VLAN_MTU);
855 if (sc->mge_hw_csum) {
856 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0);
857 if_sethwassist(ifp, MGE_CHECKSUM_FEATURES);
858 }
859 if_setcapenable(ifp, if_getcapabilities(ifp));
860
861 #ifdef DEVICE_POLLING
862 /* Advertise that polling is supported */
863 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
864 #endif
865
866 if_setinitfn(ifp, mge_init);
867 if_setstartfn(ifp, mge_start);
868 if_setioctlfn(ifp, mge_ioctl);
869
870 if_setsendqlen(ifp, MGE_TX_DESC_NUM - 1);
871 if_setsendqready(ifp);
872
873 mge_get_mac_address(sc, hwaddr);
874 ether_ifattach(ifp, hwaddr);
875 callout_init(&sc->wd_callout, 1);
876
877 /* Attach PHY(s) */
878 if (sc->phy_attached) {
879 error = mii_attach(dev, &sc->miibus, ifp, mge_ifmedia_upd,
880 mge_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
881 if (error) {
882 device_printf(dev, "MII failed to find PHY\n");
883 if_free(ifp);
884 sc->ifp = NULL;
885 mge_detach(dev);
886 return (error);
887 }
888 sc->mii = device_get_softc(sc->miibus);
889
890 /* Tell the MAC where to find the PHY so autoneg works */
891 miisc = LIST_FIRST(&sc->mii->mii_phys);
892 MGE_WRITE(sc, MGE_REG_PHYDEV, miisc->mii_phy);
893 } else {
894 /* no PHY, so use hard-coded values */
895 ifmedia_init(&sc->mge_ifmedia, 0,
896 mge_ifmedia_upd,
897 mge_ifmedia_sts);
898 ifmedia_add(&sc->mge_ifmedia,
899 IFM_ETHER | IFM_1000_T | IFM_FDX,
900 0, NULL);
901 ifmedia_set(&sc->mge_ifmedia,
902 IFM_ETHER | IFM_1000_T | IFM_FDX);
903 }
904
905 /* Attach interrupt handlers */
906 /* TODO: review flags, in part. mark RX as INTR_ENTROPY ? */
907 for (i = 1; i <= sc->mge_intr_cnt; ++i) {
908 error = bus_setup_intr(dev, sc->res[i],
909 INTR_TYPE_NET | INTR_MPSAFE,
910 NULL, *mge_intrs[(sc->mge_intr_cnt == 1 ? 0 : i)].handler,
911 sc, &sc->ih_cookie[i - 1]);
912 if (error) {
913 device_printf(dev, "could not setup %s\n",
914 mge_intrs[(sc->mge_intr_cnt == 1 ? 0 : i)].description);
915 mge_detach(dev);
916 return (error);
917 }
918 }
919
920 if (sc->switch_attached) {
921 MGE_WRITE(sc, MGE_REG_PHYDEV, MGE_SWITCH_PHYDEV);
922 device_add_child(dev, "mdio", -1);
923 bus_generic_attach(dev);
924 }
925
926 return (0);
927 }
928
929 static int
mge_detach(device_t dev)930 mge_detach(device_t dev)
931 {
932 struct mge_softc *sc;
933 int error,i;
934
935 sc = device_get_softc(dev);
936
937 /* Stop controller and free TX queue */
938 if (sc->ifp)
939 mge_shutdown(dev);
940
941 /* Wait for stopping ticks */
942 callout_drain(&sc->wd_callout);
943
944 /* Stop and release all interrupts */
945 for (i = 0; i < sc->mge_intr_cnt; ++i) {
946 if (!sc->ih_cookie[i])
947 continue;
948
949 error = bus_teardown_intr(dev, sc->res[1 + i],
950 sc->ih_cookie[i]);
951 if (error)
952 device_printf(dev, "could not release %s\n",
953 mge_intrs[(sc->mge_intr_cnt == 1 ? 0 : i + 1)].description);
954 }
955
956 /* Detach network interface */
957 if (sc->ifp) {
958 ether_ifdetach(sc->ifp);
959 if_free(sc->ifp);
960 }
961
962 /* Free DMA resources */
963 mge_free_dma(sc);
964
965 /* Free IO memory handler */
966 bus_release_resources(dev, res_spec, sc->res);
967
968 /* Destroy mutexes */
969 mtx_destroy(&sc->receive_lock);
970 mtx_destroy(&sc->transmit_lock);
971
972 if (device_get_unit(dev) == 0)
973 sx_destroy(&sx_smi);
974
975 return (0);
976 }
977
978 static void
mge_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)979 mge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
980 {
981 struct mge_softc *sc;
982 struct mii_data *mii;
983
984 sc = if_getsoftc(ifp);
985 MGE_GLOBAL_LOCK(sc);
986
987 if (!sc->phy_attached) {
988 ifmr->ifm_active = IFM_1000_T | IFM_FDX | IFM_ETHER;
989 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
990 goto out_unlock;
991 }
992
993 mii = sc->mii;
994 mii_pollstat(mii);
995
996 ifmr->ifm_active = mii->mii_media_active;
997 ifmr->ifm_status = mii->mii_media_status;
998
999 out_unlock:
1000 MGE_GLOBAL_UNLOCK(sc);
1001 }
1002
1003 static uint32_t
mge_set_port_serial_control(uint32_t media)1004 mge_set_port_serial_control(uint32_t media)
1005 {
1006 uint32_t port_config;
1007
1008 port_config = PORT_SERIAL_RES_BIT9 | PORT_SERIAL_FORCE_LINK_FAIL |
1009 PORT_SERIAL_MRU(PORT_SERIAL_MRU_1552);
1010
1011 if (IFM_TYPE(media) == IFM_ETHER) {
1012 switch(IFM_SUBTYPE(media)) {
1013 case IFM_AUTO:
1014 break;
1015 case IFM_1000_T:
1016 port_config |= (PORT_SERIAL_GMII_SPEED_1000 |
1017 PORT_SERIAL_AUTONEG | PORT_SERIAL_AUTONEG_FC
1018 | PORT_SERIAL_SPEED_AUTONEG);
1019 break;
1020 case IFM_100_TX:
1021 port_config |= (PORT_SERIAL_MII_SPEED_100 |
1022 PORT_SERIAL_AUTONEG | PORT_SERIAL_AUTONEG_FC
1023 | PORT_SERIAL_SPEED_AUTONEG);
1024 break;
1025 case IFM_10_T:
1026 port_config |= (PORT_SERIAL_AUTONEG |
1027 PORT_SERIAL_AUTONEG_FC |
1028 PORT_SERIAL_SPEED_AUTONEG);
1029 break;
1030 }
1031 if (media & IFM_FDX)
1032 port_config |= PORT_SERIAL_FULL_DUPLEX;
1033 }
1034 return (port_config);
1035 }
1036
1037 static int
mge_ifmedia_upd(if_t ifp)1038 mge_ifmedia_upd(if_t ifp)
1039 {
1040 struct mge_softc *sc = if_getsoftc(ifp);
1041
1042 /*
1043 * Do not do anything for switch here, as updating media between
1044 * MGE MAC and switch MAC is hardcoded in PCB. Changing it here would
1045 * break the link.
1046 */
1047 if (sc->phy_attached) {
1048 MGE_GLOBAL_LOCK(sc);
1049 if (if_getflags(ifp) & IFF_UP) {
1050 sc->mge_media_status = sc->mii->mii_media.ifm_media;
1051 mii_mediachg(sc->mii);
1052
1053 /* MGE MAC needs to be reinitialized. */
1054 mge_init_locked(sc);
1055
1056 }
1057 MGE_GLOBAL_UNLOCK(sc);
1058 }
1059
1060 return (0);
1061 }
1062
1063 static void
mge_init(void * arg)1064 mge_init(void *arg)
1065 {
1066 struct mge_softc *sc;
1067
1068 sc = arg;
1069 MGE_GLOBAL_LOCK(sc);
1070
1071 mge_init_locked(arg);
1072
1073 MGE_GLOBAL_UNLOCK(sc);
1074 }
1075
1076 static void
mge_init_locked(void * arg)1077 mge_init_locked(void *arg)
1078 {
1079 struct mge_softc *sc = arg;
1080 struct mge_desc_wrapper *dw;
1081 volatile uint32_t reg_val;
1082 int i, count;
1083 uint32_t media_status;
1084
1085
1086 MGE_GLOBAL_LOCK_ASSERT(sc);
1087
1088 /* Stop interface */
1089 mge_stop(sc);
1090
1091 /* Disable interrupts */
1092 mge_intrs_ctrl(sc, 0);
1093
1094 /* Set MAC address */
1095 mge_set_mac_address(sc);
1096
1097 /* Setup multicast filters */
1098 mge_setup_multicast(sc);
1099
1100 if (sc->mge_ver == 2) {
1101 MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL1, MGE_RGMII_EN);
1102 MGE_WRITE(sc, MGE_FIXED_PRIO_CONF, MGE_FIXED_PRIO_EN(0));
1103 }
1104
1105 /* Initialize TX queue configuration registers */
1106 MGE_WRITE(sc, MGE_TX_TOKEN_COUNT(0), sc->mge_tx_tok_cnt);
1107 MGE_WRITE(sc, MGE_TX_TOKEN_CONF(0), sc->mge_tx_tok_cfg);
1108 MGE_WRITE(sc, MGE_TX_ARBITER_CONF(0), sc->mge_tx_arb_cfg);
1109
1110 /* Clear TX queue configuration registers for unused queues */
1111 for (i = 1; i < 7; i++) {
1112 MGE_WRITE(sc, MGE_TX_TOKEN_COUNT(i), 0);
1113 MGE_WRITE(sc, MGE_TX_TOKEN_CONF(i), 0);
1114 MGE_WRITE(sc, MGE_TX_ARBITER_CONF(i), 0);
1115 }
1116
1117 /* Set default MTU */
1118 MGE_WRITE(sc, sc->mge_mtu, 0);
1119
1120 /* Port configuration */
1121 MGE_WRITE(sc, MGE_PORT_CONFIG,
1122 PORT_CONFIG_RXCS | PORT_CONFIG_DFLT_RXQ(0) |
1123 PORT_CONFIG_ARO_RXQ(0));
1124 MGE_WRITE(sc, MGE_PORT_EXT_CONFIG , 0x0);
1125
1126 /* Configure promisc mode */
1127 mge_set_prom_mode(sc, MGE_RX_DEFAULT_QUEUE);
1128
1129 media_status = sc->mge_media_status;
1130 if (sc->switch_attached) {
1131 media_status &= ~IFM_TMASK;
1132 media_status |= IFM_1000_T;
1133 }
1134
1135 /* Setup port configuration */
1136 reg_val = mge_set_port_serial_control(media_status);
1137 MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
1138
1139 /* Setup SDMA configuration */
1140 MGE_WRITE(sc, MGE_SDMA_CONFIG , MGE_SDMA_RX_BYTE_SWAP |
1141 MGE_SDMA_TX_BYTE_SWAP |
1142 MGE_SDMA_RX_BURST_SIZE(MGE_SDMA_BURST_16_WORD) |
1143 MGE_SDMA_TX_BURST_SIZE(MGE_SDMA_BURST_16_WORD));
1144
1145 MGE_WRITE(sc, MGE_TX_FIFO_URGENT_TRSH, 0x0);
1146
1147 MGE_WRITE(sc, MGE_TX_CUR_DESC_PTR, sc->tx_desc_start);
1148 MGE_WRITE(sc, MGE_RX_CUR_DESC_PTR(MGE_RX_DEFAULT_QUEUE),
1149 sc->rx_desc_start);
1150
1151 /* Reset descriptor indexes */
1152 sc->tx_desc_curr = 0;
1153 sc->rx_desc_curr = 0;
1154 sc->tx_desc_used_idx = 0;
1155 sc->tx_desc_used_count = 0;
1156
1157 /* Enable RX descriptors */
1158 for (i = 0; i < MGE_RX_DESC_NUM; i++) {
1159 dw = &sc->mge_rx_desc[i];
1160 dw->mge_desc->cmd_status = MGE_RX_ENABLE_INT | MGE_DMA_OWNED;
1161 dw->mge_desc->buff_size = MCLBYTES;
1162 bus_dmamap_sync(sc->mge_desc_dtag, dw->desc_dmap,
1163 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1164 }
1165
1166 /* Enable RX queue */
1167 MGE_WRITE(sc, MGE_RX_QUEUE_CMD, MGE_ENABLE_RXQ(MGE_RX_DEFAULT_QUEUE));
1168
1169 /* Enable port */
1170 reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
1171 reg_val |= PORT_SERIAL_ENABLE;
1172 MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
1173 count = 0x100000;
1174 for (;;) {
1175 reg_val = MGE_READ(sc, MGE_PORT_STATUS);
1176 if (reg_val & MGE_STATUS_LINKUP)
1177 break;
1178 DELAY(100);
1179 if (--count == 0) {
1180 if_printf(sc->ifp, "Timeout on link-up\n");
1181 break;
1182 }
1183 }
1184
1185 /* Setup interrupts coalescing */
1186 mge_set_rxic(sc);
1187 mge_set_txic(sc);
1188
1189 /* Enable interrupts */
1190 #ifdef DEVICE_POLLING
1191 /*
1192 * * ...only if polling is not turned on. Disable interrupts explicitly
1193 * if polling is enabled.
1194 */
1195 if (if_getcapenable(sc->ifp) & IFCAP_POLLING)
1196 mge_intrs_ctrl(sc, 0);
1197 else
1198 #endif /* DEVICE_POLLING */
1199 mge_intrs_ctrl(sc, 1);
1200
1201 /* Activate network interface */
1202 if_setdrvflagbits(sc->ifp, IFF_DRV_RUNNING, 0);
1203 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_OACTIVE);
1204 sc->wd_timer = 0;
1205
1206 /* Schedule watchdog timeout */
1207 if (sc->phy_attached)
1208 callout_reset(&sc->wd_callout, hz, mge_tick, sc);
1209 }
1210
1211 static void
mge_intr_rxtx(void * arg)1212 mge_intr_rxtx(void *arg)
1213 {
1214 struct mge_softc *sc;
1215 uint32_t int_cause, int_cause_ext;
1216
1217 sc = arg;
1218 MGE_GLOBAL_LOCK(sc);
1219
1220 #ifdef DEVICE_POLLING
1221 if (if_getcapenable(sc->ifp) & IFCAP_POLLING) {
1222 MGE_GLOBAL_UNLOCK(sc);
1223 return;
1224 }
1225 #endif
1226
1227 /* Get interrupt cause */
1228 int_cause = MGE_READ(sc, MGE_PORT_INT_CAUSE);
1229 int_cause_ext = MGE_READ(sc, MGE_PORT_INT_CAUSE_EXT);
1230
1231 /* Check for Transmit interrupt */
1232 if (int_cause_ext & (MGE_PORT_INT_EXT_TXBUF0 |
1233 MGE_PORT_INT_EXT_TXUR)) {
1234 MGE_WRITE(sc, MGE_PORT_INT_CAUSE_EXT, ~(int_cause_ext &
1235 (MGE_PORT_INT_EXT_TXBUF0 | MGE_PORT_INT_EXT_TXUR)));
1236 mge_intr_tx_locked(sc);
1237 }
1238
1239 MGE_TRANSMIT_UNLOCK(sc);
1240
1241 /* Check for Receive interrupt */
1242 mge_intr_rx_check(sc, int_cause, int_cause_ext);
1243
1244 MGE_RECEIVE_UNLOCK(sc);
1245 }
1246
1247 static void
mge_intr_err(void * arg)1248 mge_intr_err(void *arg)
1249 {
1250 struct mge_softc *sc;
1251 if_t ifp;
1252
1253 sc = arg;
1254 ifp = sc->ifp;
1255 if_printf(ifp, "%s\n", __FUNCTION__);
1256 }
1257
1258 static void
mge_intr_misc(void * arg)1259 mge_intr_misc(void *arg)
1260 {
1261 struct mge_softc *sc;
1262 if_t ifp;
1263
1264 sc = arg;
1265 ifp = sc->ifp;
1266 if_printf(ifp, "%s\n", __FUNCTION__);
1267 }
1268
1269 static void
mge_intr_rx(void * arg)1270 mge_intr_rx(void *arg) {
1271 struct mge_softc *sc;
1272 uint32_t int_cause, int_cause_ext;
1273
1274 sc = arg;
1275 MGE_RECEIVE_LOCK(sc);
1276
1277 #ifdef DEVICE_POLLING
1278 if (if_getcapenable(sc->ifp) & IFCAP_POLLING) {
1279 MGE_RECEIVE_UNLOCK(sc);
1280 return;
1281 }
1282 #endif
1283
1284 /* Get interrupt cause */
1285 int_cause = MGE_READ(sc, MGE_PORT_INT_CAUSE);
1286 int_cause_ext = MGE_READ(sc, MGE_PORT_INT_CAUSE_EXT);
1287
1288 mge_intr_rx_check(sc, int_cause, int_cause_ext);
1289
1290 MGE_RECEIVE_UNLOCK(sc);
1291 }
1292
1293 static void
mge_intr_rx_check(struct mge_softc * sc,uint32_t int_cause,uint32_t int_cause_ext)1294 mge_intr_rx_check(struct mge_softc *sc, uint32_t int_cause,
1295 uint32_t int_cause_ext)
1296 {
1297 /* Check for resource error */
1298 if (int_cause & MGE_PORT_INT_RXERRQ0) {
1299 mge_reinit_rx(sc);
1300 MGE_WRITE(sc, MGE_PORT_INT_CAUSE,
1301 ~(int_cause & MGE_PORT_INT_RXERRQ0));
1302 }
1303
1304 int_cause &= MGE_PORT_INT_RXQ0;
1305 int_cause_ext &= MGE_PORT_INT_EXT_RXOR;
1306
1307 if (int_cause || int_cause_ext) {
1308 MGE_WRITE(sc, MGE_PORT_INT_CAUSE, ~int_cause);
1309 MGE_WRITE(sc, MGE_PORT_INT_CAUSE_EXT, ~int_cause_ext);
1310 mge_intr_rx_locked(sc, -1);
1311 }
1312 }
1313
1314 static int
mge_intr_rx_locked(struct mge_softc * sc,int count)1315 mge_intr_rx_locked(struct mge_softc *sc, int count)
1316 {
1317 if_t ifp = sc->ifp;
1318 uint32_t status;
1319 uint16_t bufsize;
1320 struct mge_desc_wrapper* dw;
1321 struct mbuf *mb;
1322 int rx_npkts = 0;
1323
1324 MGE_RECEIVE_LOCK_ASSERT(sc);
1325
1326 while (count != 0) {
1327 dw = &sc->mge_rx_desc[sc->rx_desc_curr];
1328 bus_dmamap_sync(sc->mge_desc_dtag, dw->desc_dmap,
1329 BUS_DMASYNC_POSTREAD);
1330
1331 /* Get status */
1332 status = dw->mge_desc->cmd_status;
1333 bufsize = dw->mge_desc->buff_size;
1334 if ((status & MGE_DMA_OWNED) != 0)
1335 break;
1336
1337 if (dw->mge_desc->byte_count &&
1338 ~(status & MGE_ERR_SUMMARY)) {
1339
1340 bus_dmamap_sync(sc->mge_rx_dtag, dw->buffer_dmap,
1341 BUS_DMASYNC_POSTREAD);
1342
1343 mb = m_devget(dw->buffer->m_data,
1344 dw->mge_desc->byte_count - ETHER_CRC_LEN,
1345 0, ifp, NULL);
1346
1347 if (mb == NULL)
1348 /* Give up if no mbufs */
1349 break;
1350
1351 mb->m_len -= 2;
1352 mb->m_pkthdr.len -= 2;
1353 mb->m_data += 2;
1354
1355 mb->m_pkthdr.rcvif = ifp;
1356
1357 mge_offload_process_frame(ifp, mb, status,
1358 bufsize);
1359
1360 MGE_RECEIVE_UNLOCK(sc);
1361 if_input(ifp, mb);
1362 MGE_RECEIVE_LOCK(sc);
1363 rx_npkts++;
1364 }
1365
1366 dw->mge_desc->byte_count = 0;
1367 dw->mge_desc->cmd_status = MGE_RX_ENABLE_INT | MGE_DMA_OWNED;
1368 sc->rx_desc_curr = (++sc->rx_desc_curr % MGE_RX_DESC_NUM);
1369 bus_dmamap_sync(sc->mge_desc_dtag, dw->desc_dmap,
1370 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1371
1372 if (count > 0)
1373 count -= 1;
1374 }
1375
1376 if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_npkts);
1377
1378 return (rx_npkts);
1379 }
1380
1381 static void
mge_intr_sum(void * arg)1382 mge_intr_sum(void *arg)
1383 {
1384 struct mge_softc *sc = arg;
1385 if_t ifp;
1386
1387 ifp = sc->ifp;
1388 if_printf(ifp, "%s\n", __FUNCTION__);
1389 }
1390
1391 static void
mge_intr_tx(void * arg)1392 mge_intr_tx(void *arg)
1393 {
1394 struct mge_softc *sc = arg;
1395 uint32_t int_cause_ext;
1396
1397 MGE_TRANSMIT_LOCK(sc);
1398
1399 #ifdef DEVICE_POLLING
1400 if (if_getcapenable(sc->ifp) & IFCAP_POLLING) {
1401 MGE_TRANSMIT_UNLOCK(sc);
1402 return;
1403 }
1404 #endif
1405
1406 /* Ack the interrupt */
1407 int_cause_ext = MGE_READ(sc, MGE_PORT_INT_CAUSE_EXT);
1408 MGE_WRITE(sc, MGE_PORT_INT_CAUSE_EXT, ~(int_cause_ext &
1409 (MGE_PORT_INT_EXT_TXBUF0 | MGE_PORT_INT_EXT_TXUR)));
1410
1411 mge_intr_tx_locked(sc);
1412
1413 MGE_TRANSMIT_UNLOCK(sc);
1414 }
1415
1416 static void
mge_intr_tx_locked(struct mge_softc * sc)1417 mge_intr_tx_locked(struct mge_softc *sc)
1418 {
1419 if_t ifp = sc->ifp;
1420 struct mge_desc_wrapper *dw;
1421 struct mge_desc *desc;
1422 uint32_t status;
1423 int send = 0;
1424
1425 MGE_TRANSMIT_LOCK_ASSERT(sc);
1426
1427 /* Disable watchdog */
1428 sc->wd_timer = 0;
1429
1430 while (sc->tx_desc_used_count) {
1431 /* Get the descriptor */
1432 dw = &sc->mge_tx_desc[sc->tx_desc_used_idx];
1433 desc = dw->mge_desc;
1434 bus_dmamap_sync(sc->mge_desc_dtag, dw->desc_dmap,
1435 BUS_DMASYNC_POSTREAD);
1436
1437 /* Get descriptor status */
1438 status = desc->cmd_status;
1439
1440 if (status & MGE_DMA_OWNED)
1441 break;
1442
1443 sc->tx_desc_used_idx =
1444 (++sc->tx_desc_used_idx) % MGE_TX_DESC_NUM;
1445 sc->tx_desc_used_count--;
1446
1447 /* Update collision statistics */
1448 if (status & MGE_ERR_SUMMARY) {
1449 if ((status & MGE_ERR_MASK) == MGE_TX_ERROR_LC)
1450 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1451 if ((status & MGE_ERR_MASK) == MGE_TX_ERROR_RL)
1452 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 16);
1453 }
1454
1455 bus_dmamap_sync(sc->mge_tx_dtag, dw->buffer_dmap,
1456 BUS_DMASYNC_POSTWRITE);
1457 bus_dmamap_unload(sc->mge_tx_dtag, dw->buffer_dmap);
1458 m_freem(dw->buffer);
1459 dw->buffer = (struct mbuf*)NULL;
1460 send++;
1461
1462 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1463 }
1464
1465 if (send) {
1466 /* Now send anything that was pending */
1467 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1468 mge_start_locked(ifp);
1469 }
1470 }
1471 static int
mge_ioctl(if_t ifp,u_long command,caddr_t data)1472 mge_ioctl(if_t ifp, u_long command, caddr_t data)
1473 {
1474 struct mge_softc *sc = if_getsoftc(ifp);
1475 struct ifreq *ifr = (struct ifreq *)data;
1476 int mask, error;
1477 uint32_t flags;
1478
1479 error = 0;
1480
1481 switch (command) {
1482 case SIOCSIFFLAGS:
1483 MGE_GLOBAL_LOCK(sc);
1484
1485 if (if_getflags(ifp) & IFF_UP) {
1486 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1487 flags = if_getflags(ifp) ^ sc->mge_if_flags;
1488 if (flags & IFF_PROMISC)
1489 mge_set_prom_mode(sc,
1490 MGE_RX_DEFAULT_QUEUE);
1491
1492 if (flags & IFF_ALLMULTI)
1493 mge_setup_multicast(sc);
1494 } else
1495 mge_init_locked(sc);
1496 }
1497 else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1498 mge_stop(sc);
1499
1500 sc->mge_if_flags = if_getflags(ifp);
1501 MGE_GLOBAL_UNLOCK(sc);
1502 break;
1503 case SIOCADDMULTI:
1504 case SIOCDELMULTI:
1505 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1506 MGE_GLOBAL_LOCK(sc);
1507 mge_setup_multicast(sc);
1508 MGE_GLOBAL_UNLOCK(sc);
1509 }
1510 break;
1511 case SIOCSIFCAP:
1512 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
1513 if (mask & IFCAP_HWCSUM) {
1514 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
1515 if_setcapenablebit(ifp, IFCAP_HWCSUM & ifr->ifr_reqcap, 0);
1516 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
1517 if_sethwassist(ifp, MGE_CHECKSUM_FEATURES);
1518 else
1519 if_sethwassist(ifp, 0);
1520 }
1521 #ifdef DEVICE_POLLING
1522 if (mask & IFCAP_POLLING) {
1523 if (ifr->ifr_reqcap & IFCAP_POLLING) {
1524 error = ether_poll_register(mge_poll, ifp);
1525 if (error)
1526 return(error);
1527
1528 MGE_GLOBAL_LOCK(sc);
1529 mge_intrs_ctrl(sc, 0);
1530 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1531 MGE_GLOBAL_UNLOCK(sc);
1532 } else {
1533 error = ether_poll_deregister(ifp);
1534 MGE_GLOBAL_LOCK(sc);
1535 mge_intrs_ctrl(sc, 1);
1536 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1537 MGE_GLOBAL_UNLOCK(sc);
1538 }
1539 }
1540 #endif
1541 break;
1542 case SIOCGIFMEDIA: /* fall through */
1543 case SIOCSIFMEDIA:
1544 /*
1545 * Setting up media type via ioctls is *not* supported for MAC
1546 * which is connected to switch. Use etherswitchcfg.
1547 */
1548 if (!sc->phy_attached && (command == SIOCSIFMEDIA))
1549 return (0);
1550 else if (!sc->phy_attached) {
1551 error = ifmedia_ioctl(ifp, ifr, &sc->mge_ifmedia,
1552 command);
1553 break;
1554 }
1555
1556 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T
1557 && !(ifr->ifr_media & IFM_FDX)) {
1558 device_printf(sc->dev,
1559 "1000baseTX half-duplex unsupported\n");
1560 return 0;
1561 }
1562 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, command);
1563 break;
1564 default:
1565 error = ether_ioctl(ifp, command, data);
1566 }
1567 return (error);
1568 }
1569
1570 static int
mge_miibus_readreg(device_t dev,int phy,int reg)1571 mge_miibus_readreg(device_t dev, int phy, int reg)
1572 {
1573
1574 KASSERT(!switch_attached, ("miibus used with switch attached"));
1575
1576 return (mv_read_ext_phy(dev, phy, reg));
1577 }
1578
1579 static int
mge_miibus_writereg(device_t dev,int phy,int reg,int value)1580 mge_miibus_writereg(device_t dev, int phy, int reg, int value)
1581 {
1582
1583 KASSERT(!switch_attached, ("miibus used with switch attached"));
1584
1585 mv_write_ext_phy(dev, phy, reg, value);
1586
1587 return (0);
1588 }
1589
1590 static int
mge_probe(device_t dev)1591 mge_probe(device_t dev)
1592 {
1593
1594 if (!ofw_bus_status_okay(dev))
1595 return (ENXIO);
1596
1597 if (!ofw_bus_is_compatible(dev, "mrvl,ge"))
1598 return (ENXIO);
1599
1600 device_set_desc(dev, "Marvell Gigabit Ethernet controller");
1601 return (BUS_PROBE_DEFAULT);
1602 }
1603
1604 static int
mge_resume(device_t dev)1605 mge_resume(device_t dev)
1606 {
1607
1608 device_printf(dev, "%s\n", __FUNCTION__);
1609 return (0);
1610 }
1611
1612 static int
mge_shutdown(device_t dev)1613 mge_shutdown(device_t dev)
1614 {
1615 struct mge_softc *sc = device_get_softc(dev);
1616
1617 MGE_GLOBAL_LOCK(sc);
1618
1619 #ifdef DEVICE_POLLING
1620 if (if_getcapenable(sc->ifp) & IFCAP_POLLING)
1621 ether_poll_deregister(sc->ifp);
1622 #endif
1623
1624 mge_stop(sc);
1625
1626 MGE_GLOBAL_UNLOCK(sc);
1627
1628 return (0);
1629 }
1630
1631 static int
mge_encap(struct mge_softc * sc,struct mbuf * m0)1632 mge_encap(struct mge_softc *sc, struct mbuf *m0)
1633 {
1634 struct mge_desc_wrapper *dw = NULL;
1635 bus_dma_segment_t segs[MGE_TX_DESC_NUM];
1636 bus_dmamap_t mapp;
1637 int error;
1638 int seg, nsegs;
1639 int desc_no;
1640
1641 /* Fetch unused map */
1642 desc_no = sc->tx_desc_curr;
1643 dw = &sc->mge_tx_desc[desc_no];
1644 mapp = dw->buffer_dmap;
1645
1646 /* Create mapping in DMA memory */
1647 error = bus_dmamap_load_mbuf_sg(sc->mge_tx_dtag, mapp, m0, segs, &nsegs,
1648 BUS_DMA_NOWAIT);
1649 if (error != 0) {
1650 m_freem(m0);
1651 return (error);
1652 }
1653
1654 /* Only one segment is supported. */
1655 if (nsegs != 1) {
1656 bus_dmamap_unload(sc->mge_tx_dtag, mapp);
1657 m_freem(m0);
1658 return (-1);
1659 }
1660
1661 bus_dmamap_sync(sc->mge_tx_dtag, mapp, BUS_DMASYNC_PREWRITE);
1662
1663 /* Everything is ok, now we can send buffers */
1664 for (seg = 0; seg < nsegs; seg++) {
1665 dw->mge_desc->byte_count = segs[seg].ds_len;
1666 dw->mge_desc->buffer = segs[seg].ds_addr;
1667 dw->buffer = m0;
1668 dw->mge_desc->cmd_status = 0;
1669 if (seg == 0)
1670 mge_offload_setup_descriptor(sc, dw);
1671 dw->mge_desc->cmd_status |= MGE_TX_LAST | MGE_TX_FIRST |
1672 MGE_TX_ETH_CRC | MGE_TX_EN_INT | MGE_TX_PADDING |
1673 MGE_DMA_OWNED;
1674 }
1675
1676 bus_dmamap_sync(sc->mge_desc_dtag, dw->desc_dmap,
1677 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1678
1679 sc->tx_desc_curr = (++sc->tx_desc_curr) % MGE_TX_DESC_NUM;
1680 sc->tx_desc_used_count++;
1681 return (0);
1682 }
1683
1684 static void
mge_tick(void * msc)1685 mge_tick(void *msc)
1686 {
1687 struct mge_softc *sc = msc;
1688
1689 KASSERT(sc->phy_attached == 1, ("mge_tick while PHY not attached"));
1690
1691 MGE_GLOBAL_LOCK(sc);
1692
1693 /* Check for TX timeout */
1694 mge_watchdog(sc);
1695
1696 mii_tick(sc->mii);
1697
1698 /* Check for media type change */
1699 if(sc->mge_media_status != sc->mii->mii_media.ifm_media)
1700 mge_ifmedia_upd(sc->ifp);
1701
1702 MGE_GLOBAL_UNLOCK(sc);
1703
1704 /* Schedule another timeout one second from now */
1705 callout_reset(&sc->wd_callout, hz, mge_tick, sc);
1706
1707 return;
1708 }
1709
1710 static void
mge_watchdog(struct mge_softc * sc)1711 mge_watchdog(struct mge_softc *sc)
1712 {
1713 if_t ifp;
1714
1715 ifp = sc->ifp;
1716
1717 if (sc->wd_timer == 0 || --sc->wd_timer) {
1718 return;
1719 }
1720
1721 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1722 if_printf(ifp, "watchdog timeout\n");
1723
1724 mge_stop(sc);
1725 mge_init_locked(sc);
1726 }
1727
1728 static void
mge_start(if_t ifp)1729 mge_start(if_t ifp)
1730 {
1731 struct mge_softc *sc = if_getsoftc(ifp);
1732
1733 MGE_TRANSMIT_LOCK(sc);
1734
1735 mge_start_locked(ifp);
1736
1737 MGE_TRANSMIT_UNLOCK(sc);
1738 }
1739
1740 static void
mge_start_locked(if_t ifp)1741 mge_start_locked(if_t ifp)
1742 {
1743 struct mge_softc *sc;
1744 struct mbuf *m0, *mtmp;
1745 uint32_t reg_val, queued = 0;
1746
1747 sc = if_getsoftc(ifp);
1748
1749 MGE_TRANSMIT_LOCK_ASSERT(sc);
1750
1751 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1752 IFF_DRV_RUNNING)
1753 return;
1754
1755 for (;;) {
1756 /* Get packet from the queue */
1757 m0 = if_dequeue(ifp);
1758 if (m0 == NULL)
1759 break;
1760
1761 if (m0->m_pkthdr.csum_flags & (CSUM_IP|CSUM_TCP|CSUM_UDP) ||
1762 m0->m_flags & M_VLANTAG) {
1763 if (M_WRITABLE(m0) == 0) {
1764 mtmp = m_dup(m0, M_NOWAIT);
1765 m_freem(m0);
1766 if (mtmp == NULL)
1767 continue;
1768 m0 = mtmp;
1769 }
1770 }
1771 /* The driver support only one DMA fragment. */
1772 if (m0->m_next != NULL) {
1773 mtmp = m_defrag(m0, M_NOWAIT);
1774 if (mtmp != NULL)
1775 m0 = mtmp;
1776 }
1777
1778 /* Check for free descriptors */
1779 if (sc->tx_desc_used_count + 1 >= MGE_TX_DESC_NUM) {
1780 if_sendq_prepend(ifp, m0);
1781 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1782 break;
1783 }
1784
1785 if (mge_encap(sc, m0) != 0)
1786 break;
1787
1788 queued++;
1789 BPF_MTAP(ifp, m0);
1790 }
1791
1792 if (queued) {
1793 /* Enable transmitter and watchdog timer */
1794 reg_val = MGE_READ(sc, MGE_TX_QUEUE_CMD);
1795 MGE_WRITE(sc, MGE_TX_QUEUE_CMD, reg_val | MGE_ENABLE_TXQ);
1796 sc->wd_timer = 5;
1797 }
1798 }
1799
1800 static void
mge_stop(struct mge_softc * sc)1801 mge_stop(struct mge_softc *sc)
1802 {
1803 if_t ifp;
1804 volatile uint32_t reg_val, status;
1805 struct mge_desc_wrapper *dw;
1806 struct mge_desc *desc;
1807 int count;
1808
1809 ifp = sc->ifp;
1810
1811 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1812 return;
1813
1814 /* Stop tick engine */
1815 callout_stop(&sc->wd_callout);
1816
1817 /* Disable interface */
1818 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1819 sc->wd_timer = 0;
1820
1821 /* Disable interrupts */
1822 mge_intrs_ctrl(sc, 0);
1823
1824 /* Disable Rx and Tx */
1825 reg_val = MGE_READ(sc, MGE_TX_QUEUE_CMD);
1826 MGE_WRITE(sc, MGE_TX_QUEUE_CMD, reg_val | MGE_DISABLE_TXQ);
1827 MGE_WRITE(sc, MGE_RX_QUEUE_CMD, MGE_DISABLE_RXQ_ALL);
1828
1829 /* Remove pending data from TX queue */
1830 while (sc->tx_desc_used_idx != sc->tx_desc_curr &&
1831 sc->tx_desc_used_count) {
1832 /* Get the descriptor */
1833 dw = &sc->mge_tx_desc[sc->tx_desc_used_idx];
1834 desc = dw->mge_desc;
1835 bus_dmamap_sync(sc->mge_desc_dtag, dw->desc_dmap,
1836 BUS_DMASYNC_POSTREAD);
1837
1838 /* Get descriptor status */
1839 status = desc->cmd_status;
1840
1841 if (status & MGE_DMA_OWNED)
1842 break;
1843
1844 sc->tx_desc_used_idx = (++sc->tx_desc_used_idx) %
1845 MGE_TX_DESC_NUM;
1846 sc->tx_desc_used_count--;
1847
1848 bus_dmamap_sync(sc->mge_tx_dtag, dw->buffer_dmap,
1849 BUS_DMASYNC_POSTWRITE);
1850 bus_dmamap_unload(sc->mge_tx_dtag, dw->buffer_dmap);
1851
1852 m_freem(dw->buffer);
1853 dw->buffer = (struct mbuf*)NULL;
1854 }
1855
1856 /* Wait for end of transmission */
1857 count = 0x100000;
1858 while (count--) {
1859 reg_val = MGE_READ(sc, MGE_PORT_STATUS);
1860 if ( !(reg_val & MGE_STATUS_TX_IN_PROG) &&
1861 (reg_val & MGE_STATUS_TX_FIFO_EMPTY))
1862 break;
1863 DELAY(100);
1864 }
1865
1866 if (count == 0)
1867 if_printf(ifp,
1868 "%s: timeout while waiting for end of transmission\n",
1869 __FUNCTION__);
1870
1871 reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
1872 reg_val &= ~(PORT_SERIAL_ENABLE);
1873 MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL ,reg_val);
1874 }
1875
1876 static int
mge_suspend(device_t dev)1877 mge_suspend(device_t dev)
1878 {
1879
1880 device_printf(dev, "%s\n", __FUNCTION__);
1881 return (0);
1882 }
1883
1884 static void
mge_offload_process_frame(if_t ifp,struct mbuf * frame,uint32_t status,uint16_t bufsize)1885 mge_offload_process_frame(if_t ifp, struct mbuf *frame,
1886 uint32_t status, uint16_t bufsize)
1887 {
1888 int csum_flags = 0;
1889
1890 if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
1891 if ((status & MGE_RX_L3_IS_IP) && (status & MGE_RX_IP_OK))
1892 csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
1893
1894 if ((bufsize & MGE_RX_IP_FRAGMENT) == 0 &&
1895 (MGE_RX_L4_IS_TCP(status) || MGE_RX_L4_IS_UDP(status)) &&
1896 (status & MGE_RX_L4_CSUM_OK)) {
1897 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1898 frame->m_pkthdr.csum_data = 0xFFFF;
1899 }
1900
1901 frame->m_pkthdr.csum_flags = csum_flags;
1902 }
1903 }
1904
1905 static void
mge_offload_setup_descriptor(struct mge_softc * sc,struct mge_desc_wrapper * dw)1906 mge_offload_setup_descriptor(struct mge_softc *sc, struct mge_desc_wrapper *dw)
1907 {
1908 struct mbuf *m0 = dw->buffer;
1909 struct ether_vlan_header *eh = mtod(m0, struct ether_vlan_header *);
1910 int csum_flags = m0->m_pkthdr.csum_flags;
1911 int cmd_status = 0;
1912 struct ip *ip;
1913 int ehlen, etype;
1914
1915 if (csum_flags != 0) {
1916 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1917 etype = ntohs(eh->evl_proto);
1918 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1919 csum_flags |= MGE_TX_VLAN_TAGGED;
1920 } else {
1921 etype = ntohs(eh->evl_encap_proto);
1922 ehlen = ETHER_HDR_LEN;
1923 }
1924
1925 if (etype != ETHERTYPE_IP) {
1926 if_printf(sc->ifp,
1927 "TCP/IP Offload enabled for unsupported "
1928 "protocol!\n");
1929 return;
1930 }
1931
1932 ip = (struct ip *)(m0->m_data + ehlen);
1933 cmd_status |= MGE_TX_IP_HDR_SIZE(ip->ip_hl);
1934 cmd_status |= MGE_TX_NOT_FRAGMENT;
1935 }
1936
1937 if (csum_flags & CSUM_IP)
1938 cmd_status |= MGE_TX_GEN_IP_CSUM;
1939
1940 if (csum_flags & CSUM_TCP)
1941 cmd_status |= MGE_TX_GEN_L4_CSUM;
1942
1943 if (csum_flags & CSUM_UDP)
1944 cmd_status |= MGE_TX_GEN_L4_CSUM | MGE_TX_UDP;
1945
1946 dw->mge_desc->cmd_status |= cmd_status;
1947 }
1948
1949 static void
mge_intrs_ctrl(struct mge_softc * sc,int enable)1950 mge_intrs_ctrl(struct mge_softc *sc, int enable)
1951 {
1952
1953 if (enable) {
1954 MGE_WRITE(sc, MGE_PORT_INT_MASK , MGE_PORT_INT_RXQ0 |
1955 MGE_PORT_INT_EXTEND | MGE_PORT_INT_RXERRQ0);
1956 MGE_WRITE(sc, MGE_PORT_INT_MASK_EXT , MGE_PORT_INT_EXT_TXERR0 |
1957 MGE_PORT_INT_EXT_RXOR | MGE_PORT_INT_EXT_TXUR |
1958 MGE_PORT_INT_EXT_TXBUF0);
1959 } else {
1960 MGE_WRITE(sc, MGE_INT_CAUSE, 0x0);
1961 MGE_WRITE(sc, MGE_INT_MASK, 0x0);
1962
1963 MGE_WRITE(sc, MGE_PORT_INT_CAUSE, 0x0);
1964 MGE_WRITE(sc, MGE_PORT_INT_CAUSE_EXT, 0x0);
1965
1966 MGE_WRITE(sc, MGE_PORT_INT_MASK, 0x0);
1967 MGE_WRITE(sc, MGE_PORT_INT_MASK_EXT, 0x0);
1968 }
1969 }
1970
1971 static uint8_t
mge_crc8(uint8_t * data,int size)1972 mge_crc8(uint8_t *data, int size)
1973 {
1974 uint8_t crc = 0;
1975 static const uint8_t ct[256] = {
1976 0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15,
1977 0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D,
1978 0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65,
1979 0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D,
1980 0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5,
1981 0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD,
1982 0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85,
1983 0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD,
1984 0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2,
1985 0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA,
1986 0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2,
1987 0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A,
1988 0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32,
1989 0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A,
1990 0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42,
1991 0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A,
1992 0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C,
1993 0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4,
1994 0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC,
1995 0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4,
1996 0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C,
1997 0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44,
1998 0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C,
1999 0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34,
2000 0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B,
2001 0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63,
2002 0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B,
2003 0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13,
2004 0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB,
2005 0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83,
2006 0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB,
2007 0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3
2008 };
2009
2010 while(size--)
2011 crc = ct[crc ^ *(data++)];
2012
2013 return(crc);
2014 }
2015
2016 struct mge_hash_maddr_ctx {
2017 uint32_t smt[MGE_MCAST_REG_NUMBER];
2018 uint32_t omt[MGE_MCAST_REG_NUMBER];
2019 };
2020
2021 static u_int
mge_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)2022 mge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2023 {
2024 static const uint8_t special[5] = { 0x01, 0x00, 0x5E, 0x00, 0x00 };
2025 struct mge_hash_maddr_ctx *ctx = arg;
2026 static const uint8_t v = (MGE_RX_DEFAULT_QUEUE << 1) | 1;
2027 uint8_t *mac;
2028 int i;
2029
2030 mac = LLADDR(sdl);
2031 if (memcmp(mac, special, sizeof(special)) == 0) {
2032 i = mac[5];
2033 ctx->smt[i >> 2] |= v << ((i & 0x03) << 3);
2034 } else {
2035 i = mge_crc8(mac, ETHER_ADDR_LEN);
2036 ctx->omt[i >> 2] |= v << ((i & 0x03) << 3);
2037 }
2038 return (1);
2039 }
2040
2041 static void
mge_setup_multicast(struct mge_softc * sc)2042 mge_setup_multicast(struct mge_softc *sc)
2043 {
2044 struct mge_hash_maddr_ctx ctx;
2045 if_t ifp = sc->ifp;
2046 static const uint8_t v = (MGE_RX_DEFAULT_QUEUE << 1) | 1;
2047 int i;
2048
2049 if (if_getflags(ifp) & IFF_ALLMULTI) {
2050 for (i = 0; i < MGE_MCAST_REG_NUMBER; i++)
2051 ctx.smt[i] = ctx.omt[i] =
2052 (v << 24) | (v << 16) | (v << 8) | v;
2053 } else {
2054 memset(&ctx, 0, sizeof(ctx));
2055 if_foreach_llmaddr(ifp, mge_hash_maddr, &ctx);
2056 }
2057
2058 for (i = 0; i < MGE_MCAST_REG_NUMBER; i++) {
2059 MGE_WRITE(sc, MGE_DA_FILTER_SPEC_MCAST(i), ctx.smt[i]);
2060 MGE_WRITE(sc, MGE_DA_FILTER_OTH_MCAST(i), ctx.omt[i]);
2061 }
2062 }
2063
2064 static void
mge_set_rxic(struct mge_softc * sc)2065 mge_set_rxic(struct mge_softc *sc)
2066 {
2067 uint32_t reg;
2068
2069 if (sc->rx_ic_time > sc->mge_rx_ipg_max)
2070 sc->rx_ic_time = sc->mge_rx_ipg_max;
2071
2072 reg = MGE_READ(sc, MGE_SDMA_CONFIG);
2073 reg &= ~mge_rx_ipg(sc->mge_rx_ipg_max, sc->mge_ver);
2074 reg |= mge_rx_ipg(sc->rx_ic_time, sc->mge_ver);
2075 MGE_WRITE(sc, MGE_SDMA_CONFIG, reg);
2076 }
2077
2078 static void
mge_set_txic(struct mge_softc * sc)2079 mge_set_txic(struct mge_softc *sc)
2080 {
2081 uint32_t reg;
2082
2083 if (sc->tx_ic_time > sc->mge_tfut_ipg_max)
2084 sc->tx_ic_time = sc->mge_tfut_ipg_max;
2085
2086 reg = MGE_READ(sc, MGE_TX_FIFO_URGENT_TRSH);
2087 reg &= ~mge_tfut_ipg(sc->mge_tfut_ipg_max, sc->mge_ver);
2088 reg |= mge_tfut_ipg(sc->tx_ic_time, sc->mge_ver);
2089 MGE_WRITE(sc, MGE_TX_FIFO_URGENT_TRSH, reg);
2090 }
2091
2092 static int
mge_sysctl_ic(SYSCTL_HANDLER_ARGS)2093 mge_sysctl_ic(SYSCTL_HANDLER_ARGS)
2094 {
2095 struct mge_softc *sc = (struct mge_softc *)arg1;
2096 uint32_t time;
2097 int error;
2098
2099 time = (arg2 == MGE_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
2100 error = sysctl_handle_int(oidp, &time, 0, req);
2101 if (error != 0)
2102 return(error);
2103
2104 MGE_GLOBAL_LOCK(sc);
2105 if (arg2 == MGE_IC_RX) {
2106 sc->rx_ic_time = time;
2107 mge_set_rxic(sc);
2108 } else {
2109 sc->tx_ic_time = time;
2110 mge_set_txic(sc);
2111 }
2112 MGE_GLOBAL_UNLOCK(sc);
2113
2114 return(0);
2115 }
2116
2117 static void
mge_add_sysctls(struct mge_softc * sc)2118 mge_add_sysctls(struct mge_softc *sc)
2119 {
2120 struct sysctl_ctx_list *ctx;
2121 struct sysctl_oid_list *children;
2122 struct sysctl_oid *tree;
2123
2124 ctx = device_get_sysctl_ctx(sc->dev);
2125 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
2126 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
2127 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "MGE Interrupts coalescing");
2128 children = SYSCTL_CHILDREN(tree);
2129
2130 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
2131 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, MGE_IC_RX,
2132 mge_sysctl_ic, "I", "IC RX time threshold");
2133 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
2134 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, MGE_IC_TX,
2135 mge_sysctl_ic, "I", "IC TX time threshold");
2136 }
2137
2138 static int
mge_mdio_writereg(device_t dev,int phy,int reg,int value)2139 mge_mdio_writereg(device_t dev, int phy, int reg, int value)
2140 {
2141
2142 mv_write_ge_smi(dev, phy, reg, value);
2143
2144 return (0);
2145 }
2146
2147
2148 static int
mge_mdio_readreg(device_t dev,int phy,int reg)2149 mge_mdio_readreg(device_t dev, int phy, int reg)
2150 {
2151 int ret;
2152
2153 ret = mv_read_ge_smi(dev, phy, reg);
2154
2155 return (ret);
2156 }
2157