1&l4_cfg { /* 0x4a000000 */ 2 compatible = "ti,dra7-l4-cfg", "simple-bus"; 3 reg = <0x4a000000 0x800>, 4 <0x4a000800 0x800>, 5 <0x4a001000 0x1000>; 6 reg-names = "ap", "la", "ia0"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ 10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */ 11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */ 12 13 segment@0 { /* 0x4a000000 */ 14 compatible = "simple-bus"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 18 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 19 <0x00001000 0x00001000 0x001000>, /* ap 2 */ 20 <0x00002000 0x00002000 0x002000>, /* ap 3 */ 21 <0x00004000 0x00004000 0x001000>, /* ap 4 */ 22 <0x00005000 0x00005000 0x001000>, /* ap 5 */ 23 <0x00006000 0x00006000 0x001000>, /* ap 6 */ 24 <0x00008000 0x00008000 0x002000>, /* ap 7 */ 25 <0x0000a000 0x0000a000 0x001000>, /* ap 8 */ 26 <0x00056000 0x00056000 0x001000>, /* ap 9 */ 27 <0x00057000 0x00057000 0x001000>, /* ap 10 */ 28 <0x0005e000 0x0005e000 0x002000>, /* ap 11 */ 29 <0x00060000 0x00060000 0x001000>, /* ap 12 */ 30 <0x00080000 0x00080000 0x008000>, /* ap 13 */ 31 <0x00088000 0x00088000 0x001000>, /* ap 14 */ 32 <0x000a0000 0x000a0000 0x008000>, /* ap 15 */ 33 <0x000a8000 0x000a8000 0x001000>, /* ap 16 */ 34 <0x000d9000 0x000d9000 0x001000>, /* ap 17 */ 35 <0x000da000 0x000da000 0x001000>, /* ap 18 */ 36 <0x000dd000 0x000dd000 0x001000>, /* ap 19 */ 37 <0x000de000 0x000de000 0x001000>, /* ap 20 */ 38 <0x000e0000 0x000e0000 0x001000>, /* ap 21 */ 39 <0x000e1000 0x000e1000 0x001000>, /* ap 22 */ 40 <0x000f4000 0x000f4000 0x001000>, /* ap 23 */ 41 <0x000f5000 0x000f5000 0x001000>, /* ap 24 */ 42 <0x000f6000 0x000f6000 0x001000>, /* ap 25 */ 43 <0x000f7000 0x000f7000 0x001000>, /* ap 26 */ 44 <0x00090000 0x00090000 0x008000>, /* ap 59 */ 45 <0x00098000 0x00098000 0x001000>; /* ap 60 */ 46 47 target-module@2000 { /* 0x4a002000, ap 3 08.0 */ 48 compatible = "ti,sysc-omap4", "ti,sysc"; 49 reg = <0x2000 0x4>; 50 reg-names = "rev"; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 ranges = <0x0 0x2000 0x2000>; 54 55 scm: scm@0 { 56 compatible = "ti,dra7-scm-core", "simple-bus"; 57 reg = <0 0x2000>; 58 #address-cells = <1>; 59 #size-cells = <1>; 60 ranges = <0 0 0x2000>; 61 62 scm_conf: scm_conf@0 { 63 compatible = "syscon", "simple-bus"; 64 reg = <0x0 0x1400>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 ranges = <0 0x0 0x1400>; 68 69 pbias_regulator: pbias_regulator@e00 { 70 compatible = "ti,pbias-dra7", "ti,pbias-omap"; 71 reg = <0xe00 0x4>; 72 syscon = <&scm_conf>; 73 pbias_mmc_reg: pbias_mmc_omap5 { 74 regulator-name = "pbias_mmc_omap5"; 75 regulator-min-microvolt = <1800000>; 76 regulator-max-microvolt = <3300000>; 77 }; 78 }; 79 80 phy_gmii_sel: phy-gmii-sel { 81 compatible = "ti,dra7xx-phy-gmii-sel"; 82 reg = <0x554 0x4>; 83 #phy-cells = <1>; 84 }; 85 86 scm_conf_clocks: clocks { 87 #address-cells = <1>; 88 #size-cells = <0>; 89 }; 90 }; 91 92 dra7_pmx_core: pinmux@1400 { 93 compatible = "ti,dra7-padconf", 94 "pinctrl-single"; 95 reg = <0x1400 0x0468>; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 #pinctrl-cells = <1>; 99 #interrupt-cells = <1>; 100 interrupt-controller; 101 pinctrl-single,register-width = <32>; 102 pinctrl-single,function-mask = <0x3fffffff>; 103 }; 104 105 scm_conf1: scm_conf@1c04 { 106 compatible = "syscon"; 107 reg = <0x1c04 0x0020>; 108 #syscon-cells = <2>; 109 }; 110 111 scm_conf_pcie: scm_conf@1c24 { 112 compatible = "syscon"; 113 reg = <0x1c24 0x0024>; 114 }; 115 116 sdma_xbar: dma-router@b78 { 117 compatible = "ti,dra7-dma-crossbar"; 118 reg = <0xb78 0xfc>; 119 #dma-cells = <1>; 120 dma-requests = <205>; 121 ti,dma-safe-map = <0>; 122 dma-masters = <&sdma>; 123 }; 124 125 edma_xbar: dma-router@c78 { 126 compatible = "ti,dra7-dma-crossbar"; 127 reg = <0xc78 0x7c>; 128 #dma-cells = <2>; 129 dma-requests = <204>; 130 ti,dma-safe-map = <0>; 131 dma-masters = <&edma>; 132 }; 133 }; 134 }; 135 136 target-module@5000 { /* 0x4a005000, ap 5 10.0 */ 137 compatible = "ti,sysc-omap4", "ti,sysc"; 138 reg = <0x5000 0x4>; 139 reg-names = "rev"; 140 #address-cells = <1>; 141 #size-cells = <1>; 142 ranges = <0x0 0x5000 0x1000>; 143 144 cm_core_aon: cm_core_aon@0 { 145 compatible = "ti,dra7-cm-core-aon", 146 "simple-bus"; 147 #address-cells = <1>; 148 #size-cells = <1>; 149 reg = <0 0x2000>; 150 ranges = <0 0 0x2000>; 151 152 cm_core_aon_clocks: clocks { 153 #address-cells = <1>; 154 #size-cells = <0>; 155 }; 156 157 cm_core_aon_clockdomains: clockdomains { 158 }; 159 }; 160 }; 161 162 target-module@8000 { /* 0x4a008000, ap 7 0e.0 */ 163 compatible = "ti,sysc-omap4", "ti,sysc"; 164 reg = <0x8000 0x4>; 165 reg-names = "rev"; 166 #address-cells = <1>; 167 #size-cells = <1>; 168 ranges = <0x0 0x8000 0x2000>; 169 170 cm_core: cm_core@0 { 171 compatible = "ti,dra7-cm-core", "simple-bus"; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 reg = <0 0x3000>; 175 ranges = <0 0 0x3000>; 176 177 cm_core_clocks: clocks { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 }; 181 182 cm_core_clockdomains: clockdomains { 183 }; 184 }; 185 }; 186 187 target-module@56000 { /* 0x4a056000, ap 9 02.0 */ 188 compatible = "ti,sysc-omap2", "ti,sysc"; 189 ti,hwmods = "dma_system"; 190 reg = <0x56000 0x4>, 191 <0x5602c 0x4>, 192 <0x56028 0x4>; 193 reg-names = "rev", "sysc", "syss"; 194 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 195 SYSC_OMAP2_EMUFREE | 196 SYSC_OMAP2_SOFTRESET | 197 SYSC_OMAP2_AUTOIDLE)>; 198 ti,sysc-midle = <SYSC_IDLE_FORCE>, 199 <SYSC_IDLE_NO>, 200 <SYSC_IDLE_SMART>, 201 <SYSC_IDLE_SMART_WKUP>; 202 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 203 <SYSC_IDLE_NO>, 204 <SYSC_IDLE_SMART>, 205 <SYSC_IDLE_SMART_WKUP>; 206 ti,syss-mask = <1>; 207 /* Domains (P, C): core_pwrdm, dma_clkdm */ 208 clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>; 209 clock-names = "fck"; 210 #address-cells = <1>; 211 #size-cells = <1>; 212 ranges = <0x0 0x56000 0x1000>; 213 214 sdma: dma-controller@0 { 215 compatible = "ti,omap4430-sdma"; 216 reg = <0x0 0x1000>; 217 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 221 #dma-cells = <1>; 222 dma-channels = <32>; 223 dma-requests = <127>; 224 }; 225 }; 226 227 target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */ 228 compatible = "ti,sysc"; 229 status = "disabled"; 230 #address-cells = <1>; 231 #size-cells = <1>; 232 ranges = <0x0 0x5e000 0x2000>; 233 }; 234 235 target-module@80000 { /* 0x4a080000, ap 13 20.0 */ 236 compatible = "ti,sysc-omap2", "ti,sysc"; 237 ti,hwmods = "ocp2scp1"; 238 reg = <0x80000 0x4>, 239 <0x80010 0x4>, 240 <0x80014 0x4>; 241 reg-names = "rev", "sysc", "syss"; 242 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 243 SYSC_OMAP2_AUTOIDLE)>; 244 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 245 <SYSC_IDLE_NO>, 246 <SYSC_IDLE_SMART>; 247 ti,syss-mask = <1>; 248 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 249 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>; 250 clock-names = "fck"; 251 #address-cells = <1>; 252 #size-cells = <1>; 253 ranges = <0x0 0x80000 0x8000>; 254 255 ocp2scp@0 { 256 compatible = "ti,omap-ocp2scp"; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 ranges = <0 0 0x8000>; 260 reg = <0x0 0x20>; 261 262 usb2_phy1: phy@4000 { 263 compatible = "ti,dra7x-usb2", "ti,omap-usb2"; 264 reg = <0x4000 0x400>; 265 syscon-phy-power = <&scm_conf 0x300>; 266 clocks = <&usb_phy1_always_on_clk32k>, 267 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; 268 clock-names = "wkupclk", 269 "refclk"; 270 #phy-cells = <0>; 271 }; 272 273 usb2_phy2: phy@5000 { 274 compatible = "ti,dra7x-usb2-phy2", 275 "ti,omap-usb2"; 276 reg = <0x5000 0x400>; 277 syscon-phy-power = <&scm_conf 0xe74>; 278 clocks = <&usb_phy2_always_on_clk32k>, 279 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; 280 clock-names = "wkupclk", 281 "refclk"; 282 #phy-cells = <0>; 283 }; 284 285 usb3_phy1: phy@4400 { 286 compatible = "ti,omap-usb3"; 287 reg = <0x4400 0x80>, 288 <0x4800 0x64>, 289 <0x4c00 0x40>; 290 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 291 syscon-phy-power = <&scm_conf 0x370>; 292 clocks = <&usb_phy3_always_on_clk32k>, 293 <&sys_clkin1>, 294 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; 295 clock-names = "wkupclk", 296 "sysclk", 297 "refclk"; 298 #phy-cells = <0>; 299 }; 300 }; 301 }; 302 303 target-module@90000 { /* 0x4a090000, ap 59 42.0 */ 304 compatible = "ti,sysc-omap2", "ti,sysc"; 305 ti,hwmods = "ocp2scp3"; 306 reg = <0x90000 0x4>, 307 <0x90010 0x4>, 308 <0x90014 0x4>; 309 reg-names = "rev", "sysc", "syss"; 310 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 311 SYSC_OMAP2_AUTOIDLE)>; 312 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 313 <SYSC_IDLE_NO>, 314 <SYSC_IDLE_SMART>; 315 ti,syss-mask = <1>; 316 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 317 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>; 318 clock-names = "fck"; 319 #address-cells = <1>; 320 #size-cells = <1>; 321 ranges = <0x0 0x90000 0x8000>; 322 323 ocp2scp@0 { 324 compatible = "ti,omap-ocp2scp"; 325 #address-cells = <1>; 326 #size-cells = <1>; 327 ranges = <0 0 0x8000>; 328 reg = <0x0 0x20>; 329 330 pcie1_phy: pciephy@4000 { 331 compatible = "ti,phy-pipe3-pcie"; 332 reg = <0x4000 0x80>, /* phy_rx */ 333 <0x4400 0x64>; /* phy_tx */ 334 reg-names = "phy_rx", "phy_tx"; 335 syscon-phy-power = <&scm_conf_pcie 0x1c>; 336 syscon-pcs = <&scm_conf_pcie 0x10>; 337 clocks = <&dpll_pcie_ref_ck>, 338 <&dpll_pcie_ref_m2ldo_ck>, 339 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, 340 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, 341 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, 342 <&optfclk_pciephy_div>, 343 <&sys_clkin1>; 344 clock-names = "dpll_ref", "dpll_ref_m2", 345 "wkupclk", "refclk", 346 "div-clk", "phy-div", "sysclk"; 347 #phy-cells = <0>; 348 }; 349 350 pcie2_phy: pciephy@5000 { 351 compatible = "ti,phy-pipe3-pcie"; 352 reg = <0x5000 0x80>, /* phy_rx */ 353 <0x5400 0x64>; /* phy_tx */ 354 reg-names = "phy_rx", "phy_tx"; 355 syscon-phy-power = <&scm_conf_pcie 0x20>; 356 syscon-pcs = <&scm_conf_pcie 0x10>; 357 clocks = <&dpll_pcie_ref_ck>, 358 <&dpll_pcie_ref_m2ldo_ck>, 359 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, 360 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, 361 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, 362 <&optfclk_pciephy_div>, 363 <&sys_clkin1>; 364 clock-names = "dpll_ref", "dpll_ref_m2", 365 "wkupclk", "refclk", 366 "div-clk", "phy-div", "sysclk"; 367 #phy-cells = <0>; 368 status = "disabled"; 369 }; 370 371 sata_phy: phy@6000 { 372 compatible = "ti,phy-pipe3-sata"; 373 reg = <0x6000 0x80>, /* phy_rx */ 374 <0x6400 0x64>, /* phy_tx */ 375 <0x6800 0x40>; /* pll_ctrl */ 376 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 377 syscon-phy-power = <&scm_conf 0x374>; 378 clocks = <&sys_clkin1>, 379 <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; 380 clock-names = "sysclk", "refclk"; 381 syscon-pllreset = <&scm_conf 0x3fc>; 382 #phy-cells = <0>; 383 }; 384 }; 385 }; 386 387 target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */ 388 compatible = "ti,sysc"; 389 status = "disabled"; 390 #address-cells = <1>; 391 #size-cells = <1>; 392 ranges = <0x0 0xa0000 0x8000>; 393 }; 394 395 target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */ 396 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 397 ti,hwmods = "smartreflex_mpu"; 398 reg = <0xd9038 0x4>; 399 reg-names = "sysc"; 400 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 401 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 402 <SYSC_IDLE_NO>, 403 <SYSC_IDLE_SMART>, 404 <SYSC_IDLE_SMART_WKUP>; 405 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ 406 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; 407 clock-names = "fck"; 408 #address-cells = <1>; 409 #size-cells = <1>; 410 ranges = <0x0 0xd9000 0x1000>; 411 412 /* SmartReflex child device marked reserved in TRM */ 413 }; 414 415 target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */ 416 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 417 ti,hwmods = "smartreflex_core"; 418 reg = <0xdd038 0x4>; 419 reg-names = "sysc"; 420 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 421 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 422 <SYSC_IDLE_NO>, 423 <SYSC_IDLE_SMART>, 424 <SYSC_IDLE_SMART_WKUP>; 425 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ 426 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; 427 clock-names = "fck"; 428 #address-cells = <1>; 429 #size-cells = <1>; 430 ranges = <0x0 0xdd000 0x1000>; 431 432 /* SmartReflex child device marked reserved in TRM */ 433 }; 434 435 target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */ 436 compatible = "ti,sysc"; 437 status = "disabled"; 438 #address-cells = <1>; 439 #size-cells = <1>; 440 ranges = <0x0 0xe0000 0x1000>; 441 }; 442 443 target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */ 444 compatible = "ti,sysc-omap4", "ti,sysc"; 445 ti,hwmods = "mailbox1"; 446 reg = <0xf4000 0x4>, 447 <0xf4010 0x4>; 448 reg-names = "rev", "sysc"; 449 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 450 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 451 <SYSC_IDLE_NO>, 452 <SYSC_IDLE_SMART>; 453 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 454 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>; 455 clock-names = "fck"; 456 #address-cells = <1>; 457 #size-cells = <1>; 458 ranges = <0x0 0xf4000 0x1000>; 459 460 mailbox1: mailbox@0 { 461 compatible = "ti,omap4-mailbox"; 462 reg = <0x0 0x200>; 463 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 466 #mbox-cells = <1>; 467 ti,mbox-num-users = <3>; 468 ti,mbox-num-fifos = <8>; 469 status = "disabled"; 470 }; 471 }; 472 473 target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */ 474 compatible = "ti,sysc-omap2", "ti,sysc"; 475 ti,hwmods = "spinlock"; 476 reg = <0xf6000 0x4>, 477 <0xf6010 0x4>, 478 <0xf6014 0x4>; 479 reg-names = "rev", "sysc", "syss"; 480 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 481 SYSC_OMAP2_SOFTRESET | 482 SYSC_OMAP2_AUTOIDLE)>; 483 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 484 <SYSC_IDLE_NO>, 485 <SYSC_IDLE_SMART>; 486 ti,syss-mask = <1>; 487 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 488 clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>; 489 clock-names = "fck"; 490 #address-cells = <1>; 491 #size-cells = <1>; 492 ranges = <0x0 0xf6000 0x1000>; 493 494 hwspinlock: spinlock@0 { 495 compatible = "ti,omap4-hwspinlock"; 496 reg = <0x0 0x1000>; 497 #hwlock-cells = <1>; 498 }; 499 }; 500 }; 501 502 segment@100000 { /* 0x4a100000 */ 503 compatible = "simple-bus"; 504 #address-cells = <1>; 505 #size-cells = <1>; 506 ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */ 507 <0x00003000 0x00103000 0x001000>, /* ap 28 */ 508 <0x00008000 0x00108000 0x001000>, /* ap 29 */ 509 <0x00009000 0x00109000 0x001000>, /* ap 30 */ 510 <0x00040000 0x00140000 0x010000>, /* ap 31 */ 511 <0x00050000 0x00150000 0x001000>, /* ap 32 */ 512 <0x00051000 0x00151000 0x001000>, /* ap 33 */ 513 <0x00052000 0x00152000 0x001000>, /* ap 34 */ 514 <0x00053000 0x00153000 0x001000>, /* ap 35 */ 515 <0x00054000 0x00154000 0x001000>, /* ap 36 */ 516 <0x00055000 0x00155000 0x001000>, /* ap 37 */ 517 <0x00056000 0x00156000 0x001000>, /* ap 38 */ 518 <0x00057000 0x00157000 0x001000>, /* ap 39 */ 519 <0x00058000 0x00158000 0x001000>, /* ap 40 */ 520 <0x0005b000 0x0015b000 0x001000>, /* ap 41 */ 521 <0x0005c000 0x0015c000 0x001000>, /* ap 42 */ 522 <0x0005d000 0x0015d000 0x001000>, /* ap 45 */ 523 <0x0005e000 0x0015e000 0x001000>, /* ap 46 */ 524 <0x0005f000 0x0015f000 0x001000>, /* ap 47 */ 525 <0x00060000 0x00160000 0x001000>, /* ap 48 */ 526 <0x00061000 0x00161000 0x001000>, /* ap 49 */ 527 <0x00062000 0x00162000 0x001000>, /* ap 50 */ 528 <0x00063000 0x00163000 0x001000>, /* ap 51 */ 529 <0x00064000 0x00164000 0x001000>, /* ap 52 */ 530 <0x00065000 0x00165000 0x001000>, /* ap 53 */ 531 <0x00066000 0x00166000 0x001000>, /* ap 54 */ 532 <0x00067000 0x00167000 0x001000>, /* ap 55 */ 533 <0x00068000 0x00168000 0x001000>, /* ap 56 */ 534 <0x0006d000 0x0016d000 0x001000>, /* ap 57 */ 535 <0x0006e000 0x0016e000 0x001000>, /* ap 58 */ 536 <0x00071000 0x00171000 0x001000>, /* ap 61 */ 537 <0x00072000 0x00172000 0x001000>, /* ap 62 */ 538 <0x00073000 0x00173000 0x001000>, /* ap 63 */ 539 <0x00074000 0x00174000 0x001000>, /* ap 64 */ 540 <0x00075000 0x00175000 0x001000>, /* ap 65 */ 541 <0x00076000 0x00176000 0x001000>, /* ap 66 */ 542 <0x00077000 0x00177000 0x001000>, /* ap 67 */ 543 <0x00078000 0x00178000 0x001000>, /* ap 68 */ 544 <0x00081000 0x00181000 0x001000>, /* ap 69 */ 545 <0x00082000 0x00182000 0x001000>, /* ap 70 */ 546 <0x00083000 0x00183000 0x001000>, /* ap 71 */ 547 <0x00084000 0x00184000 0x001000>, /* ap 72 */ 548 <0x00085000 0x00185000 0x001000>, /* ap 73 */ 549 <0x00086000 0x00186000 0x001000>, /* ap 74 */ 550 <0x00087000 0x00187000 0x001000>, /* ap 75 */ 551 <0x00088000 0x00188000 0x001000>, /* ap 76 */ 552 <0x00069000 0x00169000 0x001000>, /* ap 103 */ 553 <0x0006a000 0x0016a000 0x001000>, /* ap 104 */ 554 <0x00079000 0x00179000 0x001000>, /* ap 105 */ 555 <0x0007a000 0x0017a000 0x001000>, /* ap 106 */ 556 <0x0006b000 0x0016b000 0x001000>, /* ap 107 */ 557 <0x0006c000 0x0016c000 0x001000>, /* ap 108 */ 558 <0x0007b000 0x0017b000 0x001000>, /* ap 121 */ 559 <0x0007c000 0x0017c000 0x001000>, /* ap 122 */ 560 <0x0007d000 0x0017d000 0x001000>, /* ap 123 */ 561 <0x0007e000 0x0017e000 0x001000>, /* ap 124 */ 562 <0x00059000 0x00159000 0x001000>, /* ap 125 */ 563 <0x0005a000 0x0015a000 0x001000>; /* ap 126 */ 564 565 target-module@2000 { /* 0x4a102000, ap 27 3c.0 */ 566 compatible = "ti,sysc"; 567 status = "disabled"; 568 #address-cells = <1>; 569 #size-cells = <1>; 570 ranges = <0x0 0x2000 0x1000>; 571 }; 572 573 target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ 574 compatible = "ti,sysc"; 575 status = "disabled"; 576 #address-cells = <1>; 577 #size-cells = <1>; 578 ranges = <0x0 0x8000 0x1000>; 579 }; 580 581 target-module@40000 { /* 0x4a140000, ap 31 06.0 */ 582 compatible = "ti,sysc"; 583 status = "disabled"; 584 #address-cells = <1>; 585 #size-cells = <1>; 586 ranges = <0x0 0x40000 0x10000>; 587 }; 588 589 target-module@51000 { /* 0x4a151000, ap 33 50.0 */ 590 compatible = "ti,sysc"; 591 status = "disabled"; 592 #address-cells = <1>; 593 #size-cells = <1>; 594 ranges = <0x0 0x51000 0x1000>; 595 }; 596 597 target-module@53000 { /* 0x4a153000, ap 35 54.0 */ 598 compatible = "ti,sysc"; 599 status = "disabled"; 600 #address-cells = <1>; 601 #size-cells = <1>; 602 ranges = <0x0 0x53000 0x1000>; 603 }; 604 605 target-module@55000 { /* 0x4a155000, ap 37 46.0 */ 606 compatible = "ti,sysc"; 607 status = "disabled"; 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0x0 0x55000 0x1000>; 611 }; 612 613 target-module@57000 { /* 0x4a157000, ap 39 58.0 */ 614 compatible = "ti,sysc"; 615 status = "disabled"; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 ranges = <0x0 0x57000 0x1000>; 619 }; 620 621 target-module@59000 { /* 0x4a159000, ap 125 6a.0 */ 622 compatible = "ti,sysc"; 623 status = "disabled"; 624 #address-cells = <1>; 625 #size-cells = <1>; 626 ranges = <0x0 0x59000 0x1000>; 627 }; 628 629 target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */ 630 compatible = "ti,sysc"; 631 status = "disabled"; 632 #address-cells = <1>; 633 #size-cells = <1>; 634 ranges = <0x0 0x5b000 0x1000>; 635 }; 636 637 target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */ 638 compatible = "ti,sysc"; 639 status = "disabled"; 640 #address-cells = <1>; 641 #size-cells = <1>; 642 ranges = <0x0 0x5d000 0x1000>; 643 }; 644 645 target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */ 646 compatible = "ti,sysc"; 647 status = "disabled"; 648 #address-cells = <1>; 649 #size-cells = <1>; 650 ranges = <0x0 0x5f000 0x1000>; 651 }; 652 653 target-module@61000 { /* 0x4a161000, ap 49 32.0 */ 654 compatible = "ti,sysc"; 655 status = "disabled"; 656 #address-cells = <1>; 657 #size-cells = <1>; 658 ranges = <0x0 0x61000 0x1000>; 659 }; 660 661 target-module@63000 { /* 0x4a163000, ap 51 5c.0 */ 662 compatible = "ti,sysc"; 663 status = "disabled"; 664 #address-cells = <1>; 665 #size-cells = <1>; 666 ranges = <0x0 0x63000 0x1000>; 667 }; 668 669 target-module@65000 { /* 0x4a165000, ap 53 4e.0 */ 670 compatible = "ti,sysc"; 671 status = "disabled"; 672 #address-cells = <1>; 673 #size-cells = <1>; 674 ranges = <0x0 0x65000 0x1000>; 675 }; 676 677 target-module@67000 { /* 0x4a167000, ap 55 5e.0 */ 678 compatible = "ti,sysc"; 679 status = "disabled"; 680 #address-cells = <1>; 681 #size-cells = <1>; 682 ranges = <0x0 0x67000 0x1000>; 683 }; 684 685 target-module@69000 { /* 0x4a169000, ap 103 4a.0 */ 686 compatible = "ti,sysc"; 687 status = "disabled"; 688 #address-cells = <1>; 689 #size-cells = <1>; 690 ranges = <0x0 0x69000 0x1000>; 691 }; 692 693 target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */ 694 compatible = "ti,sysc"; 695 status = "disabled"; 696 #address-cells = <1>; 697 #size-cells = <1>; 698 ranges = <0x0 0x6b000 0x1000>; 699 }; 700 701 target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */ 702 compatible = "ti,sysc"; 703 status = "disabled"; 704 #address-cells = <1>; 705 #size-cells = <1>; 706 ranges = <0x0 0x6d000 0x1000>; 707 }; 708 709 target-module@71000 { /* 0x4a171000, ap 61 48.0 */ 710 compatible = "ti,sysc"; 711 status = "disabled"; 712 #address-cells = <1>; 713 #size-cells = <1>; 714 ranges = <0x0 0x71000 0x1000>; 715 }; 716 717 target-module@73000 { /* 0x4a173000, ap 63 2a.0 */ 718 compatible = "ti,sysc"; 719 status = "disabled"; 720 #address-cells = <1>; 721 #size-cells = <1>; 722 ranges = <0x0 0x73000 0x1000>; 723 }; 724 725 target-module@75000 { /* 0x4a175000, ap 65 64.0 */ 726 compatible = "ti,sysc"; 727 status = "disabled"; 728 #address-cells = <1>; 729 #size-cells = <1>; 730 ranges = <0x0 0x75000 0x1000>; 731 }; 732 733 target-module@77000 { /* 0x4a177000, ap 67 66.0 */ 734 compatible = "ti,sysc"; 735 status = "disabled"; 736 #address-cells = <1>; 737 #size-cells = <1>; 738 ranges = <0x0 0x77000 0x1000>; 739 }; 740 741 target-module@79000 { /* 0x4a179000, ap 105 34.0 */ 742 compatible = "ti,sysc"; 743 status = "disabled"; 744 #address-cells = <1>; 745 #size-cells = <1>; 746 ranges = <0x0 0x79000 0x1000>; 747 }; 748 749 target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */ 750 compatible = "ti,sysc"; 751 status = "disabled"; 752 #address-cells = <1>; 753 #size-cells = <1>; 754 ranges = <0x0 0x7b000 0x1000>; 755 }; 756 757 target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */ 758 compatible = "ti,sysc"; 759 status = "disabled"; 760 #address-cells = <1>; 761 #size-cells = <1>; 762 ranges = <0x0 0x7d000 0x1000>; 763 }; 764 765 target-module@81000 { /* 0x4a181000, ap 69 26.0 */ 766 compatible = "ti,sysc"; 767 status = "disabled"; 768 #address-cells = <1>; 769 #size-cells = <1>; 770 ranges = <0x0 0x81000 0x1000>; 771 }; 772 773 target-module@83000 { /* 0x4a183000, ap 71 2e.0 */ 774 compatible = "ti,sysc"; 775 status = "disabled"; 776 #address-cells = <1>; 777 #size-cells = <1>; 778 ranges = <0x0 0x83000 0x1000>; 779 }; 780 781 target-module@85000 { /* 0x4a185000, ap 73 36.0 */ 782 compatible = "ti,sysc"; 783 status = "disabled"; 784 #address-cells = <1>; 785 #size-cells = <1>; 786 ranges = <0x0 0x85000 0x1000>; 787 }; 788 789 target-module@87000 { /* 0x4a187000, ap 75 74.0 */ 790 compatible = "ti,sysc"; 791 status = "disabled"; 792 #address-cells = <1>; 793 #size-cells = <1>; 794 ranges = <0x0 0x87000 0x1000>; 795 }; 796 }; 797 798 segment@200000 { /* 0x4a200000 */ 799 compatible = "simple-bus"; 800 #address-cells = <1>; 801 #size-cells = <1>; 802 ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */ 803 <0x00019000 0x00219000 0x001000>, /* ap 44 */ 804 <0x00000000 0x00200000 0x001000>, /* ap 77 */ 805 <0x00001000 0x00201000 0x001000>, /* ap 78 */ 806 <0x0000a000 0x0020a000 0x001000>, /* ap 79 */ 807 <0x0000b000 0x0020b000 0x001000>, /* ap 80 */ 808 <0x0000c000 0x0020c000 0x001000>, /* ap 81 */ 809 <0x0000d000 0x0020d000 0x001000>, /* ap 82 */ 810 <0x0000e000 0x0020e000 0x001000>, /* ap 83 */ 811 <0x0000f000 0x0020f000 0x001000>, /* ap 84 */ 812 <0x00010000 0x00210000 0x001000>, /* ap 85 */ 813 <0x00011000 0x00211000 0x001000>, /* ap 86 */ 814 <0x00012000 0x00212000 0x001000>, /* ap 87 */ 815 <0x00013000 0x00213000 0x001000>, /* ap 88 */ 816 <0x00014000 0x00214000 0x001000>, /* ap 89 */ 817 <0x00015000 0x00215000 0x001000>, /* ap 90 */ 818 <0x0002a000 0x0022a000 0x001000>, /* ap 91 */ 819 <0x0002b000 0x0022b000 0x001000>, /* ap 92 */ 820 <0x0001c000 0x0021c000 0x001000>, /* ap 93 */ 821 <0x0001d000 0x0021d000 0x001000>, /* ap 94 */ 822 <0x0001e000 0x0021e000 0x001000>, /* ap 95 */ 823 <0x0001f000 0x0021f000 0x001000>, /* ap 96 */ 824 <0x00020000 0x00220000 0x001000>, /* ap 97 */ 825 <0x00021000 0x00221000 0x001000>, /* ap 98 */ 826 <0x00024000 0x00224000 0x001000>, /* ap 99 */ 827 <0x00025000 0x00225000 0x001000>, /* ap 100 */ 828 <0x00026000 0x00226000 0x001000>, /* ap 101 */ 829 <0x00027000 0x00227000 0x001000>, /* ap 102 */ 830 <0x0002c000 0x0022c000 0x001000>, /* ap 109 */ 831 <0x0002d000 0x0022d000 0x001000>, /* ap 110 */ 832 <0x0002e000 0x0022e000 0x001000>, /* ap 111 */ 833 <0x0002f000 0x0022f000 0x001000>, /* ap 112 */ 834 <0x00030000 0x00230000 0x001000>, /* ap 113 */ 835 <0x00031000 0x00231000 0x001000>, /* ap 114 */ 836 <0x00032000 0x00232000 0x001000>, /* ap 115 */ 837 <0x00033000 0x00233000 0x001000>, /* ap 116 */ 838 <0x00034000 0x00234000 0x001000>, /* ap 117 */ 839 <0x00035000 0x00235000 0x001000>, /* ap 118 */ 840 <0x00036000 0x00236000 0x001000>, /* ap 119 */ 841 <0x00037000 0x00237000 0x001000>, /* ap 120 */ 842 <0x0001a000 0x0021a000 0x001000>, /* ap 127 */ 843 <0x0001b000 0x0021b000 0x001000>; /* ap 128 */ 844 845 target-module@0 { /* 0x4a200000, ap 77 3e.0 */ 846 compatible = "ti,sysc"; 847 status = "disabled"; 848 #address-cells = <1>; 849 #size-cells = <1>; 850 ranges = <0x0 0x0 0x1000>; 851 }; 852 853 target-module@a000 { /* 0x4a20a000, ap 79 30.0 */ 854 compatible = "ti,sysc"; 855 status = "disabled"; 856 #address-cells = <1>; 857 #size-cells = <1>; 858 ranges = <0x0 0xa000 0x1000>; 859 }; 860 861 target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */ 862 compatible = "ti,sysc"; 863 status = "disabled"; 864 #address-cells = <1>; 865 #size-cells = <1>; 866 ranges = <0x0 0xc000 0x1000>; 867 }; 868 869 target-module@e000 { /* 0x4a20e000, ap 83 22.0 */ 870 compatible = "ti,sysc"; 871 status = "disabled"; 872 #address-cells = <1>; 873 #size-cells = <1>; 874 ranges = <0x0 0xe000 0x1000>; 875 }; 876 877 target-module@10000 { /* 0x4a210000, ap 85 14.0 */ 878 compatible = "ti,sysc"; 879 status = "disabled"; 880 #address-cells = <1>; 881 #size-cells = <1>; 882 ranges = <0x0 0x10000 0x1000>; 883 }; 884 885 target-module@12000 { /* 0x4a212000, ap 87 16.0 */ 886 compatible = "ti,sysc"; 887 status = "disabled"; 888 #address-cells = <1>; 889 #size-cells = <1>; 890 ranges = <0x0 0x12000 0x1000>; 891 }; 892 893 target-module@14000 { /* 0x4a214000, ap 89 1c.0 */ 894 compatible = "ti,sysc"; 895 status = "disabled"; 896 #address-cells = <1>; 897 #size-cells = <1>; 898 ranges = <0x0 0x14000 0x1000>; 899 }; 900 901 target-module@18000 { /* 0x4a218000, ap 43 12.0 */ 902 compatible = "ti,sysc"; 903 status = "disabled"; 904 #address-cells = <1>; 905 #size-cells = <1>; 906 ranges = <0x0 0x18000 0x1000>; 907 }; 908 909 target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */ 910 compatible = "ti,sysc"; 911 status = "disabled"; 912 #address-cells = <1>; 913 #size-cells = <1>; 914 ranges = <0x0 0x1a000 0x1000>; 915 }; 916 917 target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */ 918 compatible = "ti,sysc"; 919 status = "disabled"; 920 #address-cells = <1>; 921 #size-cells = <1>; 922 ranges = <0x0 0x1c000 0x1000>; 923 }; 924 925 target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */ 926 compatible = "ti,sysc"; 927 status = "disabled"; 928 #address-cells = <1>; 929 #size-cells = <1>; 930 ranges = <0x0 0x1e000 0x1000>; 931 }; 932 933 target-module@20000 { /* 0x4a220000, ap 97 24.0 */ 934 compatible = "ti,sysc"; 935 status = "disabled"; 936 #address-cells = <1>; 937 #size-cells = <1>; 938 ranges = <0x0 0x20000 0x1000>; 939 }; 940 941 target-module@24000 { /* 0x4a224000, ap 99 44.0 */ 942 compatible = "ti,sysc"; 943 status = "disabled"; 944 #address-cells = <1>; 945 #size-cells = <1>; 946 ranges = <0x0 0x24000 0x1000>; 947 }; 948 949 target-module@26000 { /* 0x4a226000, ap 101 2c.0 */ 950 compatible = "ti,sysc"; 951 status = "disabled"; 952 #address-cells = <1>; 953 #size-cells = <1>; 954 ranges = <0x0 0x26000 0x1000>; 955 }; 956 957 target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */ 958 compatible = "ti,sysc"; 959 status = "disabled"; 960 #address-cells = <1>; 961 #size-cells = <1>; 962 ranges = <0x0 0x2a000 0x1000>; 963 }; 964 965 target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */ 966 compatible = "ti,sysc"; 967 status = "disabled"; 968 #address-cells = <1>; 969 #size-cells = <1>; 970 ranges = <0x0 0x2c000 0x1000>; 971 }; 972 973 target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */ 974 compatible = "ti,sysc"; 975 status = "disabled"; 976 #address-cells = <1>; 977 #size-cells = <1>; 978 ranges = <0x0 0x2e000 0x1000>; 979 }; 980 981 target-module@30000 { /* 0x4a230000, ap 113 70.0 */ 982 compatible = "ti,sysc"; 983 status = "disabled"; 984 #address-cells = <1>; 985 #size-cells = <1>; 986 ranges = <0x0 0x30000 0x1000>; 987 }; 988 989 target-module@32000 { /* 0x4a232000, ap 115 5a.0 */ 990 compatible = "ti,sysc"; 991 status = "disabled"; 992 #address-cells = <1>; 993 #size-cells = <1>; 994 ranges = <0x0 0x32000 0x1000>; 995 }; 996 997 target-module@34000 { /* 0x4a234000, ap 117 76.1 */ 998 compatible = "ti,sysc"; 999 status = "disabled"; 1000 #address-cells = <1>; 1001 #size-cells = <1>; 1002 ranges = <0x0 0x34000 0x1000>; 1003 }; 1004 1005 target-module@36000 { /* 0x4a236000, ap 119 62.0 */ 1006 compatible = "ti,sysc"; 1007 status = "disabled"; 1008 #address-cells = <1>; 1009 #size-cells = <1>; 1010 ranges = <0x0 0x36000 0x1000>; 1011 }; 1012 }; 1013}; 1014 1015&l4_per1 { /* 0x48000000 */ 1016 compatible = "ti,dra7-l4-per1", "simple-bus"; 1017 reg = <0x48000000 0x800>, 1018 <0x48000800 0x800>, 1019 <0x48001000 0x400>, 1020 <0x48001400 0x400>, 1021 <0x48001800 0x400>, 1022 <0x48001c00 0x400>; 1023 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 1024 #address-cells = <1>; 1025 #size-cells = <1>; 1026 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ 1027 <0x00200000 0x48200000 0x200000>; /* segment 1 */ 1028 1029 segment@0 { /* 0x48000000 */ 1030 compatible = "simple-bus"; 1031 #address-cells = <1>; 1032 #size-cells = <1>; 1033 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 1034 <0x00001000 0x00001000 0x000400>, /* ap 1 */ 1035 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 1036 <0x00020000 0x00020000 0x001000>, /* ap 3 */ 1037 <0x00021000 0x00021000 0x001000>, /* ap 4 */ 1038 <0x00032000 0x00032000 0x001000>, /* ap 5 */ 1039 <0x00033000 0x00033000 0x001000>, /* ap 6 */ 1040 <0x00034000 0x00034000 0x001000>, /* ap 7 */ 1041 <0x00035000 0x00035000 0x001000>, /* ap 8 */ 1042 <0x00036000 0x00036000 0x001000>, /* ap 9 */ 1043 <0x00037000 0x00037000 0x001000>, /* ap 10 */ 1044 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ 1045 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ 1046 <0x00055000 0x00055000 0x001000>, /* ap 13 */ 1047 <0x00056000 0x00056000 0x001000>, /* ap 14 */ 1048 <0x00057000 0x00057000 0x001000>, /* ap 15 */ 1049 <0x00058000 0x00058000 0x001000>, /* ap 16 */ 1050 <0x00059000 0x00059000 0x001000>, /* ap 17 */ 1051 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ 1052 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ 1053 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ 1054 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ 1055 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ 1056 <0x00060000 0x00060000 0x001000>, /* ap 23 */ 1057 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ 1058 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ 1059 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ 1060 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ 1061 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ 1062 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ 1063 <0x00070000 0x00070000 0x001000>, /* ap 30 */ 1064 <0x00071000 0x00071000 0x001000>, /* ap 31 */ 1065 <0x00072000 0x00072000 0x001000>, /* ap 32 */ 1066 <0x00073000 0x00073000 0x001000>, /* ap 33 */ 1067 <0x00061000 0x00061000 0x001000>, /* ap 34 */ 1068 <0x00053000 0x00053000 0x001000>, /* ap 35 */ 1069 <0x00054000 0x00054000 0x001000>, /* ap 36 */ 1070 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ 1071 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ 1072 <0x00078000 0x00078000 0x001000>, /* ap 39 */ 1073 <0x00079000 0x00079000 0x001000>, /* ap 40 */ 1074 <0x00086000 0x00086000 0x001000>, /* ap 41 */ 1075 <0x00087000 0x00087000 0x001000>, /* ap 42 */ 1076 <0x00088000 0x00088000 0x001000>, /* ap 43 */ 1077 <0x00089000 0x00089000 0x001000>, /* ap 44 */ 1078 <0x00051000 0x00051000 0x001000>, /* ap 45 */ 1079 <0x00052000 0x00052000 0x001000>, /* ap 46 */ 1080 <0x00098000 0x00098000 0x001000>, /* ap 47 */ 1081 <0x00099000 0x00099000 0x001000>, /* ap 48 */ 1082 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ 1083 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ 1084 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ 1085 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ 1086 <0x00068000 0x00068000 0x001000>, /* ap 53 */ 1087 <0x00069000 0x00069000 0x001000>, /* ap 54 */ 1088 <0x00090000 0x00090000 0x002000>, /* ap 55 */ 1089 <0x00092000 0x00092000 0x001000>, /* ap 56 */ 1090 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ 1091 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ 1092 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ 1093 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ 1094 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ 1095 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ 1096 <0x00066000 0x00066000 0x001000>, /* ap 63 */ 1097 <0x00067000 0x00067000 0x001000>, /* ap 64 */ 1098 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ 1099 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ 1100 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ 1101 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ 1102 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ 1103 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ 1104 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ 1105 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ 1106 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ 1107 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ 1108 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ 1109 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ 1110 <0x00001400 0x00001400 0x000400>, /* ap 77 */ 1111 <0x00001800 0x00001800 0x000400>, /* ap 78 */ 1112 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ 1113 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ 1114 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ 1115 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ 1116 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ 1117 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ 1118 1119 target-module@20000 { /* 0x48020000, ap 3 04.0 */ 1120 compatible = "ti,sysc-omap2", "ti,sysc"; 1121 ti,hwmods = "uart3"; 1122 reg = <0x20050 0x4>, 1123 <0x20054 0x4>, 1124 <0x20058 0x4>; 1125 reg-names = "rev", "sysc", "syss"; 1126 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1127 SYSC_OMAP2_SOFTRESET | 1128 SYSC_OMAP2_AUTOIDLE)>; 1129 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1130 <SYSC_IDLE_NO>, 1131 <SYSC_IDLE_SMART>, 1132 <SYSC_IDLE_SMART_WKUP>; 1133 ti,syss-mask = <1>; 1134 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1135 clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>; 1136 clock-names = "fck"; 1137 #address-cells = <1>; 1138 #size-cells = <1>; 1139 ranges = <0x0 0x20000 0x1000>; 1140 1141 uart3: serial@0 { 1142 compatible = "ti,dra742-uart", "ti,omap4-uart"; 1143 reg = <0x0 0x100>; 1144 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1145 clock-frequency = <48000000>; 1146 status = "disabled"; 1147 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; 1148 dma-names = "tx", "rx"; 1149 }; 1150 }; 1151 1152 target-module@32000 { /* 0x48032000, ap 5 3e.0 */ 1153 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1154 ti,hwmods = "timer2"; 1155 reg = <0x32000 0x4>, 1156 <0x32010 0x4>; 1157 reg-names = "rev", "sysc"; 1158 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1159 SYSC_OMAP4_SOFTRESET)>; 1160 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1161 <SYSC_IDLE_NO>, 1162 <SYSC_IDLE_SMART>, 1163 <SYSC_IDLE_SMART_WKUP>; 1164 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1165 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>; 1166 clock-names = "fck"; 1167 #address-cells = <1>; 1168 #size-cells = <1>; 1169 ranges = <0x0 0x32000 0x1000>; 1170 1171 timer2: timer@0 { 1172 compatible = "ti,omap5430-timer"; 1173 reg = <0x0 0x80>; 1174 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>; 1175 clock-names = "fck"; 1176 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1177 }; 1178 }; 1179 1180 target-module@34000 { /* 0x48034000, ap 7 46.0 */ 1181 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1182 ti,hwmods = "timer3"; 1183 reg = <0x34000 0x4>, 1184 <0x34010 0x4>; 1185 reg-names = "rev", "sysc"; 1186 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1187 SYSC_OMAP4_SOFTRESET)>; 1188 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1189 <SYSC_IDLE_NO>, 1190 <SYSC_IDLE_SMART>, 1191 <SYSC_IDLE_SMART_WKUP>; 1192 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1193 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>; 1194 clock-names = "fck"; 1195 #address-cells = <1>; 1196 #size-cells = <1>; 1197 ranges = <0x0 0x34000 0x1000>; 1198 1199 timer3: timer@0 { 1200 compatible = "ti,omap5430-timer"; 1201 reg = <0x0 0x80>; 1202 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>; 1203 clock-names = "fck"; 1204 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1205 }; 1206 }; 1207 1208 target-module@36000 { /* 0x48036000, ap 9 4e.0 */ 1209 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1210 ti,hwmods = "timer4"; 1211 reg = <0x36000 0x4>, 1212 <0x36010 0x4>; 1213 reg-names = "rev", "sysc"; 1214 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1215 SYSC_OMAP4_SOFTRESET)>; 1216 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1217 <SYSC_IDLE_NO>, 1218 <SYSC_IDLE_SMART>, 1219 <SYSC_IDLE_SMART_WKUP>; 1220 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1221 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; 1222 clock-names = "fck"; 1223 #address-cells = <1>; 1224 #size-cells = <1>; 1225 ranges = <0x0 0x36000 0x1000>; 1226 1227 timer4: timer@0 { 1228 compatible = "ti,omap5430-timer"; 1229 reg = <0x0 0x80>; 1230 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>; 1231 clock-names = "fck"; 1232 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1233 }; 1234 }; 1235 1236 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ 1237 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1238 ti,hwmods = "timer9"; 1239 reg = <0x3e000 0x4>, 1240 <0x3e010 0x4>; 1241 reg-names = "rev", "sysc"; 1242 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1243 SYSC_OMAP4_SOFTRESET)>; 1244 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1245 <SYSC_IDLE_NO>, 1246 <SYSC_IDLE_SMART>, 1247 <SYSC_IDLE_SMART_WKUP>; 1248 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1249 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>; 1250 clock-names = "fck"; 1251 #address-cells = <1>; 1252 #size-cells = <1>; 1253 ranges = <0x0 0x3e000 0x1000>; 1254 1255 timer9: timer@0 { 1256 compatible = "ti,omap5430-timer"; 1257 reg = <0x0 0x80>; 1258 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>; 1259 clock-names = "fck"; 1260 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1261 }; 1262 }; 1263 1264 target-module@51000 { /* 0x48051000, ap 45 2e.0 */ 1265 compatible = "ti,sysc-omap2", "ti,sysc"; 1266 ti,hwmods = "gpio7"; 1267 reg = <0x51000 0x4>, 1268 <0x51010 0x4>, 1269 <0x51114 0x4>; 1270 reg-names = "rev", "sysc", "syss"; 1271 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1272 SYSC_OMAP2_SOFTRESET | 1273 SYSC_OMAP2_AUTOIDLE)>; 1274 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1275 <SYSC_IDLE_NO>, 1276 <SYSC_IDLE_SMART>, 1277 <SYSC_IDLE_SMART_WKUP>; 1278 ti,syss-mask = <1>; 1279 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1280 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>, 1281 <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>; 1282 clock-names = "fck", "dbclk"; 1283 #address-cells = <1>; 1284 #size-cells = <1>; 1285 ranges = <0x0 0x51000 0x1000>; 1286 1287 gpio7: gpio@0 { 1288 compatible = "ti,omap4-gpio"; 1289 reg = <0x0 0x200>; 1290 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1291 gpio-controller; 1292 #gpio-cells = <2>; 1293 interrupt-controller; 1294 #interrupt-cells = <2>; 1295 }; 1296 }; 1297 1298 target-module@53000 { /* 0x48053000, ap 35 36.0 */ 1299 compatible = "ti,sysc-omap2", "ti,sysc"; 1300 ti,hwmods = "gpio8"; 1301 reg = <0x53000 0x4>, 1302 <0x53010 0x4>, 1303 <0x53114 0x4>; 1304 reg-names = "rev", "sysc", "syss"; 1305 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1306 SYSC_OMAP2_SOFTRESET | 1307 SYSC_OMAP2_AUTOIDLE)>; 1308 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1309 <SYSC_IDLE_NO>, 1310 <SYSC_IDLE_SMART>, 1311 <SYSC_IDLE_SMART_WKUP>; 1312 ti,syss-mask = <1>; 1313 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1314 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>, 1315 <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>; 1316 clock-names = "fck", "dbclk"; 1317 #address-cells = <1>; 1318 #size-cells = <1>; 1319 ranges = <0x0 0x53000 0x1000>; 1320 1321 gpio8: gpio@0 { 1322 compatible = "ti,omap4-gpio"; 1323 reg = <0x0 0x200>; 1324 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1325 gpio-controller; 1326 #gpio-cells = <2>; 1327 interrupt-controller; 1328 #interrupt-cells = <2>; 1329 }; 1330 }; 1331 1332 target-module@55000 { /* 0x48055000, ap 13 0e.0 */ 1333 compatible = "ti,sysc-omap2", "ti,sysc"; 1334 ti,hwmods = "gpio2"; 1335 reg = <0x55000 0x4>, 1336 <0x55010 0x4>, 1337 <0x55114 0x4>; 1338 reg-names = "rev", "sysc", "syss"; 1339 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1340 SYSC_OMAP2_SOFTRESET | 1341 SYSC_OMAP2_AUTOIDLE)>; 1342 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1343 <SYSC_IDLE_NO>, 1344 <SYSC_IDLE_SMART>, 1345 <SYSC_IDLE_SMART_WKUP>; 1346 ti,syss-mask = <1>; 1347 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1348 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>, 1349 <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>; 1350 clock-names = "fck", "dbclk"; 1351 #address-cells = <1>; 1352 #size-cells = <1>; 1353 ranges = <0x0 0x55000 0x1000>; 1354 1355 gpio2: gpio@0 { 1356 compatible = "ti,omap4-gpio"; 1357 reg = <0x0 0x200>; 1358 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1359 gpio-controller; 1360 #gpio-cells = <2>; 1361 interrupt-controller; 1362 #interrupt-cells = <2>; 1363 }; 1364 }; 1365 1366 target-module@57000 { /* 0x48057000, ap 15 06.0 */ 1367 compatible = "ti,sysc-omap2", "ti,sysc"; 1368 ti,hwmods = "gpio3"; 1369 reg = <0x57000 0x4>, 1370 <0x57010 0x4>, 1371 <0x57114 0x4>; 1372 reg-names = "rev", "sysc", "syss"; 1373 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1374 SYSC_OMAP2_SOFTRESET | 1375 SYSC_OMAP2_AUTOIDLE)>; 1376 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1377 <SYSC_IDLE_NO>, 1378 <SYSC_IDLE_SMART>, 1379 <SYSC_IDLE_SMART_WKUP>; 1380 ti,syss-mask = <1>; 1381 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1382 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>, 1383 <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>; 1384 clock-names = "fck", "dbclk"; 1385 #address-cells = <1>; 1386 #size-cells = <1>; 1387 ranges = <0x0 0x57000 0x1000>; 1388 1389 gpio3: gpio@0 { 1390 compatible = "ti,omap4-gpio"; 1391 reg = <0x0 0x200>; 1392 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1393 gpio-controller; 1394 #gpio-cells = <2>; 1395 interrupt-controller; 1396 #interrupt-cells = <2>; 1397 }; 1398 }; 1399 1400 target-module@59000 { /* 0x48059000, ap 17 16.0 */ 1401 compatible = "ti,sysc-omap2", "ti,sysc"; 1402 ti,hwmods = "gpio4"; 1403 reg = <0x59000 0x4>, 1404 <0x59010 0x4>, 1405 <0x59114 0x4>; 1406 reg-names = "rev", "sysc", "syss"; 1407 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1408 SYSC_OMAP2_SOFTRESET | 1409 SYSC_OMAP2_AUTOIDLE)>; 1410 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1411 <SYSC_IDLE_NO>, 1412 <SYSC_IDLE_SMART>, 1413 <SYSC_IDLE_SMART_WKUP>; 1414 ti,syss-mask = <1>; 1415 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1416 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>, 1417 <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>; 1418 clock-names = "fck", "dbclk"; 1419 #address-cells = <1>; 1420 #size-cells = <1>; 1421 ranges = <0x0 0x59000 0x1000>; 1422 1423 gpio4: gpio@0 { 1424 compatible = "ti,omap4-gpio"; 1425 reg = <0x0 0x200>; 1426 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1427 gpio-controller; 1428 #gpio-cells = <2>; 1429 interrupt-controller; 1430 #interrupt-cells = <2>; 1431 }; 1432 }; 1433 1434 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ 1435 compatible = "ti,sysc-omap2", "ti,sysc"; 1436 ti,hwmods = "gpio5"; 1437 reg = <0x5b000 0x4>, 1438 <0x5b010 0x4>, 1439 <0x5b114 0x4>; 1440 reg-names = "rev", "sysc", "syss"; 1441 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1442 SYSC_OMAP2_SOFTRESET | 1443 SYSC_OMAP2_AUTOIDLE)>; 1444 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1445 <SYSC_IDLE_NO>, 1446 <SYSC_IDLE_SMART>, 1447 <SYSC_IDLE_SMART_WKUP>; 1448 ti,syss-mask = <1>; 1449 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1450 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>, 1451 <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>; 1452 clock-names = "fck", "dbclk"; 1453 #address-cells = <1>; 1454 #size-cells = <1>; 1455 ranges = <0x0 0x5b000 0x1000>; 1456 1457 gpio5: gpio@0 { 1458 compatible = "ti,omap4-gpio"; 1459 reg = <0x0 0x200>; 1460 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1461 gpio-controller; 1462 #gpio-cells = <2>; 1463 interrupt-controller; 1464 #interrupt-cells = <2>; 1465 }; 1466 }; 1467 1468 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ 1469 compatible = "ti,sysc-omap2", "ti,sysc"; 1470 ti,hwmods = "gpio6"; 1471 reg = <0x5d000 0x4>, 1472 <0x5d010 0x4>, 1473 <0x5d114 0x4>; 1474 reg-names = "rev", "sysc", "syss"; 1475 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1476 SYSC_OMAP2_SOFTRESET | 1477 SYSC_OMAP2_AUTOIDLE)>; 1478 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1479 <SYSC_IDLE_NO>, 1480 <SYSC_IDLE_SMART>, 1481 <SYSC_IDLE_SMART_WKUP>; 1482 ti,syss-mask = <1>; 1483 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1484 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>, 1485 <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>; 1486 clock-names = "fck", "dbclk"; 1487 #address-cells = <1>; 1488 #size-cells = <1>; 1489 ranges = <0x0 0x5d000 0x1000>; 1490 1491 gpio6: gpio@0 { 1492 compatible = "ti,omap4-gpio"; 1493 reg = <0x0 0x200>; 1494 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1495 gpio-controller; 1496 #gpio-cells = <2>; 1497 interrupt-controller; 1498 #interrupt-cells = <2>; 1499 }; 1500 }; 1501 1502 target-module@60000 { /* 0x48060000, ap 23 32.0 */ 1503 compatible = "ti,sysc-omap2", "ti,sysc"; 1504 ti,hwmods = "i2c3"; 1505 reg = <0x60000 0x8>, 1506 <0x60010 0x8>, 1507 <0x60090 0x8>; 1508 reg-names = "rev", "sysc", "syss"; 1509 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1510 SYSC_OMAP2_ENAWAKEUP | 1511 SYSC_OMAP2_SOFTRESET | 1512 SYSC_OMAP2_AUTOIDLE)>; 1513 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1514 <SYSC_IDLE_NO>, 1515 <SYSC_IDLE_SMART>, 1516 <SYSC_IDLE_SMART_WKUP>; 1517 ti,syss-mask = <1>; 1518 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1519 clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>; 1520 clock-names = "fck"; 1521 #address-cells = <1>; 1522 #size-cells = <1>; 1523 ranges = <0x0 0x60000 0x1000>; 1524 1525 i2c3: i2c@0 { 1526 compatible = "ti,omap4-i2c"; 1527 reg = <0x0 0x100>; 1528 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 status = "disabled"; 1532 }; 1533 }; 1534 1535 target-module@66000 { /* 0x48066000, ap 63 14.0 */ 1536 compatible = "ti,sysc-omap2", "ti,sysc"; 1537 ti,hwmods = "uart5"; 1538 reg = <0x66050 0x4>, 1539 <0x66054 0x4>, 1540 <0x66058 0x4>; 1541 reg-names = "rev", "sysc", "syss"; 1542 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1543 SYSC_OMAP2_SOFTRESET | 1544 SYSC_OMAP2_AUTOIDLE)>; 1545 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1546 <SYSC_IDLE_NO>, 1547 <SYSC_IDLE_SMART>, 1548 <SYSC_IDLE_SMART_WKUP>; 1549 ti,syss-mask = <1>; 1550 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1551 clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>; 1552 clock-names = "fck"; 1553 #address-cells = <1>; 1554 #size-cells = <1>; 1555 ranges = <0x0 0x66000 0x1000>; 1556 1557 uart5: serial@0 { 1558 compatible = "ti,dra742-uart", "ti,omap4-uart"; 1559 reg = <0x0 0x100>; 1560 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1561 clock-frequency = <48000000>; 1562 status = "disabled"; 1563 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; 1564 dma-names = "tx", "rx"; 1565 }; 1566 }; 1567 1568 target-module@68000 { /* 0x48068000, ap 53 1c.0 */ 1569 compatible = "ti,sysc-omap2", "ti,sysc"; 1570 ti,hwmods = "uart6"; 1571 reg = <0x68050 0x4>, 1572 <0x68054 0x4>, 1573 <0x68058 0x4>; 1574 reg-names = "rev", "sysc", "syss"; 1575 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1576 SYSC_OMAP2_SOFTRESET | 1577 SYSC_OMAP2_AUTOIDLE)>; 1578 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1579 <SYSC_IDLE_NO>, 1580 <SYSC_IDLE_SMART>, 1581 <SYSC_IDLE_SMART_WKUP>; 1582 ti,syss-mask = <1>; 1583 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 1584 clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>; 1585 clock-names = "fck"; 1586 #address-cells = <1>; 1587 #size-cells = <1>; 1588 ranges = <0x0 0x68000 0x1000>; 1589 1590 uart6: serial@0 { 1591 compatible = "ti,dra742-uart", "ti,omap4-uart"; 1592 reg = <0x0 0x100>; 1593 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1594 clock-frequency = <48000000>; 1595 status = "disabled"; 1596 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; 1597 dma-names = "tx", "rx"; 1598 }; 1599 }; 1600 1601 target-module@6a000 { /* 0x4806a000, ap 24 24.0 */ 1602 compatible = "ti,sysc-omap2", "ti,sysc"; 1603 ti,hwmods = "uart1"; 1604 reg = <0x6a050 0x4>, 1605 <0x6a054 0x4>, 1606 <0x6a058 0x4>; 1607 reg-names = "rev", "sysc", "syss"; 1608 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1609 SYSC_OMAP2_SOFTRESET | 1610 SYSC_OMAP2_AUTOIDLE)>; 1611 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1612 <SYSC_IDLE_NO>, 1613 <SYSC_IDLE_SMART>, 1614 <SYSC_IDLE_SMART_WKUP>; 1615 ti,syss-mask = <1>; 1616 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1617 clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>; 1618 clock-names = "fck"; 1619 #address-cells = <1>; 1620 #size-cells = <1>; 1621 ranges = <0x0 0x6a000 0x1000>; 1622 1623 uart1: serial@0 { 1624 compatible = "ti,dra742-uart", "ti,omap4-uart"; 1625 reg = <0x0 0x100>; 1626 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1627 clock-frequency = <48000000>; 1628 status = "disabled"; 1629 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; 1630 dma-names = "tx", "rx"; 1631 }; 1632 }; 1633 1634 target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */ 1635 compatible = "ti,sysc-omap2", "ti,sysc"; 1636 ti,hwmods = "uart2"; 1637 reg = <0x6c050 0x4>, 1638 <0x6c054 0x4>, 1639 <0x6c058 0x4>; 1640 reg-names = "rev", "sysc", "syss"; 1641 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1642 SYSC_OMAP2_SOFTRESET | 1643 SYSC_OMAP2_AUTOIDLE)>; 1644 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1645 <SYSC_IDLE_NO>, 1646 <SYSC_IDLE_SMART>, 1647 <SYSC_IDLE_SMART_WKUP>; 1648 ti,syss-mask = <1>; 1649 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1650 clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>; 1651 clock-names = "fck"; 1652 #address-cells = <1>; 1653 #size-cells = <1>; 1654 ranges = <0x0 0x6c000 0x1000>; 1655 1656 uart2: serial@0 { 1657 compatible = "ti,dra742-uart", "ti,omap4-uart"; 1658 reg = <0x0 0x100>; 1659 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1660 clock-frequency = <48000000>; 1661 status = "disabled"; 1662 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; 1663 dma-names = "tx", "rx"; 1664 }; 1665 }; 1666 1667 target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */ 1668 compatible = "ti,sysc-omap2", "ti,sysc"; 1669 ti,hwmods = "uart4"; 1670 reg = <0x6e050 0x4>, 1671 <0x6e054 0x4>, 1672 <0x6e058 0x4>; 1673 reg-names = "rev", "sysc", "syss"; 1674 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1675 SYSC_OMAP2_SOFTRESET | 1676 SYSC_OMAP2_AUTOIDLE)>; 1677 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1678 <SYSC_IDLE_NO>, 1679 <SYSC_IDLE_SMART>, 1680 <SYSC_IDLE_SMART_WKUP>; 1681 ti,syss-mask = <1>; 1682 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1683 clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>; 1684 clock-names = "fck"; 1685 #address-cells = <1>; 1686 #size-cells = <1>; 1687 ranges = <0x0 0x6e000 0x1000>; 1688 1689 uart4: serial@0 { 1690 compatible = "ti,dra742-uart", "ti,omap4-uart"; 1691 reg = <0x0 0x100>; 1692 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1693 clock-frequency = <48000000>; 1694 status = "disabled"; 1695 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; 1696 dma-names = "tx", "rx"; 1697 }; 1698 }; 1699 1700 target-module@70000 { /* 0x48070000, ap 30 22.0 */ 1701 compatible = "ti,sysc-omap2", "ti,sysc"; 1702 ti,hwmods = "i2c1"; 1703 reg = <0x70000 0x8>, 1704 <0x70010 0x8>, 1705 <0x70090 0x8>; 1706 reg-names = "rev", "sysc", "syss"; 1707 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1708 SYSC_OMAP2_ENAWAKEUP | 1709 SYSC_OMAP2_SOFTRESET | 1710 SYSC_OMAP2_AUTOIDLE)>; 1711 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1712 <SYSC_IDLE_NO>, 1713 <SYSC_IDLE_SMART>, 1714 <SYSC_IDLE_SMART_WKUP>; 1715 ti,syss-mask = <1>; 1716 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1717 clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>; 1718 clock-names = "fck"; 1719 #address-cells = <1>; 1720 #size-cells = <1>; 1721 ranges = <0x0 0x70000 0x1000>; 1722 1723 i2c1: i2c@0 { 1724 compatible = "ti,omap4-i2c"; 1725 reg = <0x0 0x100>; 1726 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 status = "disabled"; 1730 }; 1731 }; 1732 1733 target-module@72000 { /* 0x48072000, ap 32 2a.0 */ 1734 compatible = "ti,sysc-omap2", "ti,sysc"; 1735 ti,hwmods = "i2c2"; 1736 reg = <0x72000 0x8>, 1737 <0x72010 0x8>, 1738 <0x72090 0x8>; 1739 reg-names = "rev", "sysc", "syss"; 1740 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1741 SYSC_OMAP2_ENAWAKEUP | 1742 SYSC_OMAP2_SOFTRESET | 1743 SYSC_OMAP2_AUTOIDLE)>; 1744 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1745 <SYSC_IDLE_NO>, 1746 <SYSC_IDLE_SMART>, 1747 <SYSC_IDLE_SMART_WKUP>; 1748 ti,syss-mask = <1>; 1749 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1750 clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>; 1751 clock-names = "fck"; 1752 #address-cells = <1>; 1753 #size-cells = <1>; 1754 ranges = <0x0 0x72000 0x1000>; 1755 1756 i2c2: i2c@0 { 1757 compatible = "ti,omap4-i2c"; 1758 reg = <0x0 0x100>; 1759 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1760 #address-cells = <1>; 1761 #size-cells = <0>; 1762 status = "disabled"; 1763 }; 1764 }; 1765 1766 target-module@78000 { /* 0x48078000, ap 39 0a.0 */ 1767 compatible = "ti,sysc-omap2", "ti,sysc"; 1768 ti,hwmods = "elm"; 1769 reg = <0x78000 0x4>, 1770 <0x78010 0x4>, 1771 <0x78014 0x4>; 1772 reg-names = "rev", "sysc", "syss"; 1773 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1774 SYSC_OMAP2_SOFTRESET | 1775 SYSC_OMAP2_AUTOIDLE)>; 1776 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1777 <SYSC_IDLE_NO>, 1778 <SYSC_IDLE_SMART>, 1779 <SYSC_IDLE_SMART_WKUP>; 1780 ti,syss-mask = <1>; 1781 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1782 clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>; 1783 clock-names = "fck"; 1784 #address-cells = <1>; 1785 #size-cells = <1>; 1786 ranges = <0x0 0x78000 0x1000>; 1787 1788 elm: elm@0 { 1789 compatible = "ti,am3352-elm"; 1790 reg = <0x0 0xfc0>; /* device IO registers */ 1791 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1792 status = "disabled"; 1793 }; 1794 }; 1795 1796 target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */ 1797 compatible = "ti,sysc-omap2", "ti,sysc"; 1798 ti,hwmods = "i2c4"; 1799 reg = <0x7a000 0x8>, 1800 <0x7a010 0x8>, 1801 <0x7a090 0x8>; 1802 reg-names = "rev", "sysc", "syss"; 1803 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1804 SYSC_OMAP2_ENAWAKEUP | 1805 SYSC_OMAP2_SOFTRESET | 1806 SYSC_OMAP2_AUTOIDLE)>; 1807 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1808 <SYSC_IDLE_NO>, 1809 <SYSC_IDLE_SMART>, 1810 <SYSC_IDLE_SMART_WKUP>; 1811 ti,syss-mask = <1>; 1812 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1813 clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>; 1814 clock-names = "fck"; 1815 #address-cells = <1>; 1816 #size-cells = <1>; 1817 ranges = <0x0 0x7a000 0x1000>; 1818 1819 i2c4: i2c@0 { 1820 compatible = "ti,omap4-i2c"; 1821 reg = <0x0 0x100>; 1822 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 status = "disabled"; 1826 }; 1827 }; 1828 1829 target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */ 1830 compatible = "ti,sysc-omap2", "ti,sysc"; 1831 ti,hwmods = "i2c5"; 1832 reg = <0x7c000 0x8>, 1833 <0x7c010 0x8>, 1834 <0x7c090 0x8>; 1835 reg-names = "rev", "sysc", "syss"; 1836 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1837 SYSC_OMAP2_ENAWAKEUP | 1838 SYSC_OMAP2_SOFTRESET | 1839 SYSC_OMAP2_AUTOIDLE)>; 1840 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1841 <SYSC_IDLE_NO>, 1842 <SYSC_IDLE_SMART>, 1843 <SYSC_IDLE_SMART_WKUP>; 1844 ti,syss-mask = <1>; 1845 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 1846 clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>; 1847 clock-names = "fck"; 1848 #address-cells = <1>; 1849 #size-cells = <1>; 1850 ranges = <0x0 0x7c000 0x1000>; 1851 1852 i2c5: i2c@0 { 1853 compatible = "ti,omap4-i2c"; 1854 reg = <0x0 0x100>; 1855 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1856 #address-cells = <1>; 1857 #size-cells = <0>; 1858 status = "disabled"; 1859 }; 1860 }; 1861 1862 target-module@86000 { /* 0x48086000, ap 41 5e.0 */ 1863 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1864 ti,hwmods = "timer10"; 1865 reg = <0x86000 0x4>, 1866 <0x86010 0x4>; 1867 reg-names = "rev", "sysc"; 1868 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1869 SYSC_OMAP4_SOFTRESET)>; 1870 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1871 <SYSC_IDLE_NO>, 1872 <SYSC_IDLE_SMART>, 1873 <SYSC_IDLE_SMART_WKUP>; 1874 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1875 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>; 1876 clock-names = "fck"; 1877 #address-cells = <1>; 1878 #size-cells = <1>; 1879 ranges = <0x0 0x86000 0x1000>; 1880 1881 timer10: timer@0 { 1882 compatible = "ti,omap5430-timer"; 1883 reg = <0x0 0x80>; 1884 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>; 1885 clock-names = "fck"; 1886 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1887 }; 1888 }; 1889 1890 target-module@88000 { /* 0x48088000, ap 43 66.0 */ 1891 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1892 ti,hwmods = "timer11"; 1893 reg = <0x88000 0x4>, 1894 <0x88010 0x4>; 1895 reg-names = "rev", "sysc"; 1896 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1897 SYSC_OMAP4_SOFTRESET)>; 1898 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1899 <SYSC_IDLE_NO>, 1900 <SYSC_IDLE_SMART>, 1901 <SYSC_IDLE_SMART_WKUP>; 1902 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1903 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>; 1904 clock-names = "fck"; 1905 #address-cells = <1>; 1906 #size-cells = <1>; 1907 ranges = <0x0 0x88000 0x1000>; 1908 1909 timer11: timer@0 { 1910 compatible = "ti,omap5430-timer"; 1911 reg = <0x0 0x80>; 1912 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>; 1913 clock-names = "fck"; 1914 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1915 }; 1916 }; 1917 1918 target-module@90000 { /* 0x48090000, ap 55 12.0 */ 1919 compatible = "ti,sysc-omap2", "ti,sysc"; 1920 ti,hwmods = "rng"; 1921 reg = <0x91fe0 0x4>, 1922 <0x91fe4 0x4>; 1923 reg-names = "rev", "sysc"; 1924 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; 1925 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1926 <SYSC_IDLE_NO>; 1927 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 1928 clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>; 1929 clock-names = "fck"; 1930 #address-cells = <1>; 1931 #size-cells = <1>; 1932 ranges = <0x0 0x90000 0x2000>; 1933 1934 rng: rng@0 { 1935 compatible = "ti,omap4-rng"; 1936 reg = <0x0 0x2000>; 1937 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1938 clocks = <&l3_iclk_div>; 1939 clock-names = "fck"; 1940 }; 1941 }; 1942 1943 target-module@98000 { /* 0x48098000, ap 47 08.0 */ 1944 compatible = "ti,sysc-omap4", "ti,sysc"; 1945 ti,hwmods = "mcspi1"; 1946 reg = <0x98000 0x4>, 1947 <0x98010 0x4>; 1948 reg-names = "rev", "sysc"; 1949 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1950 SYSC_OMAP4_SOFTRESET)>; 1951 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1952 <SYSC_IDLE_NO>, 1953 <SYSC_IDLE_SMART>, 1954 <SYSC_IDLE_SMART_WKUP>; 1955 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1956 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>; 1957 clock-names = "fck"; 1958 #address-cells = <1>; 1959 #size-cells = <1>; 1960 ranges = <0x0 0x98000 0x1000>; 1961 1962 mcspi1: spi@0 { 1963 compatible = "ti,omap4-mcspi"; 1964 reg = <0x0 0x200>; 1965 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1966 #address-cells = <1>; 1967 #size-cells = <0>; 1968 ti,spi-num-cs = <4>; 1969 dmas = <&sdma_xbar 35>, 1970 <&sdma_xbar 36>, 1971 <&sdma_xbar 37>, 1972 <&sdma_xbar 38>, 1973 <&sdma_xbar 39>, 1974 <&sdma_xbar 40>, 1975 <&sdma_xbar 41>, 1976 <&sdma_xbar 42>; 1977 dma-names = "tx0", "rx0", "tx1", "rx1", 1978 "tx2", "rx2", "tx3", "rx3"; 1979 status = "disabled"; 1980 }; 1981 }; 1982 1983 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ 1984 compatible = "ti,sysc-omap4", "ti,sysc"; 1985 ti,hwmods = "mcspi2"; 1986 reg = <0x9a000 0x4>, 1987 <0x9a010 0x4>; 1988 reg-names = "rev", "sysc"; 1989 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1990 SYSC_OMAP4_SOFTRESET)>; 1991 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1992 <SYSC_IDLE_NO>, 1993 <SYSC_IDLE_SMART>, 1994 <SYSC_IDLE_SMART_WKUP>; 1995 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1996 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>; 1997 clock-names = "fck"; 1998 #address-cells = <1>; 1999 #size-cells = <1>; 2000 ranges = <0x0 0x9a000 0x1000>; 2001 2002 mcspi2: spi@0 { 2003 compatible = "ti,omap4-mcspi"; 2004 reg = <0x0 0x200>; 2005 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 2006 #address-cells = <1>; 2007 #size-cells = <0>; 2008 ti,spi-num-cs = <2>; 2009 dmas = <&sdma_xbar 43>, 2010 <&sdma_xbar 44>, 2011 <&sdma_xbar 45>, 2012 <&sdma_xbar 46>; 2013 dma-names = "tx0", "rx0", "tx1", "rx1"; 2014 status = "disabled"; 2015 }; 2016 }; 2017 2018 target-module@9c000 { /* 0x4809c000, ap 51 38.0 */ 2019 compatible = "ti,sysc-omap4", "ti,sysc"; 2020 ti,hwmods = "mmc1"; 2021 reg = <0x9c000 0x4>, 2022 <0x9c010 0x4>; 2023 reg-names = "rev", "sysc"; 2024 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2025 SYSC_OMAP4_SOFTRESET)>; 2026 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2027 <SYSC_IDLE_NO>, 2028 <SYSC_IDLE_SMART>, 2029 <SYSC_IDLE_SMART_WKUP>; 2030 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2031 <SYSC_IDLE_NO>, 2032 <SYSC_IDLE_SMART>, 2033 <SYSC_IDLE_SMART_WKUP>; 2034 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 2035 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>; 2036 clock-names = "fck"; 2037 #address-cells = <1>; 2038 #size-cells = <1>; 2039 ranges = <0x0 0x9c000 0x1000>; 2040 2041 mmc1: mmc@0 { 2042 compatible = "ti,dra7-sdhci"; 2043 reg = <0x0 0x400>; 2044 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 2045 status = "disabled"; 2046 pbias-supply = <&pbias_mmc_reg>; 2047 max-frequency = <192000000>; 2048 mmc-ddr-1_8v; 2049 mmc-ddr-3_3v; 2050 }; 2051 }; 2052 2053 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ 2054 compatible = "ti,sysc"; 2055 status = "disabled"; 2056 #address-cells = <1>; 2057 #size-cells = <1>; 2058 ranges = <0x0 0xa2000 0x1000>; 2059 }; 2060 2061 target-module@a4000 { /* 0x480a4000, ap 57 42.0 */ 2062 compatible = "ti,sysc"; 2063 status = "disabled"; 2064 #address-cells = <1>; 2065 #size-cells = <1>; 2066 ranges = <0x00000000 0x000a4000 0x00001000>, 2067 <0x00001000 0x000a5000 0x00001000>; 2068 }; 2069 2070 target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */ 2071 compatible = "ti,sysc"; 2072 status = "disabled"; 2073 #address-cells = <1>; 2074 #size-cells = <1>; 2075 ranges = <0x0 0xa8000 0x4000>; 2076 }; 2077 2078 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ 2079 compatible = "ti,sysc-omap4", "ti,sysc"; 2080 ti,hwmods = "mmc3"; 2081 reg = <0xad000 0x4>, 2082 <0xad010 0x4>; 2083 reg-names = "rev", "sysc"; 2084 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2085 SYSC_OMAP4_SOFTRESET)>; 2086 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2087 <SYSC_IDLE_NO>, 2088 <SYSC_IDLE_SMART>, 2089 <SYSC_IDLE_SMART_WKUP>; 2090 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2091 <SYSC_IDLE_NO>, 2092 <SYSC_IDLE_SMART>, 2093 <SYSC_IDLE_SMART_WKUP>; 2094 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2095 clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>; 2096 clock-names = "fck"; 2097 #address-cells = <1>; 2098 #size-cells = <1>; 2099 ranges = <0x0 0xad000 0x1000>; 2100 2101 mmc3: mmc@0 { 2102 compatible = "ti,dra7-sdhci"; 2103 reg = <0x0 0x400>; 2104 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 2105 status = "disabled"; 2106 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ 2107 max-frequency = <64000000>; 2108 /* SDMA is not supported */ 2109 sdhci-caps-mask = <0x0 0x400000>; 2110 }; 2111 }; 2112 2113 target-module@b2000 { /* 0x480b2000, ap 37 52.0 */ 2114 compatible = "ti,sysc-omap2", "ti,sysc"; 2115 ti,hwmods = "hdq1w"; 2116 reg = <0xb2000 0x4>, 2117 <0xb2014 0x4>, 2118 <0xb2018 0x4>; 2119 reg-names = "rev", "sysc", "syss"; 2120 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2121 SYSC_OMAP2_AUTOIDLE)>; 2122 ti,syss-mask = <1>; 2123 ti,no-reset-on-init; 2124 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2125 clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>; 2126 clock-names = "fck"; 2127 #address-cells = <1>; 2128 #size-cells = <1>; 2129 ranges = <0x0 0xb2000 0x1000>; 2130 2131 hdqw1w: 1w@0 { 2132 compatible = "ti,omap3-1w"; 2133 reg = <0x0 0x1000>; 2134 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2135 }; 2136 }; 2137 2138 target-module@b4000 { /* 0x480b4000, ap 65 40.0 */ 2139 compatible = "ti,sysc-omap4", "ti,sysc"; 2140 ti,hwmods = "mmc2"; 2141 reg = <0xb4000 0x4>, 2142 <0xb4010 0x4>; 2143 reg-names = "rev", "sysc"; 2144 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2145 SYSC_OMAP4_SOFTRESET)>; 2146 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2147 <SYSC_IDLE_NO>, 2148 <SYSC_IDLE_SMART>, 2149 <SYSC_IDLE_SMART_WKUP>; 2150 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2151 <SYSC_IDLE_NO>, 2152 <SYSC_IDLE_SMART>, 2153 <SYSC_IDLE_SMART_WKUP>; 2154 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 2155 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>; 2156 clock-names = "fck"; 2157 #address-cells = <1>; 2158 #size-cells = <1>; 2159 ranges = <0x0 0xb4000 0x1000>; 2160 2161 mmc2: mmc@0 { 2162 compatible = "ti,dra7-sdhci"; 2163 reg = <0x0 0x400>; 2164 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2165 status = "disabled"; 2166 max-frequency = <192000000>; 2167 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ 2168 sdhci-caps-mask = <0x7 0x0>; 2169 mmc-hs200-1_8v; 2170 mmc-ddr-1_8v; 2171 mmc-ddr-3_3v; 2172 }; 2173 }; 2174 2175 target-module@b8000 { /* 0x480b8000, ap 67 48.0 */ 2176 compatible = "ti,sysc-omap4", "ti,sysc"; 2177 ti,hwmods = "mcspi3"; 2178 reg = <0xb8000 0x4>, 2179 <0xb8010 0x4>; 2180 reg-names = "rev", "sysc"; 2181 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2182 SYSC_OMAP4_SOFTRESET)>; 2183 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2184 <SYSC_IDLE_NO>, 2185 <SYSC_IDLE_SMART>, 2186 <SYSC_IDLE_SMART_WKUP>; 2187 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2188 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>; 2189 clock-names = "fck"; 2190 #address-cells = <1>; 2191 #size-cells = <1>; 2192 ranges = <0x0 0xb8000 0x1000>; 2193 2194 mcspi3: spi@0 { 2195 compatible = "ti,omap4-mcspi"; 2196 reg = <0x0 0x200>; 2197 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2198 #address-cells = <1>; 2199 #size-cells = <0>; 2200 ti,spi-num-cs = <2>; 2201 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; 2202 dma-names = "tx0", "rx0"; 2203 status = "disabled"; 2204 }; 2205 }; 2206 2207 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ 2208 compatible = "ti,sysc-omap4", "ti,sysc"; 2209 ti,hwmods = "mcspi4"; 2210 reg = <0xba000 0x4>, 2211 <0xba010 0x4>; 2212 reg-names = "rev", "sysc"; 2213 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2214 SYSC_OMAP4_SOFTRESET)>; 2215 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2216 <SYSC_IDLE_NO>, 2217 <SYSC_IDLE_SMART>, 2218 <SYSC_IDLE_SMART_WKUP>; 2219 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2220 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>; 2221 clock-names = "fck"; 2222 #address-cells = <1>; 2223 #size-cells = <1>; 2224 ranges = <0x0 0xba000 0x1000>; 2225 2226 mcspi4: spi@0 { 2227 compatible = "ti,omap4-mcspi"; 2228 reg = <0x0 0x200>; 2229 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 2230 #address-cells = <1>; 2231 #size-cells = <0>; 2232 ti,spi-num-cs = <1>; 2233 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; 2234 dma-names = "tx0", "rx0"; 2235 status = "disabled"; 2236 }; 2237 }; 2238 2239 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ 2240 compatible = "ti,sysc-omap4", "ti,sysc"; 2241 ti,hwmods = "mmc4"; 2242 reg = <0xd1000 0x4>, 2243 <0xd1010 0x4>; 2244 reg-names = "rev", "sysc"; 2245 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2246 SYSC_OMAP4_SOFTRESET)>; 2247 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2248 <SYSC_IDLE_NO>, 2249 <SYSC_IDLE_SMART>, 2250 <SYSC_IDLE_SMART_WKUP>; 2251 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2252 <SYSC_IDLE_NO>, 2253 <SYSC_IDLE_SMART>, 2254 <SYSC_IDLE_SMART_WKUP>; 2255 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2256 clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>; 2257 clock-names = "fck"; 2258 #address-cells = <1>; 2259 #size-cells = <1>; 2260 ranges = <0x0 0xd1000 0x1000>; 2261 2262 mmc4: mmc@0 { 2263 compatible = "ti,dra7-sdhci"; 2264 reg = <0x0 0x400>; 2265 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2266 status = "disabled"; 2267 max-frequency = <192000000>; 2268 /* SDMA is not supported */ 2269 sdhci-caps-mask = <0x0 0x400000>; 2270 }; 2271 }; 2272 2273 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ 2274 compatible = "ti,sysc"; 2275 status = "disabled"; 2276 #address-cells = <1>; 2277 #size-cells = <1>; 2278 ranges = <0x0 0xd5000 0x1000>; 2279 }; 2280 }; 2281 2282 segment@200000 { /* 0x48200000 */ 2283 compatible = "simple-bus"; 2284 #address-cells = <1>; 2285 #size-cells = <1>; 2286 }; 2287}; 2288 2289&l4_per2 { /* 0x48400000 */ 2290 compatible = "ti,dra7-l4-per2", "simple-bus"; 2291 reg = <0x48400000 0x800>, 2292 <0x48400800 0x800>, 2293 <0x48401000 0x400>, 2294 <0x48401400 0x400>, 2295 <0x48401800 0x400>; 2296 reg-names = "ap", "la", "ia0", "ia1", "ia2"; 2297 #address-cells = <1>; 2298 #size-cells = <1>; 2299 ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */ 2300 <0x45800000 0x45800000 0x400000>, /* L3 data port */ 2301 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ 2302 <0x46000000 0x46000000 0x400000>, /* L3 data port */ 2303 <0x48436000 0x48436000 0x400000>, /* L3 data port */ 2304 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ 2305 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ 2306 <0x48450000 0x48450000 0x400000>, /* L3 data port */ 2307 <0x48454000 0x48454000 0x400000>; /* L3 data port */ 2308 2309 segment@0 { /* 0x48400000 */ 2310 compatible = "simple-bus"; 2311 #address-cells = <1>; 2312 #size-cells = <1>; 2313 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 2314 <0x00001000 0x00001000 0x000400>, /* ap 1 */ 2315 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 2316 <0x00084000 0x00084000 0x004000>, /* ap 3 */ 2317 <0x00001400 0x00001400 0x000400>, /* ap 4 */ 2318 <0x00001800 0x00001800 0x000400>, /* ap 5 */ 2319 <0x00088000 0x00088000 0x001000>, /* ap 6 */ 2320 <0x0002c000 0x0002c000 0x001000>, /* ap 7 */ 2321 <0x0002d000 0x0002d000 0x001000>, /* ap 8 */ 2322 <0x00060000 0x00060000 0x002000>, /* ap 9 */ 2323 <0x00062000 0x00062000 0x001000>, /* ap 10 */ 2324 <0x00064000 0x00064000 0x002000>, /* ap 11 */ 2325 <0x00066000 0x00066000 0x001000>, /* ap 12 */ 2326 <0x00068000 0x00068000 0x002000>, /* ap 13 */ 2327 <0x0006a000 0x0006a000 0x001000>, /* ap 14 */ 2328 <0x0006c000 0x0006c000 0x002000>, /* ap 15 */ 2329 <0x0006e000 0x0006e000 0x001000>, /* ap 16 */ 2330 <0x00036000 0x00036000 0x001000>, /* ap 17 */ 2331 <0x00037000 0x00037000 0x001000>, /* ap 18 */ 2332 <0x00070000 0x00070000 0x002000>, /* ap 19 */ 2333 <0x00072000 0x00072000 0x001000>, /* ap 20 */ 2334 <0x0003a000 0x0003a000 0x001000>, /* ap 21 */ 2335 <0x0003b000 0x0003b000 0x001000>, /* ap 22 */ 2336 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ 2337 <0x0003d000 0x0003d000 0x001000>, /* ap 24 */ 2338 <0x0003e000 0x0003e000 0x001000>, /* ap 25 */ 2339 <0x0003f000 0x0003f000 0x001000>, /* ap 26 */ 2340 <0x00040000 0x00040000 0x001000>, /* ap 27 */ 2341 <0x00041000 0x00041000 0x001000>, /* ap 28 */ 2342 <0x00042000 0x00042000 0x001000>, /* ap 29 */ 2343 <0x00043000 0x00043000 0x001000>, /* ap 30 */ 2344 <0x00080000 0x00080000 0x002000>, /* ap 31 */ 2345 <0x00082000 0x00082000 0x001000>, /* ap 32 */ 2346 <0x0004a000 0x0004a000 0x001000>, /* ap 33 */ 2347 <0x0004b000 0x0004b000 0x001000>, /* ap 34 */ 2348 <0x00074000 0x00074000 0x002000>, /* ap 35 */ 2349 <0x00076000 0x00076000 0x001000>, /* ap 36 */ 2350 <0x00050000 0x00050000 0x001000>, /* ap 37 */ 2351 <0x00051000 0x00051000 0x001000>, /* ap 38 */ 2352 <0x00078000 0x00078000 0x002000>, /* ap 39 */ 2353 <0x0007a000 0x0007a000 0x001000>, /* ap 40 */ 2354 <0x00054000 0x00054000 0x001000>, /* ap 41 */ 2355 <0x00055000 0x00055000 0x001000>, /* ap 42 */ 2356 <0x0007c000 0x0007c000 0x002000>, /* ap 43 */ 2357 <0x0007e000 0x0007e000 0x001000>, /* ap 44 */ 2358 <0x0004c000 0x0004c000 0x001000>, /* ap 45 */ 2359 <0x0004d000 0x0004d000 0x001000>, /* ap 46 */ 2360 <0x00020000 0x00020000 0x001000>, /* ap 47 */ 2361 <0x00021000 0x00021000 0x001000>, /* ap 48 */ 2362 <0x00022000 0x00022000 0x001000>, /* ap 49 */ 2363 <0x00023000 0x00023000 0x001000>, /* ap 50 */ 2364 <0x00024000 0x00024000 0x001000>, /* ap 51 */ 2365 <0x00025000 0x00025000 0x001000>, /* ap 52 */ 2366 <0x00046000 0x00046000 0x001000>, /* ap 53 */ 2367 <0x00047000 0x00047000 0x001000>, /* ap 54 */ 2368 <0x00048000 0x00048000 0x001000>, /* ap 55 */ 2369 <0x00049000 0x00049000 0x001000>, /* ap 56 */ 2370 <0x00058000 0x00058000 0x002000>, /* ap 57 */ 2371 <0x0005a000 0x0005a000 0x001000>, /* ap 58 */ 2372 <0x0005b000 0x0005b000 0x001000>, /* ap 59 */ 2373 <0x0005c000 0x0005c000 0x001000>, /* ap 60 */ 2374 <0x0005d000 0x0005d000 0x001000>, /* ap 61 */ 2375 <0x0005e000 0x0005e000 0x001000>, /* ap 62 */ 2376 <0x45800000 0x45800000 0x400000>, /* L3 data port */ 2377 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ 2378 <0x46000000 0x46000000 0x400000>, /* L3 data port */ 2379 <0x48436000 0x48436000 0x400000>, /* L3 data port */ 2380 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ 2381 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ 2382 <0x48450000 0x48450000 0x400000>, /* L3 data port */ 2383 <0x48454000 0x48454000 0x400000>; /* L3 data port */ 2384 2385 target-module@20000 { /* 0x48420000, ap 47 02.0 */ 2386 compatible = "ti,sysc-omap2", "ti,sysc"; 2387 ti,hwmods = "uart7"; 2388 reg = <0x20050 0x4>, 2389 <0x20054 0x4>, 2390 <0x20058 0x4>; 2391 reg-names = "rev", "sysc", "syss"; 2392 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2393 SYSC_OMAP2_SOFTRESET | 2394 SYSC_OMAP2_AUTOIDLE)>; 2395 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2396 <SYSC_IDLE_NO>, 2397 <SYSC_IDLE_SMART>, 2398 <SYSC_IDLE_SMART_WKUP>; 2399 ti,syss-mask = <1>; 2400 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2401 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>; 2402 clock-names = "fck"; 2403 #address-cells = <1>; 2404 #size-cells = <1>; 2405 ranges = <0x0 0x20000 0x1000>; 2406 2407 uart7: serial@0 { 2408 compatible = "ti,dra742-uart", "ti,omap4-uart"; 2409 reg = <0x0 0x100>; 2410 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 2411 clock-frequency = <48000000>; 2412 status = "disabled"; 2413 }; 2414 }; 2415 2416 target-module@22000 { /* 0x48422000, ap 49 0a.0 */ 2417 compatible = "ti,sysc-omap2", "ti,sysc"; 2418 ti,hwmods = "uart8"; 2419 reg = <0x22050 0x4>, 2420 <0x22054 0x4>, 2421 <0x22058 0x4>; 2422 reg-names = "rev", "sysc", "syss"; 2423 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2424 SYSC_OMAP2_SOFTRESET | 2425 SYSC_OMAP2_AUTOIDLE)>; 2426 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2427 <SYSC_IDLE_NO>, 2428 <SYSC_IDLE_SMART>, 2429 <SYSC_IDLE_SMART_WKUP>; 2430 ti,syss-mask = <1>; 2431 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2432 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>; 2433 clock-names = "fck"; 2434 #address-cells = <1>; 2435 #size-cells = <1>; 2436 ranges = <0x0 0x22000 0x1000>; 2437 2438 uart8: serial@0 { 2439 compatible = "ti,dra742-uart", "ti,omap4-uart"; 2440 reg = <0x0 0x100>; 2441 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 2442 clock-frequency = <48000000>; 2443 status = "disabled"; 2444 }; 2445 }; 2446 2447 target-module@24000 { /* 0x48424000, ap 51 12.0 */ 2448 compatible = "ti,sysc-omap2", "ti,sysc"; 2449 ti,hwmods = "uart9"; 2450 reg = <0x24050 0x4>, 2451 <0x24054 0x4>, 2452 <0x24058 0x4>; 2453 reg-names = "rev", "sysc", "syss"; 2454 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2455 SYSC_OMAP2_SOFTRESET | 2456 SYSC_OMAP2_AUTOIDLE)>; 2457 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2458 <SYSC_IDLE_NO>, 2459 <SYSC_IDLE_SMART>, 2460 <SYSC_IDLE_SMART_WKUP>; 2461 ti,syss-mask = <1>; 2462 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2463 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>; 2464 clock-names = "fck"; 2465 #address-cells = <1>; 2466 #size-cells = <1>; 2467 ranges = <0x0 0x24000 0x1000>; 2468 2469 uart9: serial@0 { 2470 compatible = "ti,dra742-uart", "ti,omap4-uart"; 2471 reg = <0x0 0x100>; 2472 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 2473 clock-frequency = <48000000>; 2474 status = "disabled"; 2475 }; 2476 }; 2477 2478 target-module@2c000 { /* 0x4842c000, ap 7 18.0 */ 2479 compatible = "ti,sysc"; 2480 status = "disabled"; 2481 #address-cells = <1>; 2482 #size-cells = <1>; 2483 ranges = <0x0 0x2c000 0x1000>; 2484 }; 2485 2486 target-module@36000 { /* 0x48436000, ap 17 06.0 */ 2487 compatible = "ti,sysc"; 2488 status = "disabled"; 2489 #address-cells = <1>; 2490 #size-cells = <1>; 2491 ranges = <0x0 0x36000 0x1000>; 2492 }; 2493 2494 target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */ 2495 compatible = "ti,sysc"; 2496 status = "disabled"; 2497 #address-cells = <1>; 2498 #size-cells = <1>; 2499 ranges = <0x0 0x3a000 0x1000>; 2500 }; 2501 2502 target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ 2503 compatible = "ti,sysc-omap4", "ti,sysc"; 2504 reg = <0x3c000 0x4>; 2505 reg-names = "rev"; 2506 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>; 2507 clock-names = "fck"; 2508 #address-cells = <1>; 2509 #size-cells = <1>; 2510 ranges = <0x0 0x3c000 0x1000>; 2511 2512 atl: atl@0 { 2513 compatible = "ti,dra7-atl"; 2514 reg = <0x0 0x3ff>; 2515 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, 2516 <&atl_clkin2_ck>, <&atl_clkin3_ck>; 2517 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 2518 clock-names = "fck"; 2519 status = "disabled"; 2520 }; 2521 }; 2522 2523 target-module@3e000 { /* 0x4843e000, ap 25 30.0 */ 2524 compatible = "ti,sysc-omap4", "ti,sysc"; 2525 ti,hwmods = "epwmss0"; 2526 reg = <0x3e000 0x4>, 2527 <0x3e004 0x4>; 2528 reg-names = "rev", "sysc"; 2529 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2530 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2531 <SYSC_IDLE_NO>, 2532 <SYSC_IDLE_SMART>; 2533 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2534 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>; 2535 clock-names = "fck"; 2536 #address-cells = <1>; 2537 #size-cells = <1>; 2538 ranges = <0x0 0x3e000 0x1000>; 2539 2540 epwmss0: epwmss@0 { 2541 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 2542 reg = <0x0 0x30>; 2543 #address-cells = <1>; 2544 #size-cells = <1>; 2545 status = "disabled"; 2546 ranges = <0 0 0x1000>; 2547 2548 ecap0: ecap@100 { 2549 compatible = "ti,dra746-ecap", 2550 "ti,am3352-ecap"; 2551 #pwm-cells = <3>; 2552 reg = <0x100 0x80>; 2553 clocks = <&l4_root_clk_div>; 2554 clock-names = "fck"; 2555 status = "disabled"; 2556 }; 2557 2558 ehrpwm0: pwm@200 { 2559 compatible = "ti,dra746-ehrpwm", 2560 "ti,am3352-ehrpwm"; 2561 #pwm-cells = <3>; 2562 reg = <0x200 0x80>; 2563 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; 2564 clock-names = "tbclk", "fck"; 2565 status = "disabled"; 2566 }; 2567 }; 2568 }; 2569 2570 target-module@40000 { /* 0x48440000, ap 27 38.0 */ 2571 compatible = "ti,sysc-omap4", "ti,sysc"; 2572 ti,hwmods = "epwmss1"; 2573 reg = <0x40000 0x4>, 2574 <0x40004 0x4>; 2575 reg-names = "rev", "sysc"; 2576 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2577 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2578 <SYSC_IDLE_NO>, 2579 <SYSC_IDLE_SMART>; 2580 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2581 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>; 2582 clock-names = "fck"; 2583 #address-cells = <1>; 2584 #size-cells = <1>; 2585 ranges = <0x0 0x40000 0x1000>; 2586 2587 epwmss1: epwmss@0 { 2588 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 2589 reg = <0x0 0x30>; 2590 #address-cells = <1>; 2591 #size-cells = <1>; 2592 status = "disabled"; 2593 ranges = <0 0 0x1000>; 2594 2595 ecap1: ecap@100 { 2596 compatible = "ti,dra746-ecap", 2597 "ti,am3352-ecap"; 2598 #pwm-cells = <3>; 2599 reg = <0x100 0x80>; 2600 clocks = <&l4_root_clk_div>; 2601 clock-names = "fck"; 2602 status = "disabled"; 2603 }; 2604 2605 ehrpwm1: pwm@200 { 2606 compatible = "ti,dra746-ehrpwm", 2607 "ti,am3352-ehrpwm"; 2608 #pwm-cells = <3>; 2609 reg = <0x200 0x80>; 2610 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; 2611 clock-names = "tbclk", "fck"; 2612 status = "disabled"; 2613 }; 2614 }; 2615 }; 2616 2617 target-module@42000 { /* 0x48442000, ap 29 20.0 */ 2618 compatible = "ti,sysc-omap4", "ti,sysc"; 2619 ti,hwmods = "epwmss2"; 2620 reg = <0x42000 0x4>, 2621 <0x42004 0x4>; 2622 reg-names = "rev", "sysc"; 2623 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2624 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2625 <SYSC_IDLE_NO>, 2626 <SYSC_IDLE_SMART>; 2627 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2628 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>; 2629 clock-names = "fck"; 2630 #address-cells = <1>; 2631 #size-cells = <1>; 2632 ranges = <0x0 0x42000 0x1000>; 2633 2634 epwmss2: epwmss@0 { 2635 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 2636 reg = <0x0 0x30>; 2637 #address-cells = <1>; 2638 #size-cells = <1>; 2639 status = "disabled"; 2640 ranges = <0 0 0x1000>; 2641 2642 ecap2: ecap@100 { 2643 compatible = "ti,dra746-ecap", 2644 "ti,am3352-ecap"; 2645 #pwm-cells = <3>; 2646 reg = <0x100 0x80>; 2647 clocks = <&l4_root_clk_div>; 2648 clock-names = "fck"; 2649 status = "disabled"; 2650 }; 2651 2652 ehrpwm2: pwm@200 { 2653 compatible = "ti,dra746-ehrpwm", 2654 "ti,am3352-ehrpwm"; 2655 #pwm-cells = <3>; 2656 reg = <0x200 0x80>; 2657 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; 2658 clock-names = "tbclk", "fck"; 2659 status = "disabled"; 2660 }; 2661 }; 2662 }; 2663 2664 target-module@46000 { /* 0x48446000, ap 53 40.0 */ 2665 compatible = "ti,sysc"; 2666 status = "disabled"; 2667 #address-cells = <1>; 2668 #size-cells = <1>; 2669 ranges = <0x0 0x46000 0x1000>; 2670 }; 2671 2672 target-module@48000 { /* 0x48448000, ap 55 48.0 */ 2673 compatible = "ti,sysc"; 2674 status = "disabled"; 2675 #address-cells = <1>; 2676 #size-cells = <1>; 2677 ranges = <0x0 0x48000 0x1000>; 2678 }; 2679 2680 target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */ 2681 compatible = "ti,sysc"; 2682 status = "disabled"; 2683 #address-cells = <1>; 2684 #size-cells = <1>; 2685 ranges = <0x0 0x4a000 0x1000>; 2686 }; 2687 2688 target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */ 2689 compatible = "ti,sysc"; 2690 status = "disabled"; 2691 #address-cells = <1>; 2692 #size-cells = <1>; 2693 ranges = <0x0 0x4c000 0x1000>; 2694 }; 2695 2696 target-module@50000 { /* 0x48450000, ap 37 24.0 */ 2697 compatible = "ti,sysc"; 2698 status = "disabled"; 2699 #address-cells = <1>; 2700 #size-cells = <1>; 2701 ranges = <0x0 0x50000 0x1000>; 2702 }; 2703 2704 target-module@54000 { /* 0x48454000, ap 41 2c.0 */ 2705 compatible = "ti,sysc"; 2706 status = "disabled"; 2707 #address-cells = <1>; 2708 #size-cells = <1>; 2709 ranges = <0x0 0x54000 0x1000>; 2710 }; 2711 2712 target-module@58000 { /* 0x48458000, ap 57 28.0 */ 2713 compatible = "ti,sysc"; 2714 status = "disabled"; 2715 #address-cells = <1>; 2716 #size-cells = <1>; 2717 ranges = <0x0 0x58000 0x2000>; 2718 }; 2719 2720 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ 2721 compatible = "ti,sysc"; 2722 status = "disabled"; 2723 #address-cells = <1>; 2724 #size-cells = <1>; 2725 ranges = <0x0 0x5b000 0x1000>; 2726 }; 2727 2728 target-module@5d000 { /* 0x4845d000, ap 61 22.0 */ 2729 compatible = "ti,sysc"; 2730 status = "disabled"; 2731 #address-cells = <1>; 2732 #size-cells = <1>; 2733 ranges = <0x0 0x5d000 0x1000>; 2734 }; 2735 2736 target-module@60000 { /* 0x48460000, ap 9 0e.0 */ 2737 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2738 ti,hwmods = "mcasp1"; 2739 reg = <0x60000 0x4>, 2740 <0x60004 0x4>; 2741 reg-names = "rev", "sysc"; 2742 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2743 <SYSC_IDLE_NO>, 2744 <SYSC_IDLE_SMART>; 2745 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 2746 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, 2747 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2748 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; 2749 clock-names = "fck", "ahclkx", "ahclkr"; 2750 #address-cells = <1>; 2751 #size-cells = <1>; 2752 ranges = <0x0 0x60000 0x2000>, 2753 <0x45800000 0x45800000 0x400000>; 2754 2755 mcasp1: mcasp@0 { 2756 compatible = "ti,dra7-mcasp-audio"; 2757 reg = <0x0 0x2000>, 2758 <0x45800000 0x1000>; /* L3 data port */ 2759 reg-names = "mpu","dat"; 2760 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2761 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2762 interrupt-names = "tx", "rx"; 2763 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; 2764 dma-names = "tx", "rx"; 2765 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>, 2766 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2767 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; 2768 clock-names = "fck", "ahclkx", "ahclkr"; 2769 status = "disabled"; 2770 }; 2771 }; 2772 2773 target-module@64000 { /* 0x48464000, ap 11 1e.0 */ 2774 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2775 ti,hwmods = "mcasp2"; 2776 reg = <0x64000 0x4>, 2777 <0x64004 0x4>; 2778 reg-names = "rev", "sysc"; 2779 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2780 <SYSC_IDLE_NO>, 2781 <SYSC_IDLE_SMART>; 2782 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2783 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, 2784 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, 2785 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; 2786 clock-names = "fck", "ahclkx", "ahclkr"; 2787 #address-cells = <1>; 2788 #size-cells = <1>; 2789 ranges = <0x0 0x64000 0x2000>, 2790 <0x45c00000 0x45c00000 0x400000>; 2791 2792 mcasp2: mcasp@0 { 2793 compatible = "ti,dra7-mcasp-audio"; 2794 reg = <0x0 0x2000>, 2795 <0x45c00000 0x1000>; /* L3 data port */ 2796 reg-names = "mpu","dat"; 2797 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2798 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2799 interrupt-names = "tx", "rx"; 2800 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; 2801 dma-names = "tx", "rx"; 2802 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>, 2803 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, 2804 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; 2805 clock-names = "fck", "ahclkx", "ahclkr"; 2806 status = "disabled"; 2807 }; 2808 }; 2809 2810 target-module@68000 { /* 0x48468000, ap 13 26.0 */ 2811 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2812 ti,hwmods = "mcasp3"; 2813 reg = <0x68000 0x4>, 2814 <0x68004 0x4>; 2815 reg-names = "rev", "sysc"; 2816 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2817 <SYSC_IDLE_NO>, 2818 <SYSC_IDLE_SMART>; 2819 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2820 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, 2821 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>, 2822 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>; 2823 clock-names = "fck", "ahclkx", "ahclkr"; 2824 #address-cells = <1>; 2825 #size-cells = <1>; 2826 ranges = <0x0 0x68000 0x2000>, 2827 <0x46000000 0x46000000 0x400000>; 2828 2829 mcasp3: mcasp@0 { 2830 compatible = "ti,dra7-mcasp-audio"; 2831 reg = <0x0 0x2000>, 2832 <0x46000000 0x1000>; /* L3 data port */ 2833 reg-names = "mpu","dat"; 2834 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2835 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2836 interrupt-names = "tx", "rx"; 2837 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; 2838 dma-names = "tx", "rx"; 2839 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>, 2840 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 2841 clock-names = "fck", "ahclkx"; 2842 status = "disabled"; 2843 }; 2844 }; 2845 2846 target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ 2847 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2848 ti,hwmods = "mcasp4"; 2849 reg = <0x6c000 0x4>, 2850 <0x6c004 0x4>; 2851 reg-names = "rev", "sysc"; 2852 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2853 <SYSC_IDLE_NO>, 2854 <SYSC_IDLE_SMART>; 2855 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2856 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, 2857 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>, 2858 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>; 2859 clock-names = "fck", "ahclkx", "ahclkr"; 2860 #address-cells = <1>; 2861 #size-cells = <1>; 2862 ranges = <0x0 0x6c000 0x2000>, 2863 <0x48436000 0x48436000 0x400000>; 2864 2865 mcasp4: mcasp@0 { 2866 compatible = "ti,dra7-mcasp-audio"; 2867 reg = <0x0 0x2000>, 2868 <0x48436000 0x1000>; /* L3 data port */ 2869 reg-names = "mpu","dat"; 2870 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 2871 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2872 interrupt-names = "tx", "rx"; 2873 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; 2874 dma-names = "tx", "rx"; 2875 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>, 2876 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; 2877 clock-names = "fck", "ahclkx"; 2878 status = "disabled"; 2879 }; 2880 }; 2881 2882 target-module@70000 { /* 0x48470000, ap 19 36.0 */ 2883 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2884 ti,hwmods = "mcasp5"; 2885 reg = <0x70000 0x4>, 2886 <0x70004 0x4>; 2887 reg-names = "rev", "sysc"; 2888 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2889 <SYSC_IDLE_NO>, 2890 <SYSC_IDLE_SMART>; 2891 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2892 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, 2893 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>, 2894 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>; 2895 clock-names = "fck", "ahclkx", "ahclkr"; 2896 #address-cells = <1>; 2897 #size-cells = <1>; 2898 ranges = <0x0 0x70000 0x2000>, 2899 <0x4843a000 0x4843a000 0x400000>; 2900 2901 mcasp5: mcasp@0 { 2902 compatible = "ti,dra7-mcasp-audio"; 2903 reg = <0x0 0x2000>, 2904 <0x4843a000 0x1000>; /* L3 data port */ 2905 reg-names = "mpu","dat"; 2906 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 2907 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 2908 interrupt-names = "tx", "rx"; 2909 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; 2910 dma-names = "tx", "rx"; 2911 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>, 2912 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; 2913 clock-names = "fck", "ahclkx"; 2914 status = "disabled"; 2915 }; 2916 }; 2917 2918 target-module@74000 { /* 0x48474000, ap 35 14.0 */ 2919 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2920 ti,hwmods = "mcasp6"; 2921 reg = <0x74000 0x4>, 2922 <0x74004 0x4>; 2923 reg-names = "rev", "sysc"; 2924 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2925 <SYSC_IDLE_NO>, 2926 <SYSC_IDLE_SMART>; 2927 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2928 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, 2929 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>, 2930 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>; 2931 clock-names = "fck", "ahclkx", "ahclkr"; 2932 #address-cells = <1>; 2933 #size-cells = <1>; 2934 ranges = <0x0 0x74000 0x2000>, 2935 <0x4844c000 0x4844c000 0x400000>; 2936 2937 mcasp6: mcasp@0 { 2938 compatible = "ti,dra7-mcasp-audio"; 2939 reg = <0x0 0x2000>, 2940 <0x4844c000 0x1000>; /* L3 data port */ 2941 reg-names = "mpu","dat"; 2942 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 2943 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 2944 interrupt-names = "tx", "rx"; 2945 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; 2946 dma-names = "tx", "rx"; 2947 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>, 2948 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; 2949 clock-names = "fck", "ahclkx"; 2950 status = "disabled"; 2951 }; 2952 }; 2953 2954 target-module@78000 { /* 0x48478000, ap 39 0c.0 */ 2955 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2956 ti,hwmods = "mcasp7"; 2957 reg = <0x78000 0x4>, 2958 <0x78004 0x4>; 2959 reg-names = "rev", "sysc"; 2960 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2961 <SYSC_IDLE_NO>, 2962 <SYSC_IDLE_SMART>; 2963 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2964 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, 2965 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>, 2966 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>; 2967 clock-names = "fck", "ahclkx", "ahclkr"; 2968 #address-cells = <1>; 2969 #size-cells = <1>; 2970 ranges = <0x0 0x78000 0x2000>, 2971 <0x48450000 0x48450000 0x400000>; 2972 2973 mcasp7: mcasp@0 { 2974 compatible = "ti,dra7-mcasp-audio"; 2975 reg = <0x0 0x2000>, 2976 <0x48450000 0x1000>; /* L3 data port */ 2977 reg-names = "mpu","dat"; 2978 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 2979 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2980 interrupt-names = "tx", "rx"; 2981 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; 2982 dma-names = "tx", "rx"; 2983 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>, 2984 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; 2985 clock-names = "fck", "ahclkx"; 2986 status = "disabled"; 2987 }; 2988 }; 2989 2990 target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ 2991 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2992 ti,hwmods = "mcasp8"; 2993 reg = <0x7c000 0x4>, 2994 <0x7c004 0x4>; 2995 reg-names = "rev", "sysc"; 2996 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2997 <SYSC_IDLE_NO>, 2998 <SYSC_IDLE_SMART>; 2999 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 3000 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, 3001 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>, 3002 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>; 3003 clock-names = "fck", "ahclkx", "ahclkr"; 3004 #address-cells = <1>; 3005 #size-cells = <1>; 3006 ranges = <0x0 0x7c000 0x2000>, 3007 <0x48454000 0x48454000 0x400000>; 3008 3009 mcasp8: mcasp@0 { 3010 compatible = "ti,dra7-mcasp-audio"; 3011 reg = <0x0 0x2000>, 3012 <0x48454000 0x1000>; /* L3 data port */ 3013 reg-names = "mpu","dat"; 3014 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 3015 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 3016 interrupt-names = "tx", "rx"; 3017 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; 3018 dma-names = "tx", "rx"; 3019 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>, 3020 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; 3021 clock-names = "fck", "ahclkx"; 3022 status = "disabled"; 3023 }; 3024 }; 3025 3026 target-module@80000 { /* 0x48480000, ap 31 16.0 */ 3027 compatible = "ti,sysc-omap4", "ti,sysc"; 3028 reg = <0x80000 0x4>; 3029 reg-names = "rev"; 3030 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>; 3031 clock-names = "fck"; 3032 #address-cells = <1>; 3033 #size-cells = <1>; 3034 ranges = <0x0 0x80000 0x2000>; 3035 3036 dcan2: can@0 { 3037 compatible = "ti,dra7-d_can"; 3038 reg = <0x0 0x2000>; 3039 syscon-raminit = <&scm_conf 0x558 1>; 3040 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 3041 clocks = <&sys_clkin1>; 3042 status = "disabled"; 3043 }; 3044 }; 3045 3046 target-module@84000 { /* 0x48484000, ap 3 10.0 */ 3047 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 3048 ti,hwmods = "gmac"; 3049 reg = <0x85200 0x4>, 3050 <0x85208 0x4>, 3051 <0x85204 0x4>; 3052 reg-names = "rev", "sysc", "syss"; 3053 ti,sysc-mask = <0>; 3054 ti,sysc-midle = <SYSC_IDLE_FORCE>, 3055 <SYSC_IDLE_NO>; 3056 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3057 <SYSC_IDLE_NO>; 3058 ti,syss-mask = <1>; 3059 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; 3060 clock-names = "fck"; 3061 #address-cells = <1>; 3062 #size-cells = <1>; 3063 ranges = <0x0 0x84000 0x4000>; 3064 /* 3065 * Do not allow gating of cpsw clock as workaround 3066 * for errata i877. Keeping internal clock disabled 3067 * causes the device switching characteristics 3068 * to degrade over time and eventually fail to meet 3069 * the data manual delay time/skew specs. 3070 */ 3071 ti,no-idle; 3072 3073 mac: ethernet@0 { 3074 compatible = "ti,dra7-cpsw","ti,cpsw"; 3075 clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; 3076 clock-names = "fck", "cpts"; 3077 cpdma_channels = <8>; 3078 ale_entries = <1024>; 3079 bd_ram_size = <0x2000>; 3080 mac_control = <0x20>; 3081 slaves = <2>; 3082 active_slave = <0>; 3083 cpts_clock_mult = <0x784CFE14>; 3084 cpts_clock_shift = <29>; 3085 reg = <0x0 0x1000 3086 0x1200 0x2e00>; 3087 #address-cells = <1>; 3088 #size-cells = <1>; 3089 3090 /* 3091 * rx_thresh_pend 3092 * rx_pend 3093 * tx_pend 3094 * misc_pend 3095 */ 3096 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 3100 ranges = <0 0 0x4000>; 3101 syscon = <&scm_conf>; 3102 status = "disabled"; 3103 3104 davinci_mdio: mdio@1000 { 3105 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 3106 #address-cells = <1>; 3107 #size-cells = <0>; 3108 ti,hwmods = "davinci_mdio"; 3109 bus_freq = <1000000>; 3110 reg = <0x1000 0x100>; 3111 }; 3112 3113 cpsw_emac0: slave@200 { 3114 /* Filled in by U-Boot */ 3115 mac-address = [ 00 00 00 00 00 00 ]; 3116 phys = <&phy_gmii_sel 1>; 3117 }; 3118 3119 cpsw_emac1: slave@300 { 3120 /* Filled in by U-Boot */ 3121 mac-address = [ 00 00 00 00 00 00 ]; 3122 phys = <&phy_gmii_sel 2>; 3123 }; 3124 }; 3125 }; 3126 }; 3127}; 3128 3129&l4_per3 { /* 0x48800000 */ 3130 compatible = "ti,dra7-l4-per3", "simple-bus"; 3131 reg = <0x48800000 0x800>, 3132 <0x48800800 0x800>, 3133 <0x48801000 0x400>, 3134 <0x48801400 0x400>, 3135 <0x48801800 0x400>; 3136 reg-names = "ap", "la", "ia0", "ia1", "ia2"; 3137 #address-cells = <1>; 3138 #size-cells = <1>; 3139 ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */ 3140 3141 segment@0 { /* 0x48800000 */ 3142 compatible = "simple-bus"; 3143 #address-cells = <1>; 3144 #size-cells = <1>; 3145 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 3146 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 3147 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 3148 <0x00001400 0x00001400 0x000400>, /* ap 3 */ 3149 <0x00001800 0x00001800 0x000400>, /* ap 4 */ 3150 <0x00020000 0x00020000 0x001000>, /* ap 5 */ 3151 <0x00021000 0x00021000 0x001000>, /* ap 6 */ 3152 <0x00022000 0x00022000 0x001000>, /* ap 7 */ 3153 <0x00023000 0x00023000 0x001000>, /* ap 8 */ 3154 <0x00024000 0x00024000 0x001000>, /* ap 9 */ 3155 <0x00025000 0x00025000 0x001000>, /* ap 10 */ 3156 <0x00026000 0x00026000 0x001000>, /* ap 11 */ 3157 <0x00027000 0x00027000 0x001000>, /* ap 12 */ 3158 <0x00028000 0x00028000 0x001000>, /* ap 13 */ 3159 <0x00029000 0x00029000 0x001000>, /* ap 14 */ 3160 <0x0002a000 0x0002a000 0x001000>, /* ap 15 */ 3161 <0x0002b000 0x0002b000 0x001000>, /* ap 16 */ 3162 <0x0002c000 0x0002c000 0x001000>, /* ap 17 */ 3163 <0x0002d000 0x0002d000 0x001000>, /* ap 18 */ 3164 <0x0002e000 0x0002e000 0x001000>, /* ap 19 */ 3165 <0x0002f000 0x0002f000 0x001000>, /* ap 20 */ 3166 <0x00170000 0x00170000 0x010000>, /* ap 21 */ 3167 <0x00180000 0x00180000 0x001000>, /* ap 22 */ 3168 <0x00190000 0x00190000 0x010000>, /* ap 23 */ 3169 <0x001a0000 0x001a0000 0x001000>, /* ap 24 */ 3170 <0x001b0000 0x001b0000 0x010000>, /* ap 25 */ 3171 <0x001c0000 0x001c0000 0x001000>, /* ap 26 */ 3172 <0x001d0000 0x001d0000 0x010000>, /* ap 27 */ 3173 <0x001e0000 0x001e0000 0x001000>, /* ap 28 */ 3174 <0x00038000 0x00038000 0x001000>, /* ap 29 */ 3175 <0x00039000 0x00039000 0x001000>, /* ap 30 */ 3176 <0x0005c000 0x0005c000 0x001000>, /* ap 31 */ 3177 <0x0005d000 0x0005d000 0x001000>, /* ap 32 */ 3178 <0x0003a000 0x0003a000 0x001000>, /* ap 33 */ 3179 <0x0003b000 0x0003b000 0x001000>, /* ap 34 */ 3180 <0x0003c000 0x0003c000 0x001000>, /* ap 35 */ 3181 <0x0003d000 0x0003d000 0x001000>, /* ap 36 */ 3182 <0x0003e000 0x0003e000 0x001000>, /* ap 37 */ 3183 <0x0003f000 0x0003f000 0x001000>, /* ap 38 */ 3184 <0x00040000 0x00040000 0x001000>, /* ap 39 */ 3185 <0x00041000 0x00041000 0x001000>, /* ap 40 */ 3186 <0x00042000 0x00042000 0x001000>, /* ap 41 */ 3187 <0x00043000 0x00043000 0x001000>, /* ap 42 */ 3188 <0x00044000 0x00044000 0x001000>, /* ap 43 */ 3189 <0x00045000 0x00045000 0x001000>, /* ap 44 */ 3190 <0x00046000 0x00046000 0x001000>, /* ap 45 */ 3191 <0x00047000 0x00047000 0x001000>, /* ap 46 */ 3192 <0x00048000 0x00048000 0x001000>, /* ap 47 */ 3193 <0x00049000 0x00049000 0x001000>, /* ap 48 */ 3194 <0x0004a000 0x0004a000 0x001000>, /* ap 49 */ 3195 <0x0004b000 0x0004b000 0x001000>, /* ap 50 */ 3196 <0x0004c000 0x0004c000 0x001000>, /* ap 51 */ 3197 <0x0004d000 0x0004d000 0x001000>, /* ap 52 */ 3198 <0x0004e000 0x0004e000 0x001000>, /* ap 53 */ 3199 <0x0004f000 0x0004f000 0x001000>, /* ap 54 */ 3200 <0x00050000 0x00050000 0x001000>, /* ap 55 */ 3201 <0x00051000 0x00051000 0x001000>, /* ap 56 */ 3202 <0x00052000 0x00052000 0x001000>, /* ap 57 */ 3203 <0x00053000 0x00053000 0x001000>, /* ap 58 */ 3204 <0x00054000 0x00054000 0x001000>, /* ap 59 */ 3205 <0x00055000 0x00055000 0x001000>, /* ap 60 */ 3206 <0x00056000 0x00056000 0x001000>, /* ap 61 */ 3207 <0x00057000 0x00057000 0x001000>, /* ap 62 */ 3208 <0x00058000 0x00058000 0x001000>, /* ap 63 */ 3209 <0x00059000 0x00059000 0x001000>, /* ap 64 */ 3210 <0x0005a000 0x0005a000 0x001000>, /* ap 65 */ 3211 <0x0005b000 0x0005b000 0x001000>, /* ap 66 */ 3212 <0x00064000 0x00064000 0x001000>, /* ap 67 */ 3213 <0x00065000 0x00065000 0x001000>, /* ap 68 */ 3214 <0x0005e000 0x0005e000 0x001000>, /* ap 69 */ 3215 <0x0005f000 0x0005f000 0x001000>, /* ap 70 */ 3216 <0x00060000 0x00060000 0x001000>, /* ap 71 */ 3217 <0x00061000 0x00061000 0x001000>, /* ap 72 */ 3218 <0x00062000 0x00062000 0x001000>, /* ap 73 */ 3219 <0x00063000 0x00063000 0x001000>, /* ap 74 */ 3220 <0x00140000 0x00140000 0x020000>, /* ap 75 */ 3221 <0x00160000 0x00160000 0x001000>, /* ap 76 */ 3222 <0x00016000 0x00016000 0x001000>, /* ap 77 */ 3223 <0x00017000 0x00017000 0x001000>, /* ap 78 */ 3224 <0x000c0000 0x000c0000 0x020000>, /* ap 79 */ 3225 <0x000e0000 0x000e0000 0x001000>, /* ap 80 */ 3226 <0x00004000 0x00004000 0x001000>, /* ap 81 */ 3227 <0x00005000 0x00005000 0x001000>, /* ap 82 */ 3228 <0x00080000 0x00080000 0x020000>, /* ap 83 */ 3229 <0x000a0000 0x000a0000 0x001000>, /* ap 84 */ 3230 <0x00100000 0x00100000 0x020000>, /* ap 85 */ 3231 <0x00120000 0x00120000 0x001000>, /* ap 86 */ 3232 <0x00010000 0x00010000 0x001000>, /* ap 87 */ 3233 <0x00011000 0x00011000 0x001000>, /* ap 88 */ 3234 <0x0000a000 0x0000a000 0x001000>, /* ap 89 */ 3235 <0x0000b000 0x0000b000 0x001000>, /* ap 90 */ 3236 <0x0001c000 0x0001c000 0x001000>, /* ap 91 */ 3237 <0x0001d000 0x0001d000 0x001000>, /* ap 92 */ 3238 <0x0001e000 0x0001e000 0x001000>, /* ap 93 */ 3239 <0x0001f000 0x0001f000 0x001000>, /* ap 94 */ 3240 <0x00002000 0x00002000 0x001000>, /* ap 95 */ 3241 <0x00003000 0x00003000 0x001000>; /* ap 96 */ 3242 3243 target-module@2000 { /* 0x48802000, ap 95 7c.0 */ 3244 compatible = "ti,sysc-omap4", "ti,sysc"; 3245 ti,hwmods = "mailbox13"; 3246 reg = <0x2000 0x4>, 3247 <0x2010 0x4>; 3248 reg-names = "rev", "sysc"; 3249 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3250 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3251 <SYSC_IDLE_NO>, 3252 <SYSC_IDLE_SMART>; 3253 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3254 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>; 3255 clock-names = "fck"; 3256 #address-cells = <1>; 3257 #size-cells = <1>; 3258 ranges = <0x0 0x2000 0x1000>; 3259 3260 mailbox13: mailbox@0 { 3261 compatible = "ti,omap4-mailbox"; 3262 reg = <0x0 0x200>; 3263 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; 3267 #mbox-cells = <1>; 3268 ti,mbox-num-users = <4>; 3269 ti,mbox-num-fifos = <12>; 3270 status = "disabled"; 3271 }; 3272 }; 3273 3274 target-module@4000 { /* 0x48804000, ap 81 20.0 */ 3275 compatible = "ti,sysc"; 3276 status = "disabled"; 3277 #address-cells = <1>; 3278 #size-cells = <1>; 3279 ranges = <0x0 0x4000 0x1000>; 3280 }; 3281 3282 target-module@a000 { /* 0x4880a000, ap 89 18.0 */ 3283 compatible = "ti,sysc"; 3284 status = "disabled"; 3285 #address-cells = <1>; 3286 #size-cells = <1>; 3287 ranges = <0x0 0xa000 0x1000>; 3288 }; 3289 3290 target-module@10000 { /* 0x48810000, ap 87 28.0 */ 3291 compatible = "ti,sysc"; 3292 status = "disabled"; 3293 #address-cells = <1>; 3294 #size-cells = <1>; 3295 ranges = <0x0 0x10000 0x1000>; 3296 }; 3297 3298 target-module@16000 { /* 0x48816000, ap 77 1e.0 */ 3299 compatible = "ti,sysc"; 3300 status = "disabled"; 3301 #address-cells = <1>; 3302 #size-cells = <1>; 3303 ranges = <0x0 0x16000 0x1000>; 3304 }; 3305 3306 target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */ 3307 compatible = "ti,sysc"; 3308 status = "disabled"; 3309 #address-cells = <1>; 3310 #size-cells = <1>; 3311 ranges = <0x0 0x1c000 0x1000>; 3312 }; 3313 3314 target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */ 3315 compatible = "ti,sysc"; 3316 status = "disabled"; 3317 #address-cells = <1>; 3318 #size-cells = <1>; 3319 ranges = <0x0 0x1e000 0x1000>; 3320 }; 3321 3322 target-module@20000 { /* 0x48820000, ap 5 08.0 */ 3323 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3324 ti,hwmods = "timer5"; 3325 reg = <0x20000 0x4>, 3326 <0x20010 0x4>; 3327 reg-names = "rev", "sysc"; 3328 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3329 SYSC_OMAP4_SOFTRESET)>; 3330 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3331 <SYSC_IDLE_NO>, 3332 <SYSC_IDLE_SMART>, 3333 <SYSC_IDLE_SMART_WKUP>; 3334 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3335 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; 3336 clock-names = "fck"; 3337 #address-cells = <1>; 3338 #size-cells = <1>; 3339 ranges = <0x0 0x20000 0x1000>; 3340 3341 timer5: timer@0 { 3342 compatible = "ti,omap5430-timer"; 3343 reg = <0x0 0x80>; 3344 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>; 3345 clock-names = "fck"; 3346 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3347 }; 3348 }; 3349 3350 target-module@22000 { /* 0x48822000, ap 7 24.0 */ 3351 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3352 ti,hwmods = "timer6"; 3353 reg = <0x22000 0x4>, 3354 <0x22010 0x4>; 3355 reg-names = "rev", "sysc"; 3356 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3357 SYSC_OMAP4_SOFTRESET)>; 3358 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3359 <SYSC_IDLE_NO>, 3360 <SYSC_IDLE_SMART>, 3361 <SYSC_IDLE_SMART_WKUP>; 3362 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3363 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; 3364 clock-names = "fck"; 3365 #address-cells = <1>; 3366 #size-cells = <1>; 3367 ranges = <0x0 0x22000 0x1000>; 3368 3369 timer6: timer@0 { 3370 compatible = "ti,omap5430-timer"; 3371 reg = <0x0 0x80>; 3372 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>; 3373 clock-names = "fck"; 3374 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3375 }; 3376 }; 3377 3378 target-module@24000 { /* 0x48824000, ap 9 26.0 */ 3379 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3380 ti,hwmods = "timer7"; 3381 reg = <0x24000 0x4>, 3382 <0x24010 0x4>; 3383 reg-names = "rev", "sysc"; 3384 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3385 SYSC_OMAP4_SOFTRESET)>; 3386 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3387 <SYSC_IDLE_NO>, 3388 <SYSC_IDLE_SMART>, 3389 <SYSC_IDLE_SMART_WKUP>; 3390 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3391 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>; 3392 clock-names = "fck"; 3393 #address-cells = <1>; 3394 #size-cells = <1>; 3395 ranges = <0x0 0x24000 0x1000>; 3396 3397 timer7: timer@0 { 3398 compatible = "ti,omap5430-timer"; 3399 reg = <0x0 0x80>; 3400 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>; 3401 clock-names = "fck"; 3402 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 3403 }; 3404 }; 3405 3406 target-module@26000 { /* 0x48826000, ap 11 0c.0 */ 3407 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3408 ti,hwmods = "timer8"; 3409 reg = <0x26000 0x4>, 3410 <0x26010 0x4>; 3411 reg-names = "rev", "sysc"; 3412 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3413 SYSC_OMAP4_SOFTRESET)>; 3414 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3415 <SYSC_IDLE_NO>, 3416 <SYSC_IDLE_SMART>, 3417 <SYSC_IDLE_SMART_WKUP>; 3418 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3419 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>; 3420 clock-names = "fck"; 3421 #address-cells = <1>; 3422 #size-cells = <1>; 3423 ranges = <0x0 0x26000 0x1000>; 3424 3425 timer8: timer@0 { 3426 compatible = "ti,omap5430-timer"; 3427 reg = <0x0 0x80>; 3428 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>; 3429 clock-names = "fck"; 3430 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 3431 }; 3432 }; 3433 3434 target-module@28000 { /* 0x48828000, ap 13 16.0 */ 3435 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3436 ti,hwmods = "timer13"; 3437 reg = <0x28000 0x4>, 3438 <0x28010 0x4>; 3439 reg-names = "rev", "sysc"; 3440 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3441 SYSC_OMAP4_SOFTRESET)>; 3442 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3443 <SYSC_IDLE_NO>, 3444 <SYSC_IDLE_SMART>, 3445 <SYSC_IDLE_SMART_WKUP>; 3446 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3447 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>; 3448 clock-names = "fck"; 3449 #address-cells = <1>; 3450 #size-cells = <1>; 3451 ranges = <0x0 0x28000 0x1000>; 3452 3453 timer13: timer@0 { 3454 compatible = "ti,omap5430-timer"; 3455 reg = <0x0 0x80>; 3456 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>; 3457 clock-names = "fck"; 3458 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 3459 }; 3460 }; 3461 3462 target-module@2a000 { /* 0x4882a000, ap 15 10.0 */ 3463 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3464 ti,hwmods = "timer14"; 3465 reg = <0x2a000 0x4>, 3466 <0x2a010 0x4>; 3467 reg-names = "rev", "sysc"; 3468 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3469 SYSC_OMAP4_SOFTRESET)>; 3470 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3471 <SYSC_IDLE_NO>, 3472 <SYSC_IDLE_SMART>, 3473 <SYSC_IDLE_SMART_WKUP>; 3474 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3475 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>; 3476 clock-names = "fck"; 3477 #address-cells = <1>; 3478 #size-cells = <1>; 3479 ranges = <0x0 0x2a000 0x1000>; 3480 3481 timer14: timer@0 { 3482 compatible = "ti,omap5430-timer"; 3483 reg = <0x0 0x80>; 3484 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>; 3485 clock-names = "fck"; 3486 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 3487 }; 3488 }; 3489 3490 target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ 3491 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3492 ti,hwmods = "timer15"; 3493 reg = <0x2c000 0x4>, 3494 <0x2c010 0x4>; 3495 reg-names = "rev", "sysc"; 3496 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3497 SYSC_OMAP4_SOFTRESET)>; 3498 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3499 <SYSC_IDLE_NO>, 3500 <SYSC_IDLE_SMART>, 3501 <SYSC_IDLE_SMART_WKUP>; 3502 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3503 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>; 3504 clock-names = "fck"; 3505 #address-cells = <1>; 3506 #size-cells = <1>; 3507 ranges = <0x0 0x2c000 0x1000>; 3508 3509 timer15: timer@0 { 3510 compatible = "ti,omap5430-timer"; 3511 reg = <0x0 0x80>; 3512 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; 3513 clock-names = "fck"; 3514 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 3515 }; 3516 }; 3517 3518 target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ 3519 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3520 ti,hwmods = "timer16"; 3521 reg = <0x2e000 0x4>, 3522 <0x2e010 0x4>; 3523 reg-names = "rev", "sysc"; 3524 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3525 SYSC_OMAP4_SOFTRESET)>; 3526 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3527 <SYSC_IDLE_NO>, 3528 <SYSC_IDLE_SMART>, 3529 <SYSC_IDLE_SMART_WKUP>; 3530 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3531 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>; 3532 clock-names = "fck"; 3533 #address-cells = <1>; 3534 #size-cells = <1>; 3535 ranges = <0x0 0x2e000 0x1000>; 3536 3537 timer16: timer@0 { 3538 compatible = "ti,omap5430-timer"; 3539 reg = <0x0 0x80>; 3540 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; 3541 clock-names = "fck"; 3542 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 3543 }; 3544 }; 3545 3546 target-module@38000 { /* 0x48838000, ap 29 12.0 */ 3547 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 3548 ti,hwmods = "rtcss"; 3549 reg = <0x38074 0x4>, 3550 <0x38078 0x4>; 3551 reg-names = "rev", "sysc"; 3552 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3553 <SYSC_IDLE_NO>, 3554 <SYSC_IDLE_SMART>, 3555 <SYSC_IDLE_SMART_WKUP>; 3556 /* Domains (P, C): rtc_pwrdm, rtc_clkdm */ 3557 clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>; 3558 clock-names = "fck"; 3559 #address-cells = <1>; 3560 #size-cells = <1>; 3561 ranges = <0x0 0x38000 0x1000>; 3562 3563 rtc: rtc@0 { 3564 compatible = "ti,am3352-rtc"; 3565 reg = <0x0 0x100>; 3566 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 3567 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 3568 clocks = <&sys_32k_ck>; 3569 }; 3570 }; 3571 3572 target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */ 3573 compatible = "ti,sysc-omap4", "ti,sysc"; 3574 ti,hwmods = "mailbox2"; 3575 reg = <0x3a000 0x4>, 3576 <0x3a010 0x4>; 3577 reg-names = "rev", "sysc"; 3578 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3579 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3580 <SYSC_IDLE_NO>, 3581 <SYSC_IDLE_SMART>; 3582 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3583 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>; 3584 clock-names = "fck"; 3585 #address-cells = <1>; 3586 #size-cells = <1>; 3587 ranges = <0x0 0x3a000 0x1000>; 3588 3589 mailbox2: mailbox@0 { 3590 compatible = "ti,omap4-mailbox"; 3591 reg = <0x0 0x200>; 3592 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 3593 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3594 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 3595 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 3596 #mbox-cells = <1>; 3597 ti,mbox-num-users = <4>; 3598 ti,mbox-num-fifos = <12>; 3599 status = "disabled"; 3600 }; 3601 }; 3602 3603 target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */ 3604 compatible = "ti,sysc-omap4", "ti,sysc"; 3605 ti,hwmods = "mailbox3"; 3606 reg = <0x3c000 0x4>, 3607 <0x3c010 0x4>; 3608 reg-names = "rev", "sysc"; 3609 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3610 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3611 <SYSC_IDLE_NO>, 3612 <SYSC_IDLE_SMART>; 3613 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3614 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>; 3615 clock-names = "fck"; 3616 #address-cells = <1>; 3617 #size-cells = <1>; 3618 ranges = <0x0 0x3c000 0x1000>; 3619 3620 mailbox3: mailbox@0 { 3621 compatible = "ti,omap4-mailbox"; 3622 reg = <0x0 0x200>; 3623 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 3627 #mbox-cells = <1>; 3628 ti,mbox-num-users = <4>; 3629 ti,mbox-num-fifos = <12>; 3630 status = "disabled"; 3631 }; 3632 }; 3633 3634 target-module@3e000 { /* 0x4883e000, ap 37 46.0 */ 3635 compatible = "ti,sysc-omap4", "ti,sysc"; 3636 ti,hwmods = "mailbox4"; 3637 reg = <0x3e000 0x4>, 3638 <0x3e010 0x4>; 3639 reg-names = "rev", "sysc"; 3640 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3641 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3642 <SYSC_IDLE_NO>, 3643 <SYSC_IDLE_SMART>; 3644 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3645 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>; 3646 clock-names = "fck"; 3647 #address-cells = <1>; 3648 #size-cells = <1>; 3649 ranges = <0x0 0x3e000 0x1000>; 3650 3651 mailbox4: mailbox@0 { 3652 compatible = "ti,omap4-mailbox"; 3653 reg = <0x0 0x200>; 3654 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 3658 #mbox-cells = <1>; 3659 ti,mbox-num-users = <4>; 3660 ti,mbox-num-fifos = <12>; 3661 status = "disabled"; 3662 }; 3663 }; 3664 3665 target-module@40000 { /* 0x48840000, ap 39 64.0 */ 3666 compatible = "ti,sysc-omap4", "ti,sysc"; 3667 ti,hwmods = "mailbox5"; 3668 reg = <0x40000 0x4>, 3669 <0x40010 0x4>; 3670 reg-names = "rev", "sysc"; 3671 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3672 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3673 <SYSC_IDLE_NO>, 3674 <SYSC_IDLE_SMART>; 3675 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3676 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>; 3677 clock-names = "fck"; 3678 #address-cells = <1>; 3679 #size-cells = <1>; 3680 ranges = <0x0 0x40000 0x1000>; 3681 3682 mailbox5: mailbox@0 { 3683 compatible = "ti,omap4-mailbox"; 3684 reg = <0x0 0x200>; 3685 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 3686 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 3687 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 3688 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 3689 #mbox-cells = <1>; 3690 ti,mbox-num-users = <4>; 3691 ti,mbox-num-fifos = <12>; 3692 status = "disabled"; 3693 }; 3694 }; 3695 3696 target-module@42000 { /* 0x48842000, ap 41 4e.0 */ 3697 compatible = "ti,sysc-omap4", "ti,sysc"; 3698 ti,hwmods = "mailbox6"; 3699 reg = <0x42000 0x4>, 3700 <0x42010 0x4>; 3701 reg-names = "rev", "sysc"; 3702 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3703 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3704 <SYSC_IDLE_NO>, 3705 <SYSC_IDLE_SMART>; 3706 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3707 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>; 3708 clock-names = "fck"; 3709 #address-cells = <1>; 3710 #size-cells = <1>; 3711 ranges = <0x0 0x42000 0x1000>; 3712 3713 mailbox6: mailbox@0 { 3714 compatible = "ti,omap4-mailbox"; 3715 reg = <0x0 0x200>; 3716 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 3720 #mbox-cells = <1>; 3721 ti,mbox-num-users = <4>; 3722 ti,mbox-num-fifos = <12>; 3723 status = "disabled"; 3724 }; 3725 }; 3726 3727 target-module@44000 { /* 0x48844000, ap 43 42.0 */ 3728 compatible = "ti,sysc-omap4", "ti,sysc"; 3729 ti,hwmods = "mailbox7"; 3730 reg = <0x44000 0x4>, 3731 <0x44010 0x4>; 3732 reg-names = "rev", "sysc"; 3733 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3734 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3735 <SYSC_IDLE_NO>, 3736 <SYSC_IDLE_SMART>; 3737 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3738 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>; 3739 clock-names = "fck"; 3740 #address-cells = <1>; 3741 #size-cells = <1>; 3742 ranges = <0x0 0x44000 0x1000>; 3743 3744 mailbox7: mailbox@0 { 3745 compatible = "ti,omap4-mailbox"; 3746 reg = <0x0 0x200>; 3747 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 3751 #mbox-cells = <1>; 3752 ti,mbox-num-users = <4>; 3753 ti,mbox-num-fifos = <12>; 3754 status = "disabled"; 3755 }; 3756 }; 3757 3758 target-module@46000 { /* 0x48846000, ap 45 48.0 */ 3759 compatible = "ti,sysc-omap4", "ti,sysc"; 3760 ti,hwmods = "mailbox8"; 3761 reg = <0x46000 0x4>, 3762 <0x46010 0x4>; 3763 reg-names = "rev", "sysc"; 3764 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3765 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3766 <SYSC_IDLE_NO>, 3767 <SYSC_IDLE_SMART>; 3768 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3769 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>; 3770 clock-names = "fck"; 3771 #address-cells = <1>; 3772 #size-cells = <1>; 3773 ranges = <0x0 0x46000 0x1000>; 3774 3775 mailbox8: mailbox@0 { 3776 compatible = "ti,omap4-mailbox"; 3777 reg = <0x0 0x200>; 3778 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 3782 #mbox-cells = <1>; 3783 ti,mbox-num-users = <4>; 3784 ti,mbox-num-fifos = <12>; 3785 status = "disabled"; 3786 }; 3787 }; 3788 3789 target-module@48000 { /* 0x48848000, ap 47 36.0 */ 3790 compatible = "ti,sysc"; 3791 status = "disabled"; 3792 #address-cells = <1>; 3793 #size-cells = <1>; 3794 ranges = <0x0 0x48000 0x1000>; 3795 }; 3796 3797 target-module@4a000 { /* 0x4884a000, ap 49 38.0 */ 3798 compatible = "ti,sysc"; 3799 status = "disabled"; 3800 #address-cells = <1>; 3801 #size-cells = <1>; 3802 ranges = <0x0 0x4a000 0x1000>; 3803 }; 3804 3805 target-module@4c000 { /* 0x4884c000, ap 51 44.0 */ 3806 compatible = "ti,sysc"; 3807 status = "disabled"; 3808 #address-cells = <1>; 3809 #size-cells = <1>; 3810 ranges = <0x0 0x4c000 0x1000>; 3811 }; 3812 3813 target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */ 3814 compatible = "ti,sysc"; 3815 status = "disabled"; 3816 #address-cells = <1>; 3817 #size-cells = <1>; 3818 ranges = <0x0 0x4e000 0x1000>; 3819 }; 3820 3821 target-module@50000 { /* 0x48850000, ap 55 40.0 */ 3822 compatible = "ti,sysc"; 3823 status = "disabled"; 3824 #address-cells = <1>; 3825 #size-cells = <1>; 3826 ranges = <0x0 0x50000 0x1000>; 3827 }; 3828 3829 target-module@52000 { /* 0x48852000, ap 57 54.0 */ 3830 compatible = "ti,sysc"; 3831 status = "disabled"; 3832 #address-cells = <1>; 3833 #size-cells = <1>; 3834 ranges = <0x0 0x52000 0x1000>; 3835 }; 3836 3837 target-module@54000 { /* 0x48854000, ap 59 1a.0 */ 3838 compatible = "ti,sysc"; 3839 status = "disabled"; 3840 #address-cells = <1>; 3841 #size-cells = <1>; 3842 ranges = <0x0 0x54000 0x1000>; 3843 }; 3844 3845 target-module@56000 { /* 0x48856000, ap 61 22.0 */ 3846 compatible = "ti,sysc"; 3847 status = "disabled"; 3848 #address-cells = <1>; 3849 #size-cells = <1>; 3850 ranges = <0x0 0x56000 0x1000>; 3851 }; 3852 3853 target-module@58000 { /* 0x48858000, ap 63 2a.0 */ 3854 compatible = "ti,sysc"; 3855 status = "disabled"; 3856 #address-cells = <1>; 3857 #size-cells = <1>; 3858 ranges = <0x0 0x58000 0x1000>; 3859 }; 3860 3861 target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */ 3862 compatible = "ti,sysc"; 3863 status = "disabled"; 3864 #address-cells = <1>; 3865 #size-cells = <1>; 3866 ranges = <0x0 0x5a000 0x1000>; 3867 }; 3868 3869 target-module@5c000 { /* 0x4885c000, ap 31 32.0 */ 3870 compatible = "ti,sysc"; 3871 status = "disabled"; 3872 #address-cells = <1>; 3873 #size-cells = <1>; 3874 ranges = <0x0 0x5c000 0x1000>; 3875 }; 3876 3877 target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */ 3878 compatible = "ti,sysc-omap4", "ti,sysc"; 3879 ti,hwmods = "mailbox9"; 3880 reg = <0x5e000 0x4>, 3881 <0x5e010 0x4>; 3882 reg-names = "rev", "sysc"; 3883 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3884 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3885 <SYSC_IDLE_NO>, 3886 <SYSC_IDLE_SMART>; 3887 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3888 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>; 3889 clock-names = "fck"; 3890 #address-cells = <1>; 3891 #size-cells = <1>; 3892 ranges = <0x0 0x5e000 0x1000>; 3893 3894 mailbox9: mailbox@0 { 3895 compatible = "ti,omap4-mailbox"; 3896 reg = <0x0 0x200>; 3897 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 3898 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 3899 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 3900 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3901 #mbox-cells = <1>; 3902 ti,mbox-num-users = <4>; 3903 ti,mbox-num-fifos = <12>; 3904 status = "disabled"; 3905 }; 3906 }; 3907 3908 target-module@60000 { /* 0x48860000, ap 71 4a.0 */ 3909 compatible = "ti,sysc-omap4", "ti,sysc"; 3910 ti,hwmods = "mailbox10"; 3911 reg = <0x60000 0x4>, 3912 <0x60010 0x4>; 3913 reg-names = "rev", "sysc"; 3914 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3915 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3916 <SYSC_IDLE_NO>, 3917 <SYSC_IDLE_SMART>; 3918 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3919 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>; 3920 clock-names = "fck"; 3921 #address-cells = <1>; 3922 #size-cells = <1>; 3923 ranges = <0x0 0x60000 0x1000>; 3924 3925 mailbox10: mailbox@0 { 3926 compatible = "ti,omap4-mailbox"; 3927 reg = <0x0 0x200>; 3928 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3932 #mbox-cells = <1>; 3933 ti,mbox-num-users = <4>; 3934 ti,mbox-num-fifos = <12>; 3935 status = "disabled"; 3936 }; 3937 }; 3938 3939 target-module@62000 { /* 0x48862000, ap 73 74.0 */ 3940 compatible = "ti,sysc-omap4", "ti,sysc"; 3941 ti,hwmods = "mailbox11"; 3942 reg = <0x62000 0x4>, 3943 <0x62010 0x4>; 3944 reg-names = "rev", "sysc"; 3945 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3946 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3947 <SYSC_IDLE_NO>, 3948 <SYSC_IDLE_SMART>; 3949 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3950 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>; 3951 clock-names = "fck"; 3952 #address-cells = <1>; 3953 #size-cells = <1>; 3954 ranges = <0x0 0x62000 0x1000>; 3955 3956 mailbox11: mailbox@0 { 3957 compatible = "ti,omap4-mailbox"; 3958 reg = <0x0 0x200>; 3959 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 3960 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 3961 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 3962 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 3963 #mbox-cells = <1>; 3964 ti,mbox-num-users = <4>; 3965 ti,mbox-num-fifos = <12>; 3966 status = "disabled"; 3967 }; 3968 }; 3969 3970 target-module@64000 { /* 0x48864000, ap 67 52.0 */ 3971 compatible = "ti,sysc-omap4", "ti,sysc"; 3972 ti,hwmods = "mailbox12"; 3973 reg = <0x64000 0x4>, 3974 <0x64010 0x4>; 3975 reg-names = "rev", "sysc"; 3976 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3977 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3978 <SYSC_IDLE_NO>, 3979 <SYSC_IDLE_SMART>; 3980 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3981 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>; 3982 clock-names = "fck"; 3983 #address-cells = <1>; 3984 #size-cells = <1>; 3985 ranges = <0x0 0x64000 0x1000>; 3986 3987 mailbox12: mailbox@0 { 3988 compatible = "ti,omap4-mailbox"; 3989 reg = <0x0 0x200>; 3990 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 3991 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 3992 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 3993 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 3994 #mbox-cells = <1>; 3995 ti,mbox-num-users = <4>; 3996 ti,mbox-num-fifos = <12>; 3997 status = "disabled"; 3998 }; 3999 }; 4000 4001 target-module@80000 { /* 0x48880000, ap 83 0e.1 */ 4002 compatible = "ti,sysc-omap4", "ti,sysc"; 4003 ti,hwmods = "usb_otg_ss1"; 4004 reg = <0x80000 0x4>, 4005 <0x80010 0x4>; 4006 reg-names = "rev", "sysc"; 4007 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 4008 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4009 <SYSC_IDLE_NO>, 4010 <SYSC_IDLE_SMART>, 4011 <SYSC_IDLE_SMART_WKUP>; 4012 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4013 <SYSC_IDLE_NO>, 4014 <SYSC_IDLE_SMART>, 4015 <SYSC_IDLE_SMART_WKUP>; 4016 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 4017 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>; 4018 clock-names = "fck"; 4019 #address-cells = <1>; 4020 #size-cells = <1>; 4021 ranges = <0x0 0x80000 0x20000>; 4022 4023 omap_dwc3_1: omap_dwc3_1@0 { 4024 compatible = "ti,dwc3"; 4025 reg = <0x0 0x10000>; 4026 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 4027 #address-cells = <1>; 4028 #size-cells = <1>; 4029 utmi-mode = <2>; 4030 ranges = <0 0 0x20000>; 4031 4032 usb1: usb@10000 { 4033 compatible = "snps,dwc3"; 4034 reg = <0x10000 0x17000>; 4035 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 4036 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 4037 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 4038 interrupt-names = "peripheral", 4039 "host", 4040 "otg"; 4041 phys = <&usb2_phy1>, <&usb3_phy1>; 4042 phy-names = "usb2-phy", "usb3-phy"; 4043 maximum-speed = "super-speed"; 4044 dr_mode = "otg"; 4045 snps,dis_u3_susphy_quirk; 4046 snps,dis_u2_susphy_quirk; 4047 }; 4048 }; 4049 }; 4050 4051 target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ 4052 compatible = "ti,sysc-omap4", "ti,sysc"; 4053 ti,hwmods = "usb_otg_ss2"; 4054 reg = <0xc0000 0x4>, 4055 <0xc0010 0x4>; 4056 reg-names = "rev", "sysc"; 4057 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 4058 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4059 <SYSC_IDLE_NO>, 4060 <SYSC_IDLE_SMART>, 4061 <SYSC_IDLE_SMART_WKUP>; 4062 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4063 <SYSC_IDLE_NO>, 4064 <SYSC_IDLE_SMART>, 4065 <SYSC_IDLE_SMART_WKUP>; 4066 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 4067 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>; 4068 clock-names = "fck"; 4069 #address-cells = <1>; 4070 #size-cells = <1>; 4071 ranges = <0x0 0xc0000 0x20000>; 4072 4073 omap_dwc3_2: omap_dwc3_2@0 { 4074 compatible = "ti,dwc3"; 4075 reg = <0x0 0x10000>; 4076 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 4077 #address-cells = <1>; 4078 #size-cells = <1>; 4079 utmi-mode = <2>; 4080 ranges = <0 0 0x20000>; 4081 4082 usb2: usb@10000 { 4083 compatible = "snps,dwc3"; 4084 reg = <0x10000 0x17000>; 4085 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 4088 interrupt-names = "peripheral", 4089 "host", 4090 "otg"; 4091 phys = <&usb2_phy2>; 4092 phy-names = "usb2-phy"; 4093 maximum-speed = "high-speed"; 4094 dr_mode = "otg"; 4095 snps,dis_u3_susphy_quirk; 4096 snps,dis_u2_susphy_quirk; 4097 snps,dis_metastability_quirk; 4098 }; 4099 }; 4100 }; 4101 4102 target-module@100000 { /* 0x48900000, ap 85 04.0 */ 4103 compatible = "ti,sysc-omap4", "ti,sysc"; 4104 ti,hwmods = "usb_otg_ss3"; 4105 reg = <0x100000 0x4>, 4106 <0x100010 0x4>; 4107 reg-names = "rev", "sysc"; 4108 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 4109 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4110 <SYSC_IDLE_NO>, 4111 <SYSC_IDLE_SMART>, 4112 <SYSC_IDLE_SMART_WKUP>; 4113 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4114 <SYSC_IDLE_NO>, 4115 <SYSC_IDLE_SMART>, 4116 <SYSC_IDLE_SMART_WKUP>; 4117 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 4118 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>; 4119 clock-names = "fck"; 4120 #address-cells = <1>; 4121 #size-cells = <1>; 4122 ranges = <0x0 0x100000 0x20000>; 4123 4124 omap_dwc3_3: omap_dwc3_3@0 { 4125 compatible = "ti,dwc3"; 4126 reg = <0x0 0x10000>; 4127 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 4128 #address-cells = <1>; 4129 #size-cells = <1>; 4130 utmi-mode = <2>; 4131 ranges = <0 0 0x20000>; 4132 status = "disabled"; 4133 4134 usb3: usb@10000 { 4135 compatible = "snps,dwc3"; 4136 reg = <0x10000 0x17000>; 4137 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 4140 interrupt-names = "peripheral", 4141 "host", 4142 "otg"; 4143 maximum-speed = "high-speed"; 4144 dr_mode = "otg"; 4145 snps,dis_u3_susphy_quirk; 4146 snps,dis_u2_susphy_quirk; 4147 }; 4148 }; 4149 }; 4150 4151 target-module@140000 { /* 0x48940000, ap 75 3c.0 */ 4152 compatible = "ti,sysc-omap4", "ti,sysc"; 4153 ti,hwmods = "usb_otg_ss4"; 4154 reg = <0x140000 0x4>, 4155 <0x140010 0x4>; 4156 reg-names = "rev", "sysc"; 4157 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 4158 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4159 <SYSC_IDLE_NO>, 4160 <SYSC_IDLE_SMART>, 4161 <SYSC_IDLE_SMART_WKUP>; 4162 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4163 <SYSC_IDLE_NO>, 4164 <SYSC_IDLE_SMART>, 4165 <SYSC_IDLE_SMART_WKUP>; 4166 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 4167 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; 4168 clock-names = "fck"; 4169 #address-cells = <1>; 4170 #size-cells = <1>; 4171 ranges = <0x0 0x140000 0x20000>; 4172 }; 4173 4174 target-module@170000 { /* 0x48970000, ap 21 0a.0 */ 4175 compatible = "ti,sysc"; 4176 status = "disabled"; 4177 #address-cells = <1>; 4178 #size-cells = <1>; 4179 ranges = <0x0 0x170000 0x10000>; 4180 }; 4181 4182 target-module@190000 { /* 0x48990000, ap 23 2e.0 */ 4183 compatible = "ti,sysc"; 4184 status = "disabled"; 4185 #address-cells = <1>; 4186 #size-cells = <1>; 4187 ranges = <0x0 0x190000 0x10000>; 4188 }; 4189 4190 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ 4191 compatible = "ti,sysc"; 4192 status = "disabled"; 4193 #address-cells = <1>; 4194 #size-cells = <1>; 4195 ranges = <0x0 0x1b0000 0x10000>; 4196 }; 4197 4198 target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */ 4199 compatible = "ti,sysc"; 4200 status = "disabled"; 4201 #address-cells = <1>; 4202 #size-cells = <1>; 4203 ranges = <0x0 0x1d0000 0x10000>; 4204 }; 4205 }; 4206}; 4207 4208&l4_wkup { /* 0x4ae00000 */ 4209 compatible = "ti,dra7-l4-wkup", "simple-bus"; 4210 reg = <0x4ae00000 0x800>, 4211 <0x4ae00800 0x800>, 4212 <0x4ae01000 0x1000>; 4213 reg-names = "ap", "la", "ia0"; 4214 #address-cells = <1>; 4215 #size-cells = <1>; 4216 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ 4217 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ 4218 <0x00020000 0x4ae20000 0x010000>, /* segment 2 */ 4219 <0x00030000 0x4ae30000 0x010000>; /* segment 3 */ 4220 4221 segment@0 { /* 0x4ae00000 */ 4222 compatible = "simple-bus"; 4223 #address-cells = <1>; 4224 #size-cells = <1>; 4225 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 4226 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 4227 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 4228 <0x00006000 0x00006000 0x002000>, /* ap 3 */ 4229 <0x00008000 0x00008000 0x001000>, /* ap 4 */ 4230 <0x00004000 0x00004000 0x001000>, /* ap 15 */ 4231 <0x00005000 0x00005000 0x001000>, /* ap 16 */ 4232 <0x0000c000 0x0000c000 0x001000>, /* ap 17 */ 4233 <0x0000d000 0x0000d000 0x001000>; /* ap 18 */ 4234 4235 target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ 4236 compatible = "ti,sysc-omap2", "ti,sysc"; 4237 ti,hwmods = "counter_32k"; 4238 reg = <0x4000 0x4>, 4239 <0x4010 0x4>; 4240 reg-names = "rev", "sysc"; 4241 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4242 <SYSC_IDLE_NO>, 4243 <SYSC_IDLE_SMART>, 4244 <SYSC_IDLE_SMART_WKUP>; 4245 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4246 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>; 4247 clock-names = "fck"; 4248 #address-cells = <1>; 4249 #size-cells = <1>; 4250 ranges = <0x0 0x4000 0x1000>; 4251 4252 counter32k: counter@0 { 4253 compatible = "ti,omap-counter32k"; 4254 reg = <0x0 0x40>; 4255 }; 4256 }; 4257 4258 target-module@6000 { /* 0x4ae06000, ap 3 10.0 */ 4259 compatible = "ti,sysc-omap4", "ti,sysc"; 4260 reg = <0x6000 0x4>; 4261 reg-names = "rev"; 4262 #address-cells = <1>; 4263 #size-cells = <1>; 4264 ranges = <0x0 0x6000 0x2000>; 4265 4266 prm: prm@0 { 4267 compatible = "ti,dra7-prm", "simple-bus"; 4268 reg = <0 0x3000>; 4269 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4270 #address-cells = <1>; 4271 #size-cells = <1>; 4272 ranges = <0 0 0x3000>; 4273 4274 prm_clocks: clocks { 4275 #address-cells = <1>; 4276 #size-cells = <0>; 4277 }; 4278 4279 prm_clockdomains: clockdomains { 4280 }; 4281 }; 4282 }; 4283 4284 target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */ 4285 compatible = "ti,sysc-omap4", "ti,sysc"; 4286 reg = <0xc000 0x4>; 4287 reg-names = "rev"; 4288 #address-cells = <1>; 4289 #size-cells = <1>; 4290 ranges = <0x0 0xc000 0x1000>; 4291 4292 scm_wkup: scm_conf@0 { 4293 compatible = "syscon"; 4294 reg = <0 0x1000>; 4295 }; 4296 }; 4297 }; 4298 4299 segment@10000 { /* 0x4ae10000 */ 4300 compatible = "simple-bus"; 4301 #address-cells = <1>; 4302 #size-cells = <1>; 4303 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ 4304 <0x00001000 0x00011000 0x001000>, /* ap 6 */ 4305 <0x00004000 0x00014000 0x001000>, /* ap 7 */ 4306 <0x00005000 0x00015000 0x001000>, /* ap 8 */ 4307 <0x00008000 0x00018000 0x001000>, /* ap 9 */ 4308 <0x00009000 0x00019000 0x001000>, /* ap 10 */ 4309 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ 4310 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ 4311 4312 target-module@0 { /* 0x4ae10000, ap 5 20.0 */ 4313 compatible = "ti,sysc-omap2", "ti,sysc"; 4314 ti,hwmods = "gpio1"; 4315 reg = <0x0 0x4>, 4316 <0x10 0x4>, 4317 <0x114 0x4>; 4318 reg-names = "rev", "sysc", "syss"; 4319 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 4320 SYSC_OMAP2_SOFTRESET | 4321 SYSC_OMAP2_AUTOIDLE)>; 4322 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4323 <SYSC_IDLE_NO>, 4324 <SYSC_IDLE_SMART>, 4325 <SYSC_IDLE_SMART_WKUP>; 4326 ti,syss-mask = <1>; 4327 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4328 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>, 4329 <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>; 4330 clock-names = "fck", "dbclk"; 4331 #address-cells = <1>; 4332 #size-cells = <1>; 4333 ranges = <0x0 0x0 0x1000>; 4334 4335 gpio1: gpio@0 { 4336 compatible = "ti,omap4-gpio"; 4337 reg = <0x0 0x200>; 4338 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 4339 gpio-controller; 4340 #gpio-cells = <2>; 4341 interrupt-controller; 4342 #interrupt-cells = <2>; 4343 }; 4344 }; 4345 4346 target-module@4000 { /* 0x4ae14000, ap 7 28.0 */ 4347 compatible = "ti,sysc-omap2", "ti,sysc"; 4348 ti,hwmods = "wd_timer2"; 4349 reg = <0x4000 0x4>, 4350 <0x4010 0x4>, 4351 <0x4014 0x4>; 4352 reg-names = "rev", "sysc", "syss"; 4353 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 4354 SYSC_OMAP2_SOFTRESET)>; 4355 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4356 <SYSC_IDLE_NO>, 4357 <SYSC_IDLE_SMART>, 4358 <SYSC_IDLE_SMART_WKUP>; 4359 ti,syss-mask = <1>; 4360 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4361 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>; 4362 clock-names = "fck"; 4363 #address-cells = <1>; 4364 #size-cells = <1>; 4365 ranges = <0x0 0x4000 0x1000>; 4366 4367 wdt2: wdt@0 { 4368 compatible = "ti,omap3-wdt"; 4369 reg = <0x0 0x80>; 4370 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 4371 }; 4372 }; 4373 4374 target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ 4375 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 4376 ti,hwmods = "timer1"; 4377 reg = <0x8000 0x4>, 4378 <0x8010 0x4>; 4379 reg-names = "rev", "sysc"; 4380 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 4381 SYSC_OMAP4_SOFTRESET)>; 4382 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4383 <SYSC_IDLE_NO>, 4384 <SYSC_IDLE_SMART>, 4385 <SYSC_IDLE_SMART_WKUP>; 4386 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4387 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>; 4388 clock-names = "fck"; 4389 #address-cells = <1>; 4390 #size-cells = <1>; 4391 ranges = <0x0 0x8000 0x1000>; 4392 4393 timer1: timer@0 { 4394 compatible = "ti,omap5430-timer"; 4395 reg = <0x0 0x80>; 4396 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; 4397 clock-names = "fck"; 4398 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4399 ti,timer-alwon; 4400 }; 4401 }; 4402 4403 target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ 4404 compatible = "ti,sysc"; 4405 status = "disabled"; 4406 #address-cells = <1>; 4407 #size-cells = <1>; 4408 ranges = <0x0 0xc000 0x1000>; 4409 }; 4410 }; 4411 4412 segment@20000 { /* 0x4ae20000 */ 4413 compatible = "simple-bus"; 4414 #address-cells = <1>; 4415 #size-cells = <1>; 4416 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ 4417 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ 4418 <0x00000000 0x00020000 0x001000>, /* ap 19 */ 4419 <0x00001000 0x00021000 0x001000>, /* ap 20 */ 4420 <0x00002000 0x00022000 0x001000>, /* ap 21 */ 4421 <0x00003000 0x00023000 0x001000>, /* ap 22 */ 4422 <0x00007000 0x00027000 0x000400>, /* ap 23 */ 4423 <0x00008000 0x00028000 0x000800>, /* ap 24 */ 4424 <0x00009000 0x00029000 0x000100>, /* ap 25 */ 4425 <0x00008800 0x00028800 0x000200>, /* ap 26 */ 4426 <0x00008a00 0x00028a00 0x000100>, /* ap 27 */ 4427 <0x0000b000 0x0002b000 0x001000>, /* ap 28 */ 4428 <0x0000c000 0x0002c000 0x001000>, /* ap 29 */ 4429 <0x0000f000 0x0002f000 0x001000>; /* ap 32 */ 4430 4431 target-module@0 { /* 0x4ae20000, ap 19 08.0 */ 4432 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 4433 ti,hwmods = "timer12"; 4434 reg = <0x0 0x4>, 4435 <0x10 0x4>; 4436 reg-names = "rev", "sysc"; 4437 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 4438 SYSC_OMAP4_SOFTRESET)>; 4439 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4440 <SYSC_IDLE_NO>, 4441 <SYSC_IDLE_SMART>, 4442 <SYSC_IDLE_SMART_WKUP>; 4443 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4444 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>; 4445 clock-names = "fck"; 4446 #address-cells = <1>; 4447 #size-cells = <1>; 4448 ranges = <0x0 0x0 0x1000>; 4449 4450 timer12: timer@0 { 4451 compatible = "ti,omap5430-timer"; 4452 reg = <0x0 0x80>; 4453 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 24>; 4454 clock-names = "fck"; 4455 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 4456 ti,timer-alwon; 4457 ti,timer-secure; 4458 }; 4459 }; 4460 4461 target-module@2000 { /* 0x4ae22000, ap 21 18.0 */ 4462 compatible = "ti,sysc"; 4463 status = "disabled"; 4464 #address-cells = <1>; 4465 #size-cells = <1>; 4466 ranges = <0x0 0x2000 0x1000>; 4467 }; 4468 4469 target-module@6000 { /* 0x4ae26000, ap 13 48.0 */ 4470 compatible = "ti,sysc"; 4471 status = "disabled"; 4472 #address-cells = <1>; 4473 #size-cells = <1>; 4474 ranges = <0x00000000 0x00006000 0x00001000>, 4475 <0x00001000 0x00007000 0x00000400>, 4476 <0x00002000 0x00008000 0x00000800>, 4477 <0x00002800 0x00008800 0x00000200>, 4478 <0x00002a00 0x00008a00 0x00000100>, 4479 <0x00003000 0x00009000 0x00000100>; 4480 }; 4481 4482 target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */ 4483 compatible = "ti,sysc-omap2", "ti,sysc"; 4484 ti,hwmods = "uart10"; 4485 reg = <0xb050 0x4>, 4486 <0xb054 0x4>, 4487 <0xb058 0x4>; 4488 reg-names = "rev", "sysc", "syss"; 4489 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 4490 SYSC_OMAP2_SOFTRESET | 4491 SYSC_OMAP2_AUTOIDLE)>; 4492 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4493 <SYSC_IDLE_NO>, 4494 <SYSC_IDLE_SMART>, 4495 <SYSC_IDLE_SMART_WKUP>; 4496 ti,syss-mask = <1>; 4497 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4498 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>; 4499 clock-names = "fck"; 4500 #address-cells = <1>; 4501 #size-cells = <1>; 4502 ranges = <0x0 0xb000 0x1000>; 4503 4504 uart10: serial@0 { 4505 compatible = "ti,dra742-uart", "ti,omap4-uart"; 4506 reg = <0x0 0x100>; 4507 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 4508 clock-frequency = <48000000>; 4509 status = "disabled"; 4510 }; 4511 }; 4512 4513 target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ 4514 compatible = "ti,sysc"; 4515 status = "disabled"; 4516 #address-cells = <1>; 4517 #size-cells = <1>; 4518 ranges = <0x0 0xf000 0x1000>; 4519 }; 4520 }; 4521 4522 segment@30000 { /* 0x4ae30000 */ 4523 compatible = "simple-bus"; 4524 #address-cells = <1>; 4525 #size-cells = <1>; 4526 ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */ 4527 <0x0000e000 0x0003e000 0x001000>, /* ap 31 */ 4528 <0x00000000 0x00030000 0x001000>, /* ap 33 */ 4529 <0x00001000 0x00031000 0x001000>, /* ap 34 */ 4530 <0x00002000 0x00032000 0x001000>, /* ap 35 */ 4531 <0x00003000 0x00033000 0x001000>, /* ap 36 */ 4532 <0x00004000 0x00034000 0x001000>, /* ap 37 */ 4533 <0x00005000 0x00035000 0x001000>, /* ap 38 */ 4534 <0x00006000 0x00036000 0x001000>, /* ap 39 */ 4535 <0x00007000 0x00037000 0x001000>, /* ap 40 */ 4536 <0x00008000 0x00038000 0x001000>, /* ap 41 */ 4537 <0x00009000 0x00039000 0x001000>, /* ap 42 */ 4538 <0x0000a000 0x0003a000 0x001000>; /* ap 43 */ 4539 4540 target-module@1000 { /* 0x4ae31000, ap 34 60.0 */ 4541 compatible = "ti,sysc"; 4542 status = "disabled"; 4543 #address-cells = <1>; 4544 #size-cells = <1>; 4545 ranges = <0x0 0x1000 0x1000>; 4546 }; 4547 4548 target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */ 4549 compatible = "ti,sysc"; 4550 status = "disabled"; 4551 #address-cells = <1>; 4552 #size-cells = <1>; 4553 ranges = <0x0 0x3000 0x1000>; 4554 }; 4555 4556 target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */ 4557 compatible = "ti,sysc"; 4558 status = "disabled"; 4559 #address-cells = <1>; 4560 #size-cells = <1>; 4561 ranges = <0x0 0x5000 0x1000>; 4562 }; 4563 4564 target-module@7000 { /* 0x4ae37000, ap 40 68.0 */ 4565 compatible = "ti,sysc"; 4566 status = "disabled"; 4567 #address-cells = <1>; 4568 #size-cells = <1>; 4569 ranges = <0x0 0x7000 0x1000>; 4570 }; 4571 4572 target-module@9000 { /* 0x4ae39000, ap 42 70.0 */ 4573 compatible = "ti,sysc"; 4574 status = "disabled"; 4575 #address-cells = <1>; 4576 #size-cells = <1>; 4577 ranges = <0x0 0x9000 0x1000>; 4578 }; 4579 4580 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ 4581 compatible = "ti,sysc-omap4", "ti,sysc"; 4582 reg = <0xc000 0x4>; 4583 reg-names = "rev"; 4584 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>; 4585 clock-names = "fck"; 4586 #address-cells = <1>; 4587 #size-cells = <1>; 4588 ranges = <0x0 0xc000 0x2000>; 4589 4590 dcan1: can@0 { 4591 compatible = "ti,dra7-d_can"; 4592 reg = <0x0 0x2000>; 4593 syscon-raminit = <&scm_conf 0x558 0>; 4594 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 4595 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; 4596 status = "disabled"; 4597 }; 4598 }; 4599 }; 4600}; 4601 4602