1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <[email protected]>
5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <[email protected]>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Some hw specific parts of this pmap were derived or influenced
29 * by NetBSD's ibm4xx pmap module. More generic code is shared with
30 * a few other pmap modules from the FreeBSD tree.
31 */
32
33 /*
34 * VM layout notes:
35 *
36 * Kernel and user threads run within one common virtual address space
37 * defined by AS=0.
38 *
39 * 32-bit pmap:
40 * Virtual address space layout:
41 * -----------------------------
42 * 0x0000_0000 - 0x7fff_ffff : user process
43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
46 * 0xc100_0000 - 0xffff_ffff : KVA
47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
51 *
52 * 64-bit pmap:
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process
56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries
57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region
58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack
59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved
60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data
61 * endkernel - msgbufp-1 : flat device tree
62 * msgbufp - kernel_pdir-1 : message buffer
63 * kernel_pdir - kernel_pp2d-1 : kernel page directory
64 * kernel_pp2d - . : kernel pointers to page directory
65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy
66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs
67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables
68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space
69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region
70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region
71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map
72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map
73 * - 0xffff_ffff_ffff_ffff : device direct map
74 */
75
76 #include <sys/cdefs.h>
77 #include "opt_ddb.h"
78 #include "opt_kstack_pages.h"
79
80 #include <sys/param.h>
81 #include <sys/conf.h>
82 #include <sys/malloc.h>
83 #include <sys/ktr.h>
84 #include <sys/proc.h>
85 #include <sys/user.h>
86 #include <sys/queue.h>
87 #include <sys/systm.h>
88 #include <sys/kernel.h>
89 #include <sys/kerneldump.h>
90 #include <sys/linker.h>
91 #include <sys/msgbuf.h>
92 #include <sys/lock.h>
93 #include <sys/mutex.h>
94 #include <sys/rwlock.h>
95 #include <sys/sched.h>
96 #include <sys/smp.h>
97 #include <sys/vmmeter.h>
98
99 #include <vm/vm.h>
100 #include <vm/vm_param.h>
101 #include <vm/vm_page.h>
102 #include <vm/vm_kern.h>
103 #include <vm/vm_pageout.h>
104 #include <vm/vm_extern.h>
105 #include <vm/vm_object.h>
106 #include <vm/vm_map.h>
107 #include <vm/vm_pager.h>
108 #include <vm/vm_phys.h>
109 #include <vm/vm_pagequeue.h>
110 #include <vm/vm_dumpset.h>
111 #include <vm/uma.h>
112
113 #include <machine/_inttypes.h>
114 #include <machine/cpu.h>
115 #include <machine/pcb.h>
116 #include <machine/platform.h>
117
118 #include <machine/tlb.h>
119 #include <machine/spr.h>
120 #include <machine/md_var.h>
121 #include <machine/mmuvar.h>
122 #include <machine/pmap.h>
123 #include <machine/pte.h>
124
125 #include <ddb/ddb.h>
126
127 #define SPARSE_MAPDEV
128
129 /* Use power-of-two mappings in mmu_booke_mapdev(), to save entries. */
130 #define POW2_MAPPINGS
131
132 #ifdef DEBUG
133 #define debugf(fmt, args...) printf(fmt, ##args)
134 #define __debug_used
135 #else
136 #define debugf(fmt, args...)
137 #define __debug_used __unused
138 #endif
139
140 #ifdef __powerpc64__
141 #define PRI0ptrX "016lx"
142 #else
143 #define PRI0ptrX "08x"
144 #endif
145
146 #define TODO panic("%s: not implemented", __func__);
147
148 extern unsigned char _etext[];
149 extern unsigned char _end[];
150
151 extern uint32_t *bootinfo;
152
153 vm_paddr_t kernload;
154 vm_offset_t kernstart;
155 vm_size_t kernsize;
156
157 /* Message buffer and tables. */
158 static vm_offset_t data_start;
159 static vm_size_t data_end;
160
161 /* Phys/avail memory regions. */
162 static struct mem_region *availmem_regions;
163 static int availmem_regions_sz;
164 static struct mem_region *physmem_regions;
165 static int physmem_regions_sz;
166
167 #ifndef __powerpc64__
168 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
169 static vm_offset_t zero_page_va;
170 static struct mtx zero_page_mutex;
171
172 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
173 static vm_offset_t copy_page_src_va;
174 static vm_offset_t copy_page_dst_va;
175 static struct mtx copy_page_mutex;
176 #endif
177
178 static struct mtx tlbivax_mutex;
179
180 /**************************************************************************/
181 /* PMAP */
182 /**************************************************************************/
183
184 static int mmu_booke_enter_locked(pmap_t, vm_offset_t, vm_page_t,
185 vm_prot_t, u_int flags, int8_t psind);
186
187 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
188 static uma_zone_t ptbl_root_zone;
189
190 /*
191 * If user pmap is processed with mmu_booke_remove and the resident count
192 * drops to 0, there are no more pages to remove, so we need not continue.
193 */
194 #define PMAP_REMOVE_DONE(pmap) \
195 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
196
197 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
198 extern int elf32_nxstack;
199 #endif
200
201 /**************************************************************************/
202 /* TLB and TID handling */
203 /**************************************************************************/
204
205 /* Translation ID busy table */
206 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
207
208 /*
209 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
210 * core revisions and should be read from h/w registers during early config.
211 */
212 uint32_t tlb0_entries;
213 uint32_t tlb0_ways;
214 uint32_t tlb0_entries_per_way;
215 uint32_t tlb1_entries;
216
217 #define TLB0_ENTRIES (tlb0_entries)
218 #define TLB0_WAYS (tlb0_ways)
219 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
220
221 #define TLB1_ENTRIES (tlb1_entries)
222
223 static tlbtid_t tid_alloc(struct pmap *);
224
225 #ifdef DDB
226 #ifdef __powerpc64__
227 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t);
228 #else
229 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
230 #endif
231 #endif
232
233 static void tlb1_read_entry(tlb_entry_t *, unsigned int);
234 static void tlb1_write_entry(tlb_entry_t *, unsigned int);
235 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
236 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t, int);
237
238 static __inline uint32_t tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma);
239
240 static vm_size_t tsize2size(unsigned int);
241 static unsigned int size2tsize(vm_size_t);
242 static unsigned long ilog2(unsigned long);
243
244 static void set_mas4_defaults(void);
245
246 static inline void tlb0_flush_entry(vm_offset_t);
247 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
248
249 /**************************************************************************/
250 /* Page table management */
251 /**************************************************************************/
252
253 static struct rwlock_padalign pvh_global_lock;
254
255 /* Data for the pv entry allocation mechanism */
256 static uma_zone_t pvzone;
257 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
258
259 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
260
261 #ifndef PMAP_SHPGPERPROC
262 #define PMAP_SHPGPERPROC 200
263 #endif
264
265 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t);
266 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
267 static int pte_remove(pmap_t, vm_offset_t, uint8_t);
268 static pte_t *pte_find(pmap_t, vm_offset_t);
269 static void kernel_pte_alloc(vm_offset_t, vm_offset_t);
270
271 static pv_entry_t pv_alloc(void);
272 static void pv_free(pv_entry_t);
273 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
274 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
275
276 static void booke_pmap_init_qpages(void);
277
278 static inline void tlb_miss_lock(void);
279 static inline void tlb_miss_unlock(void);
280
281 #ifdef SMP
282 extern tlb_entry_t __boot_tlb1[];
283 void pmap_bootstrap_ap(volatile uint32_t *);
284 #endif
285
286 /*
287 * Kernel MMU interface
288 */
289 static void mmu_booke_clear_modify(vm_page_t);
290 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t,
291 vm_size_t, vm_offset_t);
292 static void mmu_booke_copy_page(vm_page_t, vm_page_t);
293 static void mmu_booke_copy_pages(vm_page_t *,
294 vm_offset_t, vm_page_t *, vm_offset_t, int);
295 static int mmu_booke_enter(pmap_t, vm_offset_t, vm_page_t,
296 vm_prot_t, u_int flags, int8_t psind);
297 static void mmu_booke_enter_object(pmap_t, vm_offset_t, vm_offset_t,
298 vm_page_t, vm_prot_t);
299 static void mmu_booke_enter_quick(pmap_t, vm_offset_t, vm_page_t,
300 vm_prot_t);
301 static vm_paddr_t mmu_booke_extract(pmap_t, vm_offset_t);
302 static vm_page_t mmu_booke_extract_and_hold(pmap_t, vm_offset_t,
303 vm_prot_t);
304 static void mmu_booke_init(void);
305 static boolean_t mmu_booke_is_modified(vm_page_t);
306 static boolean_t mmu_booke_is_prefaultable(pmap_t, vm_offset_t);
307 static boolean_t mmu_booke_is_referenced(vm_page_t);
308 static int mmu_booke_ts_referenced(vm_page_t);
309 static vm_offset_t mmu_booke_map(vm_offset_t *, vm_paddr_t, vm_paddr_t,
310 int);
311 static int mmu_booke_mincore(pmap_t, vm_offset_t,
312 vm_paddr_t *);
313 static void mmu_booke_object_init_pt(pmap_t, vm_offset_t,
314 vm_object_t, vm_pindex_t, vm_size_t);
315 static boolean_t mmu_booke_page_exists_quick(pmap_t, vm_page_t);
316 static void mmu_booke_page_init(vm_page_t);
317 static int mmu_booke_page_wired_mappings(vm_page_t);
318 static int mmu_booke_pinit(pmap_t);
319 static void mmu_booke_pinit0(pmap_t);
320 static void mmu_booke_protect(pmap_t, vm_offset_t, vm_offset_t,
321 vm_prot_t);
322 static void mmu_booke_qenter(vm_offset_t, vm_page_t *, int);
323 static void mmu_booke_qremove(vm_offset_t, int);
324 static void mmu_booke_release(pmap_t);
325 static void mmu_booke_remove(pmap_t, vm_offset_t, vm_offset_t);
326 static void mmu_booke_remove_all(vm_page_t);
327 static void mmu_booke_remove_write(vm_page_t);
328 static void mmu_booke_unwire(pmap_t, vm_offset_t, vm_offset_t);
329 static void mmu_booke_zero_page(vm_page_t);
330 static void mmu_booke_zero_page_area(vm_page_t, int, int);
331 static void mmu_booke_activate(struct thread *);
332 static void mmu_booke_deactivate(struct thread *);
333 static void mmu_booke_bootstrap(vm_offset_t, vm_offset_t);
334 static void *mmu_booke_mapdev(vm_paddr_t, vm_size_t);
335 static void *mmu_booke_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t);
336 static void mmu_booke_unmapdev(void *, vm_size_t);
337 static vm_paddr_t mmu_booke_kextract(vm_offset_t);
338 static void mmu_booke_kenter(vm_offset_t, vm_paddr_t);
339 static void mmu_booke_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t);
340 static void mmu_booke_kremove(vm_offset_t);
341 static int mmu_booke_dev_direct_mapped(vm_paddr_t, vm_size_t);
342 static void mmu_booke_sync_icache(pmap_t, vm_offset_t,
343 vm_size_t);
344 static void mmu_booke_dumpsys_map(vm_paddr_t pa, size_t,
345 void **);
346 static void mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t,
347 void *);
348 static void mmu_booke_scan_init(void);
349 static vm_offset_t mmu_booke_quick_enter_page(vm_page_t m);
350 static void mmu_booke_quick_remove_page(vm_offset_t addr);
351 static int mmu_booke_change_attr(vm_offset_t addr,
352 vm_size_t sz, vm_memattr_t mode);
353 static int mmu_booke_decode_kernel_ptr(vm_offset_t addr,
354 int *is_user, vm_offset_t *decoded_addr);
355 static void mmu_booke_page_array_startup(long);
356 static boolean_t mmu_booke_page_is_mapped(vm_page_t m);
357 static bool mmu_booke_ps_enabled(pmap_t pmap);
358
359 static struct pmap_funcs mmu_booke_methods = {
360 /* pmap dispatcher interface */
361 .clear_modify = mmu_booke_clear_modify,
362 .copy = mmu_booke_copy,
363 .copy_page = mmu_booke_copy_page,
364 .copy_pages = mmu_booke_copy_pages,
365 .enter = mmu_booke_enter,
366 .enter_object = mmu_booke_enter_object,
367 .enter_quick = mmu_booke_enter_quick,
368 .extract = mmu_booke_extract,
369 .extract_and_hold = mmu_booke_extract_and_hold,
370 .init = mmu_booke_init,
371 .is_modified = mmu_booke_is_modified,
372 .is_prefaultable = mmu_booke_is_prefaultable,
373 .is_referenced = mmu_booke_is_referenced,
374 .ts_referenced = mmu_booke_ts_referenced,
375 .map = mmu_booke_map,
376 .mincore = mmu_booke_mincore,
377 .object_init_pt = mmu_booke_object_init_pt,
378 .page_exists_quick = mmu_booke_page_exists_quick,
379 .page_init = mmu_booke_page_init,
380 .page_wired_mappings = mmu_booke_page_wired_mappings,
381 .pinit = mmu_booke_pinit,
382 .pinit0 = mmu_booke_pinit0,
383 .protect = mmu_booke_protect,
384 .qenter = mmu_booke_qenter,
385 .qremove = mmu_booke_qremove,
386 .release = mmu_booke_release,
387 .remove = mmu_booke_remove,
388 .remove_all = mmu_booke_remove_all,
389 .remove_write = mmu_booke_remove_write,
390 .sync_icache = mmu_booke_sync_icache,
391 .unwire = mmu_booke_unwire,
392 .zero_page = mmu_booke_zero_page,
393 .zero_page_area = mmu_booke_zero_page_area,
394 .activate = mmu_booke_activate,
395 .deactivate = mmu_booke_deactivate,
396 .quick_enter_page = mmu_booke_quick_enter_page,
397 .quick_remove_page = mmu_booke_quick_remove_page,
398 .page_array_startup = mmu_booke_page_array_startup,
399 .page_is_mapped = mmu_booke_page_is_mapped,
400 .ps_enabled = mmu_booke_ps_enabled,
401
402 /* Internal interfaces */
403 .bootstrap = mmu_booke_bootstrap,
404 .dev_direct_mapped = mmu_booke_dev_direct_mapped,
405 .mapdev = mmu_booke_mapdev,
406 .mapdev_attr = mmu_booke_mapdev_attr,
407 .kenter = mmu_booke_kenter,
408 .kenter_attr = mmu_booke_kenter_attr,
409 .kextract = mmu_booke_kextract,
410 .kremove = mmu_booke_kremove,
411 .unmapdev = mmu_booke_unmapdev,
412 .change_attr = mmu_booke_change_attr,
413 .decode_kernel_ptr = mmu_booke_decode_kernel_ptr,
414
415 /* dumpsys() support */
416 .dumpsys_map_chunk = mmu_booke_dumpsys_map,
417 .dumpsys_unmap_chunk = mmu_booke_dumpsys_unmap,
418 .dumpsys_pa_init = mmu_booke_scan_init,
419 };
420
421 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods);
422
423 #ifdef __powerpc64__
424 #include "pmap_64.c"
425 #else
426 #include "pmap_32.c"
427 #endif
428
429 static vm_offset_t tlb1_map_base = VM_MAPDEV_BASE;
430
431 static __inline uint32_t
tlb_calc_wimg(vm_paddr_t pa,vm_memattr_t ma)432 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
433 {
434 uint32_t attrib;
435 int i;
436
437 if (ma != VM_MEMATTR_DEFAULT) {
438 switch (ma) {
439 case VM_MEMATTR_UNCACHEABLE:
440 return (MAS2_I | MAS2_G);
441 case VM_MEMATTR_WRITE_COMBINING:
442 case VM_MEMATTR_WRITE_BACK:
443 case VM_MEMATTR_PREFETCHABLE:
444 return (MAS2_I);
445 case VM_MEMATTR_WRITE_THROUGH:
446 return (MAS2_W | MAS2_M);
447 case VM_MEMATTR_CACHEABLE:
448 return (MAS2_M);
449 }
450 }
451
452 /*
453 * Assume the page is cache inhibited and access is guarded unless
454 * it's in our available memory array.
455 */
456 attrib = _TLB_ENTRY_IO;
457 for (i = 0; i < physmem_regions_sz; i++) {
458 if ((pa >= physmem_regions[i].mr_start) &&
459 (pa < (physmem_regions[i].mr_start +
460 physmem_regions[i].mr_size))) {
461 attrib = _TLB_ENTRY_MEM;
462 break;
463 }
464 }
465
466 return (attrib);
467 }
468
469 static inline void
tlb_miss_lock(void)470 tlb_miss_lock(void)
471 {
472 #ifdef SMP
473 struct pcpu *pc;
474
475 if (!smp_started)
476 return;
477
478 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
479 if (pc != pcpup) {
480 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
481 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
482
483 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
484 ("tlb_miss_lock: tried to lock self"));
485
486 tlb_lock(pc->pc_booke.tlb_lock);
487
488 CTR1(KTR_PMAP, "%s: locked", __func__);
489 }
490 }
491 #endif
492 }
493
494 static inline void
tlb_miss_unlock(void)495 tlb_miss_unlock(void)
496 {
497 #ifdef SMP
498 struct pcpu *pc;
499
500 if (!smp_started)
501 return;
502
503 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
504 if (pc != pcpup) {
505 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
506 __func__, pc->pc_cpuid);
507
508 tlb_unlock(pc->pc_booke.tlb_lock);
509
510 CTR1(KTR_PMAP, "%s: unlocked", __func__);
511 }
512 }
513 #endif
514 }
515
516 /* Return number of entries in TLB0. */
517 static __inline void
tlb0_get_tlbconf(void)518 tlb0_get_tlbconf(void)
519 {
520 uint32_t tlb0_cfg;
521
522 tlb0_cfg = mfspr(SPR_TLB0CFG);
523 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
524 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
525 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
526 }
527
528 /* Return number of entries in TLB1. */
529 static __inline void
tlb1_get_tlbconf(void)530 tlb1_get_tlbconf(void)
531 {
532 uint32_t tlb1_cfg;
533
534 tlb1_cfg = mfspr(SPR_TLB1CFG);
535 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
536 }
537
538 /**************************************************************************/
539 /* Page table related */
540 /**************************************************************************/
541
542 /* Allocate pv_entry structure. */
543 pv_entry_t
pv_alloc(void)544 pv_alloc(void)
545 {
546 pv_entry_t pv;
547
548 pv_entry_count++;
549 if (pv_entry_count > pv_entry_high_water)
550 pagedaemon_wakeup(0); /* XXX powerpc NUMA */
551 pv = uma_zalloc(pvzone, M_NOWAIT);
552
553 return (pv);
554 }
555
556 /* Free pv_entry structure. */
557 static __inline void
pv_free(pv_entry_t pve)558 pv_free(pv_entry_t pve)
559 {
560
561 pv_entry_count--;
562 uma_zfree(pvzone, pve);
563 }
564
565 /* Allocate and initialize pv_entry structure. */
566 static void
pv_insert(pmap_t pmap,vm_offset_t va,vm_page_t m)567 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
568 {
569 pv_entry_t pve;
570
571 //int su = (pmap == kernel_pmap);
572 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
573 // (u_int32_t)pmap, va, (u_int32_t)m);
574
575 pve = pv_alloc();
576 if (pve == NULL)
577 panic("pv_insert: no pv entries!");
578
579 pve->pv_pmap = pmap;
580 pve->pv_va = va;
581
582 /* add to pv_list */
583 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
584 rw_assert(&pvh_global_lock, RA_WLOCKED);
585
586 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
587
588 //debugf("pv_insert: e\n");
589 }
590
591 /* Destroy pv entry. */
592 static void
pv_remove(pmap_t pmap,vm_offset_t va,vm_page_t m)593 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
594 {
595 pv_entry_t pve;
596
597 //int su = (pmap == kernel_pmap);
598 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
599
600 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
601 rw_assert(&pvh_global_lock, RA_WLOCKED);
602
603 /* find pv entry */
604 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
605 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
606 /* remove from pv_list */
607 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
608 if (TAILQ_EMPTY(&m->md.pv_list))
609 vm_page_aflag_clear(m, PGA_WRITEABLE);
610
611 /* free pv entry struct */
612 pv_free(pve);
613 break;
614 }
615 }
616
617 //debugf("pv_remove: e\n");
618 }
619
620 /**************************************************************************/
621 /* PMAP related */
622 /**************************************************************************/
623
624 /*
625 * This is called during booke_init, before the system is really initialized.
626 */
627 static void
mmu_booke_bootstrap(vm_offset_t start,vm_offset_t kernelend)628 mmu_booke_bootstrap(vm_offset_t start, vm_offset_t kernelend)
629 {
630 vm_paddr_t phys_kernelend;
631 struct mem_region *mp, *mp1;
632 int cnt, i, j;
633 vm_paddr_t s, e, sz;
634 vm_paddr_t physsz, hwphyssz;
635 u_int phys_avail_count __debug_used;
636 vm_size_t kstack0_sz;
637 vm_paddr_t kstack0_phys;
638 vm_offset_t kstack0;
639 void *dpcpu;
640
641 debugf("mmu_booke_bootstrap: entered\n");
642
643 /* Set interesting system properties */
644 #ifdef __powerpc64__
645 hw_direct_map = 1;
646 #else
647 hw_direct_map = 0;
648 #endif
649 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
650 elf32_nxstack = 1;
651 #endif
652
653 /* Initialize invalidation mutex */
654 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
655
656 /* Read TLB0 size and associativity. */
657 tlb0_get_tlbconf();
658
659 /*
660 * Align kernel start and end address (kernel image).
661 * Note that kernel end does not necessarily relate to kernsize.
662 * kernsize is the size of the kernel that is actually mapped.
663 */
664 data_start = round_page(kernelend);
665 data_end = data_start;
666
667 /* Allocate the dynamic per-cpu area. */
668 dpcpu = (void *)data_end;
669 data_end += DPCPU_SIZE;
670
671 /* Allocate space for the message buffer. */
672 msgbufp = (struct msgbuf *)data_end;
673 data_end += msgbufsize;
674 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
675 (uintptr_t)msgbufp, data_end);
676
677 data_end = round_page(data_end);
678 data_end = round_page(mmu_booke_alloc_kernel_pgtables(data_end));
679
680 /* Retrieve phys/avail mem regions */
681 mem_regions(&physmem_regions, &physmem_regions_sz,
682 &availmem_regions, &availmem_regions_sz);
683
684 if (PHYS_AVAIL_ENTRIES < availmem_regions_sz)
685 panic("mmu_booke_bootstrap: phys_avail too small");
686
687 data_end = round_page(data_end);
688 vm_page_array = (vm_page_t)data_end;
689 /*
690 * Get a rough idea (upper bound) on the size of the page array. The
691 * vm_page_array will not handle any more pages than we have in the
692 * avail_regions array, and most likely much less.
693 */
694 sz = 0;
695 for (mp = availmem_regions; mp->mr_size; mp++) {
696 sz += mp->mr_size;
697 }
698 sz = (round_page(sz) / (PAGE_SIZE + sizeof(struct vm_page)));
699 data_end += round_page(sz * sizeof(struct vm_page));
700
701 /* Pre-round up to 1MB. This wastes some space, but saves TLB entries */
702 data_end = roundup2(data_end, 1 << 20);
703
704 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end);
705 debugf(" kernstart: %#zx\n", kernstart);
706 debugf(" kernsize: %#zx\n", kernsize);
707
708 if (data_end - kernstart > kernsize) {
709 kernsize += tlb1_mapin_region(kernstart + kernsize,
710 kernload + kernsize, (data_end - kernstart) - kernsize,
711 _TLB_ENTRY_MEM);
712 }
713 data_end = kernstart + kernsize;
714 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end);
715
716 /*
717 * Clear the structures - note we can only do it safely after the
718 * possible additional TLB1 translations are in place (above) so that
719 * all range up to the currently calculated 'data_end' is covered.
720 */
721 bzero((void *)data_start, data_end - data_start);
722 dpcpu_init(dpcpu, 0);
723
724 /*******************************************************/
725 /* Set the start and end of kva. */
726 /*******************************************************/
727 virtual_avail = round_page(data_end);
728 virtual_end = VM_MAX_KERNEL_ADDRESS;
729
730 #ifndef __powerpc64__
731 /* Allocate KVA space for page zero/copy operations. */
732 zero_page_va = virtual_avail;
733 virtual_avail += PAGE_SIZE;
734 copy_page_src_va = virtual_avail;
735 virtual_avail += PAGE_SIZE;
736 copy_page_dst_va = virtual_avail;
737 virtual_avail += PAGE_SIZE;
738 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va);
739 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va);
740 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va);
741
742 /* Initialize page zero/copy mutexes. */
743 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
744 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
745
746 /* Allocate KVA space for ptbl bufs. */
747 ptbl_buf_pool_vabase = virtual_avail;
748 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
749 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
750 ptbl_buf_pool_vabase, virtual_avail);
751 #endif
752
753 /* Calculate corresponding physical addresses for the kernel region. */
754 phys_kernelend = kernload + kernsize;
755 debugf("kernel image and allocated data:\n");
756 debugf(" kernload = 0x%09jx\n", (uintmax_t)kernload);
757 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart);
758 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize);
759
760 /*
761 * Remove kernel physical address range from avail regions list. Page
762 * align all regions. Non-page aligned memory isn't very interesting
763 * to us. Also, sort the entries for ascending addresses.
764 */
765
766 sz = 0;
767 cnt = availmem_regions_sz;
768 debugf("processing avail regions:\n");
769 for (mp = availmem_regions; mp->mr_size; mp++) {
770 s = mp->mr_start;
771 e = mp->mr_start + mp->mr_size;
772 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e);
773 /* Check whether this region holds all of the kernel. */
774 if (s < kernload && e > phys_kernelend) {
775 availmem_regions[cnt].mr_start = phys_kernelend;
776 availmem_regions[cnt++].mr_size = e - phys_kernelend;
777 e = kernload;
778 }
779 /* Look whether this regions starts within the kernel. */
780 if (s >= kernload && s < phys_kernelend) {
781 if (e <= phys_kernelend)
782 goto empty;
783 s = phys_kernelend;
784 }
785 /* Now look whether this region ends within the kernel. */
786 if (e > kernload && e <= phys_kernelend) {
787 if (s >= kernload)
788 goto empty;
789 e = kernload;
790 }
791 /* Now page align the start and size of the region. */
792 s = round_page(s);
793 e = trunc_page(e);
794 if (e < s)
795 e = s;
796 sz = e - s;
797 debugf("%09jx-%09jx = %jx\n",
798 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz);
799
800 /* Check whether some memory is left here. */
801 if (sz == 0) {
802 empty:
803 memmove(mp, mp + 1,
804 (cnt - (mp - availmem_regions)) * sizeof(*mp));
805 cnt--;
806 mp--;
807 continue;
808 }
809
810 /* Do an insertion sort. */
811 for (mp1 = availmem_regions; mp1 < mp; mp1++)
812 if (s < mp1->mr_start)
813 break;
814 if (mp1 < mp) {
815 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
816 mp1->mr_start = s;
817 mp1->mr_size = sz;
818 } else {
819 mp->mr_start = s;
820 mp->mr_size = sz;
821 }
822 }
823 availmem_regions_sz = cnt;
824
825 /*******************************************************/
826 /* Steal physical memory for kernel stack from the end */
827 /* of the first avail region */
828 /*******************************************************/
829 kstack0_sz = kstack_pages * PAGE_SIZE;
830 kstack0_phys = availmem_regions[0].mr_start +
831 availmem_regions[0].mr_size;
832 kstack0_phys -= kstack0_sz;
833 availmem_regions[0].mr_size -= kstack0_sz;
834
835 /*******************************************************/
836 /* Fill in phys_avail table, based on availmem_regions */
837 /*******************************************************/
838 phys_avail_count = 0;
839 physsz = 0;
840 hwphyssz = 0;
841 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
842
843 debugf("fill in phys_avail:\n");
844 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
845 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
846 (uintmax_t)availmem_regions[i].mr_start,
847 (uintmax_t)availmem_regions[i].mr_start +
848 availmem_regions[i].mr_size,
849 (uintmax_t)availmem_regions[i].mr_size);
850
851 if (hwphyssz != 0 &&
852 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
853 debugf(" hw.physmem adjust\n");
854 if (physsz < hwphyssz) {
855 phys_avail[j] = availmem_regions[i].mr_start;
856 phys_avail[j + 1] =
857 availmem_regions[i].mr_start +
858 hwphyssz - physsz;
859 physsz = hwphyssz;
860 phys_avail_count++;
861 dump_avail[j] = phys_avail[j];
862 dump_avail[j + 1] = phys_avail[j + 1];
863 }
864 break;
865 }
866
867 phys_avail[j] = availmem_regions[i].mr_start;
868 phys_avail[j + 1] = availmem_regions[i].mr_start +
869 availmem_regions[i].mr_size;
870 phys_avail_count++;
871 physsz += availmem_regions[i].mr_size;
872 dump_avail[j] = phys_avail[j];
873 dump_avail[j + 1] = phys_avail[j + 1];
874 }
875 physmem = btoc(physsz);
876
877 /* Calculate the last available physical address. */
878 for (i = 0; phys_avail[i + 2] != 0; i += 2)
879 ;
880 Maxmem = powerpc_btop(phys_avail[i + 1]);
881
882 debugf("Maxmem = 0x%08lx\n", Maxmem);
883 debugf("phys_avail_count = %d\n", phys_avail_count);
884 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n",
885 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem);
886
887 #ifdef __powerpc64__
888 /*
889 * Map the physical memory contiguously in TLB1.
890 * Round so it fits into a single mapping.
891 */
892 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0,
893 phys_avail[i + 1], _TLB_ENTRY_MEM);
894 #endif
895
896 /*******************************************************/
897 /* Initialize (statically allocated) kernel pmap. */
898 /*******************************************************/
899 PMAP_LOCK_INIT(kernel_pmap);
900
901 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap);
902 kernel_pte_alloc(virtual_avail, kernstart);
903 for (i = 0; i < MAXCPU; i++) {
904 kernel_pmap->pm_tid[i] = TID_KERNEL;
905
906 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
907 tidbusy[i][TID_KERNEL] = kernel_pmap;
908 }
909
910 /* Mark kernel_pmap active on all CPUs */
911 CPU_FILL(&kernel_pmap->pm_active);
912
913 /*
914 * Initialize the global pv list lock.
915 */
916 rw_init(&pvh_global_lock, "pmap pv global");
917
918 /*******************************************************/
919 /* Final setup */
920 /*******************************************************/
921
922 /* Enter kstack0 into kernel map, provide guard page */
923 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
924 thread0.td_kstack = kstack0;
925 thread0.td_kstack_pages = kstack_pages;
926
927 debugf("kstack_sz = 0x%08jx\n", (uintmax_t)kstack0_sz);
928 debugf("kstack0_phys at 0x%09jx - 0x%09jx\n",
929 (uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz);
930 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
931 kstack0, kstack0 + kstack0_sz);
932
933 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
934 for (i = 0; i < kstack_pages; i++) {
935 mmu_booke_kenter(kstack0, kstack0_phys);
936 kstack0 += PAGE_SIZE;
937 kstack0_phys += PAGE_SIZE;
938 }
939
940 pmap_bootstrapped = 1;
941
942 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
943 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
944
945 debugf("mmu_booke_bootstrap: exit\n");
946 }
947
948 #ifdef SMP
949 void
tlb1_ap_prep(void)950 tlb1_ap_prep(void)
951 {
952 tlb_entry_t *e, tmp;
953 unsigned int i;
954
955 /* Prepare TLB1 image for AP processors */
956 e = __boot_tlb1;
957 for (i = 0; i < TLB1_ENTRIES; i++) {
958 tlb1_read_entry(&tmp, i);
959
960 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED))
961 memcpy(e++, &tmp, sizeof(tmp));
962 }
963 }
964
965 void
pmap_bootstrap_ap(volatile uint32_t * trcp __unused)966 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
967 {
968 int i;
969
970 /*
971 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
972 * have the snapshot of its contents in the s/w __boot_tlb1[] table
973 * created by tlb1_ap_prep(), so use these values directly to
974 * (re)program AP's TLB1 hardware.
975 *
976 * Start at index 1 because index 0 has the kernel map.
977 */
978 for (i = 1; i < TLB1_ENTRIES; i++) {
979 if (__boot_tlb1[i].mas1 & MAS1_VALID)
980 tlb1_write_entry(&__boot_tlb1[i], i);
981 }
982
983 set_mas4_defaults();
984 }
985 #endif
986
987 static void
booke_pmap_init_qpages(void)988 booke_pmap_init_qpages(void)
989 {
990 struct pcpu *pc;
991 int i;
992
993 CPU_FOREACH(i) {
994 pc = pcpu_find(i);
995 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
996 if (pc->pc_qmap_addr == 0)
997 panic("pmap_init_qpages: unable to allocate KVA");
998 }
999 }
1000
1001 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL);
1002
1003 /*
1004 * Get the physical page address for the given pmap/virtual address.
1005 */
1006 static vm_paddr_t
mmu_booke_extract(pmap_t pmap,vm_offset_t va)1007 mmu_booke_extract(pmap_t pmap, vm_offset_t va)
1008 {
1009 vm_paddr_t pa;
1010
1011 PMAP_LOCK(pmap);
1012 pa = pte_vatopa(pmap, va);
1013 PMAP_UNLOCK(pmap);
1014
1015 return (pa);
1016 }
1017
1018 /*
1019 * Extract the physical page address associated with the given
1020 * kernel virtual address.
1021 */
1022 static vm_paddr_t
mmu_booke_kextract(vm_offset_t va)1023 mmu_booke_kextract(vm_offset_t va)
1024 {
1025 tlb_entry_t e;
1026 vm_paddr_t p = 0;
1027 int i;
1028
1029 #ifdef __powerpc64__
1030 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS)
1031 return (DMAP_TO_PHYS(va));
1032 #endif
1033
1034 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
1035 p = pte_vatopa(kernel_pmap, va);
1036
1037 if (p == 0) {
1038 /* Check TLB1 mappings */
1039 for (i = 0; i < TLB1_ENTRIES; i++) {
1040 tlb1_read_entry(&e, i);
1041 if (!(e.mas1 & MAS1_VALID))
1042 continue;
1043 if (va >= e.virt && va < e.virt + e.size)
1044 return (e.phys + (va - e.virt));
1045 }
1046 }
1047
1048 return (p);
1049 }
1050
1051 /*
1052 * Initialize the pmap module.
1053 *
1054 * Called by vm_mem_init(), to initialize any structures that the pmap system
1055 * needs to map virtual memory.
1056 */
1057 static void
mmu_booke_init(void)1058 mmu_booke_init(void)
1059 {
1060 int shpgperproc = PMAP_SHPGPERPROC;
1061
1062 /*
1063 * Initialize the address space (zone) for the pv entries. Set a
1064 * high water mark so that the system can recover from excessive
1065 * numbers of pv entries.
1066 */
1067 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1068 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1069
1070 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1071 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1072
1073 TUNABLE_INT_FETCH("vm.pmap.pv_entry_max", &pv_entry_max);
1074 pv_entry_high_water = 9 * (pv_entry_max / 10);
1075
1076 uma_zone_reserve_kva(pvzone, pv_entry_max);
1077
1078 /* Pre-fill pvzone with initial number of pv entries. */
1079 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1080
1081 /* Create a UMA zone for page table roots. */
1082 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE,
1083 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM);
1084
1085 /* Initialize ptbl allocation. */
1086 ptbl_init();
1087 }
1088
1089 /*
1090 * Map a list of wired pages into kernel virtual address space. This is
1091 * intended for temporary mappings which do not need page modification or
1092 * references recorded. Existing mappings in the region are overwritten.
1093 */
1094 static void
mmu_booke_qenter(vm_offset_t sva,vm_page_t * m,int count)1095 mmu_booke_qenter(vm_offset_t sva, vm_page_t *m, int count)
1096 {
1097 vm_offset_t va;
1098
1099 va = sva;
1100 while (count-- > 0) {
1101 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(*m));
1102 va += PAGE_SIZE;
1103 m++;
1104 }
1105 }
1106
1107 /*
1108 * Remove page mappings from kernel virtual address space. Intended for
1109 * temporary mappings entered by mmu_booke_qenter.
1110 */
1111 static void
mmu_booke_qremove(vm_offset_t sva,int count)1112 mmu_booke_qremove(vm_offset_t sva, int count)
1113 {
1114 vm_offset_t va;
1115
1116 va = sva;
1117 while (count-- > 0) {
1118 mmu_booke_kremove(va);
1119 va += PAGE_SIZE;
1120 }
1121 }
1122
1123 /*
1124 * Map a wired page into kernel virtual address space.
1125 */
1126 static void
mmu_booke_kenter(vm_offset_t va,vm_paddr_t pa)1127 mmu_booke_kenter(vm_offset_t va, vm_paddr_t pa)
1128 {
1129
1130 mmu_booke_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
1131 }
1132
1133 static void
mmu_booke_kenter_attr(vm_offset_t va,vm_paddr_t pa,vm_memattr_t ma)1134 mmu_booke_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1135 {
1136 uint32_t flags;
1137 pte_t *pte;
1138
1139 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1140 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1141
1142 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1143 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
1144 flags |= PTE_PS_4KB;
1145
1146 pte = pte_find(kernel_pmap, va);
1147 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE"));
1148
1149 mtx_lock_spin(&tlbivax_mutex);
1150 tlb_miss_lock();
1151
1152 if (PTE_ISVALID(pte)) {
1153 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1154
1155 /* Flush entry from TLB0 */
1156 tlb0_flush_entry(va);
1157 }
1158
1159 *pte = PTE_RPN_FROM_PA(pa) | flags;
1160
1161 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1162 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1163 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1164
1165 /* Flush the real memory from the instruction cache. */
1166 if ((flags & (PTE_I | PTE_G)) == 0)
1167 __syncicache((void *)va, PAGE_SIZE);
1168
1169 tlb_miss_unlock();
1170 mtx_unlock_spin(&tlbivax_mutex);
1171 }
1172
1173 /*
1174 * Remove a page from kernel page table.
1175 */
1176 static void
mmu_booke_kremove(vm_offset_t va)1177 mmu_booke_kremove(vm_offset_t va)
1178 {
1179 pte_t *pte;
1180
1181 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va);
1182
1183 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1184 (va <= VM_MAX_KERNEL_ADDRESS)),
1185 ("mmu_booke_kremove: invalid va"));
1186
1187 pte = pte_find(kernel_pmap, va);
1188
1189 if (!PTE_ISVALID(pte)) {
1190 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1191
1192 return;
1193 }
1194
1195 mtx_lock_spin(&tlbivax_mutex);
1196 tlb_miss_lock();
1197
1198 /* Invalidate entry in TLB0, update PTE. */
1199 tlb0_flush_entry(va);
1200 *pte = 0;
1201
1202 tlb_miss_unlock();
1203 mtx_unlock_spin(&tlbivax_mutex);
1204 }
1205
1206 /*
1207 * Figure out where a given kernel pointer (usually in a fault) points
1208 * to from the VM's perspective, potentially remapping into userland's
1209 * address space.
1210 */
1211 static int
mmu_booke_decode_kernel_ptr(vm_offset_t addr,int * is_user,vm_offset_t * decoded_addr)1212 mmu_booke_decode_kernel_ptr(vm_offset_t addr, int *is_user,
1213 vm_offset_t *decoded_addr)
1214 {
1215
1216 if (trunc_page(addr) <= VM_MAXUSER_ADDRESS)
1217 *is_user = 1;
1218 else
1219 *is_user = 0;
1220
1221 *decoded_addr = addr;
1222 return (0);
1223 }
1224
1225 static boolean_t
mmu_booke_page_is_mapped(vm_page_t m)1226 mmu_booke_page_is_mapped(vm_page_t m)
1227 {
1228
1229 return (!TAILQ_EMPTY(&(m)->md.pv_list));
1230 }
1231
1232 static bool
mmu_booke_ps_enabled(pmap_t pmap __unused)1233 mmu_booke_ps_enabled(pmap_t pmap __unused)
1234 {
1235 return (false);
1236 }
1237
1238 /*
1239 * Initialize pmap associated with process 0.
1240 */
1241 static void
mmu_booke_pinit0(pmap_t pmap)1242 mmu_booke_pinit0(pmap_t pmap)
1243 {
1244
1245 PMAP_LOCK_INIT(pmap);
1246 mmu_booke_pinit(pmap);
1247 PCPU_SET(curpmap, pmap);
1248 }
1249
1250 /*
1251 * Insert the given physical page at the specified virtual address in the
1252 * target physical map with the protection requested. If specified the page
1253 * will be wired down.
1254 */
1255 static int
mmu_booke_enter(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,u_int flags,int8_t psind)1256 mmu_booke_enter(pmap_t pmap, vm_offset_t va, vm_page_t m,
1257 vm_prot_t prot, u_int flags, int8_t psind)
1258 {
1259 int error;
1260
1261 rw_wlock(&pvh_global_lock);
1262 PMAP_LOCK(pmap);
1263 error = mmu_booke_enter_locked(pmap, va, m, prot, flags, psind);
1264 PMAP_UNLOCK(pmap);
1265 rw_wunlock(&pvh_global_lock);
1266 return (error);
1267 }
1268
1269 static int
mmu_booke_enter_locked(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,u_int pmap_flags,int8_t psind __unused)1270 mmu_booke_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
1271 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
1272 {
1273 pte_t *pte;
1274 vm_paddr_t pa;
1275 pte_t flags;
1276 int error, su, sync;
1277
1278 pa = VM_PAGE_TO_PHYS(m);
1279 su = (pmap == kernel_pmap);
1280 sync = 0;
1281
1282 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1283 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
1284 // (u_int32_t)pmap, su, pmap->pm_tid,
1285 // (u_int32_t)m, va, pa, prot, flags);
1286
1287 if (su) {
1288 KASSERT(((va >= virtual_avail) &&
1289 (va <= VM_MAX_KERNEL_ADDRESS)),
1290 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1291 } else {
1292 KASSERT((va <= VM_MAXUSER_ADDRESS),
1293 ("mmu_booke_enter_locked: user pmap, non user va"));
1294 }
1295 if ((m->oflags & VPO_UNMANAGED) == 0) {
1296 if ((pmap_flags & PMAP_ENTER_QUICK_LOCKED) == 0)
1297 VM_PAGE_OBJECT_BUSY_ASSERT(m);
1298 else
1299 VM_OBJECT_ASSERT_LOCKED(m->object);
1300 }
1301
1302 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1303
1304 /*
1305 * If there is an existing mapping, and the physical address has not
1306 * changed, must be protection or wiring change.
1307 */
1308 if (((pte = pte_find(pmap, va)) != NULL) &&
1309 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1310
1311 /*
1312 * Before actually updating pte->flags we calculate and
1313 * prepare its new value in a helper var.
1314 */
1315 flags = *pte;
1316 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1317
1318 /* Wiring change, just update stats. */
1319 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
1320 if (!PTE_ISWIRED(pte)) {
1321 flags |= PTE_WIRED;
1322 pmap->pm_stats.wired_count++;
1323 }
1324 } else {
1325 if (PTE_ISWIRED(pte)) {
1326 flags &= ~PTE_WIRED;
1327 pmap->pm_stats.wired_count--;
1328 }
1329 }
1330
1331 if (prot & VM_PROT_WRITE) {
1332 /* Add write permissions. */
1333 flags |= PTE_SW;
1334 if (!su)
1335 flags |= PTE_UW;
1336
1337 if ((flags & PTE_MANAGED) != 0)
1338 vm_page_aflag_set(m, PGA_WRITEABLE);
1339 } else {
1340 /* Handle modified pages, sense modify status. */
1341
1342 /*
1343 * The PTE_MODIFIED flag could be set by underlying
1344 * TLB misses since we last read it (above), possibly
1345 * other CPUs could update it so we check in the PTE
1346 * directly rather than rely on that saved local flags
1347 * copy.
1348 */
1349 if (PTE_ISMODIFIED(pte))
1350 vm_page_dirty(m);
1351 }
1352
1353 if (prot & VM_PROT_EXECUTE) {
1354 flags |= PTE_SX;
1355 if (!su)
1356 flags |= PTE_UX;
1357
1358 /*
1359 * Check existing flags for execute permissions: if we
1360 * are turning execute permissions on, icache should
1361 * be flushed.
1362 */
1363 if ((*pte & (PTE_UX | PTE_SX)) == 0)
1364 sync++;
1365 }
1366
1367 flags &= ~PTE_REFERENCED;
1368
1369 /*
1370 * The new flags value is all calculated -- only now actually
1371 * update the PTE.
1372 */
1373 mtx_lock_spin(&tlbivax_mutex);
1374 tlb_miss_lock();
1375
1376 tlb0_flush_entry(va);
1377 *pte &= ~PTE_FLAGS_MASK;
1378 *pte |= flags;
1379
1380 tlb_miss_unlock();
1381 mtx_unlock_spin(&tlbivax_mutex);
1382
1383 } else {
1384 /*
1385 * If there is an existing mapping, but it's for a different
1386 * physical address, pte_enter() will delete the old mapping.
1387 */
1388 //if ((pte != NULL) && PTE_ISVALID(pte))
1389 // debugf("mmu_booke_enter_locked: replace\n");
1390 //else
1391 // debugf("mmu_booke_enter_locked: new\n");
1392
1393 /* Now set up the flags and install the new mapping. */
1394 flags = (PTE_SR | PTE_VALID);
1395 flags |= PTE_M;
1396
1397 if (!su)
1398 flags |= PTE_UR;
1399
1400 if (prot & VM_PROT_WRITE) {
1401 flags |= PTE_SW;
1402 if (!su)
1403 flags |= PTE_UW;
1404
1405 if ((m->oflags & VPO_UNMANAGED) == 0)
1406 vm_page_aflag_set(m, PGA_WRITEABLE);
1407 }
1408
1409 if (prot & VM_PROT_EXECUTE) {
1410 flags |= PTE_SX;
1411 if (!su)
1412 flags |= PTE_UX;
1413 }
1414
1415 /* If its wired update stats. */
1416 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
1417 flags |= PTE_WIRED;
1418
1419 error = pte_enter(pmap, m, va, flags,
1420 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
1421 if (error != 0)
1422 return (KERN_RESOURCE_SHORTAGE);
1423
1424 if ((flags & PMAP_ENTER_WIRED) != 0)
1425 pmap->pm_stats.wired_count++;
1426
1427 /* Flush the real memory from the instruction cache. */
1428 if (prot & VM_PROT_EXECUTE)
1429 sync++;
1430 }
1431
1432 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1433 __syncicache((void *)va, PAGE_SIZE);
1434 sync = 0;
1435 }
1436
1437 return (KERN_SUCCESS);
1438 }
1439
1440 /*
1441 * Maps a sequence of resident pages belonging to the same object.
1442 * The sequence begins with the given page m_start. This page is
1443 * mapped at the given virtual address start. Each subsequent page is
1444 * mapped at a virtual address that is offset from start by the same
1445 * amount as the page is offset from m_start within the object. The
1446 * last page in the sequence is the page with the largest offset from
1447 * m_start that can be mapped at a virtual address less than the given
1448 * virtual address end. Not every virtual page between start and end
1449 * is mapped; only those for which a resident page exists with the
1450 * corresponding offset from m_start are mapped.
1451 */
1452 static void
mmu_booke_enter_object(pmap_t pmap,vm_offset_t start,vm_offset_t end,vm_page_t m_start,vm_prot_t prot)1453 mmu_booke_enter_object(pmap_t pmap, vm_offset_t start,
1454 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1455 {
1456 vm_page_t m;
1457 vm_pindex_t diff, psize;
1458
1459 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1460
1461 psize = atop(end - start);
1462 m = m_start;
1463 rw_wlock(&pvh_global_lock);
1464 PMAP_LOCK(pmap);
1465 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1466 mmu_booke_enter_locked(pmap, start + ptoa(diff), m,
1467 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1468 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0);
1469 m = TAILQ_NEXT(m, listq);
1470 }
1471 PMAP_UNLOCK(pmap);
1472 rw_wunlock(&pvh_global_lock);
1473 }
1474
1475 static void
mmu_booke_enter_quick(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot)1476 mmu_booke_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m,
1477 vm_prot_t prot)
1478 {
1479
1480 rw_wlock(&pvh_global_lock);
1481 PMAP_LOCK(pmap);
1482 mmu_booke_enter_locked(pmap, va, m,
1483 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP |
1484 PMAP_ENTER_QUICK_LOCKED, 0);
1485 PMAP_UNLOCK(pmap);
1486 rw_wunlock(&pvh_global_lock);
1487 }
1488
1489 /*
1490 * Remove the given range of addresses from the specified map.
1491 *
1492 * It is assumed that the start and end are properly rounded to the page size.
1493 */
1494 static void
mmu_booke_remove(pmap_t pmap,vm_offset_t va,vm_offset_t endva)1495 mmu_booke_remove(pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1496 {
1497 pte_t *pte;
1498 uint8_t hold_flag;
1499
1500 int su = (pmap == kernel_pmap);
1501
1502 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1503 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1504
1505 if (su) {
1506 KASSERT(((va >= virtual_avail) &&
1507 (va <= VM_MAX_KERNEL_ADDRESS)),
1508 ("mmu_booke_remove: kernel pmap, non kernel va"));
1509 } else {
1510 KASSERT((va <= VM_MAXUSER_ADDRESS),
1511 ("mmu_booke_remove: user pmap, non user va"));
1512 }
1513
1514 if (PMAP_REMOVE_DONE(pmap)) {
1515 //debugf("mmu_booke_remove: e (empty)\n");
1516 return;
1517 }
1518
1519 hold_flag = PTBL_HOLD_FLAG(pmap);
1520 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1521
1522 rw_wlock(&pvh_global_lock);
1523 PMAP_LOCK(pmap);
1524 for (; va < endva; va += PAGE_SIZE) {
1525 pte = pte_find_next(pmap, &va);
1526 if ((pte == NULL) || !PTE_ISVALID(pte))
1527 break;
1528 if (va >= endva)
1529 break;
1530 pte_remove(pmap, va, hold_flag);
1531 }
1532 PMAP_UNLOCK(pmap);
1533 rw_wunlock(&pvh_global_lock);
1534
1535 //debugf("mmu_booke_remove: e\n");
1536 }
1537
1538 /*
1539 * Remove physical page from all pmaps in which it resides.
1540 */
1541 static void
mmu_booke_remove_all(vm_page_t m)1542 mmu_booke_remove_all(vm_page_t m)
1543 {
1544 pv_entry_t pv, pvn;
1545 uint8_t hold_flag;
1546
1547 rw_wlock(&pvh_global_lock);
1548 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_link, pvn) {
1549 PMAP_LOCK(pv->pv_pmap);
1550 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1551 pte_remove(pv->pv_pmap, pv->pv_va, hold_flag);
1552 PMAP_UNLOCK(pv->pv_pmap);
1553 }
1554 vm_page_aflag_clear(m, PGA_WRITEABLE);
1555 rw_wunlock(&pvh_global_lock);
1556 }
1557
1558 /*
1559 * Map a range of physical addresses into kernel virtual address space.
1560 */
1561 static vm_offset_t
mmu_booke_map(vm_offset_t * virt,vm_paddr_t pa_start,vm_paddr_t pa_end,int prot)1562 mmu_booke_map(vm_offset_t *virt, vm_paddr_t pa_start,
1563 vm_paddr_t pa_end, int prot)
1564 {
1565 vm_offset_t sva = *virt;
1566 vm_offset_t va = sva;
1567
1568 #ifdef __powerpc64__
1569 /* XXX: Handle memory not starting at 0x0. */
1570 if (pa_end < ctob(Maxmem))
1571 return (PHYS_TO_DMAP(pa_start));
1572 #endif
1573
1574 while (pa_start < pa_end) {
1575 mmu_booke_kenter(va, pa_start);
1576 va += PAGE_SIZE;
1577 pa_start += PAGE_SIZE;
1578 }
1579 *virt = va;
1580
1581 return (sva);
1582 }
1583
1584 /*
1585 * The pmap must be activated before it's address space can be accessed in any
1586 * way.
1587 */
1588 static void
mmu_booke_activate(struct thread * td)1589 mmu_booke_activate(struct thread *td)
1590 {
1591 pmap_t pmap;
1592 u_int cpuid;
1593
1594 pmap = &td->td_proc->p_vmspace->vm_pmap;
1595
1596 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")",
1597 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1598
1599 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1600
1601 sched_pin();
1602
1603 cpuid = PCPU_GET(cpuid);
1604 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1605 PCPU_SET(curpmap, pmap);
1606
1607 if (pmap->pm_tid[cpuid] == TID_NONE)
1608 tid_alloc(pmap);
1609
1610 /* Load PID0 register with pmap tid value. */
1611 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1612 __asm __volatile("isync");
1613
1614 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
1615
1616 sched_unpin();
1617
1618 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1619 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1620 }
1621
1622 /*
1623 * Deactivate the specified process's address space.
1624 */
1625 static void
mmu_booke_deactivate(struct thread * td)1626 mmu_booke_deactivate(struct thread *td)
1627 {
1628 pmap_t pmap;
1629
1630 pmap = &td->td_proc->p_vmspace->vm_pmap;
1631
1632 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
1633 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1634
1635 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
1636
1637 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1638 PCPU_SET(curpmap, NULL);
1639 }
1640
1641 /*
1642 * Copy the range specified by src_addr/len
1643 * from the source map to the range dst_addr/len
1644 * in the destination map.
1645 *
1646 * This routine is only advisory and need not do anything.
1647 */
1648 static void
mmu_booke_copy(pmap_t dst_pmap,pmap_t src_pmap,vm_offset_t dst_addr,vm_size_t len,vm_offset_t src_addr)1649 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap,
1650 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1651 {
1652
1653 }
1654
1655 /*
1656 * Set the physical protection on the specified range of this map as requested.
1657 */
1658 static void
mmu_booke_protect(pmap_t pmap,vm_offset_t sva,vm_offset_t eva,vm_prot_t prot)1659 mmu_booke_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1660 vm_prot_t prot)
1661 {
1662 vm_offset_t va;
1663 vm_page_t m;
1664 pte_t *pte;
1665
1666 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1667 mmu_booke_remove(pmap, sva, eva);
1668 return;
1669 }
1670
1671 if (prot & VM_PROT_WRITE)
1672 return;
1673
1674 PMAP_LOCK(pmap);
1675 for (va = sva; va < eva; va += PAGE_SIZE) {
1676 if ((pte = pte_find(pmap, va)) != NULL) {
1677 if (PTE_ISVALID(pte)) {
1678 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1679
1680 mtx_lock_spin(&tlbivax_mutex);
1681 tlb_miss_lock();
1682
1683 /* Handle modified pages. */
1684 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1685 vm_page_dirty(m);
1686
1687 tlb0_flush_entry(va);
1688 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1689
1690 tlb_miss_unlock();
1691 mtx_unlock_spin(&tlbivax_mutex);
1692 }
1693 }
1694 }
1695 PMAP_UNLOCK(pmap);
1696 }
1697
1698 /*
1699 * Clear the write and modified bits in each of the given page's mappings.
1700 */
1701 static void
mmu_booke_remove_write(vm_page_t m)1702 mmu_booke_remove_write(vm_page_t m)
1703 {
1704 pv_entry_t pv;
1705 pte_t *pte;
1706
1707 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1708 ("mmu_booke_remove_write: page %p is not managed", m));
1709 vm_page_assert_busied(m);
1710
1711 if (!pmap_page_is_write_mapped(m))
1712 return;
1713 rw_wlock(&pvh_global_lock);
1714 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1715 PMAP_LOCK(pv->pv_pmap);
1716 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) {
1717 if (PTE_ISVALID(pte)) {
1718 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1719
1720 mtx_lock_spin(&tlbivax_mutex);
1721 tlb_miss_lock();
1722
1723 /* Handle modified pages. */
1724 if (PTE_ISMODIFIED(pte))
1725 vm_page_dirty(m);
1726
1727 /* Flush mapping from TLB0. */
1728 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1729
1730 tlb_miss_unlock();
1731 mtx_unlock_spin(&tlbivax_mutex);
1732 }
1733 }
1734 PMAP_UNLOCK(pv->pv_pmap);
1735 }
1736 vm_page_aflag_clear(m, PGA_WRITEABLE);
1737 rw_wunlock(&pvh_global_lock);
1738 }
1739
1740 /*
1741 * Atomically extract and hold the physical page with the given
1742 * pmap and virtual address pair if that mapping permits the given
1743 * protection.
1744 */
1745 static vm_page_t
mmu_booke_extract_and_hold(pmap_t pmap,vm_offset_t va,vm_prot_t prot)1746 mmu_booke_extract_and_hold(pmap_t pmap, vm_offset_t va,
1747 vm_prot_t prot)
1748 {
1749 pte_t *pte;
1750 vm_page_t m;
1751 uint32_t pte_wbit;
1752
1753 m = NULL;
1754 PMAP_LOCK(pmap);
1755 pte = pte_find(pmap, va);
1756 if ((pte != NULL) && PTE_ISVALID(pte)) {
1757 if (pmap == kernel_pmap)
1758 pte_wbit = PTE_SW;
1759 else
1760 pte_wbit = PTE_UW;
1761
1762 if ((*pte & pte_wbit) != 0 || (prot & VM_PROT_WRITE) == 0) {
1763 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1764 if (!vm_page_wire_mapped(m))
1765 m = NULL;
1766 }
1767 }
1768 PMAP_UNLOCK(pmap);
1769 return (m);
1770 }
1771
1772 /*
1773 * Initialize a vm_page's machine-dependent fields.
1774 */
1775 static void
mmu_booke_page_init(vm_page_t m)1776 mmu_booke_page_init(vm_page_t m)
1777 {
1778
1779 m->md.pv_tracked = 0;
1780 TAILQ_INIT(&m->md.pv_list);
1781 }
1782
1783 /*
1784 * Return whether or not the specified physical page was modified
1785 * in any of physical maps.
1786 */
1787 static boolean_t
mmu_booke_is_modified(vm_page_t m)1788 mmu_booke_is_modified(vm_page_t m)
1789 {
1790 pte_t *pte;
1791 pv_entry_t pv;
1792 boolean_t rv;
1793
1794 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1795 ("mmu_booke_is_modified: page %p is not managed", m));
1796 rv = FALSE;
1797
1798 /*
1799 * If the page is not busied then this check is racy.
1800 */
1801 if (!pmap_page_is_write_mapped(m))
1802 return (FALSE);
1803
1804 rw_wlock(&pvh_global_lock);
1805 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1806 PMAP_LOCK(pv->pv_pmap);
1807 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1808 PTE_ISVALID(pte)) {
1809 if (PTE_ISMODIFIED(pte))
1810 rv = TRUE;
1811 }
1812 PMAP_UNLOCK(pv->pv_pmap);
1813 if (rv)
1814 break;
1815 }
1816 rw_wunlock(&pvh_global_lock);
1817 return (rv);
1818 }
1819
1820 /*
1821 * Return whether or not the specified virtual address is eligible
1822 * for prefault.
1823 */
1824 static boolean_t
mmu_booke_is_prefaultable(pmap_t pmap,vm_offset_t addr)1825 mmu_booke_is_prefaultable(pmap_t pmap, vm_offset_t addr)
1826 {
1827
1828 return (FALSE);
1829 }
1830
1831 /*
1832 * Return whether or not the specified physical page was referenced
1833 * in any physical maps.
1834 */
1835 static boolean_t
mmu_booke_is_referenced(vm_page_t m)1836 mmu_booke_is_referenced(vm_page_t m)
1837 {
1838 pte_t *pte;
1839 pv_entry_t pv;
1840 boolean_t rv;
1841
1842 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1843 ("mmu_booke_is_referenced: page %p is not managed", m));
1844 rv = FALSE;
1845 rw_wlock(&pvh_global_lock);
1846 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1847 PMAP_LOCK(pv->pv_pmap);
1848 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1849 PTE_ISVALID(pte)) {
1850 if (PTE_ISREFERENCED(pte))
1851 rv = TRUE;
1852 }
1853 PMAP_UNLOCK(pv->pv_pmap);
1854 if (rv)
1855 break;
1856 }
1857 rw_wunlock(&pvh_global_lock);
1858 return (rv);
1859 }
1860
1861 /*
1862 * Clear the modify bits on the specified physical page.
1863 */
1864 static void
mmu_booke_clear_modify(vm_page_t m)1865 mmu_booke_clear_modify(vm_page_t m)
1866 {
1867 pte_t *pte;
1868 pv_entry_t pv;
1869
1870 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1871 ("mmu_booke_clear_modify: page %p is not managed", m));
1872 vm_page_assert_busied(m);
1873
1874 if (!pmap_page_is_write_mapped(m))
1875 return;
1876
1877 rw_wlock(&pvh_global_lock);
1878 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1879 PMAP_LOCK(pv->pv_pmap);
1880 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1881 PTE_ISVALID(pte)) {
1882 mtx_lock_spin(&tlbivax_mutex);
1883 tlb_miss_lock();
1884
1885 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
1886 tlb0_flush_entry(pv->pv_va);
1887 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
1888 PTE_REFERENCED);
1889 }
1890
1891 tlb_miss_unlock();
1892 mtx_unlock_spin(&tlbivax_mutex);
1893 }
1894 PMAP_UNLOCK(pv->pv_pmap);
1895 }
1896 rw_wunlock(&pvh_global_lock);
1897 }
1898
1899 /*
1900 * Return a count of reference bits for a page, clearing those bits.
1901 * It is not necessary for every reference bit to be cleared, but it
1902 * is necessary that 0 only be returned when there are truly no
1903 * reference bits set.
1904 *
1905 * As an optimization, update the page's dirty field if a modified bit is
1906 * found while counting reference bits. This opportunistic update can be
1907 * performed at low cost and can eliminate the need for some future calls
1908 * to pmap_is_modified(). However, since this function stops after
1909 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
1910 * dirty pages. Those dirty pages will only be detected by a future call
1911 * to pmap_is_modified().
1912 */
1913 static int
mmu_booke_ts_referenced(vm_page_t m)1914 mmu_booke_ts_referenced(vm_page_t m)
1915 {
1916 pte_t *pte;
1917 pv_entry_t pv;
1918 int count;
1919
1920 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1921 ("mmu_booke_ts_referenced: page %p is not managed", m));
1922 count = 0;
1923 rw_wlock(&pvh_global_lock);
1924 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1925 PMAP_LOCK(pv->pv_pmap);
1926 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1927 PTE_ISVALID(pte)) {
1928 if (PTE_ISMODIFIED(pte))
1929 vm_page_dirty(m);
1930 if (PTE_ISREFERENCED(pte)) {
1931 mtx_lock_spin(&tlbivax_mutex);
1932 tlb_miss_lock();
1933
1934 tlb0_flush_entry(pv->pv_va);
1935 *pte &= ~PTE_REFERENCED;
1936
1937 tlb_miss_unlock();
1938 mtx_unlock_spin(&tlbivax_mutex);
1939
1940 if (++count >= PMAP_TS_REFERENCED_MAX) {
1941 PMAP_UNLOCK(pv->pv_pmap);
1942 break;
1943 }
1944 }
1945 }
1946 PMAP_UNLOCK(pv->pv_pmap);
1947 }
1948 rw_wunlock(&pvh_global_lock);
1949 return (count);
1950 }
1951
1952 /*
1953 * Clear the wired attribute from the mappings for the specified range of
1954 * addresses in the given pmap. Every valid mapping within that range must
1955 * have the wired attribute set. In contrast, invalid mappings cannot have
1956 * the wired attribute set, so they are ignored.
1957 *
1958 * The wired attribute of the page table entry is not a hardware feature, so
1959 * there is no need to invalidate any TLB entries.
1960 */
1961 static void
mmu_booke_unwire(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)1962 mmu_booke_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1963 {
1964 vm_offset_t va;
1965 pte_t *pte;
1966
1967 PMAP_LOCK(pmap);
1968 for (va = sva; va < eva; va += PAGE_SIZE) {
1969 if ((pte = pte_find(pmap, va)) != NULL &&
1970 PTE_ISVALID(pte)) {
1971 if (!PTE_ISWIRED(pte))
1972 panic("mmu_booke_unwire: pte %p isn't wired",
1973 pte);
1974 *pte &= ~PTE_WIRED;
1975 pmap->pm_stats.wired_count--;
1976 }
1977 }
1978 PMAP_UNLOCK(pmap);
1979
1980 }
1981
1982 /*
1983 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
1984 * page. This count may be changed upwards or downwards in the future; it is
1985 * only necessary that true be returned for a small subset of pmaps for proper
1986 * page aging.
1987 */
1988 static boolean_t
mmu_booke_page_exists_quick(pmap_t pmap,vm_page_t m)1989 mmu_booke_page_exists_quick(pmap_t pmap, vm_page_t m)
1990 {
1991 pv_entry_t pv;
1992 int loops;
1993 boolean_t rv;
1994
1995 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1996 ("mmu_booke_page_exists_quick: page %p is not managed", m));
1997 loops = 0;
1998 rv = FALSE;
1999 rw_wlock(&pvh_global_lock);
2000 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2001 if (pv->pv_pmap == pmap) {
2002 rv = TRUE;
2003 break;
2004 }
2005 if (++loops >= 16)
2006 break;
2007 }
2008 rw_wunlock(&pvh_global_lock);
2009 return (rv);
2010 }
2011
2012 /*
2013 * Return the number of managed mappings to the given physical page that are
2014 * wired.
2015 */
2016 static int
mmu_booke_page_wired_mappings(vm_page_t m)2017 mmu_booke_page_wired_mappings(vm_page_t m)
2018 {
2019 pv_entry_t pv;
2020 pte_t *pte;
2021 int count = 0;
2022
2023 if ((m->oflags & VPO_UNMANAGED) != 0)
2024 return (count);
2025 rw_wlock(&pvh_global_lock);
2026 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2027 PMAP_LOCK(pv->pv_pmap);
2028 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL)
2029 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2030 count++;
2031 PMAP_UNLOCK(pv->pv_pmap);
2032 }
2033 rw_wunlock(&pvh_global_lock);
2034 return (count);
2035 }
2036
2037 static int
mmu_booke_dev_direct_mapped(vm_paddr_t pa,vm_size_t size)2038 mmu_booke_dev_direct_mapped(vm_paddr_t pa, vm_size_t size)
2039 {
2040 int i;
2041 vm_offset_t va;
2042
2043 /*
2044 * This currently does not work for entries that
2045 * overlap TLB1 entries.
2046 */
2047 for (i = 0; i < TLB1_ENTRIES; i ++) {
2048 if (tlb1_iomapped(i, pa, size, &va) == 0)
2049 return (0);
2050 }
2051
2052 return (EFAULT);
2053 }
2054
2055 void
mmu_booke_dumpsys_map(vm_paddr_t pa,size_t sz,void ** va)2056 mmu_booke_dumpsys_map(vm_paddr_t pa, size_t sz, void **va)
2057 {
2058 vm_paddr_t ppa;
2059 vm_offset_t ofs;
2060 vm_size_t gran;
2061
2062 /* Minidumps are based on virtual memory addresses. */
2063 if (do_minidump) {
2064 *va = (void *)(vm_offset_t)pa;
2065 return;
2066 }
2067
2068 /* Raw physical memory dumps don't have a virtual address. */
2069 /* We always map a 256MB page at 256M. */
2070 gran = 256 * 1024 * 1024;
2071 ppa = rounddown2(pa, gran);
2072 ofs = pa - ppa;
2073 *va = (void *)gran;
2074 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
2075
2076 if (sz > (gran - ofs))
2077 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
2078 _TLB_ENTRY_IO);
2079 }
2080
2081 void
mmu_booke_dumpsys_unmap(vm_paddr_t pa,size_t sz,void * va)2082 mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t sz, void *va)
2083 {
2084 vm_paddr_t ppa;
2085 vm_offset_t ofs;
2086 vm_size_t gran;
2087 tlb_entry_t e;
2088 int i;
2089
2090 /* Minidumps are based on virtual memory addresses. */
2091 /* Nothing to do... */
2092 if (do_minidump)
2093 return;
2094
2095 for (i = 0; i < TLB1_ENTRIES; i++) {
2096 tlb1_read_entry(&e, i);
2097 if (!(e.mas1 & MAS1_VALID))
2098 break;
2099 }
2100
2101 /* Raw physical memory dumps don't have a virtual address. */
2102 i--;
2103 e.mas1 = 0;
2104 e.mas2 = 0;
2105 e.mas3 = 0;
2106 tlb1_write_entry(&e, i);
2107
2108 gran = 256 * 1024 * 1024;
2109 ppa = rounddown2(pa, gran);
2110 ofs = pa - ppa;
2111 if (sz > (gran - ofs)) {
2112 i--;
2113 e.mas1 = 0;
2114 e.mas2 = 0;
2115 e.mas3 = 0;
2116 tlb1_write_entry(&e, i);
2117 }
2118 }
2119
2120 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2121
2122 void
mmu_booke_scan_init(void)2123 mmu_booke_scan_init(void)
2124 {
2125 vm_offset_t va;
2126 pte_t *pte;
2127 int i;
2128
2129 if (!do_minidump) {
2130 /* Initialize phys. segments for dumpsys(). */
2131 memset(&dump_map, 0, sizeof(dump_map));
2132 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
2133 &availmem_regions_sz);
2134 for (i = 0; i < physmem_regions_sz; i++) {
2135 dump_map[i].pa_start = physmem_regions[i].mr_start;
2136 dump_map[i].pa_size = physmem_regions[i].mr_size;
2137 }
2138 return;
2139 }
2140
2141 /* Virtual segments for minidumps: */
2142 memset(&dump_map, 0, sizeof(dump_map));
2143
2144 /* 1st: kernel .data and .bss. */
2145 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2146 dump_map[0].pa_size =
2147 round_page((uintptr_t)_end) - dump_map[0].pa_start;
2148
2149 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2150 dump_map[1].pa_start = data_start;
2151 dump_map[1].pa_size = data_end - data_start;
2152
2153 /* 3rd: kernel VM. */
2154 va = dump_map[1].pa_start + dump_map[1].pa_size;
2155 /* Find start of next chunk (from va). */
2156 while (va < virtual_end) {
2157 /* Don't dump the buffer cache. */
2158 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2159 va = kmi.buffer_eva;
2160 continue;
2161 }
2162 pte = pte_find(kernel_pmap, va);
2163 if (pte != NULL && PTE_ISVALID(pte))
2164 break;
2165 va += PAGE_SIZE;
2166 }
2167 if (va < virtual_end) {
2168 dump_map[2].pa_start = va;
2169 va += PAGE_SIZE;
2170 /* Find last page in chunk. */
2171 while (va < virtual_end) {
2172 /* Don't run into the buffer cache. */
2173 if (va == kmi.buffer_sva)
2174 break;
2175 pte = pte_find(kernel_pmap, va);
2176 if (pte == NULL || !PTE_ISVALID(pte))
2177 break;
2178 va += PAGE_SIZE;
2179 }
2180 dump_map[2].pa_size = va - dump_map[2].pa_start;
2181 }
2182 }
2183
2184 /*
2185 * Map a set of physical memory pages into the kernel virtual address space.
2186 * Return a pointer to where it is mapped. This routine is intended to be used
2187 * for mapping device memory, NOT real memory.
2188 */
2189 static void *
mmu_booke_mapdev(vm_paddr_t pa,vm_size_t size)2190 mmu_booke_mapdev(vm_paddr_t pa, vm_size_t size)
2191 {
2192
2193 return (mmu_booke_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT));
2194 }
2195
2196 static int
tlb1_find_pa(vm_paddr_t pa,tlb_entry_t * e)2197 tlb1_find_pa(vm_paddr_t pa, tlb_entry_t *e)
2198 {
2199 int i;
2200
2201 for (i = 0; i < TLB1_ENTRIES; i++) {
2202 tlb1_read_entry(e, i);
2203 if ((e->mas1 & MAS1_VALID) == 0)
2204 continue;
2205 if (e->phys == pa)
2206 return (i);
2207 }
2208 return (-1);
2209 }
2210
2211 static void *
mmu_booke_mapdev_attr(vm_paddr_t pa,vm_size_t size,vm_memattr_t ma)2212 mmu_booke_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2213 {
2214 tlb_entry_t e;
2215 vm_paddr_t tmppa;
2216 #ifndef __powerpc64__
2217 uintptr_t tmpva;
2218 #endif
2219 uintptr_t va, retva;
2220 vm_size_t sz;
2221 int i;
2222 int wimge;
2223
2224 /*
2225 * Check if this is premapped in TLB1.
2226 */
2227 sz = size;
2228 tmppa = pa;
2229 va = ~0;
2230 wimge = tlb_calc_wimg(pa, ma);
2231 for (i = 0; i < TLB1_ENTRIES; i++) {
2232 tlb1_read_entry(&e, i);
2233 if (!(e.mas1 & MAS1_VALID))
2234 continue;
2235 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2236 continue;
2237 if (tmppa >= e.phys && tmppa < e.phys + e.size) {
2238 va = e.virt + (pa - e.phys);
2239 tmppa = e.phys + e.size;
2240 sz -= MIN(sz, e.size - (pa - e.phys));
2241 while (sz > 0 && (i = tlb1_find_pa(tmppa, &e)) != -1) {
2242 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2243 break;
2244 sz -= MIN(sz, e.size);
2245 tmppa = e.phys + e.size;
2246 }
2247 if (sz != 0)
2248 break;
2249 return ((void *)va);
2250 }
2251 }
2252
2253 size = roundup(size, PAGE_SIZE);
2254
2255 #ifdef __powerpc64__
2256 KASSERT(pa < VM_MAPDEV_PA_MAX,
2257 ("Unsupported physical address! %lx", pa));
2258 va = VM_MAPDEV_BASE + pa;
2259 retva = va;
2260 #ifdef POW2_MAPPINGS
2261 /*
2262 * Align the mapping to a power of 2 size, taking into account that we
2263 * may need to increase the size multiple times to satisfy the size and
2264 * alignment requirements.
2265 *
2266 * This works in the general case because it's very rare (near never?)
2267 * to have different access properties (WIMG) within a single
2268 * power-of-two region. If a design does call for that, POW2_MAPPINGS
2269 * can be undefined, and exact mappings will be used instead.
2270 */
2271 sz = size;
2272 size = roundup2(size, 1 << ilog2(size));
2273 while (rounddown2(va, size) + size < va + sz)
2274 size <<= 1;
2275 va = rounddown2(va, size);
2276 pa = rounddown2(pa, size);
2277 #endif
2278 #else
2279 /*
2280 * The device mapping area is between VM_MAXUSER_ADDRESS and
2281 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing.
2282 */
2283 #ifdef SPARSE_MAPDEV
2284 /*
2285 * With a sparse mapdev, align to the largest starting region. This
2286 * could feasibly be optimized for a 'best-fit' alignment, but that
2287 * calculation could be very costly.
2288 * Align to the smaller of:
2289 * - first set bit in overlap of (pa & size mask)
2290 * - largest size envelope
2291 *
2292 * It's possible the device mapping may start at a PA that's not larger
2293 * than the size mask, so we need to offset in to maximize the TLB entry
2294 * range and minimize the number of used TLB entries.
2295 */
2296 do {
2297 tmpva = tlb1_map_base;
2298 sz = ffsl((~((1 << flsl(size-1)) - 1)) & pa);
2299 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1;
2300 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa);
2301 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
2302 #endif
2303 va = atomic_fetchadd_int(&tlb1_map_base, size);
2304 retva = va;
2305 #endif
2306
2307 if (tlb1_mapin_region(va, pa, size, tlb_calc_wimg(pa, ma)) != size)
2308 return (NULL);
2309
2310 return ((void *)retva);
2311 }
2312
2313 /*
2314 * 'Unmap' a range mapped by mmu_booke_mapdev().
2315 */
2316 static void
mmu_booke_unmapdev(void * p,vm_size_t size)2317 mmu_booke_unmapdev(void *p, vm_size_t size)
2318 {
2319 #ifdef SUPPORTS_SHRINKING_TLB1
2320 vm_offset_t base, offset, va;
2321
2322 /*
2323 * Unmap only if this is inside kernel virtual space.
2324 */
2325 va = (vm_offset_t)p;
2326 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2327 base = trunc_page(va);
2328 offset = va & PAGE_MASK;
2329 size = roundup(offset + size, PAGE_SIZE);
2330 mmu_booke_qremove(base, atop(size));
2331 kva_free(base, size);
2332 }
2333 #endif
2334 }
2335
2336 /*
2337 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2338 * specified pmap. This eliminates the blast of soft faults on process startup
2339 * and immediately after an mmap.
2340 */
2341 static void
mmu_booke_object_init_pt(pmap_t pmap,vm_offset_t addr,vm_object_t object,vm_pindex_t pindex,vm_size_t size)2342 mmu_booke_object_init_pt(pmap_t pmap, vm_offset_t addr,
2343 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2344 {
2345
2346 VM_OBJECT_ASSERT_WLOCKED(object);
2347 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2348 ("mmu_booke_object_init_pt: non-device object"));
2349 }
2350
2351 /*
2352 * Perform the pmap work for mincore.
2353 */
2354 static int
mmu_booke_mincore(pmap_t pmap,vm_offset_t addr,vm_paddr_t * pap)2355 mmu_booke_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
2356 {
2357
2358 /* XXX: this should be implemented at some point */
2359 return (0);
2360 }
2361
2362 static int
mmu_booke_change_attr(vm_offset_t addr,vm_size_t sz,vm_memattr_t mode)2363 mmu_booke_change_attr(vm_offset_t addr, vm_size_t sz, vm_memattr_t mode)
2364 {
2365 vm_offset_t va;
2366 pte_t *pte;
2367 int i, j;
2368 tlb_entry_t e;
2369
2370 addr = trunc_page(addr);
2371
2372 /* Only allow changes to mapped kernel addresses. This includes:
2373 * - KVA
2374 * - DMAP (powerpc64)
2375 * - Device mappings
2376 */
2377 if (addr <= VM_MAXUSER_ADDRESS ||
2378 #ifdef __powerpc64__
2379 (addr >= tlb1_map_base && addr < DMAP_BASE_ADDRESS) ||
2380 (addr > DMAP_MAX_ADDRESS && addr < VM_MIN_KERNEL_ADDRESS) ||
2381 #else
2382 (addr >= tlb1_map_base && addr < VM_MIN_KERNEL_ADDRESS) ||
2383 #endif
2384 (addr > VM_MAX_KERNEL_ADDRESS))
2385 return (EINVAL);
2386
2387 /* Check TLB1 mappings */
2388 for (i = 0; i < TLB1_ENTRIES; i++) {
2389 tlb1_read_entry(&e, i);
2390 if (!(e.mas1 & MAS1_VALID))
2391 continue;
2392 if (addr >= e.virt && addr < e.virt + e.size)
2393 break;
2394 }
2395 if (i < TLB1_ENTRIES) {
2396 /* Only allow full mappings to be modified for now. */
2397 /* Validate the range. */
2398 for (j = i, va = addr; va < addr + sz; va += e.size, j++) {
2399 tlb1_read_entry(&e, j);
2400 if (va != e.virt || (sz - (va - addr) < e.size))
2401 return (EINVAL);
2402 }
2403 for (va = addr; va < addr + sz; va += e.size, i++) {
2404 tlb1_read_entry(&e, i);
2405 e.mas2 &= ~MAS2_WIMGE_MASK;
2406 e.mas2 |= tlb_calc_wimg(e.phys, mode);
2407
2408 /*
2409 * Write it out to the TLB. Should really re-sync with other
2410 * cores.
2411 */
2412 tlb1_write_entry(&e, i);
2413 }
2414 return (0);
2415 }
2416
2417 /* Not in TLB1, try through pmap */
2418 /* First validate the range. */
2419 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2420 pte = pte_find(kernel_pmap, va);
2421 if (pte == NULL || !PTE_ISVALID(pte))
2422 return (EINVAL);
2423 }
2424
2425 mtx_lock_spin(&tlbivax_mutex);
2426 tlb_miss_lock();
2427 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2428 pte = pte_find(kernel_pmap, va);
2429 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
2430 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT;
2431 tlb0_flush_entry(va);
2432 }
2433 tlb_miss_unlock();
2434 mtx_unlock_spin(&tlbivax_mutex);
2435
2436 return (0);
2437 }
2438
2439 static void
mmu_booke_page_array_startup(long pages)2440 mmu_booke_page_array_startup(long pages)
2441 {
2442 vm_page_array_size = pages;
2443 }
2444
2445 /**************************************************************************/
2446 /* TID handling */
2447 /**************************************************************************/
2448
2449 /*
2450 * Allocate a TID. If necessary, steal one from someone else.
2451 * The new TID is flushed from the TLB before returning.
2452 */
2453 static tlbtid_t
tid_alloc(pmap_t pmap)2454 tid_alloc(pmap_t pmap)
2455 {
2456 tlbtid_t tid;
2457 int thiscpu;
2458
2459 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2460
2461 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2462
2463 thiscpu = PCPU_GET(cpuid);
2464
2465 tid = PCPU_GET(booke.tid_next);
2466 if (tid > TID_MAX)
2467 tid = TID_MIN;
2468 PCPU_SET(booke.tid_next, tid + 1);
2469
2470 /* If we are stealing TID then clear the relevant pmap's field */
2471 if (tidbusy[thiscpu][tid] != NULL) {
2472 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2473
2474 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2475
2476 /* Flush all entries from TLB0 matching this TID. */
2477 tid_flush(tid);
2478 }
2479
2480 tidbusy[thiscpu][tid] = pmap;
2481 pmap->pm_tid[thiscpu] = tid;
2482 __asm __volatile("msync; isync");
2483
2484 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2485 PCPU_GET(booke.tid_next));
2486
2487 return (tid);
2488 }
2489
2490 /**************************************************************************/
2491 /* TLB0 handling */
2492 /**************************************************************************/
2493
2494 /* Convert TLB0 va and way number to tlb0[] table index. */
2495 static inline unsigned int
tlb0_tableidx(vm_offset_t va,unsigned int way)2496 tlb0_tableidx(vm_offset_t va, unsigned int way)
2497 {
2498 unsigned int idx;
2499
2500 idx = (way * TLB0_ENTRIES_PER_WAY);
2501 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2502 return (idx);
2503 }
2504
2505 /*
2506 * Invalidate TLB0 entry.
2507 */
2508 static inline void
tlb0_flush_entry(vm_offset_t va)2509 tlb0_flush_entry(vm_offset_t va)
2510 {
2511
2512 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2513
2514 mtx_assert(&tlbivax_mutex, MA_OWNED);
2515
2516 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2517 __asm __volatile("isync; msync");
2518 __asm __volatile("tlbsync; msync");
2519
2520 CTR1(KTR_PMAP, "%s: e", __func__);
2521 }
2522
2523 /**************************************************************************/
2524 /* TLB1 handling */
2525 /**************************************************************************/
2526
2527 /*
2528 * TLB1 mapping notes:
2529 *
2530 * TLB1[0] Kernel text and data.
2531 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
2532 * windows, other devices mappings.
2533 */
2534
2535 /*
2536 * Read an entry from given TLB1 slot.
2537 */
2538 void
tlb1_read_entry(tlb_entry_t * entry,unsigned int slot)2539 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
2540 {
2541 register_t msr;
2542 uint32_t mas0;
2543
2544 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__));
2545
2546 msr = mfmsr();
2547 __asm __volatile("wrteei 0");
2548
2549 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot);
2550 mtspr(SPR_MAS0, mas0);
2551 __asm __volatile("isync; tlbre");
2552
2553 entry->mas1 = mfspr(SPR_MAS1);
2554 entry->mas2 = mfspr(SPR_MAS2);
2555 entry->mas3 = mfspr(SPR_MAS3);
2556
2557 switch ((mfpvr() >> 16) & 0xFFFF) {
2558 case FSL_E500v2:
2559 case FSL_E500mc:
2560 case FSL_E5500:
2561 case FSL_E6500:
2562 entry->mas7 = mfspr(SPR_MAS7);
2563 break;
2564 default:
2565 entry->mas7 = 0;
2566 break;
2567 }
2568 __asm __volatile("wrtee %0" :: "r"(msr));
2569
2570 entry->virt = entry->mas2 & MAS2_EPN_MASK;
2571 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) |
2572 (entry->mas3 & MAS3_RPN);
2573 entry->size =
2574 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT);
2575 }
2576
2577 struct tlbwrite_args {
2578 tlb_entry_t *e;
2579 unsigned int idx;
2580 };
2581
2582 static uint32_t
tlb1_find_free(void)2583 tlb1_find_free(void)
2584 {
2585 tlb_entry_t e;
2586 int i;
2587
2588 for (i = 0; i < TLB1_ENTRIES; i++) {
2589 tlb1_read_entry(&e, i);
2590 if ((e.mas1 & MAS1_VALID) == 0)
2591 return (i);
2592 }
2593 return (-1);
2594 }
2595
2596 static void
tlb1_purge_va_range(vm_offset_t va,vm_size_t size)2597 tlb1_purge_va_range(vm_offset_t va, vm_size_t size)
2598 {
2599 tlb_entry_t e;
2600 int i;
2601
2602 for (i = 0; i < TLB1_ENTRIES; i++) {
2603 tlb1_read_entry(&e, i);
2604 if ((e.mas1 & MAS1_VALID) == 0)
2605 continue;
2606 if ((e.mas2 & MAS2_EPN_MASK) >= va &&
2607 (e.mas2 & MAS2_EPN_MASK) < va + size) {
2608 mtspr(SPR_MAS1, e.mas1 & ~MAS1_VALID);
2609 __asm __volatile("isync; tlbwe; isync; msync");
2610 }
2611 }
2612 }
2613
2614 static void
tlb1_write_entry_int(void * arg)2615 tlb1_write_entry_int(void *arg)
2616 {
2617 struct tlbwrite_args *args = arg;
2618 uint32_t idx, mas0;
2619
2620 idx = args->idx;
2621 if (idx == -1) {
2622 tlb1_purge_va_range(args->e->virt, args->e->size);
2623 idx = tlb1_find_free();
2624 if (idx == -1)
2625 panic("No free TLB1 entries!\n");
2626 }
2627 /* Select entry */
2628 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2629
2630 mtspr(SPR_MAS0, mas0);
2631 mtspr(SPR_MAS1, args->e->mas1);
2632 mtspr(SPR_MAS2, args->e->mas2);
2633 mtspr(SPR_MAS3, args->e->mas3);
2634 switch ((mfpvr() >> 16) & 0xFFFF) {
2635 case FSL_E500mc:
2636 case FSL_E5500:
2637 case FSL_E6500:
2638 mtspr(SPR_MAS8, 0);
2639 /* FALLTHROUGH */
2640 case FSL_E500v2:
2641 mtspr(SPR_MAS7, args->e->mas7);
2642 break;
2643 default:
2644 break;
2645 }
2646
2647 __asm __volatile("isync; tlbwe; isync; msync");
2648
2649 }
2650
2651 static void
tlb1_write_entry_sync(void * arg)2652 tlb1_write_entry_sync(void *arg)
2653 {
2654 /* Empty synchronization point for smp_rendezvous(). */
2655 }
2656
2657 /*
2658 * Write given entry to TLB1 hardware.
2659 */
2660 static void
tlb1_write_entry(tlb_entry_t * e,unsigned int idx)2661 tlb1_write_entry(tlb_entry_t *e, unsigned int idx)
2662 {
2663 struct tlbwrite_args args;
2664
2665 args.e = e;
2666 args.idx = idx;
2667
2668 #ifdef SMP
2669 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) {
2670 mb();
2671 smp_rendezvous(tlb1_write_entry_sync,
2672 tlb1_write_entry_int,
2673 tlb1_write_entry_sync, &args);
2674 } else
2675 #endif
2676 {
2677 register_t msr;
2678
2679 msr = mfmsr();
2680 __asm __volatile("wrteei 0");
2681 tlb1_write_entry_int(&args);
2682 __asm __volatile("wrtee %0" :: "r"(msr));
2683 }
2684 }
2685
2686 /*
2687 * Convert TLB TSIZE value to mapped region size.
2688 */
2689 static vm_size_t
tsize2size(unsigned int tsize)2690 tsize2size(unsigned int tsize)
2691 {
2692
2693 /*
2694 * size = 4^tsize KB
2695 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2696 */
2697
2698 return ((1 << (2 * tsize)) * 1024);
2699 }
2700
2701 /*
2702 * Convert region size (must be power of 4) to TLB TSIZE value.
2703 */
2704 static unsigned int
size2tsize(vm_size_t size)2705 size2tsize(vm_size_t size)
2706 {
2707
2708 return (ilog2(size) / 2 - 5);
2709 }
2710
2711 /*
2712 * Register permanent kernel mapping in TLB1.
2713 *
2714 * Entries are created starting from index 0 (current free entry is
2715 * kept in tlb1_idx) and are not supposed to be invalidated.
2716 */
2717 int
tlb1_set_entry(vm_offset_t va,vm_paddr_t pa,vm_size_t size,uint32_t flags)2718 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
2719 uint32_t flags)
2720 {
2721 tlb_entry_t e;
2722 uint32_t ts, tid;
2723 int tsize, index;
2724
2725 /* First try to update an existing entry. */
2726 for (index = 0; index < TLB1_ENTRIES; index++) {
2727 tlb1_read_entry(&e, index);
2728 /* Check if we're just updating the flags, and update them. */
2729 if (e.phys == pa && e.virt == va && e.size == size) {
2730 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2731 tlb1_write_entry(&e, index);
2732 return (0);
2733 }
2734 }
2735
2736 /* Convert size to TSIZE */
2737 tsize = size2tsize(size);
2738
2739 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2740 /* XXX TS is hard coded to 0 for now as we only use single address space */
2741 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2742
2743 e.phys = pa;
2744 e.virt = va;
2745 e.size = size;
2746 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2747 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2748 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2749
2750 /* Set supervisor RWX permission bits */
2751 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2752 e.mas7 = (pa >> 32) & MAS7_RPN;
2753
2754 tlb1_write_entry(&e, -1);
2755
2756 return (0);
2757 }
2758
2759 /*
2760 * Map in contiguous RAM region into the TLB1.
2761 */
2762 static vm_size_t
tlb1_mapin_region(vm_offset_t va,vm_paddr_t pa,vm_size_t size,int wimge)2763 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size, int wimge)
2764 {
2765 vm_offset_t base;
2766 vm_size_t mapped, sz, ssize;
2767
2768 mapped = 0;
2769 base = va;
2770 ssize = size;
2771
2772 while (size > 0) {
2773 sz = 1UL << (ilog2(size) & ~1);
2774 /* Align size to PA */
2775 if (pa % sz != 0) {
2776 do {
2777 sz >>= 2;
2778 } while (pa % sz != 0);
2779 }
2780 /* Now align from there to VA */
2781 if (va % sz != 0) {
2782 do {
2783 sz >>= 2;
2784 } while (va % sz != 0);
2785 }
2786 #ifdef __powerpc64__
2787 /*
2788 * Clamp TLB1 entries to 4G.
2789 *
2790 * While the e6500 supports up to 1TB mappings, the e5500
2791 * only supports up to 4G mappings. (0b1011)
2792 *
2793 * If any e6500 machines capable of supporting a very
2794 * large amount of memory appear in the future, we can
2795 * revisit this.
2796 *
2797 * For now, though, since we have plenty of space in TLB1,
2798 * always avoid creating entries larger than 4GB.
2799 */
2800 sz = MIN(sz, 1UL << 32);
2801 #endif
2802 if (bootverbose)
2803 printf("Wiring VA=%p to PA=%jx (size=%lx)\n",
2804 (void *)va, (uintmax_t)pa, (long)sz);
2805 if (tlb1_set_entry(va, pa, sz,
2806 _TLB_ENTRY_SHARED | wimge) < 0)
2807 return (mapped);
2808 size -= sz;
2809 pa += sz;
2810 va += sz;
2811 }
2812
2813 mapped = (va - base);
2814 if (bootverbose)
2815 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n",
2816 mapped, mapped - ssize);
2817
2818 return (mapped);
2819 }
2820
2821 /*
2822 * TLB1 initialization routine, to be called after the very first
2823 * assembler level setup done in locore.S.
2824 */
2825 void
tlb1_init(void)2826 tlb1_init(void)
2827 {
2828 vm_offset_t mas2;
2829 uint32_t mas0, mas1, mas3, mas7;
2830 uint32_t tsz;
2831
2832 tlb1_get_tlbconf();
2833
2834 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
2835 mtspr(SPR_MAS0, mas0);
2836 __asm __volatile("isync; tlbre");
2837
2838 mas1 = mfspr(SPR_MAS1);
2839 mas2 = mfspr(SPR_MAS2);
2840 mas3 = mfspr(SPR_MAS3);
2841 mas7 = mfspr(SPR_MAS7);
2842
2843 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
2844 (mas3 & MAS3_RPN);
2845
2846 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2847 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
2848 kernstart = trunc_page(mas2);
2849
2850 /* Setup TLB miss defaults */
2851 set_mas4_defaults();
2852 }
2853
2854 /*
2855 * pmap_early_io_unmap() should be used in short conjunction with
2856 * pmap_early_io_map(), as in the following snippet:
2857 *
2858 * x = pmap_early_io_map(...);
2859 * <do something with x>
2860 * pmap_early_io_unmap(x, size);
2861 *
2862 * And avoiding more allocations between.
2863 */
2864 void
pmap_early_io_unmap(vm_offset_t va,vm_size_t size)2865 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
2866 {
2867 int i;
2868 tlb_entry_t e;
2869 vm_size_t isize;
2870
2871 size = roundup(size, PAGE_SIZE);
2872 isize = size;
2873 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) {
2874 tlb1_read_entry(&e, i);
2875 if (!(e.mas1 & MAS1_VALID))
2876 continue;
2877 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) {
2878 size -= e.size;
2879 e.mas1 &= ~MAS1_VALID;
2880 tlb1_write_entry(&e, i);
2881 }
2882 }
2883 if (tlb1_map_base == va + isize)
2884 tlb1_map_base -= isize;
2885 }
2886
2887 vm_offset_t
pmap_early_io_map(vm_paddr_t pa,vm_size_t size)2888 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
2889 {
2890 vm_paddr_t pa_base;
2891 vm_offset_t va, sz;
2892 int i;
2893 tlb_entry_t e;
2894
2895 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
2896
2897 for (i = 0; i < TLB1_ENTRIES; i++) {
2898 tlb1_read_entry(&e, i);
2899 if (!(e.mas1 & MAS1_VALID))
2900 continue;
2901 if (pa >= e.phys && (pa + size) <=
2902 (e.phys + e.size))
2903 return (e.virt + (pa - e.phys));
2904 }
2905
2906 pa_base = rounddown(pa, PAGE_SIZE);
2907 size = roundup(size + (pa - pa_base), PAGE_SIZE);
2908 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
2909 va = tlb1_map_base + (pa - pa_base);
2910
2911 do {
2912 sz = 1 << (ilog2(size) & ~1);
2913 tlb1_set_entry(tlb1_map_base, pa_base, sz,
2914 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO);
2915 size -= sz;
2916 pa_base += sz;
2917 tlb1_map_base += sz;
2918 } while (size > 0);
2919
2920 return (va);
2921 }
2922
2923 void
pmap_track_page(pmap_t pmap,vm_offset_t va)2924 pmap_track_page(pmap_t pmap, vm_offset_t va)
2925 {
2926 vm_paddr_t pa;
2927 vm_page_t page;
2928 struct pv_entry *pve;
2929
2930 va = trunc_page(va);
2931 pa = pmap_kextract(va);
2932 page = PHYS_TO_VM_PAGE(pa);
2933
2934 rw_wlock(&pvh_global_lock);
2935 PMAP_LOCK(pmap);
2936
2937 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) {
2938 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
2939 goto out;
2940 }
2941 }
2942 page->md.pv_tracked = true;
2943 pv_insert(pmap, va, page);
2944 out:
2945 PMAP_UNLOCK(pmap);
2946 rw_wunlock(&pvh_global_lock);
2947 }
2948
2949 /*
2950 * Setup MAS4 defaults.
2951 * These values are loaded to MAS0-2 on a TLB miss.
2952 */
2953 static void
set_mas4_defaults(void)2954 set_mas4_defaults(void)
2955 {
2956 uint32_t mas4;
2957
2958 /* Defaults: TLB0, PID0, TSIZED=4K */
2959 mas4 = MAS4_TLBSELD0;
2960 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
2961 #ifdef SMP
2962 mas4 |= MAS4_MD;
2963 #endif
2964 mtspr(SPR_MAS4, mas4);
2965 __asm __volatile("isync");
2966 }
2967
2968 /*
2969 * Return 0 if the physical IO range is encompassed by one of the
2970 * the TLB1 entries, otherwise return related error code.
2971 */
2972 static int
tlb1_iomapped(int i,vm_paddr_t pa,vm_size_t size,vm_offset_t * va)2973 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
2974 {
2975 uint32_t prot;
2976 vm_paddr_t pa_start;
2977 vm_paddr_t pa_end;
2978 unsigned int entry_tsize;
2979 vm_size_t entry_size;
2980 tlb_entry_t e;
2981
2982 *va = (vm_offset_t)NULL;
2983
2984 tlb1_read_entry(&e, i);
2985 /* Skip invalid entries */
2986 if (!(e.mas1 & MAS1_VALID))
2987 return (EINVAL);
2988
2989 /*
2990 * The entry must be cache-inhibited, guarded, and r/w
2991 * so it can function as an i/o page
2992 */
2993 prot = e.mas2 & (MAS2_I | MAS2_G);
2994 if (prot != (MAS2_I | MAS2_G))
2995 return (EPERM);
2996
2997 prot = e.mas3 & (MAS3_SR | MAS3_SW);
2998 if (prot != (MAS3_SR | MAS3_SW))
2999 return (EPERM);
3000
3001 /* The address should be within the entry range. */
3002 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3003 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3004
3005 entry_size = tsize2size(entry_tsize);
3006 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) |
3007 (e.mas3 & MAS3_RPN);
3008 pa_end = pa_start + entry_size;
3009
3010 if ((pa < pa_start) || ((pa + size) > pa_end))
3011 return (ERANGE);
3012
3013 /* Return virtual address of this mapping. */
3014 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start);
3015 return (0);
3016 }
3017
3018 #ifdef DDB
3019 /* Print out contents of the MAS registers for each TLB0 entry */
3020 static void
3021 #ifdef __powerpc64__
tlb_print_entry(int i,uint32_t mas1,uint64_t mas2,uint32_t mas3,uint32_t mas7)3022 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3,
3023 #else
3024 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
3025 #endif
3026 uint32_t mas7)
3027 {
3028 int as;
3029 char desc[3];
3030 tlbtid_t tid;
3031 vm_size_t size;
3032 unsigned int tsize;
3033
3034 desc[2] = '\0';
3035 if (mas1 & MAS1_VALID)
3036 desc[0] = 'V';
3037 else
3038 desc[0] = ' ';
3039
3040 if (mas1 & MAS1_IPROT)
3041 desc[1] = 'P';
3042 else
3043 desc[1] = ' ';
3044
3045 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
3046 tid = MAS1_GETTID(mas1);
3047
3048 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3049 size = 0;
3050 if (tsize)
3051 size = tsize2size(tsize);
3052
3053 printf("%3d: (%s) [AS=%d] "
3054 "sz = 0x%jx tsz = %d tid = %d mas1 = 0x%08x "
3055 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n",
3056 i, desc, as, (uintmax_t)size, tsize, tid, mas1, mas2, mas3, mas7);
3057 }
3058
DB_SHOW_COMMAND(tlb0,tlb0_print_tlbentries)3059 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
3060 {
3061 uint32_t mas0, mas1, mas3, mas7;
3062 #ifdef __powerpc64__
3063 uint64_t mas2;
3064 #else
3065 uint32_t mas2;
3066 #endif
3067 int entryidx, way, idx;
3068
3069 printf("TLB0 entries:\n");
3070 for (way = 0; way < TLB0_WAYS; way ++)
3071 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
3072 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
3073 mtspr(SPR_MAS0, mas0);
3074
3075 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
3076 mtspr(SPR_MAS2, mas2);
3077
3078 __asm __volatile("isync; tlbre");
3079
3080 mas1 = mfspr(SPR_MAS1);
3081 mas2 = mfspr(SPR_MAS2);
3082 mas3 = mfspr(SPR_MAS3);
3083 mas7 = mfspr(SPR_MAS7);
3084
3085 idx = tlb0_tableidx(mas2, way);
3086 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
3087 }
3088 }
3089
3090 /*
3091 * Print out contents of the MAS registers for each TLB1 entry
3092 */
DB_SHOW_COMMAND(tlb1,tlb1_print_tlbentries)3093 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
3094 {
3095 uint32_t mas0, mas1, mas3, mas7;
3096 #ifdef __powerpc64__
3097 uint64_t mas2;
3098 #else
3099 uint32_t mas2;
3100 #endif
3101 int i;
3102
3103 printf("TLB1 entries:\n");
3104 for (i = 0; i < TLB1_ENTRIES; i++) {
3105 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3106 mtspr(SPR_MAS0, mas0);
3107
3108 __asm __volatile("isync; tlbre");
3109
3110 mas1 = mfspr(SPR_MAS1);
3111 mas2 = mfspr(SPR_MAS2);
3112 mas3 = mfspr(SPR_MAS3);
3113 mas7 = mfspr(SPR_MAS7);
3114
3115 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3116 }
3117 }
3118 #endif
3119