1 /*-
2 * Copyright (c) 2016 Hiroki Mori. All rights reserved.
3 * Copyright (C) 2007
4 * Oleksandr Tymoshenko <[email protected]>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
25 * THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * $Id: $
28 *
29 */
30
31 #include "opt_platform.h"
32 #include "opt_ar531x.h"
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 /*
38 * AR531x Ethernet interface driver
39 * copy from mips/idt/if_kr.c and netbsd code
40 */
41 #include <sys/param.h>
42 #include <sys/endian.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
45 #include <sys/mbuf.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/lock.h>
49 #include <sys/module.h>
50 #include <sys/mutex.h>
51 #include <sys/socket.h>
52 #include <sys/taskqueue.h>
53 #include <sys/kdb.h>
54
55 #include <net/if.h>
56 #include <net/if_arp.h>
57 #include <net/ethernet.h>
58 #include <net/if_dl.h>
59 #include <net/if_media.h>
60 #include <net/if_types.h>
61 #include <net/if_var.h>
62
63 #include <net/bpf.h>
64
65 #include <machine/bus.h>
66 #include <machine/resource.h>
67 #include <sys/bus.h>
68 #include <sys/rman.h>
69
70 #ifdef INTRNG
71 #include <machine/intr.h>
72 #endif
73
74 #include <dev/mii/mii.h>
75 #include <dev/mii/miivar.h>
76
77 #ifdef ARE_MDIO
78 #include <dev/mdio/mdio.h>
79 #include <dev/etherswitch/miiproxy.h>
80 #include "mdio_if.h"
81 #endif
82
83 MODULE_DEPEND(are, ether, 1, 1, 1);
84 MODULE_DEPEND(are, miibus, 1, 1, 1);
85
86 #include "miibus_if.h"
87
88 #include <mips/atheros/ar531x/ar5315reg.h>
89 #include <mips/atheros/ar531x/ar5312reg.h>
90 #include <mips/atheros/ar531x/ar5315_setup.h>
91 #include <mips/atheros/ar531x/if_arereg.h>
92
93 #ifdef ARE_DEBUG
94 void dump_txdesc(struct are_softc *, int);
95 void dump_status_reg(struct are_softc *);
96 #endif
97
98 static int are_attach(device_t);
99 static int are_detach(device_t);
100 static int are_ifmedia_upd(struct ifnet *);
101 static void are_ifmedia_sts(struct ifnet *, struct ifmediareq *);
102 static int are_ioctl(struct ifnet *, u_long, caddr_t);
103 static void are_init(void *);
104 static void are_init_locked(struct are_softc *);
105 static void are_link_task(void *, int);
106 static int are_miibus_readreg(device_t, int, int);
107 static void are_miibus_statchg(device_t);
108 static int are_miibus_writereg(device_t, int, int, int);
109 static int are_probe(device_t);
110 static void are_reset(struct are_softc *);
111 static int are_resume(device_t);
112 static int are_rx_ring_init(struct are_softc *);
113 static int are_tx_ring_init(struct are_softc *);
114 static int are_shutdown(device_t);
115 static void are_start(struct ifnet *);
116 static void are_start_locked(struct ifnet *);
117 static void are_stop(struct are_softc *);
118 static int are_suspend(device_t);
119
120 static void are_rx(struct are_softc *);
121 static void are_tx(struct are_softc *);
122 static void are_intr(void *);
123 static void are_tick(void *);
124
125 static void are_dmamap_cb(void *, bus_dma_segment_t *, int, int);
126 static int are_dma_alloc(struct are_softc *);
127 static void are_dma_free(struct are_softc *);
128 static int are_newbuf(struct are_softc *, int);
129 static __inline void are_fixup_rx(struct mbuf *);
130
131 static void are_hinted_child(device_t bus, const char *dname, int dunit);
132
133 static device_method_t are_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, are_probe),
136 DEVMETHOD(device_attach, are_attach),
137 DEVMETHOD(device_detach, are_detach),
138 DEVMETHOD(device_suspend, are_suspend),
139 DEVMETHOD(device_resume, are_resume),
140 DEVMETHOD(device_shutdown, are_shutdown),
141
142 /* MII interface */
143 DEVMETHOD(miibus_readreg, are_miibus_readreg),
144 DEVMETHOD(miibus_writereg, are_miibus_writereg),
145 DEVMETHOD(miibus_statchg, are_miibus_statchg),
146
147 /* bus interface */
148 DEVMETHOD(bus_add_child, device_add_child_ordered),
149 DEVMETHOD(bus_hinted_child, are_hinted_child),
150
151 DEVMETHOD_END
152 };
153
154 static driver_t are_driver = {
155 "are",
156 are_methods,
157 sizeof(struct are_softc)
158 };
159
160 static devclass_t are_devclass;
161
162 DRIVER_MODULE(are, nexus, are_driver, are_devclass, 0, 0);
163 #ifdef ARE_MII
164 DRIVER_MODULE(miibus, are, miibus_driver, miibus_devclass, 0, 0);
165 #endif
166
167 #ifdef ARE_MDIO
168 static int aremdio_probe(device_t);
169 static int aremdio_attach(device_t);
170 static int aremdio_detach(device_t);
171
172 /*
173 * Declare an additional, separate driver for accessing the MDIO bus.
174 */
175 static device_method_t aremdio_methods[] = {
176 /* Device interface */
177 DEVMETHOD(device_probe, aremdio_probe),
178 DEVMETHOD(device_attach, aremdio_attach),
179 DEVMETHOD(device_detach, aremdio_detach),
180
181 /* bus interface */
182 DEVMETHOD(bus_add_child, device_add_child_ordered),
183
184 /* MDIO access */
185 DEVMETHOD(mdio_readreg, are_miibus_readreg),
186 DEVMETHOD(mdio_writereg, are_miibus_writereg),
187 };
188
189 DEFINE_CLASS_0(aremdio, aremdio_driver, aremdio_methods,
190 sizeof(struct are_softc));
191 static devclass_t aremdio_devclass;
192
193 DRIVER_MODULE(miiproxy, are, miiproxy_driver, miiproxy_devclass, 0, 0);
194 DRIVER_MODULE(aremdio, nexus, aremdio_driver, aremdio_devclass, 0, 0);
195 DRIVER_MODULE(mdio, aremdio, mdio_driver, mdio_devclass, 0, 0);
196 #endif
197
198 static int
are_probe(device_t dev)199 are_probe(device_t dev)
200 {
201
202 device_set_desc(dev, "AR531x Ethernet interface");
203 return (0);
204 }
205
206 static int
are_attach(device_t dev)207 are_attach(device_t dev)
208 {
209 struct ifnet *ifp;
210 struct are_softc *sc;
211 int error = 0;
212 #ifdef INTRNG
213 int enetirq;
214 #else
215 int rid;
216 #endif
217 int unit;
218 char * local_macstr;
219 int count;
220 int i;
221
222 sc = device_get_softc(dev);
223 unit = device_get_unit(dev);
224 sc->are_dev = dev;
225
226 /* hardcode macaddress */
227 sc->are_eaddr[0] = 0x00;
228 sc->are_eaddr[1] = 0x0C;
229 sc->are_eaddr[2] = 0x42;
230 sc->are_eaddr[3] = 0x09;
231 sc->are_eaddr[4] = 0x5E;
232 sc->are_eaddr[5] = 0x6B;
233
234 /* try to get from hints */
235 if (!resource_string_value(device_get_name(dev),
236 device_get_unit(dev), "macaddr", (const char **)&local_macstr)) {
237 uint32_t tmpmac[ETHER_ADDR_LEN];
238
239 /* Have a MAC address; should use it */
240 device_printf(dev, "Overriding MAC address from environment: '%s'\n",
241 local_macstr);
242
243 /* Extract out the MAC address */
244 /* XXX this should all be a generic method */
245 count = sscanf(local_macstr, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
246 &tmpmac[0], &tmpmac[1],
247 &tmpmac[2], &tmpmac[3],
248 &tmpmac[4], &tmpmac[5]);
249 if (count == 6) {
250 /* Valid! */
251 for (i = 0; i < ETHER_ADDR_LEN; i++)
252 sc->are_eaddr[i] = tmpmac[i];
253 }
254 }
255
256 mtx_init(&sc->are_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
257 MTX_DEF);
258 callout_init_mtx(&sc->are_stat_callout, &sc->are_mtx, 0);
259 TASK_INIT(&sc->are_link_task, 0, are_link_task, sc);
260
261 /* Map control/status registers. */
262 sc->are_rid = 0;
263 sc->are_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->are_rid,
264 RF_ACTIVE | RF_SHAREABLE);
265
266 if (sc->are_res == NULL) {
267 device_printf(dev, "couldn't map memory\n");
268 error = ENXIO;
269 goto fail;
270 }
271
272 sc->are_btag = rman_get_bustag(sc->are_res);
273 sc->are_bhandle = rman_get_bushandle(sc->are_res);
274
275 #ifndef INTRNG
276 /* Allocate interrupts */
277 rid = 0;
278 sc->are_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
279 RF_SHAREABLE | RF_ACTIVE);
280
281 if (sc->are_irq == NULL) {
282 device_printf(dev, "couldn't map interrupt\n");
283 error = ENXIO;
284 goto fail;
285 }
286 #endif
287
288 /* Allocate ifnet structure. */
289 ifp = sc->are_ifp = if_alloc(IFT_ETHER);
290
291 if (ifp == NULL) {
292 device_printf(dev, "couldn't allocate ifnet structure\n");
293 error = ENOSPC;
294 goto fail;
295 }
296 ifp->if_softc = sc;
297 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
298 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
299 ifp->if_ioctl = are_ioctl;
300 ifp->if_start = are_start;
301 ifp->if_init = are_init;
302 sc->are_if_flags = ifp->if_flags;
303
304 /* ifqmaxlen is sysctl value in net/if.c */
305 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
306 ifp->if_snd.ifq_maxlen = ifqmaxlen;
307 IFQ_SET_READY(&ifp->if_snd);
308
309 /* Tell the upper layer(s) we support long frames. */
310 ifp->if_capabilities |= IFCAP_VLAN_MTU;
311
312 ifp->if_capenable = ifp->if_capabilities;
313
314 if (are_dma_alloc(sc) != 0) {
315 error = ENXIO;
316 goto fail;
317 }
318
319 CSR_WRITE_4(sc, CSR_BUSMODE, BUSMODE_SWR);
320 DELAY(1000);
321
322 #ifdef ARE_MDIO
323 sc->are_miiproxy = mii_attach_proxy(sc->are_dev);
324 #endif
325
326 #ifdef ARE_MII
327 /* Do MII setup. */
328 error = mii_attach(dev, &sc->are_miibus, ifp, are_ifmedia_upd,
329 are_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
330 if (error != 0) {
331 device_printf(dev, "attaching PHYs failed\n");
332 goto fail;
333 }
334 #else
335 ifmedia_init(&sc->are_ifmedia, 0, are_ifmedia_upd, are_ifmedia_sts);
336
337 ifmedia_add(&sc->are_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
338 ifmedia_set(&sc->are_ifmedia, IFM_ETHER | IFM_AUTO);
339 #endif
340
341 /* Call MI attach routine. */
342 ether_ifattach(ifp, sc->are_eaddr);
343
344 #ifdef INTRNG
345 char *name;
346 if (ar531x_soc >= AR531X_SOC_AR5315) {
347 enetirq = AR5315_CPU_IRQ_ENET;
348 name = "enet";
349 } else {
350 if (device_get_unit(dev) == 0) {
351 enetirq = AR5312_IRQ_ENET0;
352 name = "enet0";
353 } else {
354 enetirq = AR5312_IRQ_ENET1;
355 name = "enet1";
356 }
357 }
358 cpu_establish_hardintr(name, NULL, are_intr, sc, enetirq,
359 INTR_TYPE_NET, NULL);
360 #else
361 /* Hook interrupt last to avoid having to lock softc */
362 error = bus_setup_intr(dev, sc->are_irq, INTR_TYPE_NET | INTR_MPSAFE,
363 NULL, are_intr, sc, &sc->are_intrhand);
364
365 if (error) {
366 device_printf(dev, "couldn't set up irq\n");
367 ether_ifdetach(ifp);
368 goto fail;
369 }
370 #endif
371
372 fail:
373 if (error)
374 are_detach(dev);
375
376 return (error);
377 }
378
379 static int
are_detach(device_t dev)380 are_detach(device_t dev)
381 {
382 struct are_softc *sc = device_get_softc(dev);
383 struct ifnet *ifp = sc->are_ifp;
384
385 KASSERT(mtx_initialized(&sc->are_mtx), ("vr mutex not initialized"));
386
387 /* These should only be active if attach succeeded */
388 if (device_is_attached(dev)) {
389 ARE_LOCK(sc);
390 sc->are_detach = 1;
391 are_stop(sc);
392 ARE_UNLOCK(sc);
393 taskqueue_drain(taskqueue_swi, &sc->are_link_task);
394 ether_ifdetach(ifp);
395 }
396 #ifdef ARE_MII
397 if (sc->are_miibus)
398 device_delete_child(dev, sc->are_miibus);
399 #endif
400 bus_generic_detach(dev);
401
402 if (sc->are_intrhand)
403 bus_teardown_intr(dev, sc->are_irq, sc->are_intrhand);
404 if (sc->are_irq)
405 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->are_irq);
406
407 if (sc->are_res)
408 bus_release_resource(dev, SYS_RES_MEMORY, sc->are_rid,
409 sc->are_res);
410
411 if (ifp)
412 if_free(ifp);
413
414 are_dma_free(sc);
415
416 mtx_destroy(&sc->are_mtx);
417
418 return (0);
419
420 }
421
422 static int
are_suspend(device_t dev)423 are_suspend(device_t dev)
424 {
425
426 panic("%s", __func__);
427 return 0;
428 }
429
430 static int
are_resume(device_t dev)431 are_resume(device_t dev)
432 {
433
434 panic("%s", __func__);
435 return 0;
436 }
437
438 static int
are_shutdown(device_t dev)439 are_shutdown(device_t dev)
440 {
441 struct are_softc *sc;
442
443 sc = device_get_softc(dev);
444
445 ARE_LOCK(sc);
446 are_stop(sc);
447 ARE_UNLOCK(sc);
448
449 return (0);
450 }
451
452 static int
are_miibus_readreg(device_t dev,int phy,int reg)453 are_miibus_readreg(device_t dev, int phy, int reg)
454 {
455 struct are_softc * sc = device_get_softc(dev);
456 uint32_t addr;
457 int i;
458
459 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT);
460 CSR_WRITE_4(sc, CSR_MIIADDR, addr);
461 for (i = 0; i < 100000000; i++) {
462 if ((CSR_READ_4(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0)
463 break;
464 }
465
466 return (CSR_READ_4(sc, CSR_MIIDATA) & 0xffff);
467 }
468
469 static int
are_miibus_writereg(device_t dev,int phy,int reg,int data)470 are_miibus_writereg(device_t dev, int phy, int reg, int data)
471 {
472 struct are_softc * sc = device_get_softc(dev);
473 uint32_t addr;
474 int i;
475
476 /* write the data register */
477 CSR_WRITE_4(sc, CSR_MIIDATA, data);
478
479 /* write the address to latch it in */
480 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) |
481 MIIADDR_WRITE;
482 CSR_WRITE_4(sc, CSR_MIIADDR, addr);
483
484 for (i = 0; i < 100000000; i++) {
485 if ((CSR_READ_4(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0)
486 break;
487 }
488
489 return (0);
490 }
491
492 static void
are_miibus_statchg(device_t dev)493 are_miibus_statchg(device_t dev)
494 {
495 struct are_softc *sc;
496
497 sc = device_get_softc(dev);
498 taskqueue_enqueue(taskqueue_swi, &sc->are_link_task);
499 }
500
501 static void
are_link_task(void * arg,int pending)502 are_link_task(void *arg, int pending)
503 {
504 #ifdef ARE_MII
505 struct are_softc *sc;
506 struct mii_data *mii;
507 struct ifnet *ifp;
508 /* int lfdx, mfdx; */
509
510 sc = (struct are_softc *)arg;
511
512 ARE_LOCK(sc);
513 mii = device_get_softc(sc->are_miibus);
514 ifp = sc->are_ifp;
515 if (mii == NULL || ifp == NULL ||
516 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
517 ARE_UNLOCK(sc);
518 return;
519 }
520
521 if (mii->mii_media_status & IFM_ACTIVE) {
522 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
523 sc->are_link_status = 1;
524 } else
525 sc->are_link_status = 0;
526
527 ARE_UNLOCK(sc);
528 #endif
529 }
530
531 static void
are_reset(struct are_softc * sc)532 are_reset(struct are_softc *sc)
533 {
534 int i;
535
536 CSR_WRITE_4(sc, CSR_BUSMODE, BUSMODE_SWR);
537
538 /*
539 * The chip doesn't take itself out of reset automatically.
540 * We need to do so after 2us.
541 */
542 DELAY(10);
543 CSR_WRITE_4(sc, CSR_BUSMODE, 0);
544
545 for (i = 0; i < 1000; i++) {
546 /*
547 * Wait a bit for the reset to complete before peeking
548 * at the chip again.
549 */
550 DELAY(10);
551 if ((CSR_READ_4(sc, CSR_BUSMODE) & BUSMODE_SWR) == 0)
552 break;
553 }
554
555 if (CSR_READ_4(sc, CSR_BUSMODE) & BUSMODE_SWR)
556 device_printf(sc->are_dev, "reset time out\n");
557
558 DELAY(1000);
559 }
560
561 static void
are_init(void * xsc)562 are_init(void *xsc)
563 {
564 struct are_softc *sc = xsc;
565
566 ARE_LOCK(sc);
567 are_init_locked(sc);
568 ARE_UNLOCK(sc);
569 }
570
571 static void
are_init_locked(struct are_softc * sc)572 are_init_locked(struct are_softc *sc)
573 {
574 struct ifnet *ifp = sc->are_ifp;
575 #ifdef ARE_MII
576 struct mii_data *mii;
577 #endif
578
579 ARE_LOCK_ASSERT(sc);
580
581 #ifdef ARE_MII
582 mii = device_get_softc(sc->are_miibus);
583 #endif
584
585 are_stop(sc);
586 are_reset(sc);
587
588 /* Init circular RX list. */
589 if (are_rx_ring_init(sc) != 0) {
590 device_printf(sc->are_dev,
591 "initialization failed: no memory for rx buffers\n");
592 are_stop(sc);
593 return;
594 }
595
596 /* Init tx descriptors. */
597 are_tx_ring_init(sc);
598
599 /*
600 * Initialize the BUSMODE register.
601 */
602 CSR_WRITE_4(sc, CSR_BUSMODE,
603 /* XXX: not sure if this is a good thing or not... */
604 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW);
605
606 /*
607 * Initialize the interrupt mask and enable interrupts.
608 */
609 /* normal interrupts */
610 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS;
611
612 /* abnormal interrupts */
613 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF |
614 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS;
615
616 sc->sc_rxint_mask = STATUS_RI|STATUS_RU;
617 sc->sc_txint_mask = STATUS_TI|STATUS_UNF|STATUS_TJT;
618
619 sc->sc_rxint_mask &= sc->sc_inten;
620 sc->sc_txint_mask &= sc->sc_inten;
621
622 CSR_WRITE_4(sc, CSR_INTEN, sc->sc_inten);
623 CSR_WRITE_4(sc, CSR_STATUS, 0xffffffff);
624
625 /*
626 * Give the transmit and receive rings to the chip.
627 */
628 CSR_WRITE_4(sc, CSR_TXLIST, ARE_TX_RING_ADDR(sc, 0));
629 CSR_WRITE_4(sc, CSR_RXLIST, ARE_RX_RING_ADDR(sc, 0));
630
631 /*
632 * Set the station address.
633 */
634 CSR_WRITE_4(sc, CSR_MACHI, sc->are_eaddr[5] << 16 | sc->are_eaddr[4]);
635 CSR_WRITE_4(sc, CSR_MACLO, sc->are_eaddr[3] << 24 |
636 sc->are_eaddr[2] << 16 | sc->are_eaddr[1] << 8 | sc->are_eaddr[0]);
637
638 /*
639 * Start the mac.
640 */
641 CSR_WRITE_4(sc, CSR_FLOWC, FLOWC_FCE);
642 CSR_WRITE_4(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE |
643 MACCTL_PM | MACCTL_FDX | MACCTL_HBD | MACCTL_RA);
644
645 /*
646 * Write out the opmode.
647 */
648 CSR_WRITE_4(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | OPMODE_SF |
649 OPMODE_TR_64);
650
651 /*
652 * Start the receive process.
653 */
654 CSR_WRITE_4(sc, CSR_RXPOLL, RXPOLL_RPD);
655
656 sc->are_link_status = 1;
657 #ifdef ARE_MII
658 mii_mediachg(mii);
659 #endif
660
661 ifp->if_drv_flags |= IFF_DRV_RUNNING;
662 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
663
664 callout_reset(&sc->are_stat_callout, hz, are_tick, sc);
665 }
666
667 static void
are_start(struct ifnet * ifp)668 are_start(struct ifnet *ifp)
669 {
670 struct are_softc *sc;
671
672 sc = ifp->if_softc;
673
674 ARE_LOCK(sc);
675 are_start_locked(ifp);
676 ARE_UNLOCK(sc);
677 }
678
679 /*
680 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
681 * pointers to the fragment pointers.
682 */
683 static int
are_encap(struct are_softc * sc,struct mbuf ** m_head)684 are_encap(struct are_softc *sc, struct mbuf **m_head)
685 {
686 struct are_txdesc *txd;
687 struct are_desc *desc, *prev_desc;
688 struct mbuf *m;
689 bus_dma_segment_t txsegs[ARE_MAXFRAGS];
690 uint32_t link_addr;
691 int error, i, nsegs, prod, si, prev_prod;
692 int txstat;
693 int startcount;
694 int padlen;
695
696 startcount = sc->are_cdata.are_tx_cnt;
697
698 ARE_LOCK_ASSERT(sc);
699
700 /*
701 * Some VIA Rhine wants packet buffers to be longword
702 * aligned, but very often our mbufs aren't. Rather than
703 * waste time trying to decide when to copy and when not
704 * to copy, just do it all the time.
705 */
706 m = m_defrag(*m_head, M_NOWAIT);
707 if (m == NULL) {
708 device_printf(sc->are_dev, "are_encap m_defrag error\n");
709 m_freem(*m_head);
710 *m_head = NULL;
711 return (ENOBUFS);
712 }
713 *m_head = m;
714
715 /*
716 * The Rhine chip doesn't auto-pad, so we have to make
717 * sure to pad short frames out to the minimum frame length
718 * ourselves.
719 */
720 if ((*m_head)->m_pkthdr.len < ARE_MIN_FRAMELEN) {
721 m = *m_head;
722 padlen = ARE_MIN_FRAMELEN - m->m_pkthdr.len;
723 if (M_WRITABLE(m) == 0) {
724 /* Get a writable copy. */
725 m = m_dup(*m_head, M_NOWAIT);
726 m_freem(*m_head);
727 if (m == NULL) {
728 device_printf(sc->are_dev, "are_encap m_dup error\n");
729 *m_head = NULL;
730 return (ENOBUFS);
731 }
732 *m_head = m;
733 }
734 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
735 m = m_defrag(m, M_NOWAIT);
736 if (m == NULL) {
737 device_printf(sc->are_dev, "are_encap m_defrag error\n");
738 m_freem(*m_head);
739 *m_head = NULL;
740 return (ENOBUFS);
741 }
742 }
743 /*
744 * Manually pad short frames, and zero the pad space
745 * to avoid leaking data.
746 */
747 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
748 m->m_pkthdr.len += padlen;
749 m->m_len = m->m_pkthdr.len;
750 *m_head = m;
751 }
752
753 prod = sc->are_cdata.are_tx_prod;
754 txd = &sc->are_cdata.are_txdesc[prod];
755 error = bus_dmamap_load_mbuf_sg(sc->are_cdata.are_tx_tag,
756 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
757 if (error == EFBIG) {
758 device_printf(sc->are_dev, "are_encap EFBIG error\n");
759 m = m_defrag(*m_head, M_NOWAIT);
760 if (m == NULL) {
761 m_freem(*m_head);
762 *m_head = NULL;
763 return (ENOBUFS);
764 }
765 *m_head = m;
766 error = bus_dmamap_load_mbuf_sg(sc->are_cdata.are_tx_tag,
767 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
768 if (error != 0) {
769 m_freem(*m_head);
770 *m_head = NULL;
771 return (error);
772 }
773
774 } else if (error != 0)
775 return (error);
776 if (nsegs == 0) {
777 m_freem(*m_head);
778 *m_head = NULL;
779 return (EIO);
780 }
781
782 /* Check number of available descriptors. */
783 if (sc->are_cdata.are_tx_cnt + nsegs >= (ARE_TX_RING_CNT - 1)) {
784 bus_dmamap_unload(sc->are_cdata.are_tx_tag, txd->tx_dmamap);
785 return (ENOBUFS);
786 }
787
788 txd->tx_m = *m_head;
789 bus_dmamap_sync(sc->are_cdata.are_tx_tag, txd->tx_dmamap,
790 BUS_DMASYNC_PREWRITE);
791
792 si = prod;
793
794 /*
795 * Make a list of descriptors for this packet. DMA controller will
796 * walk through it while are_link is not zero. The last one should
797 * have COF flag set, to pickup next chain from NDPTR
798 */
799 prev_prod = prod;
800 desc = prev_desc = NULL;
801 for (i = 0; i < nsegs; i++) {
802 desc = &sc->are_rdata.are_tx_ring[prod];
803 desc->are_stat = ADSTAT_OWN;
804 desc->are_devcs = ARE_DMASIZE(txsegs[i].ds_len);
805 desc->are_addr = txsegs[i].ds_addr;
806 /* link with previous descriptor */
807 /* end of descriptor */
808 if (prod == ARE_TX_RING_CNT - 1)
809 desc->are_devcs |= ADCTL_ER;
810
811 sc->are_cdata.are_tx_cnt++;
812 prev_desc = desc;
813 ARE_INC(prod, ARE_TX_RING_CNT);
814 }
815
816 /*
817 * Set mark last fragment with LD flag
818 */
819 if (desc) {
820 desc->are_devcs |= ADCTL_Tx_IC;
821 desc->are_devcs |= ADCTL_Tx_LS;
822 }
823
824 /* Update producer index. */
825 sc->are_cdata.are_tx_prod = prod;
826
827 /* Sync descriptors. */
828 bus_dmamap_sync(sc->are_cdata.are_tx_ring_tag,
829 sc->are_cdata.are_tx_ring_map,
830 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
831
832 /* Start transmitting */
833 /* Check if new list is queued in NDPTR */
834 txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7;
835 if (startcount == 0 && (txstat == 0 || txstat == 6)) {
836 desc = &sc->are_rdata.are_tx_ring[si];
837 desc->are_devcs |= ADCTL_Tx_FS;
838 }
839 else {
840 link_addr = ARE_TX_RING_ADDR(sc, si);
841 /* Get previous descriptor */
842 si = (si + ARE_TX_RING_CNT - 1) % ARE_TX_RING_CNT;
843 desc = &sc->are_rdata.are_tx_ring[si];
844 desc->are_devcs &= ~(ADCTL_Tx_IC | ADCTL_Tx_LS);
845 }
846
847 return (0);
848 }
849
850 static void
are_start_locked(struct ifnet * ifp)851 are_start_locked(struct ifnet *ifp)
852 {
853 struct are_softc *sc;
854 struct mbuf *m_head;
855 int enq;
856 int txstat;
857
858 sc = ifp->if_softc;
859
860 ARE_LOCK_ASSERT(sc);
861
862 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
863 IFF_DRV_RUNNING || sc->are_link_status == 0 )
864 return;
865
866 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
867 sc->are_cdata.are_tx_cnt < ARE_TX_RING_CNT - 2; ) {
868 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
869 if (m_head == NULL)
870 break;
871 /*
872 * Pack the data into the transmit ring. If we
873 * don't have room, set the OACTIVE flag and wait
874 * for the NIC to drain the ring.
875 */
876 if (are_encap(sc, &m_head)) {
877 if (m_head == NULL)
878 break;
879 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
880 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
881 break;
882 }
883
884 enq++;
885 /*
886 * If there's a BPF listener, bounce a copy of this frame
887 * to him.
888 */
889 ETHER_BPF_MTAP(ifp, m_head);
890 }
891
892 if (enq > 0) {
893 txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7;
894 if (txstat == 0 || txstat == 6) {
895 /* Transmit Process Stat is stop or suspended */
896 CSR_WRITE_4(sc, CSR_TXPOLL, TXPOLL_TPD);
897 }
898 }
899 }
900
901 static void
are_stop(struct are_softc * sc)902 are_stop(struct are_softc *sc)
903 {
904 struct ifnet *ifp;
905
906 ARE_LOCK_ASSERT(sc);
907
908 ifp = sc->are_ifp;
909 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
910 callout_stop(&sc->are_stat_callout);
911
912 /* Disable interrupts. */
913 CSR_WRITE_4(sc, CSR_INTEN, 0);
914
915 /* Stop the transmit and receive processes. */
916 CSR_WRITE_4(sc, CSR_OPMODE, 0);
917 CSR_WRITE_4(sc, CSR_RXLIST, 0);
918 CSR_WRITE_4(sc, CSR_TXLIST, 0);
919 CSR_WRITE_4(sc, CSR_MACCTL,
920 CSR_READ_4(sc, CSR_MACCTL) & ~(MACCTL_TE | MACCTL_RE));
921
922 }
923
924 static int
are_set_filter(struct are_softc * sc)925 are_set_filter(struct are_softc *sc)
926 {
927 struct ifnet *ifp;
928 int mchash[2];
929 int macctl;
930
931 ifp = sc->are_ifp;
932
933 macctl = CSR_READ_4(sc, CSR_MACCTL);
934 macctl &= ~(MACCTL_PR | MACCTL_PM);
935 macctl |= MACCTL_HBD;
936
937 if (ifp->if_flags & IFF_PROMISC)
938 macctl |= MACCTL_PR;
939
940 /* Todo: hash table set.
941 * But I don't know how to use multicast hash table at this soc.
942 */
943
944 /* this is allmulti */
945 mchash[0] = mchash[1] = 0xffffffff;
946 macctl |= MACCTL_PM;
947
948 CSR_WRITE_4(sc, CSR_HTLO, mchash[0]);
949 CSR_WRITE_4(sc, CSR_HTHI, mchash[1]);
950 CSR_WRITE_4(sc, CSR_MACCTL, macctl);
951
952 return 0;
953 }
954
955 static int
are_ioctl(struct ifnet * ifp,u_long command,caddr_t data)956 are_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
957 {
958 struct are_softc *sc = ifp->if_softc;
959 struct ifreq *ifr = (struct ifreq *) data;
960 #ifdef ARE_MII
961 struct mii_data *mii;
962 #endif
963 int error;
964
965 switch (command) {
966 case SIOCSIFFLAGS:
967 ARE_LOCK(sc);
968 if (ifp->if_flags & IFF_UP) {
969 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
970 if ((ifp->if_flags ^ sc->are_if_flags) &
971 (IFF_PROMISC | IFF_ALLMULTI))
972 are_set_filter(sc);
973 } else {
974 if (sc->are_detach == 0)
975 are_init_locked(sc);
976 }
977 } else {
978 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
979 are_stop(sc);
980 }
981 sc->are_if_flags = ifp->if_flags;
982 ARE_UNLOCK(sc);
983 error = 0;
984 break;
985 case SIOCADDMULTI:
986 case SIOCDELMULTI:
987 ARE_LOCK(sc);
988 are_set_filter(sc);
989 ARE_UNLOCK(sc);
990 error = 0;
991 break;
992 case SIOCGIFMEDIA:
993 case SIOCSIFMEDIA:
994 #ifdef ARE_MII
995 mii = device_get_softc(sc->are_miibus);
996 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
997 #else
998 error = ifmedia_ioctl(ifp, ifr, &sc->are_ifmedia, command);
999 #endif
1000 break;
1001 case SIOCSIFCAP:
1002 error = 0;
1003 break;
1004 default:
1005 error = ether_ioctl(ifp, command, data);
1006 break;
1007 }
1008
1009 return (error);
1010 }
1011
1012 /*
1013 * Set media options.
1014 */
1015 static int
are_ifmedia_upd(struct ifnet * ifp)1016 are_ifmedia_upd(struct ifnet *ifp)
1017 {
1018 #ifdef ARE_MII
1019 struct are_softc *sc;
1020 struct mii_data *mii;
1021 struct mii_softc *miisc;
1022 int error;
1023
1024 sc = ifp->if_softc;
1025 ARE_LOCK(sc);
1026 mii = device_get_softc(sc->are_miibus);
1027 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1028 PHY_RESET(miisc);
1029 error = mii_mediachg(mii);
1030 ARE_UNLOCK(sc);
1031
1032 return (error);
1033 #else
1034 return (0);
1035 #endif
1036 }
1037
1038 /*
1039 * Report current media status.
1040 */
1041 static void
are_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1042 are_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1043 {
1044 #ifdef ARE_MII
1045 struct are_softc *sc = ifp->if_softc;
1046 struct mii_data *mii;
1047
1048 mii = device_get_softc(sc->are_miibus);
1049 ARE_LOCK(sc);
1050 mii_pollstat(mii);
1051 ifmr->ifm_active = mii->mii_media_active;
1052 ifmr->ifm_status = mii->mii_media_status;
1053 ARE_UNLOCK(sc);
1054 #else
1055 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
1056 #endif
1057 }
1058
1059 struct are_dmamap_arg {
1060 bus_addr_t are_busaddr;
1061 };
1062
1063 static void
are_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)1064 are_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1065 {
1066 struct are_dmamap_arg *ctx;
1067
1068 if (error != 0)
1069 return;
1070 ctx = arg;
1071 ctx->are_busaddr = segs[0].ds_addr;
1072 }
1073
1074 static int
are_dma_alloc(struct are_softc * sc)1075 are_dma_alloc(struct are_softc *sc)
1076 {
1077 struct are_dmamap_arg ctx;
1078 struct are_txdesc *txd;
1079 struct are_rxdesc *rxd;
1080 int error, i;
1081
1082 /* Create parent DMA tag. */
1083 error = bus_dma_tag_create(
1084 bus_get_dma_tag(sc->are_dev), /* parent */
1085 1, 0, /* alignment, boundary */
1086 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1087 BUS_SPACE_MAXADDR, /* highaddr */
1088 NULL, NULL, /* filter, filterarg */
1089 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1090 0, /* nsegments */
1091 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1092 0, /* flags */
1093 NULL, NULL, /* lockfunc, lockarg */
1094 &sc->are_cdata.are_parent_tag);
1095 if (error != 0) {
1096 device_printf(sc->are_dev, "failed to create parent DMA tag\n");
1097 goto fail;
1098 }
1099 /* Create tag for Tx ring. */
1100 error = bus_dma_tag_create(
1101 sc->are_cdata.are_parent_tag, /* parent */
1102 ARE_RING_ALIGN, 0, /* alignment, boundary */
1103 BUS_SPACE_MAXADDR, /* lowaddr */
1104 BUS_SPACE_MAXADDR, /* highaddr */
1105 NULL, NULL, /* filter, filterarg */
1106 ARE_TX_RING_SIZE, /* maxsize */
1107 1, /* nsegments */
1108 ARE_TX_RING_SIZE, /* maxsegsize */
1109 0, /* flags */
1110 NULL, NULL, /* lockfunc, lockarg */
1111 &sc->are_cdata.are_tx_ring_tag);
1112 if (error != 0) {
1113 device_printf(sc->are_dev, "failed to create Tx ring DMA tag\n");
1114 goto fail;
1115 }
1116
1117 /* Create tag for Rx ring. */
1118 error = bus_dma_tag_create(
1119 sc->are_cdata.are_parent_tag, /* parent */
1120 ARE_RING_ALIGN, 0, /* alignment, boundary */
1121 BUS_SPACE_MAXADDR, /* lowaddr */
1122 BUS_SPACE_MAXADDR, /* highaddr */
1123 NULL, NULL, /* filter, filterarg */
1124 ARE_RX_RING_SIZE, /* maxsize */
1125 1, /* nsegments */
1126 ARE_RX_RING_SIZE, /* maxsegsize */
1127 0, /* flags */
1128 NULL, NULL, /* lockfunc, lockarg */
1129 &sc->are_cdata.are_rx_ring_tag);
1130 if (error != 0) {
1131 device_printf(sc->are_dev, "failed to create Rx ring DMA tag\n");
1132 goto fail;
1133 }
1134
1135 /* Create tag for Tx buffers. */
1136 error = bus_dma_tag_create(
1137 sc->are_cdata.are_parent_tag, /* parent */
1138 sizeof(uint32_t), 0, /* alignment, boundary */
1139 BUS_SPACE_MAXADDR, /* lowaddr */
1140 BUS_SPACE_MAXADDR, /* highaddr */
1141 NULL, NULL, /* filter, filterarg */
1142 MCLBYTES * ARE_MAXFRAGS, /* maxsize */
1143 ARE_MAXFRAGS, /* nsegments */
1144 MCLBYTES, /* maxsegsize */
1145 0, /* flags */
1146 NULL, NULL, /* lockfunc, lockarg */
1147 &sc->are_cdata.are_tx_tag);
1148 if (error != 0) {
1149 device_printf(sc->are_dev, "failed to create Tx DMA tag\n");
1150 goto fail;
1151 }
1152
1153 /* Create tag for Rx buffers. */
1154 error = bus_dma_tag_create(
1155 sc->are_cdata.are_parent_tag, /* parent */
1156 ARE_RX_ALIGN, 0, /* alignment, boundary */
1157 BUS_SPACE_MAXADDR, /* lowaddr */
1158 BUS_SPACE_MAXADDR, /* highaddr */
1159 NULL, NULL, /* filter, filterarg */
1160 MCLBYTES, /* maxsize */
1161 1, /* nsegments */
1162 MCLBYTES, /* maxsegsize */
1163 0, /* flags */
1164 NULL, NULL, /* lockfunc, lockarg */
1165 &sc->are_cdata.are_rx_tag);
1166 if (error != 0) {
1167 device_printf(sc->are_dev, "failed to create Rx DMA tag\n");
1168 goto fail;
1169 }
1170
1171 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1172 error = bus_dmamem_alloc(sc->are_cdata.are_tx_ring_tag,
1173 (void **)&sc->are_rdata.are_tx_ring, BUS_DMA_WAITOK |
1174 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->are_cdata.are_tx_ring_map);
1175 if (error != 0) {
1176 device_printf(sc->are_dev,
1177 "failed to allocate DMA'able memory for Tx ring\n");
1178 goto fail;
1179 }
1180
1181 ctx.are_busaddr = 0;
1182 error = bus_dmamap_load(sc->are_cdata.are_tx_ring_tag,
1183 sc->are_cdata.are_tx_ring_map, sc->are_rdata.are_tx_ring,
1184 ARE_TX_RING_SIZE, are_dmamap_cb, &ctx, 0);
1185 if (error != 0 || ctx.are_busaddr == 0) {
1186 device_printf(sc->are_dev,
1187 "failed to load DMA'able memory for Tx ring\n");
1188 goto fail;
1189 }
1190 sc->are_rdata.are_tx_ring_paddr = ctx.are_busaddr;
1191
1192 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1193 error = bus_dmamem_alloc(sc->are_cdata.are_rx_ring_tag,
1194 (void **)&sc->are_rdata.are_rx_ring, BUS_DMA_WAITOK |
1195 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->are_cdata.are_rx_ring_map);
1196 if (error != 0) {
1197 device_printf(sc->are_dev,
1198 "failed to allocate DMA'able memory for Rx ring\n");
1199 goto fail;
1200 }
1201
1202 ctx.are_busaddr = 0;
1203 error = bus_dmamap_load(sc->are_cdata.are_rx_ring_tag,
1204 sc->are_cdata.are_rx_ring_map, sc->are_rdata.are_rx_ring,
1205 ARE_RX_RING_SIZE, are_dmamap_cb, &ctx, 0);
1206 if (error != 0 || ctx.are_busaddr == 0) {
1207 device_printf(sc->are_dev,
1208 "failed to load DMA'able memory for Rx ring\n");
1209 goto fail;
1210 }
1211 sc->are_rdata.are_rx_ring_paddr = ctx.are_busaddr;
1212
1213 /* Create DMA maps for Tx buffers. */
1214 for (i = 0; i < ARE_TX_RING_CNT; i++) {
1215 txd = &sc->are_cdata.are_txdesc[i];
1216 txd->tx_m = NULL;
1217 txd->tx_dmamap = NULL;
1218 error = bus_dmamap_create(sc->are_cdata.are_tx_tag, 0,
1219 &txd->tx_dmamap);
1220 if (error != 0) {
1221 device_printf(sc->are_dev,
1222 "failed to create Tx dmamap\n");
1223 goto fail;
1224 }
1225 }
1226 /* Create DMA maps for Rx buffers. */
1227 if ((error = bus_dmamap_create(sc->are_cdata.are_rx_tag, 0,
1228 &sc->are_cdata.are_rx_sparemap)) != 0) {
1229 device_printf(sc->are_dev,
1230 "failed to create spare Rx dmamap\n");
1231 goto fail;
1232 }
1233 for (i = 0; i < ARE_RX_RING_CNT; i++) {
1234 rxd = &sc->are_cdata.are_rxdesc[i];
1235 rxd->rx_m = NULL;
1236 rxd->rx_dmamap = NULL;
1237 error = bus_dmamap_create(sc->are_cdata.are_rx_tag, 0,
1238 &rxd->rx_dmamap);
1239 if (error != 0) {
1240 device_printf(sc->are_dev,
1241 "failed to create Rx dmamap\n");
1242 goto fail;
1243 }
1244 }
1245
1246 fail:
1247 return (error);
1248 }
1249
1250 static void
are_dma_free(struct are_softc * sc)1251 are_dma_free(struct are_softc *sc)
1252 {
1253 struct are_txdesc *txd;
1254 struct are_rxdesc *rxd;
1255 int i;
1256
1257 /* Tx ring. */
1258 if (sc->are_cdata.are_tx_ring_tag) {
1259 if (sc->are_rdata.are_tx_ring_paddr)
1260 bus_dmamap_unload(sc->are_cdata.are_tx_ring_tag,
1261 sc->are_cdata.are_tx_ring_map);
1262 if (sc->are_rdata.are_tx_ring)
1263 bus_dmamem_free(sc->are_cdata.are_tx_ring_tag,
1264 sc->are_rdata.are_tx_ring,
1265 sc->are_cdata.are_tx_ring_map);
1266 sc->are_rdata.are_tx_ring = NULL;
1267 sc->are_rdata.are_tx_ring_paddr = 0;
1268 bus_dma_tag_destroy(sc->are_cdata.are_tx_ring_tag);
1269 sc->are_cdata.are_tx_ring_tag = NULL;
1270 }
1271 /* Rx ring. */
1272 if (sc->are_cdata.are_rx_ring_tag) {
1273 if (sc->are_rdata.are_rx_ring_paddr)
1274 bus_dmamap_unload(sc->are_cdata.are_rx_ring_tag,
1275 sc->are_cdata.are_rx_ring_map);
1276 if (sc->are_rdata.are_rx_ring)
1277 bus_dmamem_free(sc->are_cdata.are_rx_ring_tag,
1278 sc->are_rdata.are_rx_ring,
1279 sc->are_cdata.are_rx_ring_map);
1280 sc->are_rdata.are_rx_ring = NULL;
1281 sc->are_rdata.are_rx_ring_paddr = 0;
1282 bus_dma_tag_destroy(sc->are_cdata.are_rx_ring_tag);
1283 sc->are_cdata.are_rx_ring_tag = NULL;
1284 }
1285 /* Tx buffers. */
1286 if (sc->are_cdata.are_tx_tag) {
1287 for (i = 0; i < ARE_TX_RING_CNT; i++) {
1288 txd = &sc->are_cdata.are_txdesc[i];
1289 if (txd->tx_dmamap) {
1290 bus_dmamap_destroy(sc->are_cdata.are_tx_tag,
1291 txd->tx_dmamap);
1292 txd->tx_dmamap = NULL;
1293 }
1294 }
1295 bus_dma_tag_destroy(sc->are_cdata.are_tx_tag);
1296 sc->are_cdata.are_tx_tag = NULL;
1297 }
1298 /* Rx buffers. */
1299 if (sc->are_cdata.are_rx_tag) {
1300 for (i = 0; i < ARE_RX_RING_CNT; i++) {
1301 rxd = &sc->are_cdata.are_rxdesc[i];
1302 if (rxd->rx_dmamap) {
1303 bus_dmamap_destroy(sc->are_cdata.are_rx_tag,
1304 rxd->rx_dmamap);
1305 rxd->rx_dmamap = NULL;
1306 }
1307 }
1308 if (sc->are_cdata.are_rx_sparemap) {
1309 bus_dmamap_destroy(sc->are_cdata.are_rx_tag,
1310 sc->are_cdata.are_rx_sparemap);
1311 sc->are_cdata.are_rx_sparemap = 0;
1312 }
1313 bus_dma_tag_destroy(sc->are_cdata.are_rx_tag);
1314 sc->are_cdata.are_rx_tag = NULL;
1315 }
1316
1317 if (sc->are_cdata.are_parent_tag) {
1318 bus_dma_tag_destroy(sc->are_cdata.are_parent_tag);
1319 sc->are_cdata.are_parent_tag = NULL;
1320 }
1321 }
1322
1323 /*
1324 * Initialize the transmit descriptors.
1325 */
1326 static int
are_tx_ring_init(struct are_softc * sc)1327 are_tx_ring_init(struct are_softc *sc)
1328 {
1329 struct are_ring_data *rd;
1330 struct are_txdesc *txd;
1331 bus_addr_t addr;
1332 int i;
1333
1334 sc->are_cdata.are_tx_prod = 0;
1335 sc->are_cdata.are_tx_cons = 0;
1336 sc->are_cdata.are_tx_cnt = 0;
1337 sc->are_cdata.are_tx_pkts = 0;
1338
1339 rd = &sc->are_rdata;
1340 bzero(rd->are_tx_ring, ARE_TX_RING_SIZE);
1341 for (i = 0; i < ARE_TX_RING_CNT; i++) {
1342 if (i == ARE_TX_RING_CNT - 1)
1343 addr = ARE_TX_RING_ADDR(sc, 0);
1344 else
1345 addr = ARE_TX_RING_ADDR(sc, i + 1);
1346 rd->are_tx_ring[i].are_stat = 0;
1347 rd->are_tx_ring[i].are_devcs = 0;
1348 rd->are_tx_ring[i].are_addr = 0;
1349 rd->are_tx_ring[i].are_link = addr;
1350 txd = &sc->are_cdata.are_txdesc[i];
1351 txd->tx_m = NULL;
1352 }
1353
1354 bus_dmamap_sync(sc->are_cdata.are_tx_ring_tag,
1355 sc->are_cdata.are_tx_ring_map,
1356 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1357
1358 return (0);
1359 }
1360
1361 /*
1362 * Initialize the RX descriptors and allocate mbufs for them. Note that
1363 * we arrange the descriptors in a closed ring, so that the last descriptor
1364 * points back to the first.
1365 */
1366 static int
are_rx_ring_init(struct are_softc * sc)1367 are_rx_ring_init(struct are_softc *sc)
1368 {
1369 struct are_ring_data *rd;
1370 struct are_rxdesc *rxd;
1371 bus_addr_t addr;
1372 int i;
1373
1374 sc->are_cdata.are_rx_cons = 0;
1375
1376 rd = &sc->are_rdata;
1377 bzero(rd->are_rx_ring, ARE_RX_RING_SIZE);
1378 for (i = 0; i < ARE_RX_RING_CNT; i++) {
1379 rxd = &sc->are_cdata.are_rxdesc[i];
1380 rxd->rx_m = NULL;
1381 rxd->desc = &rd->are_rx_ring[i];
1382 if (i == ARE_RX_RING_CNT - 1)
1383 addr = ARE_RX_RING_ADDR(sc, 0);
1384 else
1385 addr = ARE_RX_RING_ADDR(sc, i + 1);
1386 rd->are_rx_ring[i].are_stat = ADSTAT_OWN;
1387 rd->are_rx_ring[i].are_devcs = ADCTL_CH;
1388 if (i == ARE_RX_RING_CNT - 1)
1389 rd->are_rx_ring[i].are_devcs |= ADCTL_ER;
1390 rd->are_rx_ring[i].are_addr = 0;
1391 rd->are_rx_ring[i].are_link = addr;
1392 if (are_newbuf(sc, i) != 0)
1393 return (ENOBUFS);
1394 }
1395
1396 bus_dmamap_sync(sc->are_cdata.are_rx_ring_tag,
1397 sc->are_cdata.are_rx_ring_map,
1398 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1399
1400 return (0);
1401 }
1402
1403 /*
1404 * Initialize an RX descriptor and attach an MBUF cluster.
1405 */
1406 static int
are_newbuf(struct are_softc * sc,int idx)1407 are_newbuf(struct are_softc *sc, int idx)
1408 {
1409 struct are_desc *desc;
1410 struct are_rxdesc *rxd;
1411 struct mbuf *m;
1412 bus_dma_segment_t segs[1];
1413 bus_dmamap_t map;
1414 int nsegs;
1415
1416 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1417 if (m == NULL)
1418 return (ENOBUFS);
1419 m->m_len = m->m_pkthdr.len = MCLBYTES;
1420
1421 /* tcp header boundary margin */
1422 m_adj(m, 4);
1423
1424 if (bus_dmamap_load_mbuf_sg(sc->are_cdata.are_rx_tag,
1425 sc->are_cdata.are_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1426 m_freem(m);
1427 return (ENOBUFS);
1428 }
1429 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1430
1431 rxd = &sc->are_cdata.are_rxdesc[idx];
1432 if (rxd->rx_m != NULL) {
1433 /*
1434 * THis is if_kr.c original code but make bug. Make scranble on buffer data.
1435 * bus_dmamap_sync(sc->are_cdata.are_rx_tag, rxd->rx_dmamap,
1436 * BUS_DMASYNC_POSTREAD);
1437 */
1438 bus_dmamap_unload(sc->are_cdata.are_rx_tag, rxd->rx_dmamap);
1439 }
1440 map = rxd->rx_dmamap;
1441 rxd->rx_dmamap = sc->are_cdata.are_rx_sparemap;
1442 sc->are_cdata.are_rx_sparemap = map;
1443 bus_dmamap_sync(sc->are_cdata.are_rx_tag, rxd->rx_dmamap,
1444 BUS_DMASYNC_PREREAD);
1445 rxd->rx_m = m;
1446 desc = rxd->desc;
1447 desc->are_addr = segs[0].ds_addr;
1448 desc->are_devcs |= ARE_DMASIZE(segs[0].ds_len);
1449 rxd->saved_ca = desc->are_addr ;
1450 rxd->saved_ctl = desc->are_stat ;
1451
1452 return (0);
1453 }
1454
1455 static __inline void
are_fixup_rx(struct mbuf * m)1456 are_fixup_rx(struct mbuf *m)
1457 {
1458 int i;
1459 uint16_t *src, *dst;
1460
1461 src = mtod(m, uint16_t *);
1462 dst = src - 1;
1463
1464 for (i = 0; i < m->m_len / sizeof(uint16_t); i++) {
1465 *dst++ = *src++;
1466 }
1467
1468 if (m->m_len % sizeof(uint16_t))
1469 *(uint8_t *)dst = *(uint8_t *)src;
1470
1471 m->m_data -= ETHER_ALIGN;
1472 }
1473
1474 static void
are_tx(struct are_softc * sc)1475 are_tx(struct are_softc *sc)
1476 {
1477 struct are_txdesc *txd;
1478 struct are_desc *cur_tx;
1479 struct ifnet *ifp;
1480 uint32_t ctl, devcs;
1481 int cons, prod;
1482
1483 ARE_LOCK_ASSERT(sc);
1484
1485 cons = sc->are_cdata.are_tx_cons;
1486 prod = sc->are_cdata.are_tx_prod;
1487 if (cons == prod)
1488 return;
1489
1490 bus_dmamap_sync(sc->are_cdata.are_tx_ring_tag,
1491 sc->are_cdata.are_tx_ring_map,
1492 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1493
1494 ifp = sc->are_ifp;
1495 /*
1496 * Go through our tx list and free mbufs for those
1497 * frames that have been transmitted.
1498 */
1499 for (; cons != prod; ARE_INC(cons, ARE_TX_RING_CNT)) {
1500 cur_tx = &sc->are_rdata.are_tx_ring[cons];
1501 ctl = cur_tx->are_stat;
1502 devcs = cur_tx->are_devcs;
1503 /* Check if descriptor has "finished" flag */
1504 if (ARE_DMASIZE(devcs) == 0)
1505 break;
1506
1507 sc->are_cdata.are_tx_cnt--;
1508 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1509
1510 txd = &sc->are_cdata.are_txdesc[cons];
1511
1512 if ((ctl & ADSTAT_Tx_ES) == 0)
1513 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1514 else {
1515 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1516 }
1517
1518 bus_dmamap_sync(sc->are_cdata.are_tx_tag, txd->tx_dmamap,
1519 BUS_DMASYNC_POSTWRITE);
1520 bus_dmamap_unload(sc->are_cdata.are_tx_tag, txd->tx_dmamap);
1521
1522 /* Free only if it's first descriptor in list */
1523 if (txd->tx_m)
1524 m_freem(txd->tx_m);
1525 txd->tx_m = NULL;
1526
1527 /* reset descriptor */
1528 cur_tx->are_stat = 0;
1529 cur_tx->are_devcs = 0;
1530 cur_tx->are_addr = 0;
1531 }
1532
1533 sc->are_cdata.are_tx_cons = cons;
1534
1535 bus_dmamap_sync(sc->are_cdata.are_tx_ring_tag,
1536 sc->are_cdata.are_tx_ring_map, BUS_DMASYNC_PREWRITE);
1537 }
1538
1539 static void
are_rx(struct are_softc * sc)1540 are_rx(struct are_softc *sc)
1541 {
1542 struct are_rxdesc *rxd;
1543 struct ifnet *ifp = sc->are_ifp;
1544 int cons, prog, packet_len, error;
1545 struct are_desc *cur_rx;
1546 struct mbuf *m;
1547
1548 ARE_LOCK_ASSERT(sc);
1549
1550 cons = sc->are_cdata.are_rx_cons;
1551
1552 bus_dmamap_sync(sc->are_cdata.are_rx_ring_tag,
1553 sc->are_cdata.are_rx_ring_map,
1554 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1555
1556 for (prog = 0; prog < ARE_RX_RING_CNT; ARE_INC(cons, ARE_RX_RING_CNT)) {
1557 cur_rx = &sc->are_rdata.are_rx_ring[cons];
1558 rxd = &sc->are_cdata.are_rxdesc[cons];
1559 m = rxd->rx_m;
1560
1561 if ((cur_rx->are_stat & ADSTAT_OWN) == ADSTAT_OWN)
1562 break;
1563
1564 prog++;
1565
1566 packet_len = ADSTAT_Rx_LENGTH(cur_rx->are_stat);
1567 /* Assume it's error */
1568 error = 1;
1569
1570 if (packet_len < 64)
1571 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1572 else if ((cur_rx->are_stat & ADSTAT_Rx_DE) == 0) {
1573 error = 0;
1574 bus_dmamap_sync(sc->are_cdata.are_rx_tag, rxd->rx_dmamap,
1575 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1576 m = rxd->rx_m;
1577 /* Skip 4 bytes of CRC */
1578 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
1579 are_fixup_rx(m);
1580 m->m_pkthdr.rcvif = ifp;
1581 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1582
1583 ARE_UNLOCK(sc);
1584 (*ifp->if_input)(ifp, m);
1585 ARE_LOCK(sc);
1586 }
1587
1588 if (error) {
1589 /* Restore CONTROL and CA values, reset DEVCS */
1590 cur_rx->are_stat = rxd->saved_ctl;
1591 cur_rx->are_addr = rxd->saved_ca;
1592 cur_rx->are_devcs = 0;
1593 }
1594 else {
1595 /* Reinit descriptor */
1596 cur_rx->are_stat = ADSTAT_OWN;
1597 cur_rx->are_devcs = 0;
1598 if (cons == ARE_RX_RING_CNT - 1)
1599 cur_rx->are_devcs |= ADCTL_ER;
1600 cur_rx->are_addr = 0;
1601 if (are_newbuf(sc, cons) != 0) {
1602 device_printf(sc->are_dev,
1603 "Failed to allocate buffer\n");
1604 break;
1605 }
1606 }
1607
1608 bus_dmamap_sync(sc->are_cdata.are_rx_ring_tag,
1609 sc->are_cdata.are_rx_ring_map,
1610 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1611 }
1612
1613 if (prog > 0) {
1614 sc->are_cdata.are_rx_cons = cons;
1615
1616 bus_dmamap_sync(sc->are_cdata.are_rx_ring_tag,
1617 sc->are_cdata.are_rx_ring_map,
1618 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1619 }
1620 }
1621
1622 static void
are_intr(void * arg)1623 are_intr(void *arg)
1624 {
1625 struct are_softc *sc = arg;
1626 uint32_t status;
1627 struct ifnet *ifp = sc->are_ifp;
1628
1629 ARE_LOCK(sc);
1630
1631 /* mask out interrupts */
1632
1633 status = CSR_READ_4(sc, CSR_STATUS);
1634 if (status) {
1635 CSR_WRITE_4(sc, CSR_STATUS, status);
1636 }
1637 if (status & sc->sc_rxint_mask) {
1638 are_rx(sc);
1639 }
1640 if (status & sc->sc_txint_mask) {
1641 are_tx(sc);
1642 }
1643
1644 /* Try to get more packets going. */
1645 are_start(ifp);
1646
1647 ARE_UNLOCK(sc);
1648 }
1649
1650 static void
are_tick(void * xsc)1651 are_tick(void *xsc)
1652 {
1653 #ifdef ARE_MII
1654 struct are_softc *sc = xsc;
1655 struct mii_data *mii;
1656
1657 ARE_LOCK_ASSERT(sc);
1658
1659 mii = device_get_softc(sc->are_miibus);
1660 mii_tick(mii);
1661 callout_reset(&sc->are_stat_callout, hz, are_tick, sc);
1662 #endif
1663 }
1664
1665 static void
are_hinted_child(device_t bus,const char * dname,int dunit)1666 are_hinted_child(device_t bus, const char *dname, int dunit)
1667 {
1668 BUS_ADD_CHILD(bus, 0, dname, dunit);
1669 device_printf(bus, "hinted child %s%d\n", dname, dunit);
1670 }
1671
1672 #ifdef ARE_MDIO
1673 static int
aremdio_probe(device_t dev)1674 aremdio_probe(device_t dev)
1675 {
1676 device_set_desc(dev, "Atheros AR531x built-in ethernet interface, MDIO controller");
1677 return(0);
1678 }
1679
1680 static int
aremdio_attach(device_t dev)1681 aremdio_attach(device_t dev)
1682 {
1683 struct are_softc *sc;
1684 int error = 0;
1685
1686 sc = device_get_softc(dev);
1687 sc->are_dev = dev;
1688 sc->are_rid = 0;
1689 sc->are_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1690 &sc->are_rid, RF_ACTIVE | RF_SHAREABLE);
1691 if (sc->are_res == NULL) {
1692 device_printf(dev, "couldn't map memory\n");
1693 error = ENXIO;
1694 goto fail;
1695 }
1696
1697 sc->are_btag = rman_get_bustag(sc->are_res);
1698 sc->are_bhandle = rman_get_bushandle(sc->are_res);
1699
1700 bus_generic_probe(dev);
1701 bus_enumerate_hinted_children(dev);
1702 error = bus_generic_attach(dev);
1703 fail:
1704 return (error);
1705 }
1706
1707 static int
aremdio_detach(device_t dev)1708 aremdio_detach(device_t dev)
1709 {
1710 return(0);
1711 }
1712 #endif
1713
1714 #ifdef ARE_DEBUG
1715 void
dump_txdesc(struct are_softc * sc,int pos)1716 dump_txdesc(struct are_softc *sc, int pos)
1717 {
1718 struct are_desc *desc;
1719
1720 desc = &sc->are_rdata.are_tx_ring[pos];
1721 device_printf(sc->are_dev, "CSR_TXLIST %08x\n", CSR_READ_4(sc, CSR_TXLIST));
1722 device_printf(sc->are_dev, "CSR_HTBA %08x\n", CSR_READ_4(sc, CSR_HTBA));
1723 device_printf(sc->are_dev, "%d TDES0:%08x TDES1:%08x TDES2:%08x TDES3:%08x\n",
1724 pos, desc->are_stat, desc->are_devcs, desc->are_addr, desc->are_link);
1725 }
1726
1727 void
dump_status_reg(struct are_softc * sc)1728 dump_status_reg(struct are_softc *sc)
1729 {
1730 uint32_t status;
1731
1732 /* mask out interrupts */
1733
1734 device_printf(sc->are_dev, "CSR_HTBA %08x\n", CSR_READ_4(sc, CSR_HTBA));
1735 status = CSR_READ_4(sc, CSR_STATUS);
1736 device_printf(sc->are_dev, "CSR5 Status Register EB:%d TS:%d RS:%d NIS:%d AIS:%d ER:%d SE:%d LNF:%d TM:%d RWT:%d RPS:%d RU:%d RI:%d UNF:%d LNP/ANC:%d TJT:%d TU:%d TPS:%d TI:%d\n",
1737 (status >> 23 ) & 7,
1738 (status >> 20 ) & 7,
1739 (status >> 17 ) & 7,
1740 (status >> 16 ) & 1,
1741 (status >> 15 ) & 1,
1742 (status >> 14 ) & 1,
1743 (status >> 13 ) & 1,
1744 (status >> 12 ) & 1,
1745 (status >> 11 ) & 1,
1746 (status >> 9 ) & 1,
1747 (status >> 8 ) & 1,
1748 (status >> 7 ) & 1,
1749 (status >> 6 ) & 1,
1750 (status >> 5 ) & 1,
1751 (status >> 4 ) & 1,
1752 (status >> 3 ) & 1,
1753 (status >> 2 ) & 1,
1754 (status >> 1 ) & 1,
1755 (status >> 0 ) & 1);
1756
1757 }
1758 #endif
1759