1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski
5 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver.
31 */
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 #ifdef HAVE_KERNEL_OPTION_HEADERS
36 #include "opt_device_polling.h"
37 #endif
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/bus.h>
42 #include <sys/endian.h>
43 #include <sys/mbuf.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49
50 #include <net/bpf.h>
51 #include <net/ethernet.h>
52 #include <net/if.h>
53 #include <net/if_var.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/if_vlan_var.h>
59
60 #include <netinet/in_systm.h>
61 #include <netinet/in.h>
62 #include <netinet/ip.h>
63
64 #include <machine/bus.h>
65
66 #include <dev/mii/mii.h>
67 #include <dev/mii/miivar.h>
68
69 #include <dev/tsec/if_tsec.h>
70 #include <dev/tsec/if_tsecreg.h>
71
72 static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag,
73 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr,
74 const char *dname);
75 static void tsec_dma_ctl(struct tsec_softc *sc, int state);
76 static void tsec_encap(struct ifnet *ifp, struct tsec_softc *sc,
77 struct mbuf *m0, uint16_t fcb_flags, int *start_tx);
78 static void tsec_free_dma(struct tsec_softc *sc);
79 static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr);
80 static int tsec_ifmedia_upd(struct ifnet *ifp);
81 static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
82 static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map,
83 struct mbuf **mbufp, uint32_t *paddr);
84 static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs,
85 int nseg, int error);
86 static void tsec_intrs_ctl(struct tsec_softc *sc, int state);
87 static void tsec_init(void *xsc);
88 static void tsec_init_locked(struct tsec_softc *sc);
89 static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
90 static void tsec_reset_mac(struct tsec_softc *sc);
91 static void tsec_setfilter(struct tsec_softc *sc);
92 static void tsec_set_mac_address(struct tsec_softc *sc);
93 static void tsec_start(struct ifnet *ifp);
94 static void tsec_start_locked(struct ifnet *ifp);
95 static void tsec_stop(struct tsec_softc *sc);
96 static void tsec_tick(void *arg);
97 static void tsec_watchdog(struct tsec_softc *sc);
98 static void tsec_add_sysctls(struct tsec_softc *sc);
99 static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS);
100 static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS);
101 static void tsec_set_rxic(struct tsec_softc *sc);
102 static void tsec_set_txic(struct tsec_softc *sc);
103 static int tsec_receive_intr_locked(struct tsec_softc *sc, int count);
104 static void tsec_transmit_intr_locked(struct tsec_softc *sc);
105 static void tsec_error_intr_locked(struct tsec_softc *sc, int count);
106 static void tsec_offload_setup(struct tsec_softc *sc);
107 static void tsec_offload_process_frame(struct tsec_softc *sc,
108 struct mbuf *m);
109 static void tsec_setup_multicast(struct tsec_softc *sc);
110 static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu);
111
112 devclass_t tsec_devclass;
113 DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0);
114 MODULE_DEPEND(tsec, ether, 1, 1, 1);
115 MODULE_DEPEND(tsec, miibus, 1, 1, 1);
116
117 struct mtx tsec_phy_mtx;
118
119 int
tsec_attach(struct tsec_softc * sc)120 tsec_attach(struct tsec_softc *sc)
121 {
122 uint8_t hwaddr[ETHER_ADDR_LEN];
123 struct ifnet *ifp;
124 int error = 0;
125 int i;
126
127 /* Initialize global (because potentially shared) MII lock */
128 if (!mtx_initialized(&tsec_phy_mtx))
129 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF);
130
131 /* Reset all TSEC counters */
132 TSEC_TX_RX_COUNTERS_INIT(sc);
133
134 /* Stop DMA engine if enabled by firmware */
135 tsec_dma_ctl(sc, 0);
136
137 /* Reset MAC */
138 tsec_reset_mac(sc);
139
140 /* Disable interrupts for now */
141 tsec_intrs_ctl(sc, 0);
142
143 /* Configure defaults for interrupts coalescing */
144 sc->rx_ic_time = 768;
145 sc->rx_ic_count = 16;
146 sc->tx_ic_time = 768;
147 sc->tx_ic_count = 16;
148 tsec_set_rxic(sc);
149 tsec_set_txic(sc);
150 tsec_add_sysctls(sc);
151
152 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */
153 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag,
154 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC,
155 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX");
156
157 if (error) {
158 tsec_detach(sc);
159 return (ENXIO);
160 }
161
162 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
163 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag,
164 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC,
165 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX");
166 if (error) {
167 tsec_detach(sc);
168 return (ENXIO);
169 }
170
171 /* Allocate a busdma tag for TX mbufs. */
172 error = bus_dma_tag_create(NULL, /* parent */
173 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
174 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
175 BUS_SPACE_MAXADDR, /* highaddr */
176 NULL, NULL, /* filtfunc, filtfuncarg */
177 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */
178 TSEC_TX_MAX_DMA_SEGS, /* nsegments */
179 MCLBYTES, 0, /* maxsegsz, flags */
180 NULL, NULL, /* lockfunc, lockfuncarg */
181 &sc->tsec_tx_mtag); /* dmat */
182 if (error) {
183 device_printf(sc->dev, "failed to allocate busdma tag "
184 "(tx mbufs)\n");
185 tsec_detach(sc);
186 return (ENXIO);
187 }
188
189 /* Allocate a busdma tag for RX mbufs. */
190 error = bus_dma_tag_create(NULL, /* parent */
191 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */
192 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
193 BUS_SPACE_MAXADDR, /* highaddr */
194 NULL, NULL, /* filtfunc, filtfuncarg */
195 MCLBYTES, /* maxsize */
196 1, /* nsegments */
197 MCLBYTES, 0, /* maxsegsz, flags */
198 NULL, NULL, /* lockfunc, lockfuncarg */
199 &sc->tsec_rx_mtag); /* dmat */
200 if (error) {
201 device_printf(sc->dev, "failed to allocate busdma tag "
202 "(rx mbufs)\n");
203 tsec_detach(sc);
204 return (ENXIO);
205 }
206
207 /* Create TX busdma maps */
208 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
209 error = bus_dmamap_create(sc->tsec_tx_mtag, 0,
210 &sc->tx_bufmap[i].map);
211 if (error) {
212 device_printf(sc->dev, "failed to init TX ring\n");
213 tsec_detach(sc);
214 return (ENXIO);
215 }
216 sc->tx_bufmap[i].map_initialized = 1;
217 }
218
219 /* Create RX busdma maps and zero mbuf handlers */
220 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
221 error = bus_dmamap_create(sc->tsec_rx_mtag, 0,
222 &sc->rx_data[i].map);
223 if (error) {
224 device_printf(sc->dev, "failed to init RX ring\n");
225 tsec_detach(sc);
226 return (ENXIO);
227 }
228 sc->rx_data[i].mbuf = NULL;
229 }
230
231 /* Create mbufs for RX buffers */
232 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
233 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map,
234 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr);
235 if (error) {
236 device_printf(sc->dev, "can't load rx DMA map %d, "
237 "error = %d\n", i, error);
238 tsec_detach(sc);
239 return (error);
240 }
241 }
242
243 /* Create network interface for upper layers */
244 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER);
245 if (ifp == NULL) {
246 device_printf(sc->dev, "if_alloc() failed\n");
247 tsec_detach(sc);
248 return (ENOMEM);
249 }
250
251 ifp->if_softc = sc;
252 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
253 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
254 ifp->if_init = tsec_init;
255 ifp->if_start = tsec_start;
256 ifp->if_ioctl = tsec_ioctl;
257
258 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
259 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
260 IFQ_SET_READY(&ifp->if_snd);
261
262 ifp->if_capabilities = IFCAP_VLAN_MTU;
263 if (sc->is_etsec)
264 ifp->if_capabilities |= IFCAP_HWCSUM;
265
266 ifp->if_capenable = ifp->if_capabilities;
267
268 #ifdef DEVICE_POLLING
269 /* Advertise that polling is supported */
270 ifp->if_capabilities |= IFCAP_POLLING;
271 #endif
272
273 /* Attach PHY(s) */
274 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd,
275 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
276 0);
277 if (error) {
278 device_printf(sc->dev, "attaching PHYs failed\n");
279 if_free(ifp);
280 sc->tsec_ifp = NULL;
281 tsec_detach(sc);
282 return (error);
283 }
284 sc->tsec_mii = device_get_softc(sc->tsec_miibus);
285
286 /* Set MAC address */
287 tsec_get_hwaddr(sc, hwaddr);
288 ether_ifattach(ifp, hwaddr);
289
290 return (0);
291 }
292
293 int
tsec_detach(struct tsec_softc * sc)294 tsec_detach(struct tsec_softc *sc)
295 {
296
297 if (sc->tsec_ifp != NULL) {
298 #ifdef DEVICE_POLLING
299 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING)
300 ether_poll_deregister(sc->tsec_ifp);
301 #endif
302
303 /* Stop TSEC controller and free TX queue */
304 if (sc->sc_rres)
305 tsec_shutdown(sc->dev);
306
307 /* Detach network interface */
308 ether_ifdetach(sc->tsec_ifp);
309 if_free(sc->tsec_ifp);
310 sc->tsec_ifp = NULL;
311 }
312
313 /* Free DMA resources */
314 tsec_free_dma(sc);
315
316 return (0);
317 }
318
319 int
tsec_shutdown(device_t dev)320 tsec_shutdown(device_t dev)
321 {
322 struct tsec_softc *sc;
323
324 sc = device_get_softc(dev);
325
326 TSEC_GLOBAL_LOCK(sc);
327 tsec_stop(sc);
328 TSEC_GLOBAL_UNLOCK(sc);
329 return (0);
330 }
331
332 int
tsec_suspend(device_t dev)333 tsec_suspend(device_t dev)
334 {
335
336 /* TODO not implemented! */
337 return (0);
338 }
339
340 int
tsec_resume(device_t dev)341 tsec_resume(device_t dev)
342 {
343
344 /* TODO not implemented! */
345 return (0);
346 }
347
348 static void
tsec_init(void * xsc)349 tsec_init(void *xsc)
350 {
351 struct tsec_softc *sc = xsc;
352
353 TSEC_GLOBAL_LOCK(sc);
354 tsec_init_locked(sc);
355 TSEC_GLOBAL_UNLOCK(sc);
356 }
357
358 static int
tsec_mii_wait(struct tsec_softc * sc,uint32_t flags)359 tsec_mii_wait(struct tsec_softc *sc, uint32_t flags)
360 {
361 int timeout;
362
363 /*
364 * The status indicators are not set immediatly after a command.
365 * Discard the first value.
366 */
367 TSEC_PHY_READ(sc, TSEC_REG_MIIMIND);
368
369 timeout = TSEC_READ_RETRY;
370 while ((TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & flags) && --timeout)
371 DELAY(TSEC_READ_DELAY);
372
373 return (timeout == 0);
374 }
375
376 static void
tsec_init_locked(struct tsec_softc * sc)377 tsec_init_locked(struct tsec_softc *sc)
378 {
379 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr;
380 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr;
381 struct ifnet *ifp = sc->tsec_ifp;
382 uint32_t val, i;
383 int timeout;
384
385 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
386 return;
387
388 TSEC_GLOBAL_LOCK_ASSERT(sc);
389 tsec_stop(sc);
390
391 /*
392 * These steps are according to the MPC8555E PowerQUICCIII RM:
393 * 14.7 Initialization/Application Information
394 */
395
396 /* Step 1: soft reset MAC */
397 tsec_reset_mac(sc);
398
399 /* Step 2: Initialize MACCFG2 */
400 TSEC_WRITE(sc, TSEC_REG_MACCFG2,
401 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */
402 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */
403 TSEC_MACCFG2_GMII | /* I/F Mode bit */
404 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */
405 );
406
407 /* Step 3: Initialize ECNTRL
408 * While the documentation states that R100M is ignored if RPM is
409 * not set, it does seem to be needed to get the orange boxes to
410 * work (which have a Marvell 88E1111 PHY). Go figure.
411 */
412
413 /*
414 * XXX kludge - use circumstancial evidence to program ECNTRL
415 * correctly. Ideally we need some board information to guide
416 * us here.
417 */
418 i = TSEC_READ(sc, TSEC_REG_ID2);
419 val = (i & 0xffff)
420 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */
421 : TSEC_ECNTRL_R100M; /* Orange + CDS */
422 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val);
423
424 /* Step 4: Initialize MAC station address */
425 tsec_set_mac_address(sc);
426
427 /*
428 * Step 5: Assign a Physical address to the TBI so as to not conflict
429 * with the external PHY physical address
430 */
431 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5);
432
433 TSEC_PHY_LOCK(sc);
434
435 /* Step 6: Reset the management interface */
436 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT);
437
438 /* Step 7: Setup the MII Mgmt clock speed */
439 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28);
440
441 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */
442 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
443
444 TSEC_PHY_UNLOCK(sc);
445 if (timeout) {
446 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n");
447 return;
448 }
449
450 /* Step 9: Setup the MII Mgmt */
451 mii_mediachg(sc->tsec_mii);
452
453 /* Step 10: Clear IEVENT register */
454 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff);
455
456 /* Step 11: Enable interrupts */
457 #ifdef DEVICE_POLLING
458 /*
459 * ...only if polling is not turned on. Disable interrupts explicitly
460 * if polling is enabled.
461 */
462 if (ifp->if_capenable & IFCAP_POLLING )
463 tsec_intrs_ctl(sc, 0);
464 else
465 #endif /* DEVICE_POLLING */
466 tsec_intrs_ctl(sc, 1);
467
468 /* Step 12: Initialize IADDRn */
469 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0);
470 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0);
471 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0);
472 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0);
473 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0);
474 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0);
475 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0);
476 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0);
477
478 /* Step 13: Initialize GADDRn */
479 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0);
480 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0);
481 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0);
482 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0);
483 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0);
484 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0);
485 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0);
486 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0);
487
488 /* Step 14: Initialize RCTRL */
489 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0);
490
491 /* Step 15: Initialize DMACTRL */
492 tsec_dma_ctl(sc, 1);
493
494 /* Step 16: Initialize FIFO_PAUSE_CTRL */
495 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN);
496
497 /*
498 * Step 17: Initialize transmit/receive descriptor rings.
499 * Initialize TBASE and RBASE.
500 */
501 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr);
502 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr);
503
504 for (i = 0; i < TSEC_TX_NUM_DESC; i++) {
505 tx_desc[i].bufptr = 0;
506 tx_desc[i].length = 0;
507 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ?
508 TSEC_TXBD_W : 0);
509 }
510 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
511 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
512
513 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
514 rx_desc[i].bufptr = sc->rx_data[i].paddr;
515 rx_desc[i].length = 0;
516 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I |
517 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0);
518 }
519 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
520 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
521
522 /* Step 18: Initialize the maximum receive buffer length */
523 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES);
524
525 /* Step 19: Configure ethernet frame sizes */
526 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE);
527 tsec_set_mtu(sc, ifp->if_mtu);
528
529 /* Step 20: Enable Rx and RxBD sdata snooping */
530 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN);
531 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0);
532
533 /* Step 21: Reset collision counters in hardware */
534 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
535 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
536 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
537 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
538 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
539
540 /* Step 22: Mask all CAM interrupts */
541 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff);
542 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff);
543
544 /* Step 23: Enable Rx and Tx */
545 val = TSEC_READ(sc, TSEC_REG_MACCFG1);
546 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
547 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val);
548
549 /* Step 24: Reset TSEC counters for Tx and Rx rings */
550 TSEC_TX_RX_COUNTERS_INIT(sc);
551
552 /* Step 25: Setup TCP/IP Off-Load engine */
553 if (sc->is_etsec)
554 tsec_offload_setup(sc);
555
556 /* Step 26: Setup multicast filters */
557 tsec_setup_multicast(sc);
558
559 /* Step 27: Activate network interface */
560 ifp->if_drv_flags |= IFF_DRV_RUNNING;
561 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
562 sc->tsec_if_flags = ifp->if_flags;
563 sc->tsec_watchdog = 0;
564
565 /* Schedule watchdog timeout */
566 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
567 }
568
569 static void
tsec_set_mac_address(struct tsec_softc * sc)570 tsec_set_mac_address(struct tsec_softc *sc)
571 {
572 uint32_t macbuf[2] = { 0, 0 };
573 char *macbufp, *curmac;
574 int i;
575
576 TSEC_GLOBAL_LOCK_ASSERT(sc);
577
578 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)),
579 ("tsec_set_mac_address: (%d <= %zd", ETHER_ADDR_LEN,
580 sizeof(macbuf)));
581
582 macbufp = (char *)macbuf;
583 curmac = (char *)IF_LLADDR(sc->tsec_ifp);
584
585 /* Correct order of MAC address bytes */
586 for (i = 1; i <= ETHER_ADDR_LEN; i++)
587 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1];
588
589 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */
590 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]);
591 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]);
592 }
593
594 /*
595 * DMA control function, if argument state is:
596 * 0 - DMA engine will be disabled
597 * 1 - DMA engine will be enabled
598 */
599 static void
tsec_dma_ctl(struct tsec_softc * sc,int state)600 tsec_dma_ctl(struct tsec_softc *sc, int state)
601 {
602 device_t dev;
603 uint32_t dma_flags, timeout;
604
605 dev = sc->dev;
606
607 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL);
608
609 switch (state) {
610 case 0:
611 /* Temporarily clear stop graceful stop bits. */
612 tsec_dma_ctl(sc, 1000);
613
614 /* Set it again */
615 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
616 break;
617 case 1000:
618 case 1:
619 /* Set write with response (WWR), wait (WOP) and snoop bits */
620 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN |
621 DMACTRL_WWR | DMACTRL_WOP);
622
623 /* Clear graceful stop bits */
624 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS);
625 break;
626 default:
627 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n",
628 state);
629 }
630
631 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags);
632
633 switch (state) {
634 case 0:
635 /* Wait for DMA stop */
636 timeout = TSEC_READ_RETRY;
637 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) &
638 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC))))
639 DELAY(TSEC_READ_DELAY);
640
641 if (timeout == 0)
642 device_printf(dev, "tsec_dma_ctl(): timeout!\n");
643 break;
644 case 1:
645 /* Restart transmission function */
646 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
647 }
648 }
649
650 /*
651 * Interrupts control function, if argument state is:
652 * 0 - all TSEC interrupts will be masked
653 * 1 - all TSEC interrupts will be unmasked
654 */
655 static void
tsec_intrs_ctl(struct tsec_softc * sc,int state)656 tsec_intrs_ctl(struct tsec_softc *sc, int state)
657 {
658 device_t dev;
659
660 dev = sc->dev;
661
662 switch (state) {
663 case 0:
664 TSEC_WRITE(sc, TSEC_REG_IMASK, 0);
665 break;
666 case 1:
667 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN |
668 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN |
669 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN |
670 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN);
671 break;
672 default:
673 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n",
674 state);
675 }
676 }
677
678 static void
tsec_reset_mac(struct tsec_softc * sc)679 tsec_reset_mac(struct tsec_softc *sc)
680 {
681 uint32_t maccfg1_flags;
682
683 /* Set soft reset bit */
684 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
685 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET;
686 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
687
688 /* Clear soft reset bit */
689 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1);
690 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET;
691 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags);
692 }
693
694 static void
tsec_watchdog(struct tsec_softc * sc)695 tsec_watchdog(struct tsec_softc *sc)
696 {
697 struct ifnet *ifp;
698
699 TSEC_GLOBAL_LOCK_ASSERT(sc);
700
701 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0)
702 return;
703
704 ifp = sc->tsec_ifp;
705 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
706 if_printf(ifp, "watchdog timeout\n");
707
708 tsec_stop(sc);
709 tsec_init_locked(sc);
710 }
711
712 static void
tsec_start(struct ifnet * ifp)713 tsec_start(struct ifnet *ifp)
714 {
715 struct tsec_softc *sc = ifp->if_softc;
716
717 TSEC_TRANSMIT_LOCK(sc);
718 tsec_start_locked(ifp);
719 TSEC_TRANSMIT_UNLOCK(sc);
720 }
721
722 static void
tsec_start_locked(struct ifnet * ifp)723 tsec_start_locked(struct ifnet *ifp)
724 {
725 struct tsec_softc *sc;
726 struct mbuf *m0;
727 struct tsec_tx_fcb *tx_fcb;
728 int csum_flags;
729 int start_tx;
730 uint16_t fcb_flags;
731
732 sc = ifp->if_softc;
733 start_tx = 0;
734
735 TSEC_TRANSMIT_LOCK_ASSERT(sc);
736
737 if (sc->tsec_link == 0)
738 return;
739
740 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
741 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
742
743 for (;;) {
744 if (TSEC_FREE_TX_DESC(sc) < TSEC_TX_MAX_DMA_SEGS) {
745 /* No free descriptors */
746 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
747 break;
748 }
749
750 /* Get packet from the queue */
751 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
752 if (m0 == NULL)
753 break;
754
755 /* Insert TCP/IP Off-load frame control block */
756 fcb_flags = 0;
757 csum_flags = m0->m_pkthdr.csum_flags;
758 if (csum_flags) {
759 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT);
760 if (m0 == NULL)
761 break;
762
763 if (csum_flags & CSUM_IP)
764 fcb_flags |= TSEC_TX_FCB_IP4 |
765 TSEC_TX_FCB_CSUM_IP;
766
767 if (csum_flags & CSUM_TCP)
768 fcb_flags |= TSEC_TX_FCB_TCP |
769 TSEC_TX_FCB_CSUM_TCP_UDP;
770
771 if (csum_flags & CSUM_UDP)
772 fcb_flags |= TSEC_TX_FCB_UDP |
773 TSEC_TX_FCB_CSUM_TCP_UDP;
774
775 tx_fcb = mtod(m0, struct tsec_tx_fcb *);
776 tx_fcb->flags = fcb_flags;
777 tx_fcb->l3_offset = ETHER_HDR_LEN;
778 tx_fcb->l4_offset = sizeof(struct ip);
779 }
780
781 tsec_encap(ifp, sc, m0, fcb_flags, &start_tx);
782 }
783 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
784 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
785
786 if (start_tx) {
787 /* Enable transmitter and watchdog timer */
788 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
789 sc->tsec_watchdog = 5;
790 }
791 }
792
793 static void
tsec_encap(struct ifnet * ifp,struct tsec_softc * sc,struct mbuf * m0,uint16_t fcb_flags,int * start_tx)794 tsec_encap(struct ifnet *ifp, struct tsec_softc *sc, struct mbuf *m0,
795 uint16_t fcb_flags, int *start_tx)
796 {
797 bus_dma_segment_t segs[TSEC_TX_MAX_DMA_SEGS];
798 int error, i, nsegs;
799 struct tsec_bufmap *tx_bufmap;
800 uint32_t tx_idx;
801 uint16_t flags;
802
803 TSEC_TRANSMIT_LOCK_ASSERT(sc);
804
805 tx_idx = sc->tx_idx_head;
806 tx_bufmap = &sc->tx_bufmap[tx_idx];
807
808 /* Create mapping in DMA memory */
809 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, tx_bufmap->map, m0,
810 segs, &nsegs, BUS_DMA_NOWAIT);
811 if (error == EFBIG) {
812 /* Too many segments! Defrag and try again. */
813 struct mbuf *m = m_defrag(m0, M_NOWAIT);
814
815 if (m == NULL) {
816 m_freem(m0);
817 return;
818 }
819 m0 = m;
820 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag,
821 tx_bufmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
822 }
823 if (error != 0) {
824 /* Give up. */
825 m_freem(m0);
826 return;
827 }
828
829 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
830 BUS_DMASYNC_PREWRITE);
831 tx_bufmap->mbuf = m0;
832
833 /*
834 * Fill in the TX descriptors back to front so that READY bit in first
835 * descriptor is set last.
836 */
837 tx_idx = (tx_idx + (uint32_t)nsegs) & (TSEC_TX_NUM_DESC - 1);
838 sc->tx_idx_head = tx_idx;
839 flags = TSEC_TXBD_L | TSEC_TXBD_I | TSEC_TXBD_R | TSEC_TXBD_TC;
840 for (i = nsegs - 1; i >= 0; i--) {
841 struct tsec_desc *tx_desc;
842
843 tx_idx = (tx_idx - 1) & (TSEC_TX_NUM_DESC - 1);
844 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
845 tx_desc->length = segs[i].ds_len;
846 tx_desc->bufptr = segs[i].ds_addr;
847
848 if (i == 0) {
849 wmb();
850
851 if (fcb_flags != 0)
852 flags |= TSEC_TXBD_TOE;
853 }
854
855 /*
856 * Set flags:
857 * - wrap
858 * - checksum
859 * - ready to send
860 * - transmit the CRC sequence after the last data byte
861 * - interrupt after the last buffer
862 */
863 tx_desc->flags = (tx_idx == (TSEC_TX_NUM_DESC - 1) ?
864 TSEC_TXBD_W : 0) | flags;
865
866 flags &= ~(TSEC_TXBD_L | TSEC_TXBD_I);
867 }
868
869 BPF_MTAP(ifp, m0);
870 *start_tx = 1;
871 }
872
873 static void
tsec_setfilter(struct tsec_softc * sc)874 tsec_setfilter(struct tsec_softc *sc)
875 {
876 struct ifnet *ifp;
877 uint32_t flags;
878
879 ifp = sc->tsec_ifp;
880 flags = TSEC_READ(sc, TSEC_REG_RCTRL);
881
882 /* Promiscuous mode */
883 if (ifp->if_flags & IFF_PROMISC)
884 flags |= TSEC_RCTRL_PROM;
885 else
886 flags &= ~TSEC_RCTRL_PROM;
887
888 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags);
889 }
890
891 #ifdef DEVICE_POLLING
892 static poll_handler_t tsec_poll;
893
894 static int
tsec_poll(struct ifnet * ifp,enum poll_cmd cmd,int count)895 tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
896 {
897 uint32_t ie;
898 struct tsec_softc *sc = ifp->if_softc;
899 int rx_npkts;
900
901 rx_npkts = 0;
902
903 TSEC_GLOBAL_LOCK(sc);
904 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
905 TSEC_GLOBAL_UNLOCK(sc);
906 return (rx_npkts);
907 }
908
909 if (cmd == POLL_AND_CHECK_STATUS) {
910 tsec_error_intr_locked(sc, count);
911
912 /* Clear all events reported */
913 ie = TSEC_READ(sc, TSEC_REG_IEVENT);
914 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie);
915 }
916
917 tsec_transmit_intr_locked(sc);
918
919 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc);
920
921 rx_npkts = tsec_receive_intr_locked(sc, count);
922
923 TSEC_RECEIVE_UNLOCK(sc);
924
925 return (rx_npkts);
926 }
927 #endif /* DEVICE_POLLING */
928
929 static int
tsec_ioctl(struct ifnet * ifp,u_long command,caddr_t data)930 tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
931 {
932 struct tsec_softc *sc = ifp->if_softc;
933 struct ifreq *ifr = (struct ifreq *)data;
934 int mask, error = 0;
935
936 switch (command) {
937 case SIOCSIFMTU:
938 TSEC_GLOBAL_LOCK(sc);
939 if (tsec_set_mtu(sc, ifr->ifr_mtu))
940 ifp->if_mtu = ifr->ifr_mtu;
941 else
942 error = EINVAL;
943 TSEC_GLOBAL_UNLOCK(sc);
944 break;
945 case SIOCSIFFLAGS:
946 TSEC_GLOBAL_LOCK(sc);
947 if (ifp->if_flags & IFF_UP) {
948 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
949 if ((sc->tsec_if_flags ^ ifp->if_flags) &
950 IFF_PROMISC)
951 tsec_setfilter(sc);
952
953 if ((sc->tsec_if_flags ^ ifp->if_flags) &
954 IFF_ALLMULTI)
955 tsec_setup_multicast(sc);
956 } else
957 tsec_init_locked(sc);
958 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
959 tsec_stop(sc);
960
961 sc->tsec_if_flags = ifp->if_flags;
962 TSEC_GLOBAL_UNLOCK(sc);
963 break;
964 case SIOCADDMULTI:
965 case SIOCDELMULTI:
966 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
967 TSEC_GLOBAL_LOCK(sc);
968 tsec_setup_multicast(sc);
969 TSEC_GLOBAL_UNLOCK(sc);
970 }
971 case SIOCGIFMEDIA:
972 case SIOCSIFMEDIA:
973 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media,
974 command);
975 break;
976 case SIOCSIFCAP:
977 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
978 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) {
979 TSEC_GLOBAL_LOCK(sc);
980 ifp->if_capenable &= ~IFCAP_HWCSUM;
981 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap;
982 tsec_offload_setup(sc);
983 TSEC_GLOBAL_UNLOCK(sc);
984 }
985 #ifdef DEVICE_POLLING
986 if (mask & IFCAP_POLLING) {
987 if (ifr->ifr_reqcap & IFCAP_POLLING) {
988 error = ether_poll_register(tsec_poll, ifp);
989 if (error)
990 return (error);
991
992 TSEC_GLOBAL_LOCK(sc);
993 /* Disable interrupts */
994 tsec_intrs_ctl(sc, 0);
995 ifp->if_capenable |= IFCAP_POLLING;
996 TSEC_GLOBAL_UNLOCK(sc);
997 } else {
998 error = ether_poll_deregister(ifp);
999 TSEC_GLOBAL_LOCK(sc);
1000 /* Enable interrupts */
1001 tsec_intrs_ctl(sc, 1);
1002 ifp->if_capenable &= ~IFCAP_POLLING;
1003 TSEC_GLOBAL_UNLOCK(sc);
1004 }
1005 }
1006 #endif
1007 break;
1008
1009 default:
1010 error = ether_ioctl(ifp, command, data);
1011 }
1012
1013 /* Flush buffers if not empty */
1014 if (ifp->if_flags & IFF_UP)
1015 tsec_start(ifp);
1016 return (error);
1017 }
1018
1019 static int
tsec_ifmedia_upd(struct ifnet * ifp)1020 tsec_ifmedia_upd(struct ifnet *ifp)
1021 {
1022 struct tsec_softc *sc = ifp->if_softc;
1023 struct mii_data *mii;
1024
1025 TSEC_TRANSMIT_LOCK(sc);
1026
1027 mii = sc->tsec_mii;
1028 mii_mediachg(mii);
1029
1030 TSEC_TRANSMIT_UNLOCK(sc);
1031 return (0);
1032 }
1033
1034 static void
tsec_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1035 tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1036 {
1037 struct tsec_softc *sc = ifp->if_softc;
1038 struct mii_data *mii;
1039
1040 TSEC_TRANSMIT_LOCK(sc);
1041
1042 mii = sc->tsec_mii;
1043 mii_pollstat(mii);
1044
1045 ifmr->ifm_active = mii->mii_media_active;
1046 ifmr->ifm_status = mii->mii_media_status;
1047
1048 TSEC_TRANSMIT_UNLOCK(sc);
1049 }
1050
1051 static int
tsec_new_rxbuf(bus_dma_tag_t tag,bus_dmamap_t map,struct mbuf ** mbufp,uint32_t * paddr)1052 tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp,
1053 uint32_t *paddr)
1054 {
1055 struct mbuf *new_mbuf;
1056 bus_dma_segment_t seg[1];
1057 int error, nsegs;
1058
1059 KASSERT(mbufp != NULL, ("NULL mbuf pointer!"));
1060
1061 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES);
1062 if (new_mbuf == NULL)
1063 return (ENOBUFS);
1064 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size;
1065
1066 if (*mbufp) {
1067 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD);
1068 bus_dmamap_unload(tag, map);
1069 }
1070
1071 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs,
1072 BUS_DMA_NOWAIT);
1073 KASSERT(nsegs == 1, ("Too many segments returned!"));
1074 if (nsegs != 1 || error)
1075 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error);
1076
1077 #if 0
1078 if (error) {
1079 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n",
1080 error);
1081 m_freem(new_mbuf);
1082 return (ENOBUFS);
1083 }
1084 #endif
1085
1086 #if 0
1087 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0,
1088 ("Wrong alignment of RX buffer!"));
1089 #endif
1090 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD);
1091
1092 (*mbufp) = new_mbuf;
1093 (*paddr) = seg->ds_addr;
1094 return (0);
1095 }
1096
1097 static void
tsec_map_dma_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)1098 tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1099 {
1100 u_int32_t *paddr;
1101
1102 KASSERT(nseg == 1, ("wrong number of segments, should be 1"));
1103 paddr = arg;
1104 *paddr = segs->ds_addr;
1105 }
1106
1107 static int
tsec_alloc_dma_desc(device_t dev,bus_dma_tag_t * dtag,bus_dmamap_t * dmap,bus_size_t dsize,void ** vaddr,void * raddr,const char * dname)1108 tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap,
1109 bus_size_t dsize, void **vaddr, void *raddr, const char *dname)
1110 {
1111 int error;
1112
1113 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1114 error = bus_dma_tag_create(NULL, /* parent */
1115 PAGE_SIZE, 0, /* alignment, boundary */
1116 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1117 BUS_SPACE_MAXADDR, /* highaddr */
1118 NULL, NULL, /* filtfunc, filtfuncarg */
1119 dsize, 1, /* maxsize, nsegments */
1120 dsize, 0, /* maxsegsz, flags */
1121 NULL, NULL, /* lockfunc, lockfuncarg */
1122 dtag); /* dmat */
1123
1124 if (error) {
1125 device_printf(dev, "failed to allocate busdma %s tag\n",
1126 dname);
1127 (*vaddr) = NULL;
1128 return (ENXIO);
1129 }
1130
1131 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1132 dmap);
1133 if (error) {
1134 device_printf(dev, "failed to allocate %s DMA safe memory\n",
1135 dname);
1136 bus_dma_tag_destroy(*dtag);
1137 (*vaddr) = NULL;
1138 return (ENXIO);
1139 }
1140
1141 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize,
1142 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT);
1143 if (error) {
1144 device_printf(dev, "cannot get address of the %s "
1145 "descriptors\n", dname);
1146 bus_dmamem_free(*dtag, *vaddr, *dmap);
1147 bus_dma_tag_destroy(*dtag);
1148 (*vaddr) = NULL;
1149 return (ENXIO);
1150 }
1151
1152 return (0);
1153 }
1154
1155 static void
tsec_free_dma_desc(bus_dma_tag_t dtag,bus_dmamap_t dmap,void * vaddr)1156 tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr)
1157 {
1158
1159 if (vaddr == NULL)
1160 return;
1161
1162 /* Unmap descriptors from DMA memory */
1163 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD |
1164 BUS_DMASYNC_POSTWRITE);
1165 bus_dmamap_unload(dtag, dmap);
1166
1167 /* Free descriptors memory */
1168 bus_dmamem_free(dtag, vaddr, dmap);
1169
1170 /* Destroy descriptors tag */
1171 bus_dma_tag_destroy(dtag);
1172 }
1173
1174 static void
tsec_free_dma(struct tsec_softc * sc)1175 tsec_free_dma(struct tsec_softc *sc)
1176 {
1177 int i;
1178
1179 /* Free TX maps */
1180 for (i = 0; i < TSEC_TX_NUM_DESC; i++)
1181 if (sc->tx_bufmap[i].map_initialized)
1182 bus_dmamap_destroy(sc->tsec_tx_mtag,
1183 sc->tx_bufmap[i].map);
1184 /* Destroy tag for TX mbufs */
1185 bus_dma_tag_destroy(sc->tsec_tx_mtag);
1186
1187 /* Free RX mbufs and maps */
1188 for (i = 0; i < TSEC_RX_NUM_DESC; i++) {
1189 if (sc->rx_data[i].mbuf) {
1190 /* Unload buffer from DMA */
1191 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map,
1192 BUS_DMASYNC_POSTREAD);
1193 bus_dmamap_unload(sc->tsec_rx_mtag,
1194 sc->rx_data[i].map);
1195
1196 /* Free buffer */
1197 m_freem(sc->rx_data[i].mbuf);
1198 }
1199 /* Destroy map for this buffer */
1200 if (sc->rx_data[i].map != NULL)
1201 bus_dmamap_destroy(sc->tsec_rx_mtag,
1202 sc->rx_data[i].map);
1203 }
1204 /* Destroy tag for RX mbufs */
1205 bus_dma_tag_destroy(sc->tsec_rx_mtag);
1206
1207 /* Unload TX/RX descriptors */
1208 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1209 sc->tsec_tx_vaddr);
1210 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1211 sc->tsec_rx_vaddr);
1212 }
1213
1214 static void
tsec_stop(struct tsec_softc * sc)1215 tsec_stop(struct tsec_softc *sc)
1216 {
1217 struct ifnet *ifp;
1218 uint32_t tmpval;
1219
1220 TSEC_GLOBAL_LOCK_ASSERT(sc);
1221
1222 ifp = sc->tsec_ifp;
1223
1224 /* Disable interface and watchdog timer */
1225 callout_stop(&sc->tsec_callout);
1226 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1227 sc->tsec_watchdog = 0;
1228
1229 /* Disable all interrupts and stop DMA */
1230 tsec_intrs_ctl(sc, 0);
1231 tsec_dma_ctl(sc, 0);
1232
1233 /* Remove pending data from TX queue */
1234 while (sc->tx_idx_tail != sc->tx_idx_head) {
1235 bus_dmamap_sync(sc->tsec_tx_mtag,
1236 sc->tx_bufmap[sc->tx_idx_tail].map,
1237 BUS_DMASYNC_POSTWRITE);
1238 bus_dmamap_unload(sc->tsec_tx_mtag,
1239 sc->tx_bufmap[sc->tx_idx_tail].map);
1240 m_freem(sc->tx_bufmap[sc->tx_idx_tail].mbuf);
1241 sc->tx_idx_tail = (sc->tx_idx_tail + 1)
1242 & (TSEC_TX_NUM_DESC - 1);
1243 }
1244
1245 /* Disable RX and TX */
1246 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1);
1247 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN);
1248 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval);
1249 DELAY(10);
1250 }
1251
1252 static void
tsec_tick(void * arg)1253 tsec_tick(void *arg)
1254 {
1255 struct tsec_softc *sc = arg;
1256 struct ifnet *ifp;
1257 int link;
1258
1259 TSEC_GLOBAL_LOCK(sc);
1260
1261 tsec_watchdog(sc);
1262
1263 ifp = sc->tsec_ifp;
1264 link = sc->tsec_link;
1265
1266 mii_tick(sc->tsec_mii);
1267
1268 if (link == 0 && sc->tsec_link == 1 &&
1269 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)))
1270 tsec_start_locked(ifp);
1271
1272 /* Schedule another timeout one second from now. */
1273 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc);
1274
1275 TSEC_GLOBAL_UNLOCK(sc);
1276 }
1277
1278 /*
1279 * This is the core RX routine. It replenishes mbufs in the descriptor and
1280 * sends data which have been dma'ed into host memory to upper layer.
1281 *
1282 * Loops at most count times if count is > 0, or until done if count < 0.
1283 */
1284 static int
tsec_receive_intr_locked(struct tsec_softc * sc,int count)1285 tsec_receive_intr_locked(struct tsec_softc *sc, int count)
1286 {
1287 struct tsec_desc *rx_desc;
1288 struct ifnet *ifp;
1289 struct rx_data_type *rx_data;
1290 struct mbuf *m;
1291 uint32_t i;
1292 int c, rx_npkts;
1293 uint16_t flags;
1294
1295 TSEC_RECEIVE_LOCK_ASSERT(sc);
1296
1297 ifp = sc->tsec_ifp;
1298 rx_data = sc->rx_data;
1299 rx_npkts = 0;
1300
1301 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1302 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1303
1304 for (c = 0; ; c++) {
1305 if (count >= 0 && count-- == 0)
1306 break;
1307
1308 rx_desc = TSEC_GET_CUR_RX_DESC(sc);
1309 flags = rx_desc->flags;
1310
1311 /* Check if there is anything to receive */
1312 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) {
1313 /*
1314 * Avoid generating another interrupt
1315 */
1316 if (flags & TSEC_RXBD_E)
1317 TSEC_WRITE(sc, TSEC_REG_IEVENT,
1318 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1319 /*
1320 * We didn't consume current descriptor and have to
1321 * return it to the queue
1322 */
1323 TSEC_BACK_CUR_RX_DESC(sc);
1324 break;
1325 }
1326
1327 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO |
1328 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) {
1329 rx_desc->length = 0;
1330 rx_desc->flags = (rx_desc->flags &
1331 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I;
1332
1333 if (sc->frame != NULL) {
1334 m_free(sc->frame);
1335 sc->frame = NULL;
1336 }
1337
1338 continue;
1339 }
1340
1341 /* Ok... process frame */
1342 i = TSEC_GET_CUR_RX_DESC_CNT(sc);
1343 m = rx_data[i].mbuf;
1344 m->m_len = rx_desc->length;
1345
1346 if (sc->frame != NULL) {
1347 if ((flags & TSEC_RXBD_L) != 0)
1348 m->m_len -= m_length(sc->frame, NULL);
1349
1350 m->m_flags &= ~M_PKTHDR;
1351 m_cat(sc->frame, m);
1352 } else {
1353 sc->frame = m;
1354 }
1355
1356 m = NULL;
1357
1358 if ((flags & TSEC_RXBD_L) != 0) {
1359 m = sc->frame;
1360 sc->frame = NULL;
1361 }
1362
1363 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map,
1364 &rx_data[i].mbuf, &rx_data[i].paddr)) {
1365 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1366 /*
1367 * We ran out of mbufs; didn't consume current
1368 * descriptor and have to return it to the queue.
1369 */
1370 TSEC_BACK_CUR_RX_DESC(sc);
1371 break;
1372 }
1373
1374 /* Attach new buffer to descriptor and clear flags */
1375 rx_desc->bufptr = rx_data[i].paddr;
1376 rx_desc->length = 0;
1377 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) |
1378 TSEC_RXBD_E | TSEC_RXBD_I;
1379
1380 if (m != NULL) {
1381 m->m_pkthdr.rcvif = ifp;
1382
1383 m_fixhdr(m);
1384 m_adj(m, -ETHER_CRC_LEN);
1385
1386 if (sc->is_etsec)
1387 tsec_offload_process_frame(sc, m);
1388
1389 TSEC_RECEIVE_UNLOCK(sc);
1390 (*ifp->if_input)(ifp, m);
1391 TSEC_RECEIVE_LOCK(sc);
1392 rx_npkts++;
1393 }
1394 }
1395
1396 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap,
1397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1398
1399 /*
1400 * Make sure TSEC receiver is not halted.
1401 *
1402 * Various conditions can stop the TSEC receiver, but not all are
1403 * signaled and handled by error interrupt, so make sure the receiver
1404 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when
1405 * halted, and is harmless if already running.
1406 */
1407 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT);
1408 return (rx_npkts);
1409 }
1410
1411 void
tsec_receive_intr(void * arg)1412 tsec_receive_intr(void *arg)
1413 {
1414 struct tsec_softc *sc = arg;
1415
1416 TSEC_RECEIVE_LOCK(sc);
1417
1418 #ifdef DEVICE_POLLING
1419 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1420 TSEC_RECEIVE_UNLOCK(sc);
1421 return;
1422 }
1423 #endif
1424
1425 /* Confirm the interrupt was received by driver */
1426 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF);
1427 tsec_receive_intr_locked(sc, -1);
1428
1429 TSEC_RECEIVE_UNLOCK(sc);
1430 }
1431
1432 static void
tsec_transmit_intr_locked(struct tsec_softc * sc)1433 tsec_transmit_intr_locked(struct tsec_softc *sc)
1434 {
1435 struct ifnet *ifp;
1436 uint32_t tx_idx;
1437
1438 TSEC_TRANSMIT_LOCK_ASSERT(sc);
1439
1440 ifp = sc->tsec_ifp;
1441
1442 /* Update collision statistics */
1443 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, TSEC_READ(sc, TSEC_REG_MON_TNCL));
1444
1445 /* Reset collision counters in hardware */
1446 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0);
1447 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0);
1448 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0);
1449 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0);
1450 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0);
1451
1452 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1453 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1454
1455 tx_idx = sc->tx_idx_tail;
1456 while (tx_idx != sc->tx_idx_head) {
1457 struct tsec_desc *tx_desc;
1458 struct tsec_bufmap *tx_bufmap;
1459
1460 tx_desc = &sc->tsec_tx_vaddr[tx_idx];
1461 if (tx_desc->flags & TSEC_TXBD_R) {
1462 break;
1463 }
1464
1465 tx_bufmap = &sc->tx_bufmap[tx_idx];
1466 tx_idx = (tx_idx + 1) & (TSEC_TX_NUM_DESC - 1);
1467 if (tx_bufmap->mbuf == NULL)
1468 continue;
1469
1470 /*
1471 * This is the last buf in this packet, so unmap and free it.
1472 */
1473 bus_dmamap_sync(sc->tsec_tx_mtag, tx_bufmap->map,
1474 BUS_DMASYNC_POSTWRITE);
1475 bus_dmamap_unload(sc->tsec_tx_mtag, tx_bufmap->map);
1476 m_freem(tx_bufmap->mbuf);
1477 tx_bufmap->mbuf = NULL;
1478
1479 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1480 }
1481 sc->tx_idx_tail = tx_idx;
1482 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap,
1483 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1484
1485 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1486 tsec_start_locked(ifp);
1487
1488 if (sc->tx_idx_tail == sc->tx_idx_head)
1489 sc->tsec_watchdog = 0;
1490 }
1491
1492 void
tsec_transmit_intr(void * arg)1493 tsec_transmit_intr(void *arg)
1494 {
1495 struct tsec_softc *sc = arg;
1496
1497 TSEC_TRANSMIT_LOCK(sc);
1498
1499 #ifdef DEVICE_POLLING
1500 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) {
1501 TSEC_TRANSMIT_UNLOCK(sc);
1502 return;
1503 }
1504 #endif
1505 /* Confirm the interrupt was received by driver */
1506 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF);
1507 tsec_transmit_intr_locked(sc);
1508
1509 TSEC_TRANSMIT_UNLOCK(sc);
1510 }
1511
1512 static void
tsec_error_intr_locked(struct tsec_softc * sc,int count)1513 tsec_error_intr_locked(struct tsec_softc *sc, int count)
1514 {
1515 struct ifnet *ifp;
1516 uint32_t eflags;
1517
1518 TSEC_GLOBAL_LOCK_ASSERT(sc);
1519
1520 ifp = sc->tsec_ifp;
1521
1522 eflags = TSEC_READ(sc, TSEC_REG_IEVENT);
1523
1524 /* Clear events bits in hardware */
1525 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY |
1526 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT |
1527 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC |
1528 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN);
1529
1530 /* Check transmitter errors */
1531 if (eflags & TSEC_IEVENT_TXE) {
1532 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1533
1534 if (eflags & TSEC_IEVENT_LC)
1535 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1536
1537 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT);
1538 }
1539
1540 /* Check for discarded frame due to a lack of buffers */
1541 if (eflags & TSEC_IEVENT_BSY) {
1542 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1543 }
1544
1545 if (ifp->if_flags & IFF_DEBUG)
1546 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n",
1547 eflags);
1548
1549 if (eflags & TSEC_IEVENT_EBERR) {
1550 if_printf(ifp, "System bus error occurred during"
1551 "DMA transaction (flags: 0x%x)\n", eflags);
1552 tsec_init_locked(sc);
1553 }
1554
1555 if (eflags & TSEC_IEVENT_BABT)
1556 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1557
1558 if (eflags & TSEC_IEVENT_BABR)
1559 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1560 }
1561
1562 void
tsec_error_intr(void * arg)1563 tsec_error_intr(void *arg)
1564 {
1565 struct tsec_softc *sc = arg;
1566
1567 TSEC_GLOBAL_LOCK(sc);
1568 tsec_error_intr_locked(sc, -1);
1569 TSEC_GLOBAL_UNLOCK(sc);
1570 }
1571
1572 int
tsec_miibus_readreg(device_t dev,int phy,int reg)1573 tsec_miibus_readreg(device_t dev, int phy, int reg)
1574 {
1575 struct tsec_softc *sc;
1576 int timeout;
1577 int rv;
1578
1579 sc = device_get_softc(dev);
1580
1581 TSEC_PHY_LOCK();
1582 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1583 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0);
1584 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE);
1585
1586 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY);
1587 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT);
1588 TSEC_PHY_UNLOCK();
1589
1590 if (timeout)
1591 device_printf(dev, "Timeout while reading from PHY!\n");
1592
1593 return (rv);
1594 }
1595
1596 int
tsec_miibus_writereg(device_t dev,int phy,int reg,int value)1597 tsec_miibus_writereg(device_t dev, int phy, int reg, int value)
1598 {
1599 struct tsec_softc *sc;
1600 int timeout;
1601
1602 sc = device_get_softc(dev);
1603
1604 TSEC_PHY_LOCK();
1605 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg);
1606 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value);
1607 timeout = tsec_mii_wait(sc, TSEC_MIIMIND_BUSY);
1608 TSEC_PHY_UNLOCK();
1609
1610 if (timeout)
1611 device_printf(dev, "Timeout while writing to PHY!\n");
1612
1613 return (0);
1614 }
1615
1616 void
tsec_miibus_statchg(device_t dev)1617 tsec_miibus_statchg(device_t dev)
1618 {
1619 struct tsec_softc *sc;
1620 struct mii_data *mii;
1621 uint32_t ecntrl, id, tmp;
1622 int link;
1623
1624 sc = device_get_softc(dev);
1625 mii = sc->tsec_mii;
1626 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0);
1627
1628 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF;
1629
1630 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
1631 tmp |= TSEC_MACCFG2_FULLDUPLEX;
1632 else
1633 tmp &= ~TSEC_MACCFG2_FULLDUPLEX;
1634
1635 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1636 case IFM_1000_T:
1637 case IFM_1000_SX:
1638 tmp |= TSEC_MACCFG2_GMII;
1639 sc->tsec_link = link;
1640 break;
1641 case IFM_100_TX:
1642 case IFM_10_T:
1643 tmp |= TSEC_MACCFG2_MII;
1644 sc->tsec_link = link;
1645 break;
1646 case IFM_NONE:
1647 if (link)
1648 device_printf(dev, "No speed selected but link "
1649 "active!\n");
1650 sc->tsec_link = 0;
1651 return;
1652 default:
1653 sc->tsec_link = 0;
1654 device_printf(dev, "Unknown speed (%d), link %s!\n",
1655 IFM_SUBTYPE(mii->mii_media_active),
1656 ((link) ? "up" : "down"));
1657 return;
1658 }
1659 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp);
1660
1661 /* XXX kludge - use circumstantial evidence for reduced mode. */
1662 id = TSEC_READ(sc, TSEC_REG_ID2);
1663 if (id & 0xffff) {
1664 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M;
1665 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0;
1666 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl);
1667 }
1668 }
1669
1670 static void
tsec_add_sysctls(struct tsec_softc * sc)1671 tsec_add_sysctls(struct tsec_softc *sc)
1672 {
1673 struct sysctl_ctx_list *ctx;
1674 struct sysctl_oid_list *children;
1675 struct sysctl_oid *tree;
1676
1677 ctx = device_get_sysctl_ctx(sc->dev);
1678 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
1679 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal",
1680 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "TSEC Interrupts coalescing");
1681 children = SYSCTL_CHILDREN(tree);
1682
1683 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time",
1684 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX,
1685 tsec_sysctl_ic_time, "I", "IC RX time threshold (0-65535)");
1686 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count",
1687 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_RX,
1688 tsec_sysctl_ic_count, "I", "IC RX frame count threshold (0-255)");
1689
1690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time",
1691 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX,
1692 tsec_sysctl_ic_time, "I", "IC TX time threshold (0-65535)");
1693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count",
1694 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, TSEC_IC_TX,
1695 tsec_sysctl_ic_count, "I", "IC TX frame count threshold (0-255)");
1696 }
1697
1698 /*
1699 * With Interrupt Coalescing (IC) active, a transmit/receive frame
1700 * interrupt is raised either upon:
1701 *
1702 * - threshold-defined period of time elapsed, or
1703 * - threshold-defined number of frames is received/transmitted,
1704 * whichever occurs first.
1705 *
1706 * The following sysctls regulate IC behaviour (for TX/RX separately):
1707 *
1708 * dev.tsec.<unit>.int_coal.rx_time
1709 * dev.tsec.<unit>.int_coal.rx_count
1710 * dev.tsec.<unit>.int_coal.tx_time
1711 * dev.tsec.<unit>.int_coal.tx_count
1712 *
1713 * Values:
1714 *
1715 * - 0 for either time or count disables IC on the given TX/RX path
1716 *
1717 * - count: 1-255 (expresses frame count number; note that value of 1 is
1718 * effectively IC off)
1719 *
1720 * - time: 1-65535 (value corresponds to a real time period and is
1721 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer
1722 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps,
1723 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the
1724 * TSEC reference manual.
1725 */
1726 static int
tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)1727 tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS)
1728 {
1729 int error;
1730 uint32_t time;
1731 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1732
1733 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time;
1734
1735 error = sysctl_handle_int(oidp, &time, 0, req);
1736 if (error != 0)
1737 return (error);
1738
1739 if (time > 65535)
1740 return (EINVAL);
1741
1742 TSEC_IC_LOCK(sc);
1743 if (arg2 == TSEC_IC_RX) {
1744 sc->rx_ic_time = time;
1745 tsec_set_rxic(sc);
1746 } else {
1747 sc->tx_ic_time = time;
1748 tsec_set_txic(sc);
1749 }
1750 TSEC_IC_UNLOCK(sc);
1751
1752 return (0);
1753 }
1754
1755 static int
tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)1756 tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS)
1757 {
1758 int error;
1759 uint32_t count;
1760 struct tsec_softc *sc = (struct tsec_softc *)arg1;
1761
1762 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count;
1763
1764 error = sysctl_handle_int(oidp, &count, 0, req);
1765 if (error != 0)
1766 return (error);
1767
1768 if (count > 255)
1769 return (EINVAL);
1770
1771 TSEC_IC_LOCK(sc);
1772 if (arg2 == TSEC_IC_RX) {
1773 sc->rx_ic_count = count;
1774 tsec_set_rxic(sc);
1775 } else {
1776 sc->tx_ic_count = count;
1777 tsec_set_txic(sc);
1778 }
1779 TSEC_IC_UNLOCK(sc);
1780
1781 return (0);
1782 }
1783
1784 static void
tsec_set_rxic(struct tsec_softc * sc)1785 tsec_set_rxic(struct tsec_softc *sc)
1786 {
1787 uint32_t rxic_val;
1788
1789 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0)
1790 /* Disable RX IC */
1791 rxic_val = 0;
1792 else {
1793 rxic_val = 0x80000000;
1794 rxic_val |= (sc->rx_ic_count << 21);
1795 rxic_val |= sc->rx_ic_time;
1796 }
1797
1798 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val);
1799 }
1800
1801 static void
tsec_set_txic(struct tsec_softc * sc)1802 tsec_set_txic(struct tsec_softc *sc)
1803 {
1804 uint32_t txic_val;
1805
1806 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0)
1807 /* Disable TX IC */
1808 txic_val = 0;
1809 else {
1810 txic_val = 0x80000000;
1811 txic_val |= (sc->tx_ic_count << 21);
1812 txic_val |= sc->tx_ic_time;
1813 }
1814
1815 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val);
1816 }
1817
1818 static void
tsec_offload_setup(struct tsec_softc * sc)1819 tsec_offload_setup(struct tsec_softc *sc)
1820 {
1821 struct ifnet *ifp = sc->tsec_ifp;
1822 uint32_t reg;
1823
1824 TSEC_GLOBAL_LOCK_ASSERT(sc);
1825
1826 reg = TSEC_READ(sc, TSEC_REG_TCTRL);
1827 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN;
1828
1829 if (ifp->if_capenable & IFCAP_TXCSUM)
1830 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES;
1831 else
1832 ifp->if_hwassist = 0;
1833
1834 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg);
1835
1836 reg = TSEC_READ(sc, TSEC_REG_RCTRL);
1837 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP);
1838 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX;
1839
1840 if (ifp->if_capenable & IFCAP_RXCSUM)
1841 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN |
1842 TSEC_RCTRL_PRSDEP_PARSE_L234;
1843
1844 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg);
1845 }
1846
1847 static void
tsec_offload_process_frame(struct tsec_softc * sc,struct mbuf * m)1848 tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m)
1849 {
1850 struct tsec_rx_fcb rx_fcb;
1851 int csum_flags = 0;
1852 int protocol, flags;
1853
1854 TSEC_RECEIVE_LOCK_ASSERT(sc);
1855
1856 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb));
1857 flags = rx_fcb.flags;
1858 protocol = rx_fcb.protocol;
1859
1860 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) {
1861 csum_flags |= CSUM_IP_CHECKED;
1862
1863 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0)
1864 csum_flags |= CSUM_IP_VALID;
1865 }
1866
1867 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) &&
1868 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) &&
1869 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) {
1870 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1871 m->m_pkthdr.csum_data = 0xFFFF;
1872 }
1873
1874 m->m_pkthdr.csum_flags = csum_flags;
1875
1876 if (flags & TSEC_RX_FCB_VLAN) {
1877 m->m_pkthdr.ether_vtag = rx_fcb.vlan;
1878 m->m_flags |= M_VLANTAG;
1879 }
1880
1881 m_adj(m, sizeof(struct tsec_rx_fcb));
1882 }
1883
1884 static u_int
tsec_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1885 tsec_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1886 {
1887 uint32_t h, *hashtable = arg;
1888
1889 h = (ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 24) & 0xFF;
1890 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F));
1891
1892 return (1);
1893 }
1894
1895 static void
tsec_setup_multicast(struct tsec_softc * sc)1896 tsec_setup_multicast(struct tsec_softc *sc)
1897 {
1898 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
1899 struct ifnet *ifp = sc->tsec_ifp;
1900 int i;
1901
1902 TSEC_GLOBAL_LOCK_ASSERT(sc);
1903
1904 if (ifp->if_flags & IFF_ALLMULTI) {
1905 for (i = 0; i < 8; i++)
1906 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF);
1907
1908 return;
1909 }
1910
1911 if_foreach_llmaddr(ifp, tsec_hash_maddr, &hashtable);
1912
1913 for (i = 0; i < 8; i++)
1914 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]);
1915 }
1916
1917 static int
tsec_set_mtu(struct tsec_softc * sc,unsigned int mtu)1918 tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu)
1919 {
1920
1921 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
1922
1923 TSEC_GLOBAL_LOCK_ASSERT(sc);
1924
1925 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) {
1926 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu);
1927 return (mtu);
1928 }
1929
1930 return (0);
1931 }
1932