1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Contact Information :
28 * Rajesh Kumar <[email protected]>
29 * Shreyank Amartya <[email protected]>
30 */
31
32 #include <sys/cdefs.h>
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/rman.h>
40 #include <sys/smp.h>
41 #include <sys/socket.h>
42 #include <sys/sysctl.h>
43 #include <sys/systm.h>
44
45 #include <net/if.h>
46 #include <net/if_media.h>
47
48 #include <dev/mii/mii.h>
49 #include <dev/mii/miivar.h>
50
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcivar.h>
53
54 #include "xgbe.h"
55 #include "xgbe-common.h"
56
57 #include "miibus_if.h"
58 #include "ifdi_if.h"
59 #include "opt_inet.h"
60 #include "opt_inet6.h"
61
62 MALLOC_DEFINE(M_AXGBE, "axgbe", "axgbe data");
63
64 extern struct if_txrx axgbe_txrx;
65 static int axgbe_sph_enable;
66
67 /* Function prototypes */
68 static void *axgbe_register(device_t);
69 static int axgbe_if_attach_pre(if_ctx_t);
70 static int axgbe_if_attach_post(if_ctx_t);
71 static int axgbe_if_detach(if_ctx_t);
72 static void axgbe_if_stop(if_ctx_t);
73 static void axgbe_if_init(if_ctx_t);
74
75 /* Queue related routines */
76 static int axgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
77 static int axgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
78 static int axgbe_alloc_channels(if_ctx_t);
79 static void axgbe_free_channels(struct axgbe_if_softc *);
80 static void axgbe_if_queues_free(if_ctx_t);
81 static int axgbe_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
82 static int axgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
83
84 /* Interrupt related routines */
85 static void axgbe_if_disable_intr(if_ctx_t);
86 static void axgbe_if_enable_intr(if_ctx_t);
87 static int axgbe_if_msix_intr_assign(if_ctx_t, int);
88 static void xgbe_free_intr(struct xgbe_prv_data *, struct resource *, void *, int);
89
90 /* Init and Iflib routines */
91 static void axgbe_pci_init(struct xgbe_prv_data *);
92 static void axgbe_pci_stop(if_ctx_t);
93 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *, struct xgbe_channel *);
94 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *);
95 static int axgbe_if_mtu_set(if_ctx_t, uint32_t);
96 static void axgbe_if_update_admin_status(if_ctx_t);
97 static void axgbe_if_media_status(if_ctx_t, struct ifmediareq *);
98 static int axgbe_if_media_change(if_ctx_t);
99 static int axgbe_if_promisc_set(if_ctx_t, int);
100 static uint64_t axgbe_if_get_counter(if_ctx_t, ift_counter);
101 static void axgbe_if_vlan_register(if_ctx_t, uint16_t);
102 static void axgbe_if_vlan_unregister(if_ctx_t, uint16_t);
103 #if __FreeBSD_version >= 1300000
104 static bool axgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event);
105 #endif
106 static void axgbe_set_counts(if_ctx_t);
107 static void axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *);
108
109 /* MII interface registered functions */
110 static int axgbe_miibus_readreg(device_t, int, int);
111 static int axgbe_miibus_writereg(device_t, int, int, int);
112 static void axgbe_miibus_statchg(device_t);
113
114 /* ISR routines */
115 static int axgbe_dev_isr(void *);
116 static void axgbe_ecc_isr(void *);
117 static void axgbe_i2c_isr(void *);
118 static void axgbe_an_isr(void *);
119 static int axgbe_msix_que(void *);
120
121 /* Timer routines */
122 static void xgbe_service(void *, int);
123 static void xgbe_service_timer(void *);
124 static void xgbe_init_timers(struct xgbe_prv_data *);
125 static void xgbe_stop_timers(struct xgbe_prv_data *);
126
127 /* Dump routines */
128 static void xgbe_dump_prop_registers(struct xgbe_prv_data *);
129
130 /*
131 * Allocate only for MAC (BAR0) and PCS (BAR1) registers, and just point the
132 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X
133 * table.
134 */
135 static struct resource_spec axgbe_pci_mac_spec[] = {
136 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* MAC regs */
137 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, /* PCS regs */
138 { -1, 0 }
139 };
140
141 static const pci_vendor_info_t axgbe_vendor_info_array[] =
142 {
143 PVID(0x1022, 0x1458, "AMD 10 Gigabit Ethernet Driver"),
144 PVID(0x1022, 0x1459, "AMD 10 Gigabit Ethernet Driver"),
145 PVID_END
146 };
147
148 static struct xgbe_version_data xgbe_v2a = {
149 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
150 .xpcs_access = XGBE_XPCS_ACCESS_V2,
151 .mmc_64bit = 1,
152 .tx_max_fifo_size = 229376,
153 .rx_max_fifo_size = 229376,
154 .tx_tstamp_workaround = 1,
155 .ecc_support = 1,
156 .i2c_support = 1,
157 .irq_reissue_support = 1,
158 .tx_desc_prefetch = 5,
159 .rx_desc_prefetch = 5,
160 .an_cdr_workaround = 1,
161 };
162
163 static struct xgbe_version_data xgbe_v2b = {
164 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
165 .xpcs_access = XGBE_XPCS_ACCESS_V2,
166 .mmc_64bit = 1,
167 .tx_max_fifo_size = 65536,
168 .rx_max_fifo_size = 65536,
169 .tx_tstamp_workaround = 1,
170 .ecc_support = 1,
171 .i2c_support = 1,
172 .irq_reissue_support = 1,
173 .tx_desc_prefetch = 5,
174 .rx_desc_prefetch = 5,
175 .an_cdr_workaround = 1,
176 };
177
178 /* Device Interface */
179 static device_method_t ax_methods[] = {
180 DEVMETHOD(device_register, axgbe_register),
181 DEVMETHOD(device_probe, iflib_device_probe),
182 DEVMETHOD(device_attach, iflib_device_attach),
183 DEVMETHOD(device_detach, iflib_device_detach),
184
185 /* MII interface */
186 DEVMETHOD(miibus_readreg, axgbe_miibus_readreg),
187 DEVMETHOD(miibus_writereg, axgbe_miibus_writereg),
188 DEVMETHOD(miibus_statchg, axgbe_miibus_statchg),
189
190 DEVMETHOD_END
191 };
192
193 static driver_t ax_driver = {
194 "ax", ax_methods, sizeof(struct axgbe_if_softc),
195 };
196
197 DRIVER_MODULE(axp, pci, ax_driver, 0, 0);
198 DRIVER_MODULE(miibus, ax, miibus_driver, 0, 0);
199 IFLIB_PNP_INFO(pci, ax_driver, axgbe_vendor_info_array);
200
201 MODULE_DEPEND(ax, pci, 1, 1, 1);
202 MODULE_DEPEND(ax, ether, 1, 1, 1);
203 MODULE_DEPEND(ax, iflib, 1, 1, 1);
204 MODULE_DEPEND(ax, miibus, 1, 1, 1);
205
206 /* Iflib Interface */
207 static device_method_t axgbe_if_methods[] = {
208 DEVMETHOD(ifdi_attach_pre, axgbe_if_attach_pre),
209 DEVMETHOD(ifdi_attach_post, axgbe_if_attach_post),
210 DEVMETHOD(ifdi_detach, axgbe_if_detach),
211 DEVMETHOD(ifdi_init, axgbe_if_init),
212 DEVMETHOD(ifdi_stop, axgbe_if_stop),
213 DEVMETHOD(ifdi_msix_intr_assign, axgbe_if_msix_intr_assign),
214 DEVMETHOD(ifdi_intr_enable, axgbe_if_enable_intr),
215 DEVMETHOD(ifdi_intr_disable, axgbe_if_disable_intr),
216 DEVMETHOD(ifdi_tx_queue_intr_enable, axgbe_if_tx_queue_intr_enable),
217 DEVMETHOD(ifdi_rx_queue_intr_enable, axgbe_if_rx_queue_intr_enable),
218 DEVMETHOD(ifdi_tx_queues_alloc, axgbe_if_tx_queues_alloc),
219 DEVMETHOD(ifdi_rx_queues_alloc, axgbe_if_rx_queues_alloc),
220 DEVMETHOD(ifdi_queues_free, axgbe_if_queues_free),
221 DEVMETHOD(ifdi_update_admin_status, axgbe_if_update_admin_status),
222 DEVMETHOD(ifdi_mtu_set, axgbe_if_mtu_set),
223 DEVMETHOD(ifdi_media_status, axgbe_if_media_status),
224 DEVMETHOD(ifdi_media_change, axgbe_if_media_change),
225 DEVMETHOD(ifdi_promisc_set, axgbe_if_promisc_set),
226 DEVMETHOD(ifdi_get_counter, axgbe_if_get_counter),
227 DEVMETHOD(ifdi_vlan_register, axgbe_if_vlan_register),
228 DEVMETHOD(ifdi_vlan_unregister, axgbe_if_vlan_unregister),
229 #if __FreeBSD_version >= 1300000
230 DEVMETHOD(ifdi_needs_restart, axgbe_if_needs_restart),
231 #endif
232 DEVMETHOD_END
233 };
234
235 static driver_t axgbe_if_driver = {
236 "axgbe_if", axgbe_if_methods, sizeof(struct axgbe_if_softc)
237 };
238
239 /* Iflib Shared Context */
240 static struct if_shared_ctx axgbe_sctx_init = {
241 .isc_magic = IFLIB_MAGIC,
242 .isc_driver = &axgbe_if_driver,
243 .isc_q_align = PAGE_SIZE,
244 .isc_tx_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
245 .isc_tx_maxsegsize = PAGE_SIZE,
246 .isc_tso_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
247 .isc_tso_maxsegsize = PAGE_SIZE,
248 .isc_rx_maxsize = MJUM9BYTES,
249 .isc_rx_maxsegsize = MJUM9BYTES,
250 .isc_rx_nsegments = 1,
251 .isc_admin_intrcnt = 4,
252
253 .isc_vendor_info = axgbe_vendor_info_array,
254 .isc_driver_version = XGBE_DRV_VERSION,
255
256 .isc_ntxd_min = {XGBE_TX_DESC_CNT_MIN},
257 .isc_ntxd_default = {XGBE_TX_DESC_CNT_DEFAULT},
258 .isc_ntxd_max = {XGBE_TX_DESC_CNT_MAX},
259
260 .isc_ntxqs = 1,
261 .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_SCRATCH |
262 IFLIB_NEED_ZERO_CSUM | IFLIB_NEED_ETHER_PAD,
263 };
264
265 static void *
axgbe_register(device_t dev)266 axgbe_register(device_t dev)
267 {
268 int axgbe_nfl;
269 int axgbe_nrxqs;
270 int error, i;
271 char *value = NULL;
272
273 value = kern_getenv("dev.ax.sph_enable");
274 if (value) {
275 axgbe_sph_enable = strtol(value, NULL, 10);
276 freeenv(value);
277 } else {
278 /*
279 * No tunable found, generate one with default values
280 * Note: only a reboot will reveal the new kenv
281 */
282 error = kern_setenv("dev.ax.sph_enable", "1");
283 if (error) {
284 printf("Error setting tunable, using default driver values\n");
285 }
286 axgbe_sph_enable = 1;
287 }
288
289 if (!axgbe_sph_enable) {
290 axgbe_nfl = 1;
291 axgbe_nrxqs = 1;
292 } else {
293 axgbe_nfl = 2;
294 axgbe_nrxqs = 2;
295 }
296
297 axgbe_sctx_init.isc_nfl = axgbe_nfl;
298 axgbe_sctx_init.isc_nrxqs = axgbe_nrxqs;
299
300 for (i = 0 ; i < axgbe_nrxqs ; i++) {
301 axgbe_sctx_init.isc_nrxd_min[i] = XGBE_RX_DESC_CNT_MIN;
302 axgbe_sctx_init.isc_nrxd_default[i] = XGBE_RX_DESC_CNT_DEFAULT;
303 axgbe_sctx_init.isc_nrxd_max[i] = XGBE_RX_DESC_CNT_MAX;
304 }
305
306 return (&axgbe_sctx_init);
307 }
308
309 /* MII Interface Functions */
310 static int
axgbe_miibus_readreg(device_t dev,int phy,int reg)311 axgbe_miibus_readreg(device_t dev, int phy, int reg)
312 {
313 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
314 struct xgbe_prv_data *pdata = &sc->pdata;
315 int val;
316
317 axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg);
318
319 val = xgbe_phy_mii_read(pdata, phy, reg);
320
321 axgbe_printf(2, "%s: val 0x%x\n", __func__, val);
322 return (val & 0xFFFF);
323 }
324
325 static int
axgbe_miibus_writereg(device_t dev,int phy,int reg,int val)326 axgbe_miibus_writereg(device_t dev, int phy, int reg, int val)
327 {
328 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
329 struct xgbe_prv_data *pdata = &sc->pdata;
330
331 axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val);
332
333 xgbe_phy_mii_write(pdata, phy, reg, val);
334
335 return(0);
336 }
337
338 static void
axgbe_miibus_statchg(device_t dev)339 axgbe_miibus_statchg(device_t dev)
340 {
341 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
342 struct xgbe_prv_data *pdata = &sc->pdata;
343 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus);
344 if_t ifp = pdata->netdev;
345 int bmsr;
346
347 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link,
348 pdata->phy_link);
349
350 if (mii == NULL || ifp == NULL ||
351 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
352 return;
353
354 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
355 (IFM_ACTIVE | IFM_AVALID)) {
356
357 switch (IFM_SUBTYPE(mii->mii_media_active)) {
358 case IFM_10_T:
359 case IFM_100_TX:
360 pdata->phy.link = 1;
361 break;
362 case IFM_1000_T:
363 case IFM_1000_SX:
364 case IFM_2500_SX:
365 pdata->phy.link = 1;
366 break;
367 default:
368 pdata->phy.link = 0;
369 break;
370 }
371 } else
372 pdata->phy_link = 0;
373
374 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR);
375 if (bmsr & BMSR_ANEG) {
376
377 axgbe_printf(2, "%s: Autoneg Done\n", __func__);
378
379 /* Raise AN Interrupt */
380 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK,
381 XGBE_AN_CL73_INT_MASK);
382 }
383 }
384
385 static int
axgbe_if_attach_pre(if_ctx_t ctx)386 axgbe_if_attach_pre(if_ctx_t ctx)
387 {
388 struct axgbe_if_softc *sc;
389 struct xgbe_prv_data *pdata;
390 struct resource *mac_res[2];
391 if_softc_ctx_t scctx;
392 if_shared_ctx_t sctx;
393 device_t dev;
394 unsigned int ma_lo, ma_hi;
395 unsigned int reg;
396 int ret;
397
398 sc = iflib_get_softc(ctx);
399 sc->pdata.dev = dev = iflib_get_dev(ctx);
400 sc->sctx = sctx = iflib_get_sctx(ctx);
401 sc->scctx = scctx = iflib_get_softc_ctx(ctx);
402 sc->media = iflib_get_media(ctx);
403 sc->ctx = ctx;
404 sc->link_status = LINK_STATE_DOWN;
405 pdata = &sc->pdata;
406 pdata->netdev = iflib_get_ifp(ctx);
407
408 spin_lock_init(&pdata->xpcs_lock);
409
410 /* Initialize locks */
411 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF);
412 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN);
413
414 /* Allocate VLAN bitmap */
415 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO);
416 pdata->num_active_vlans = 0;
417
418 /* Get the version data */
419 DBGPR("%s: Device ID: 0x%x\n", __func__, pci_get_device(dev));
420 if (pci_get_device(dev) == 0x1458)
421 sc->pdata.vdata = &xgbe_v2a;
422 else if (pci_get_device(dev) == 0x1459)
423 sc->pdata.vdata = &xgbe_v2b;
424
425 /* PCI setup */
426 if (bus_alloc_resources(dev, axgbe_pci_mac_spec, mac_res)) {
427 axgbe_error("Unable to allocate bus resources\n");
428 ret = ENXIO;
429 goto free_vlans;
430 }
431
432 sc->pdata.xgmac_res = mac_res[0];
433 sc->pdata.xpcs_res = mac_res[1];
434
435 /* Set the PCS indirect addressing definition registers*/
436 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
437 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
438
439 /* Configure the PCS indirect addressing support */
440 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
441 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
442 pdata->xpcs_window <<= 6;
443 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
444 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
445 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
446 DBGPR("xpcs window def : %#010x\n",
447 pdata->xpcs_window_def_reg);
448 DBGPR("xpcs window sel : %#010x\n",
449 pdata->xpcs_window_sel_reg);
450 DBGPR("xpcs window : %#010x\n",
451 pdata->xpcs_window);
452 DBGPR("xpcs window size : %#010x\n",
453 pdata->xpcs_window_size);
454 DBGPR("xpcs window mask : %#010x\n",
455 pdata->xpcs_window_mask);
456
457 /* Enable all interrupts in the hardware */
458 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
459
460 /* Retrieve the MAC address */
461 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
462 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
463 pdata->mac_addr[0] = ma_lo & 0xff;
464 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
465 pdata->mac_addr[2] = (ma_lo >>16) & 0xff;
466 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
467 pdata->mac_addr[4] = ma_hi & 0xff;
468 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
469 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID)) {
470 axgbe_error("Invalid mac address\n");
471 ret = EINVAL;
472 goto release_bus_resource;
473 }
474 iflib_set_mac(ctx, pdata->mac_addr);
475
476 /* Clock settings */
477 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
478 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
479
480 /* Set the DMA coherency values */
481 pdata->coherent = 1;
482 pdata->arcr = XGBE_DMA_PCI_ARCR;
483 pdata->awcr = XGBE_DMA_PCI_AWCR;
484 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
485
486 /* Read the port property registers */
487 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
488 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
489 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
490 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
491 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
492 DBGPR("port property 0 = %#010x\n", pdata->pp0);
493 DBGPR("port property 1 = %#010x\n", pdata->pp1);
494 DBGPR("port property 2 = %#010x\n", pdata->pp2);
495 DBGPR("port property 3 = %#010x\n", pdata->pp3);
496 DBGPR("port property 4 = %#010x\n", pdata->pp4);
497
498 /* Set the maximum channels and queues */
499 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
500 MAX_TX_DMA);
501 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
502 MAX_RX_DMA);
503 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
504 MAX_TX_QUEUES);
505 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
506 MAX_RX_QUEUES);
507 DBGPR("max tx/rx channel count = %u/%u\n",
508 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
509 DBGPR("max tx/rx hw queue count = %u/%u\n",
510 pdata->tx_max_q_count, pdata->rx_max_q_count);
511
512 axgbe_set_counts(ctx);
513
514 /* Set the maximum fifo amounts */
515 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
516 TX_FIFO_SIZE);
517 pdata->tx_max_fifo_size *= 16384;
518 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
519 pdata->vdata->tx_max_fifo_size);
520 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
521 RX_FIFO_SIZE);
522 pdata->rx_max_fifo_size *= 16384;
523 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
524 pdata->vdata->rx_max_fifo_size);
525 DBGPR("max tx/rx max fifo size = %u/%u\n",
526 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
527
528 /* Initialize IFLIB if_softc_ctx_t */
529 axgbe_init_iflib_softc_ctx(sc);
530
531 /* Alloc channels */
532 if (axgbe_alloc_channels(ctx)) {
533 axgbe_error("Unable to allocate channel memory\n");
534 ret = ENOMEM;
535 goto release_bus_resource;
536 }
537
538 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
539
540 /* create the workqueue */
541 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK,
542 taskqueue_thread_enqueue, &pdata->dev_workqueue);
543 ret = taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET,
544 "axgbe dev taskq");
545 if (ret) {
546 axgbe_error("Unable to start taskqueue\n");
547 ret = ENOMEM;
548 goto free_task_queue;
549 }
550
551 /* Init timers */
552 xgbe_init_timers(pdata);
553
554 return (0);
555
556 free_task_queue:
557 taskqueue_free(pdata->dev_workqueue);
558 axgbe_free_channels(sc);
559
560 release_bus_resource:
561 bus_release_resources(dev, axgbe_pci_mac_spec, mac_res);
562
563 free_vlans:
564 free(pdata->active_vlans, M_AXGBE);
565
566 return (ret);
567 } /* axgbe_if_attach_pre */
568
569 static void
xgbe_init_all_fptrs(struct xgbe_prv_data * pdata)570 xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
571 {
572 xgbe_init_function_ptrs_dev(&pdata->hw_if);
573 xgbe_init_function_ptrs_phy(&pdata->phy_if);
574 xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
575 xgbe_init_function_ptrs_desc(&pdata->desc_if);
576
577 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
578 }
579
580 static void
axgbe_set_counts(if_ctx_t ctx)581 axgbe_set_counts(if_ctx_t ctx)
582 {
583 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
584 struct xgbe_prv_data *pdata = &sc->pdata;
585 cpuset_t lcpus;
586
587 /* Set all function pointers */
588 xgbe_init_all_fptrs(pdata);
589
590 /* Populate the hardware features */
591 xgbe_get_all_hw_features(pdata);
592
593 if (!pdata->tx_max_channel_count)
594 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
595 if (!pdata->rx_max_channel_count)
596 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
597
598 if (!pdata->tx_max_q_count)
599 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
600 if (!pdata->rx_max_q_count)
601 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
602
603 /*
604 * Calculate the number of Tx and Rx rings to be created
605 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
606 * the number of Tx queues to the number of Tx channels
607 * enabled
608 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
609 * number of Rx queues or maximum allowed
610 */
611
612 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) {
613 axgbe_error("Unable to fetch CPU list\n");
614 /* TODO - handle CPU_COPY(&all_cpus, &lcpus); */
615 }
616
617 DBGPR("ncpu %d intrcpu %d\n", mp_ncpus, CPU_COUNT(&lcpus));
618
619 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt);
620 pdata->tx_ring_count = min(pdata->tx_ring_count,
621 pdata->tx_max_channel_count);
622 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count);
623
624 pdata->tx_q_count = pdata->tx_ring_count;
625
626 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt);
627 pdata->rx_ring_count = min(pdata->rx_ring_count,
628 pdata->rx_max_channel_count);
629
630 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count);
631
632 DBGPR("TX/RX max channel count = %u/%u\n",
633 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
634 DBGPR("TX/RX max queue count = %u/%u\n",
635 pdata->tx_max_q_count, pdata->rx_max_q_count);
636 DBGPR("TX/RX DMA ring count = %u/%u\n",
637 pdata->tx_ring_count, pdata->rx_ring_count);
638 DBGPR("TX/RX hardware queue count = %u/%u\n",
639 pdata->tx_q_count, pdata->rx_q_count);
640 } /* axgbe_set_counts */
641
642 static void
axgbe_init_iflib_softc_ctx(struct axgbe_if_softc * sc)643 axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *sc)
644 {
645 struct xgbe_prv_data *pdata = &sc->pdata;
646 if_softc_ctx_t scctx = sc->scctx;
647 if_shared_ctx_t sctx = sc->sctx;
648 int i;
649
650 scctx->isc_nrxqsets = pdata->rx_q_count;
651 scctx->isc_ntxqsets = pdata->tx_q_count;
652 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev);
653 scctx->isc_tx_nsegments = 32;
654
655 for (i = 0; i < sctx->isc_ntxqs; i++) {
656 scctx->isc_txqsizes[i] =
657 roundup2(scctx->isc_ntxd[i] * sizeof(struct xgbe_ring_desc),
658 128);
659 scctx->isc_txd_size[i] = sizeof(struct xgbe_ring_desc);
660 }
661
662 for (i = 0; i < sctx->isc_nrxqs; i++) {
663 scctx->isc_rxqsizes[i] =
664 roundup2(scctx->isc_nrxd[i] * sizeof(struct xgbe_ring_desc),
665 128);
666 scctx->isc_rxd_size[i] = sizeof(struct xgbe_ring_desc);
667 }
668
669 scctx->isc_tx_tso_segments_max = 32;
670 scctx->isc_tx_tso_size_max = XGBE_TSO_MAX_SIZE;
671 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
672
673 /*
674 * Set capabilities
675 * 1) IFLIB automatically adds IFCAP_HWSTATS, so need to set explicitly
676 * 2) isc_tx_csum_flags is mandatory if IFCAP_TXCSUM (included in
677 * IFCAP_HWCSUM) is set
678 */
679 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP |
680 CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_SCTP_IPV6 |
681 CSUM_TSO);
682 scctx->isc_capenable = (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
683 IFCAP_JUMBO_MTU |
684 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER |
685 IFCAP_VLAN_HWCSUM |
686 IFCAP_TSO | IFCAP_VLAN_HWTSO);
687 scctx->isc_capabilities = scctx->isc_capenable;
688
689 /*
690 * Set rss_table_size alone when adding RSS support. rss_table_mask
691 * will be set by IFLIB based on rss_table_size
692 */
693 scctx->isc_rss_table_size = XGBE_RSS_MAX_TABLE_SIZE;
694
695 scctx->isc_ntxqsets_max = XGBE_MAX_QUEUES;
696 scctx->isc_nrxqsets_max = XGBE_MAX_QUEUES;
697
698 scctx->isc_txrx = &axgbe_txrx;
699 }
700
701 static int
axgbe_alloc_channels(if_ctx_t ctx)702 axgbe_alloc_channels(if_ctx_t ctx)
703 {
704 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
705 struct xgbe_prv_data *pdata = &sc->pdata;
706 struct xgbe_channel *channel;
707 int i, j, count;
708
709 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count,
710 pdata->rx_ring_count);
711
712 /* Iflibe sets based on isc_ntxqsets/nrxqsets */
713 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
714
715 /* Allocate channel memory */
716 for (i = 0; i < count ; i++) {
717 channel = (struct xgbe_channel*)malloc(sizeof(struct xgbe_channel),
718 M_AXGBE, M_NOWAIT | M_ZERO);
719
720 if (channel == NULL) {
721 for (j = 0; j < i; j++) {
722 free(pdata->channel[j], M_AXGBE);
723 pdata->channel[j] = NULL;
724 }
725 return (ENOMEM);
726 }
727
728 pdata->channel[i] = channel;
729 }
730
731 pdata->total_channel_count = count;
732 DBGPR("Channel count set to: %u\n", pdata->total_channel_count);
733
734 for (i = 0; i < count; i++) {
735
736 channel = pdata->channel[i];
737 snprintf(channel->name, sizeof(channel->name), "channel-%d",i);
738
739 channel->pdata = pdata;
740 channel->queue_index = i;
741 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
742 bus_space_subregion(channel->dma_tag,
743 rman_get_bushandle(pdata->xgmac_res),
744 DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC,
745 &channel->dma_handle);
746 channel->tx_ring = NULL;
747 channel->rx_ring = NULL;
748 }
749
750 return (0);
751 } /* axgbe_alloc_channels */
752
753 static void
axgbe_free_channels(struct axgbe_if_softc * sc)754 axgbe_free_channels(struct axgbe_if_softc *sc)
755 {
756 struct xgbe_prv_data *pdata = &sc->pdata;
757 int i;
758
759 for (i = 0; i < pdata->total_channel_count ; i++) {
760 free(pdata->channel[i], M_AXGBE);
761 pdata->channel[i] = NULL;
762 }
763
764 pdata->total_channel_count = 0;
765 pdata->channel_count = 0;
766 }
767
768 static void
xgbe_service(void * ctx,int pending)769 xgbe_service(void *ctx, int pending)
770 {
771 struct xgbe_prv_data *pdata = ctx;
772 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)pdata;
773 bool prev_state = false;
774
775 /* Get previous link status */
776 prev_state = pdata->phy.link;
777
778 pdata->phy_if.phy_status(pdata);
779
780 if (prev_state != pdata->phy.link) {
781 pdata->phy_link = pdata->phy.link;
782 axgbe_if_update_admin_status(sc->ctx);
783 }
784
785 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
786 }
787
788 static void
xgbe_service_timer(void * data)789 xgbe_service_timer(void *data)
790 {
791 struct xgbe_prv_data *pdata = data;
792
793 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
794 }
795
796 static void
xgbe_init_timers(struct xgbe_prv_data * pdata)797 xgbe_init_timers(struct xgbe_prv_data *pdata)
798 {
799 callout_init(&pdata->service_timer, 1);
800 }
801
802 static void
xgbe_start_timers(struct xgbe_prv_data * pdata)803 xgbe_start_timers(struct xgbe_prv_data *pdata)
804 {
805 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
806 }
807
808 static void
xgbe_stop_timers(struct xgbe_prv_data * pdata)809 xgbe_stop_timers(struct xgbe_prv_data *pdata)
810 {
811 callout_drain(&pdata->service_timer);
812 callout_stop(&pdata->service_timer);
813 }
814
815 static void
xgbe_dump_phy_registers(struct xgbe_prv_data * pdata)816 xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
817 {
818 axgbe_printf(1, "\n************* PHY Reg dump *********************\n");
819
820 axgbe_printf(1, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
821 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
822 axgbe_printf(1, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
823 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
824 axgbe_printf(1, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
825 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
826 axgbe_printf(1, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
827 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
828 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
829 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
830 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
831 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
832 axgbe_printf(1, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
833 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
834 axgbe_printf(1, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
835 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
836 axgbe_printf(1, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
837 MDIO_AN_ADVERTISE,
838 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
839 axgbe_printf(1, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
840 MDIO_AN_ADVERTISE + 1,
841 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
842 axgbe_printf(1, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
843 MDIO_AN_ADVERTISE + 2,
844 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
845 axgbe_printf(1, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
846 MDIO_AN_COMP_STAT,
847 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
848
849 axgbe_printf(1, "\n************************************************\n");
850 }
851
852 static void
xgbe_dump_prop_registers(struct xgbe_prv_data * pdata)853 xgbe_dump_prop_registers(struct xgbe_prv_data *pdata)
854 {
855 int i;
856
857 axgbe_printf(1, "\n************* PROP Reg dump ********************\n");
858
859 for (i = 0 ; i < 38 ; i++) {
860 axgbe_printf(1, "PROP Offset 0x%08x = %08x\n",
861 (XP_PROP_0 + (i * 4)), XP_IOREAD(pdata,
862 (XP_PROP_0 + (i * 4))));
863 }
864 }
865
866 static void
xgbe_dump_dma_registers(struct xgbe_prv_data * pdata,int ch)867 xgbe_dump_dma_registers(struct xgbe_prv_data *pdata, int ch)
868 {
869 struct xgbe_channel *channel;
870 int i;
871
872 axgbe_printf(1, "\n************* DMA Reg dump *********************\n");
873
874 axgbe_printf(1, "DMA MR Reg (%08x) = %08x\n", DMA_MR,
875 XGMAC_IOREAD(pdata, DMA_MR));
876 axgbe_printf(1, "DMA SBMR Reg (%08x) = %08x\n", DMA_SBMR,
877 XGMAC_IOREAD(pdata, DMA_SBMR));
878 axgbe_printf(1, "DMA ISR Reg (%08x) = %08x\n", DMA_ISR,
879 XGMAC_IOREAD(pdata, DMA_ISR));
880 axgbe_printf(1, "DMA AXIARCR Reg (%08x) = %08x\n", DMA_AXIARCR,
881 XGMAC_IOREAD(pdata, DMA_AXIARCR));
882 axgbe_printf(1, "DMA AXIAWCR Reg (%08x) = %08x\n", DMA_AXIAWCR,
883 XGMAC_IOREAD(pdata, DMA_AXIAWCR));
884 axgbe_printf(1, "DMA AXIAWARCR Reg (%08x) = %08x\n", DMA_AXIAWARCR,
885 XGMAC_IOREAD(pdata, DMA_AXIAWARCR));
886 axgbe_printf(1, "DMA DSR0 Reg (%08x) = %08x\n", DMA_DSR0,
887 XGMAC_IOREAD(pdata, DMA_DSR0));
888 axgbe_printf(1, "DMA DSR1 Reg (%08x) = %08x\n", DMA_DSR1,
889 XGMAC_IOREAD(pdata, DMA_DSR1));
890 axgbe_printf(1, "DMA DSR2 Reg (%08x) = %08x\n", DMA_DSR2,
891 XGMAC_IOREAD(pdata, DMA_DSR2));
892 axgbe_printf(1, "DMA DSR3 Reg (%08x) = %08x\n", DMA_DSR3,
893 XGMAC_IOREAD(pdata, DMA_DSR3));
894 axgbe_printf(1, "DMA DSR4 Reg (%08x) = %08x\n", DMA_DSR4,
895 XGMAC_IOREAD(pdata, DMA_DSR4));
896 axgbe_printf(1, "DMA TXEDMACR Reg (%08x) = %08x\n", DMA_TXEDMACR,
897 XGMAC_IOREAD(pdata, DMA_TXEDMACR));
898 axgbe_printf(1, "DMA RXEDMACR Reg (%08x) = %08x\n", DMA_RXEDMACR,
899 XGMAC_IOREAD(pdata, DMA_RXEDMACR));
900
901 for (i = 0 ; i < 8 ; i++ ) {
902
903 if (ch >= 0) {
904 if (i != ch)
905 continue;
906 }
907
908 channel = pdata->channel[i];
909
910 axgbe_printf(1, "\n************* DMA CH %d dump ****************\n", i);
911
912 axgbe_printf(1, "DMA_CH_CR Reg (%08x) = %08x\n",
913 DMA_CH_CR, XGMAC_DMA_IOREAD(channel, DMA_CH_CR));
914 axgbe_printf(1, "DMA_CH_TCR Reg (%08x) = %08x\n",
915 DMA_CH_TCR, XGMAC_DMA_IOREAD(channel, DMA_CH_TCR));
916 axgbe_printf(1, "DMA_CH_RCR Reg (%08x) = %08x\n",
917 DMA_CH_RCR, XGMAC_DMA_IOREAD(channel, DMA_CH_RCR));
918 axgbe_printf(1, "DMA_CH_TDLR_HI Reg (%08x) = %08x\n",
919 DMA_CH_TDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_HI));
920 axgbe_printf(1, "DMA_CH_TDLR_LO Reg (%08x) = %08x\n",
921 DMA_CH_TDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_LO));
922 axgbe_printf(1, "DMA_CH_RDLR_HI Reg (%08x) = %08x\n",
923 DMA_CH_RDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_HI));
924 axgbe_printf(1, "DMA_CH_RDLR_LO Reg (%08x) = %08x\n",
925 DMA_CH_RDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_LO));
926 axgbe_printf(1, "DMA_CH_TDTR_LO Reg (%08x) = %08x\n",
927 DMA_CH_TDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO));
928 axgbe_printf(1, "DMA_CH_RDTR_LO Reg (%08x) = %08x\n",
929 DMA_CH_RDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTR_LO));
930 axgbe_printf(1, "DMA_CH_TDRLR Reg (%08x) = %08x\n",
931 DMA_CH_TDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_TDRLR));
932 axgbe_printf(1, "DMA_CH_RDRLR Reg (%08x) = %08x\n",
933 DMA_CH_RDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_RDRLR));
934 axgbe_printf(1, "DMA_CH_IER Reg (%08x) = %08x\n",
935 DMA_CH_IER, XGMAC_DMA_IOREAD(channel, DMA_CH_IER));
936 axgbe_printf(1, "DMA_CH_RIWT Reg (%08x) = %08x\n",
937 DMA_CH_RIWT, XGMAC_DMA_IOREAD(channel, DMA_CH_RIWT));
938 axgbe_printf(1, "DMA_CH_CATDR_LO Reg (%08x) = %08x\n",
939 DMA_CH_CATDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATDR_LO));
940 axgbe_printf(1, "DMA_CH_CARDR_LO Reg (%08x) = %08x\n",
941 DMA_CH_CARDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARDR_LO));
942 axgbe_printf(1, "DMA_CH_CATBR_HI Reg (%08x) = %08x\n",
943 DMA_CH_CATBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_HI));
944 axgbe_printf(1, "DMA_CH_CATBR_LO Reg (%08x) = %08x\n",
945 DMA_CH_CATBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_LO));
946 axgbe_printf(1, "DMA_CH_CARBR_HI Reg (%08x) = %08x\n",
947 DMA_CH_CARBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_HI));
948 axgbe_printf(1, "DMA_CH_CARBR_LO Reg (%08x) = %08x\n",
949 DMA_CH_CARBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_LO));
950 axgbe_printf(1, "DMA_CH_SR Reg (%08x) = %08x\n",
951 DMA_CH_SR, XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
952 axgbe_printf(1, "DMA_CH_DSR Reg (%08x) = %08x\n",
953 DMA_CH_DSR, XGMAC_DMA_IOREAD(channel, DMA_CH_DSR));
954 axgbe_printf(1, "DMA_CH_DCFL Reg (%08x) = %08x\n",
955 DMA_CH_DCFL, XGMAC_DMA_IOREAD(channel, DMA_CH_DCFL));
956 axgbe_printf(1, "DMA_CH_MFC Reg (%08x) = %08x\n",
957 DMA_CH_MFC, XGMAC_DMA_IOREAD(channel, DMA_CH_MFC));
958 axgbe_printf(1, "DMA_CH_TDTRO Reg (%08x) = %08x\n",
959 DMA_CH_TDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTRO));
960 axgbe_printf(1, "DMA_CH_RDTRO Reg (%08x) = %08x\n",
961 DMA_CH_RDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTRO));
962 axgbe_printf(1, "DMA_CH_TDWRO Reg (%08x) = %08x\n",
963 DMA_CH_TDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDWRO));
964 axgbe_printf(1, "DMA_CH_RDWRO Reg (%08x) = %08x\n",
965 DMA_CH_RDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDWRO));
966 }
967 }
968
969 static void
xgbe_dump_mtl_registers(struct xgbe_prv_data * pdata)970 xgbe_dump_mtl_registers(struct xgbe_prv_data *pdata)
971 {
972 int i;
973
974 axgbe_printf(1, "\n************* MTL Reg dump *********************\n");
975
976 axgbe_printf(1, "MTL OMR Reg (%08x) = %08x\n", MTL_OMR,
977 XGMAC_IOREAD(pdata, MTL_OMR));
978 axgbe_printf(1, "MTL FDCR Reg (%08x) = %08x\n", MTL_FDCR,
979 XGMAC_IOREAD(pdata, MTL_FDCR));
980 axgbe_printf(1, "MTL FDSR Reg (%08x) = %08x\n", MTL_FDSR,
981 XGMAC_IOREAD(pdata, MTL_FDSR));
982 axgbe_printf(1, "MTL FDDR Reg (%08x) = %08x\n", MTL_FDDR,
983 XGMAC_IOREAD(pdata, MTL_FDDR));
984 axgbe_printf(1, "MTL ISR Reg (%08x) = %08x\n", MTL_ISR,
985 XGMAC_IOREAD(pdata, MTL_ISR));
986 axgbe_printf(1, "MTL RQDCM0R Reg (%08x) = %08x\n", MTL_RQDCM0R,
987 XGMAC_IOREAD(pdata, MTL_RQDCM0R));
988 axgbe_printf(1, "MTL RQDCM1R Reg (%08x) = %08x\n", MTL_RQDCM1R,
989 XGMAC_IOREAD(pdata, MTL_RQDCM1R));
990 axgbe_printf(1, "MTL RQDCM2R Reg (%08x) = %08x\n", MTL_RQDCM2R,
991 XGMAC_IOREAD(pdata, MTL_RQDCM2R));
992 axgbe_printf(1, "MTL TCPM0R Reg (%08x) = %08x\n", MTL_TCPM0R,
993 XGMAC_IOREAD(pdata, MTL_TCPM0R));
994 axgbe_printf(1, "MTL TCPM1R Reg (%08x) = %08x\n", MTL_TCPM1R,
995 XGMAC_IOREAD(pdata, MTL_TCPM1R));
996
997 for (i = 0 ; i < 8 ; i++ ) {
998
999 axgbe_printf(1, "\n************* MTL CH %d dump ****************\n", i);
1000
1001 axgbe_printf(1, "MTL_Q_TQOMR Reg (%08x) = %08x\n",
1002 MTL_Q_TQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR));
1003 axgbe_printf(1, "MTL_Q_TQUR Reg (%08x) = %08x\n",
1004 MTL_Q_TQUR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQUR));
1005 axgbe_printf(1, "MTL_Q_TQDR Reg (%08x) = %08x\n",
1006 MTL_Q_TQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQDR));
1007 axgbe_printf(1, "MTL_Q_TC0ETSCR Reg (%08x) = %08x\n",
1008 MTL_Q_TC0ETSCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSCR));
1009 axgbe_printf(1, "MTL_Q_TC0ETSSR Reg (%08x) = %08x\n",
1010 MTL_Q_TC0ETSSR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSSR));
1011 axgbe_printf(1, "MTL_Q_TC0QWR Reg (%08x) = %08x\n",
1012 MTL_Q_TC0QWR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0QWR));
1013
1014 axgbe_printf(1, "MTL_Q_RQOMR Reg (%08x) = %08x\n",
1015 MTL_Q_RQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR));
1016 axgbe_printf(1, "MTL_Q_RQMPOCR Reg (%08x) = %08x\n",
1017 MTL_Q_RQMPOCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQMPOCR));
1018 axgbe_printf(1, "MTL_Q_RQDR Reg (%08x) = %08x\n",
1019 MTL_Q_RQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQDR));
1020 axgbe_printf(1, "MTL_Q_RQCR Reg (%08x) = %08x\n",
1021 MTL_Q_RQCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQCR));
1022 axgbe_printf(1, "MTL_Q_RQFCR Reg (%08x) = %08x\n",
1023 MTL_Q_RQFCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR));
1024 axgbe_printf(1, "MTL_Q_IER Reg (%08x) = %08x\n",
1025 MTL_Q_IER, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_IER));
1026 axgbe_printf(1, "MTL_Q_ISR Reg (%08x) = %08x\n",
1027 MTL_Q_ISR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR));
1028 }
1029 }
1030
1031 static void
xgbe_dump_mac_registers(struct xgbe_prv_data * pdata)1032 xgbe_dump_mac_registers(struct xgbe_prv_data *pdata)
1033 {
1034 axgbe_printf(1, "\n************* MAC Reg dump **********************\n");
1035
1036 axgbe_printf(1, "MAC TCR Reg (%08x) = %08x\n", MAC_TCR,
1037 XGMAC_IOREAD(pdata, MAC_TCR));
1038 axgbe_printf(1, "MAC RCR Reg (%08x) = %08x\n", MAC_RCR,
1039 XGMAC_IOREAD(pdata, MAC_RCR));
1040 axgbe_printf(1, "MAC PFR Reg (%08x) = %08x\n", MAC_PFR,
1041 XGMAC_IOREAD(pdata, MAC_PFR));
1042 axgbe_printf(1, "MAC WTR Reg (%08x) = %08x\n", MAC_WTR,
1043 XGMAC_IOREAD(pdata, MAC_WTR));
1044 axgbe_printf(1, "MAC HTR0 Reg (%08x) = %08x\n", MAC_HTR0,
1045 XGMAC_IOREAD(pdata, MAC_HTR0));
1046 axgbe_printf(1, "MAC HTR1 Reg (%08x) = %08x\n", MAC_HTR1,
1047 XGMAC_IOREAD(pdata, MAC_HTR1));
1048 axgbe_printf(1, "MAC HTR2 Reg (%08x) = %08x\n", MAC_HTR2,
1049 XGMAC_IOREAD(pdata, MAC_HTR2));
1050 axgbe_printf(1, "MAC HTR3 Reg (%08x) = %08x\n", MAC_HTR3,
1051 XGMAC_IOREAD(pdata, MAC_HTR3));
1052 axgbe_printf(1, "MAC HTR4 Reg (%08x) = %08x\n", MAC_HTR4,
1053 XGMAC_IOREAD(pdata, MAC_HTR4));
1054 axgbe_printf(1, "MAC HTR5 Reg (%08x) = %08x\n", MAC_HTR5,
1055 XGMAC_IOREAD(pdata, MAC_HTR5));
1056 axgbe_printf(1, "MAC HTR6 Reg (%08x) = %08x\n", MAC_HTR6,
1057 XGMAC_IOREAD(pdata, MAC_HTR6));
1058 axgbe_printf(1, "MAC HTR7 Reg (%08x) = %08x\n", MAC_HTR7,
1059 XGMAC_IOREAD(pdata, MAC_HTR7));
1060 axgbe_printf(1, "MAC VLANTR Reg (%08x) = %08x\n", MAC_VLANTR,
1061 XGMAC_IOREAD(pdata, MAC_VLANTR));
1062 axgbe_printf(1, "MAC VLANHTR Reg (%08x) = %08x\n", MAC_VLANHTR,
1063 XGMAC_IOREAD(pdata, MAC_VLANHTR));
1064 axgbe_printf(1, "MAC VLANIR Reg (%08x) = %08x\n", MAC_VLANIR,
1065 XGMAC_IOREAD(pdata, MAC_VLANIR));
1066 axgbe_printf(1, "MAC IVLANIR Reg (%08x) = %08x\n", MAC_IVLANIR,
1067 XGMAC_IOREAD(pdata, MAC_IVLANIR));
1068 axgbe_printf(1, "MAC RETMR Reg (%08x) = %08x\n", MAC_RETMR,
1069 XGMAC_IOREAD(pdata, MAC_RETMR));
1070 axgbe_printf(1, "MAC Q0TFCR Reg (%08x) = %08x\n", MAC_Q0TFCR,
1071 XGMAC_IOREAD(pdata, MAC_Q0TFCR));
1072 axgbe_printf(1, "MAC Q1TFCR Reg (%08x) = %08x\n", MAC_Q1TFCR,
1073 XGMAC_IOREAD(pdata, MAC_Q1TFCR));
1074 axgbe_printf(1, "MAC Q2TFCR Reg (%08x) = %08x\n", MAC_Q2TFCR,
1075 XGMAC_IOREAD(pdata, MAC_Q2TFCR));
1076 axgbe_printf(1, "MAC Q3TFCR Reg (%08x) = %08x\n", MAC_Q3TFCR,
1077 XGMAC_IOREAD(pdata, MAC_Q3TFCR));
1078 axgbe_printf(1, "MAC Q4TFCR Reg (%08x) = %08x\n", MAC_Q4TFCR,
1079 XGMAC_IOREAD(pdata, MAC_Q4TFCR));
1080 axgbe_printf(1, "MAC Q5TFCR Reg (%08x) = %08x\n", MAC_Q5TFCR,
1081 XGMAC_IOREAD(pdata, MAC_Q5TFCR));
1082 axgbe_printf(1, "MAC Q6TFCR Reg (%08x) = %08x\n", MAC_Q6TFCR,
1083 XGMAC_IOREAD(pdata, MAC_Q6TFCR));
1084 axgbe_printf(1, "MAC Q7TFCR Reg (%08x) = %08x\n", MAC_Q7TFCR,
1085 XGMAC_IOREAD(pdata, MAC_Q7TFCR));
1086 axgbe_printf(1, "MAC RFCR Reg (%08x) = %08x\n", MAC_RFCR,
1087 XGMAC_IOREAD(pdata, MAC_RFCR));
1088 axgbe_printf(1, "MAC RQC0R Reg (%08x) = %08x\n", MAC_RQC0R,
1089 XGMAC_IOREAD(pdata, MAC_RQC0R));
1090 axgbe_printf(1, "MAC RQC1R Reg (%08x) = %08x\n", MAC_RQC1R,
1091 XGMAC_IOREAD(pdata, MAC_RQC1R));
1092 axgbe_printf(1, "MAC RQC2R Reg (%08x) = %08x\n", MAC_RQC2R,
1093 XGMAC_IOREAD(pdata, MAC_RQC2R));
1094 axgbe_printf(1, "MAC RQC3R Reg (%08x) = %08x\n", MAC_RQC3R,
1095 XGMAC_IOREAD(pdata, MAC_RQC3R));
1096 axgbe_printf(1, "MAC ISR Reg (%08x) = %08x\n", MAC_ISR,
1097 XGMAC_IOREAD(pdata, MAC_ISR));
1098 axgbe_printf(1, "MAC IER Reg (%08x) = %08x\n", MAC_IER,
1099 XGMAC_IOREAD(pdata, MAC_IER));
1100 axgbe_printf(1, "MAC RTSR Reg (%08x) = %08x\n", MAC_RTSR,
1101 XGMAC_IOREAD(pdata, MAC_RTSR));
1102 axgbe_printf(1, "MAC PMTCSR Reg (%08x) = %08x\n", MAC_PMTCSR,
1103 XGMAC_IOREAD(pdata, MAC_PMTCSR));
1104 axgbe_printf(1, "MAC RWKPFR Reg (%08x) = %08x\n", MAC_RWKPFR,
1105 XGMAC_IOREAD(pdata, MAC_RWKPFR));
1106 axgbe_printf(1, "MAC LPICSR Reg (%08x) = %08x\n", MAC_LPICSR,
1107 XGMAC_IOREAD(pdata, MAC_LPICSR));
1108 axgbe_printf(1, "MAC LPITCR Reg (%08x) = %08x\n", MAC_LPITCR,
1109 XGMAC_IOREAD(pdata, MAC_LPITCR));
1110 axgbe_printf(1, "MAC TIR Reg (%08x) = %08x\n", MAC_TIR,
1111 XGMAC_IOREAD(pdata, MAC_TIR));
1112 axgbe_printf(1, "MAC VR Reg (%08x) = %08x\n", MAC_VR,
1113 XGMAC_IOREAD(pdata, MAC_VR));
1114 axgbe_printf(1, "MAC DR Reg (%08x) = %08x\n", MAC_DR,
1115 XGMAC_IOREAD(pdata, MAC_DR));
1116 axgbe_printf(1, "MAC HWF0R Reg (%08x) = %08x\n", MAC_HWF0R,
1117 XGMAC_IOREAD(pdata, MAC_HWF0R));
1118 axgbe_printf(1, "MAC HWF1R Reg (%08x) = %08x\n", MAC_HWF1R,
1119 XGMAC_IOREAD(pdata, MAC_HWF1R));
1120 axgbe_printf(1, "MAC HWF2R Reg (%08x) = %08x\n", MAC_HWF2R,
1121 XGMAC_IOREAD(pdata, MAC_HWF2R));
1122 axgbe_printf(1, "MAC MDIOSCAR Reg (%08x) = %08x\n", MAC_MDIOSCAR,
1123 XGMAC_IOREAD(pdata, MAC_MDIOSCAR));
1124 axgbe_printf(1, "MAC MDIOSCCDR Reg (%08x) = %08x\n", MAC_MDIOSCCDR,
1125 XGMAC_IOREAD(pdata, MAC_MDIOSCCDR));
1126 axgbe_printf(1, "MAC MDIOISR Reg (%08x) = %08x\n", MAC_MDIOISR,
1127 XGMAC_IOREAD(pdata, MAC_MDIOISR));
1128 axgbe_printf(1, "MAC MDIOIER Reg (%08x) = %08x\n", MAC_MDIOIER,
1129 XGMAC_IOREAD(pdata, MAC_MDIOIER));
1130 axgbe_printf(1, "MAC MDIOCL22R Reg (%08x) = %08x\n", MAC_MDIOCL22R,
1131 XGMAC_IOREAD(pdata, MAC_MDIOCL22R));
1132 axgbe_printf(1, "MAC GPIOCR Reg (%08x) = %08x\n", MAC_GPIOCR,
1133 XGMAC_IOREAD(pdata, MAC_GPIOCR));
1134 axgbe_printf(1, "MAC GPIOSR Reg (%08x) = %08x\n", MAC_GPIOSR,
1135 XGMAC_IOREAD(pdata, MAC_GPIOSR));
1136 axgbe_printf(1, "MAC MACA0HR Reg (%08x) = %08x\n", MAC_MACA0HR,
1137 XGMAC_IOREAD(pdata, MAC_MACA0HR));
1138 axgbe_printf(1, "MAC MACA0LR Reg (%08x) = %08x\n", MAC_TCR,
1139 XGMAC_IOREAD(pdata, MAC_MACA0LR));
1140 axgbe_printf(1, "MAC MACA1HR Reg (%08x) = %08x\n", MAC_MACA1HR,
1141 XGMAC_IOREAD(pdata, MAC_MACA1HR));
1142 axgbe_printf(1, "MAC MACA1LR Reg (%08x) = %08x\n", MAC_MACA1LR,
1143 XGMAC_IOREAD(pdata, MAC_MACA1LR));
1144 axgbe_printf(1, "MAC RSSCR Reg (%08x) = %08x\n", MAC_RSSCR,
1145 XGMAC_IOREAD(pdata, MAC_RSSCR));
1146 axgbe_printf(1, "MAC RSSDR Reg (%08x) = %08x\n", MAC_RSSDR,
1147 XGMAC_IOREAD(pdata, MAC_RSSDR));
1148 axgbe_printf(1, "MAC RSSAR Reg (%08x) = %08x\n", MAC_RSSAR,
1149 XGMAC_IOREAD(pdata, MAC_RSSAR));
1150 axgbe_printf(1, "MAC TSCR Reg (%08x) = %08x\n", MAC_TSCR,
1151 XGMAC_IOREAD(pdata, MAC_TSCR));
1152 axgbe_printf(1, "MAC SSIR Reg (%08x) = %08x\n", MAC_SSIR,
1153 XGMAC_IOREAD(pdata, MAC_SSIR));
1154 axgbe_printf(1, "MAC STSR Reg (%08x) = %08x\n", MAC_STSR,
1155 XGMAC_IOREAD(pdata, MAC_STSR));
1156 axgbe_printf(1, "MAC STNR Reg (%08x) = %08x\n", MAC_STNR,
1157 XGMAC_IOREAD(pdata, MAC_STNR));
1158 axgbe_printf(1, "MAC STSUR Reg (%08x) = %08x\n", MAC_STSUR,
1159 XGMAC_IOREAD(pdata, MAC_STSUR));
1160 axgbe_printf(1, "MAC STNUR Reg (%08x) = %08x\n", MAC_STNUR,
1161 XGMAC_IOREAD(pdata, MAC_STNUR));
1162 axgbe_printf(1, "MAC TSAR Reg (%08x) = %08x\n", MAC_TSAR,
1163 XGMAC_IOREAD(pdata, MAC_TSAR));
1164 axgbe_printf(1, "MAC TSSR Reg (%08x) = %08x\n", MAC_TSSR,
1165 XGMAC_IOREAD(pdata, MAC_TSSR));
1166 axgbe_printf(1, "MAC TXSNR Reg (%08x) = %08x\n", MAC_TXSNR,
1167 XGMAC_IOREAD(pdata, MAC_TXSNR));
1168 axgbe_printf(1, "MAC TXSSR Reg (%08x) = %08x\n", MAC_TXSSR,
1169 XGMAC_IOREAD(pdata, MAC_TXSSR));
1170 }
1171
1172 static void
xgbe_dump_rmon_counters(struct xgbe_prv_data * pdata)1173 xgbe_dump_rmon_counters(struct xgbe_prv_data *pdata)
1174 {
1175 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1176
1177 axgbe_printf(1, "\n************* RMON counters dump ***************\n");
1178
1179 pdata->hw_if.read_mmc_stats(pdata);
1180
1181 axgbe_printf(1, "rmon txoctetcount_gb (%08x) = %08lx\n",
1182 MMC_TXOCTETCOUNT_GB_LO, stats->txoctetcount_gb);
1183 axgbe_printf(1, "rmon txframecount_gb (%08x) = %08lx\n",
1184 MMC_TXFRAMECOUNT_GB_LO, stats->txframecount_gb);
1185 axgbe_printf(1, "rmon txbroadcastframes_g (%08x) = %08lx\n",
1186 MMC_TXBROADCASTFRAMES_G_LO, stats->txbroadcastframes_g);
1187 axgbe_printf(1, "rmon txmulticastframes_g (%08x) = %08lx\n",
1188 MMC_TXMULTICASTFRAMES_G_LO, stats->txmulticastframes_g);
1189 axgbe_printf(1, "rmon tx64octets_gb (%08x) = %08lx\n",
1190 MMC_TX64OCTETS_GB_LO, stats->tx64octets_gb);
1191 axgbe_printf(1, "rmon tx65to127octets_gb (%08x) = %08lx\n",
1192 MMC_TX65TO127OCTETS_GB_LO, stats->tx65to127octets_gb);
1193 axgbe_printf(1, "rmon tx128to255octets_gb (%08x) = %08lx\n",
1194 MMC_TX128TO255OCTETS_GB_LO, stats->tx128to255octets_gb);
1195 axgbe_printf(1, "rmon tx256to511octets_gb (%08x) = %08lx\n",
1196 MMC_TX256TO511OCTETS_GB_LO, stats->tx256to511octets_gb);
1197 axgbe_printf(1, "rmon tx512to1023octets_gb (%08x) = %08lx\n",
1198 MMC_TX512TO1023OCTETS_GB_LO, stats->tx512to1023octets_gb);
1199 axgbe_printf(1, "rmon tx1024tomaxoctets_gb (%08x) = %08lx\n",
1200 MMC_TX1024TOMAXOCTETS_GB_LO, stats->tx1024tomaxoctets_gb);
1201 axgbe_printf(1, "rmon txunicastframes_gb (%08x) = %08lx\n",
1202 MMC_TXUNICASTFRAMES_GB_LO, stats->txunicastframes_gb);
1203 axgbe_printf(1, "rmon txmulticastframes_gb (%08x) = %08lx\n",
1204 MMC_TXMULTICASTFRAMES_GB_LO, stats->txmulticastframes_gb);
1205 axgbe_printf(1, "rmon txbroadcastframes_gb (%08x) = %08lx\n",
1206 MMC_TXBROADCASTFRAMES_GB_LO, stats->txbroadcastframes_gb);
1207 axgbe_printf(1, "rmon txunderflowerror (%08x) = %08lx\n",
1208 MMC_TXUNDERFLOWERROR_LO, stats->txunderflowerror);
1209 axgbe_printf(1, "rmon txoctetcount_g (%08x) = %08lx\n",
1210 MMC_TXOCTETCOUNT_G_LO, stats->txoctetcount_g);
1211 axgbe_printf(1, "rmon txframecount_g (%08x) = %08lx\n",
1212 MMC_TXFRAMECOUNT_G_LO, stats->txframecount_g);
1213 axgbe_printf(1, "rmon txpauseframes (%08x) = %08lx\n",
1214 MMC_TXPAUSEFRAMES_LO, stats->txpauseframes);
1215 axgbe_printf(1, "rmon txvlanframes_g (%08x) = %08lx\n",
1216 MMC_TXVLANFRAMES_G_LO, stats->txvlanframes_g);
1217 axgbe_printf(1, "rmon rxframecount_gb (%08x) = %08lx\n",
1218 MMC_RXFRAMECOUNT_GB_LO, stats->rxframecount_gb);
1219 axgbe_printf(1, "rmon rxoctetcount_gb (%08x) = %08lx\n",
1220 MMC_RXOCTETCOUNT_GB_LO, stats->rxoctetcount_gb);
1221 axgbe_printf(1, "rmon rxoctetcount_g (%08x) = %08lx\n",
1222 MMC_RXOCTETCOUNT_G_LO, stats->rxoctetcount_g);
1223 axgbe_printf(1, "rmon rxbroadcastframes_g (%08x) = %08lx\n",
1224 MMC_RXBROADCASTFRAMES_G_LO, stats->rxbroadcastframes_g);
1225 axgbe_printf(1, "rmon rxmulticastframes_g (%08x) = %08lx\n",
1226 MMC_RXMULTICASTFRAMES_G_LO, stats->rxmulticastframes_g);
1227 axgbe_printf(1, "rmon rxcrcerror (%08x) = %08lx\n",
1228 MMC_RXCRCERROR_LO, stats->rxcrcerror);
1229 axgbe_printf(1, "rmon rxrunterror (%08x) = %08lx\n",
1230 MMC_RXRUNTERROR, stats->rxrunterror);
1231 axgbe_printf(1, "rmon rxjabbererror (%08x) = %08lx\n",
1232 MMC_RXJABBERERROR, stats->rxjabbererror);
1233 axgbe_printf(1, "rmon rxundersize_g (%08x) = %08lx\n",
1234 MMC_RXUNDERSIZE_G, stats->rxundersize_g);
1235 axgbe_printf(1, "rmon rxoversize_g (%08x) = %08lx\n",
1236 MMC_RXOVERSIZE_G, stats->rxoversize_g);
1237 axgbe_printf(1, "rmon rx64octets_gb (%08x) = %08lx\n",
1238 MMC_RX64OCTETS_GB_LO, stats->rx64octets_gb);
1239 axgbe_printf(1, "rmon rx65to127octets_gb (%08x) = %08lx\n",
1240 MMC_RX65TO127OCTETS_GB_LO, stats->rx65to127octets_gb);
1241 axgbe_printf(1, "rmon rx128to255octets_gb (%08x) = %08lx\n",
1242 MMC_RX128TO255OCTETS_GB_LO, stats->rx128to255octets_gb);
1243 axgbe_printf(1, "rmon rx256to511octets_gb (%08x) = %08lx\n",
1244 MMC_RX256TO511OCTETS_GB_LO, stats->rx256to511octets_gb);
1245 axgbe_printf(1, "rmon rx512to1023octets_gb (%08x) = %08lx\n",
1246 MMC_RX512TO1023OCTETS_GB_LO, stats->rx512to1023octets_gb);
1247 axgbe_printf(1, "rmon rx1024tomaxoctets_gb (%08x) = %08lx\n",
1248 MMC_RX1024TOMAXOCTETS_GB_LO, stats->rx1024tomaxoctets_gb);
1249 axgbe_printf(1, "rmon rxunicastframes_g (%08x) = %08lx\n",
1250 MMC_RXUNICASTFRAMES_G_LO, stats->rxunicastframes_g);
1251 axgbe_printf(1, "rmon rxlengtherror (%08x) = %08lx\n",
1252 MMC_RXLENGTHERROR_LO, stats->rxlengtherror);
1253 axgbe_printf(1, "rmon rxoutofrangetype (%08x) = %08lx\n",
1254 MMC_RXOUTOFRANGETYPE_LO, stats->rxoutofrangetype);
1255 axgbe_printf(1, "rmon rxpauseframes (%08x) = %08lx\n",
1256 MMC_RXPAUSEFRAMES_LO, stats->rxpauseframes);
1257 axgbe_printf(1, "rmon rxfifooverflow (%08x) = %08lx\n",
1258 MMC_RXFIFOOVERFLOW_LO, stats->rxfifooverflow);
1259 axgbe_printf(1, "rmon rxvlanframes_gb (%08x) = %08lx\n",
1260 MMC_RXVLANFRAMES_GB_LO, stats->rxvlanframes_gb);
1261 axgbe_printf(1, "rmon rxwatchdogerror (%08x) = %08lx\n",
1262 MMC_RXWATCHDOGERROR, stats->rxwatchdogerror);
1263 }
1264
1265 void
xgbe_dump_i2c_registers(struct xgbe_prv_data * pdata)1266 xgbe_dump_i2c_registers(struct xgbe_prv_data *pdata)
1267 {
1268 axgbe_printf(1, "*************** I2C Registers **************\n");
1269 axgbe_printf(1, " IC_CON : %010x\n",
1270 XI2C_IOREAD(pdata, 0x00));
1271 axgbe_printf(1, " IC_TAR : %010x\n",
1272 XI2C_IOREAD(pdata, 0x04));
1273 axgbe_printf(1, " IC_HS_MADDR : %010x\n",
1274 XI2C_IOREAD(pdata, 0x0c));
1275 axgbe_printf(1, " IC_INTR_STAT : %010x\n",
1276 XI2C_IOREAD(pdata, 0x2c));
1277 axgbe_printf(1, " IC_INTR_MASK : %010x\n",
1278 XI2C_IOREAD(pdata, 0x30));
1279 axgbe_printf(1, " IC_RAW_INTR_STAT : %010x\n",
1280 XI2C_IOREAD(pdata, 0x34));
1281 axgbe_printf(1, " IC_RX_TL : %010x\n",
1282 XI2C_IOREAD(pdata, 0x38));
1283 axgbe_printf(1, " IC_TX_TL : %010x\n",
1284 XI2C_IOREAD(pdata, 0x3c));
1285 axgbe_printf(1, " IC_ENABLE : %010x\n",
1286 XI2C_IOREAD(pdata, 0x6c));
1287 axgbe_printf(1, " IC_STATUS : %010x\n",
1288 XI2C_IOREAD(pdata, 0x70));
1289 axgbe_printf(1, " IC_TXFLR : %010x\n",
1290 XI2C_IOREAD(pdata, 0x74));
1291 axgbe_printf(1, " IC_RXFLR : %010x\n",
1292 XI2C_IOREAD(pdata, 0x78));
1293 axgbe_printf(1, " IC_ENABLE_STATUS : %010x\n",
1294 XI2C_IOREAD(pdata, 0x9c));
1295 axgbe_printf(1, " IC_COMP_PARAM1 : %010x\n",
1296 XI2C_IOREAD(pdata, 0xf4));
1297 }
1298
1299 static void
xgbe_dump_active_vlans(struct xgbe_prv_data * pdata)1300 xgbe_dump_active_vlans(struct xgbe_prv_data *pdata)
1301 {
1302 int i;
1303
1304 for(i=0 ; i<BITS_TO_LONGS(VLAN_NVID); i++) {
1305 if (i && (i%8 == 0))
1306 axgbe_printf(1, "\n");
1307 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]);
1308 }
1309 axgbe_printf(1, "\n");
1310 }
1311
1312 static void
xgbe_default_config(struct xgbe_prv_data * pdata)1313 xgbe_default_config(struct xgbe_prv_data *pdata)
1314 {
1315 pdata->blen = DMA_SBMR_BLEN_64;
1316 pdata->pbl = DMA_PBL_128;
1317 pdata->aal = 1;
1318 pdata->rd_osr_limit = 8;
1319 pdata->wr_osr_limit = 8;
1320 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1321 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1322 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1323 pdata->rx_sf_mode = MTL_RSF_DISABLE;
1324 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1325 pdata->pause_autoneg = 1;
1326 pdata->tx_pause = 1;
1327 pdata->rx_pause = 1;
1328 pdata->phy_speed = SPEED_UNKNOWN;
1329 pdata->power_down = 0;
1330 pdata->enable_rss = 1;
1331 }
1332
1333 static int
axgbe_if_attach_post(if_ctx_t ctx)1334 axgbe_if_attach_post(if_ctx_t ctx)
1335 {
1336 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1337 struct xgbe_prv_data *pdata = &sc->pdata;
1338 if_t ifp = pdata->netdev;
1339 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1340 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1341 if_softc_ctx_t scctx = sc->scctx;
1342 int i, ret;
1343
1344 /* set split header support based on tunable */
1345 pdata->sph_enable = axgbe_sph_enable;
1346
1347 /* Initialize ECC timestamps */
1348 pdata->tx_sec_period = ticks;
1349 pdata->tx_ded_period = ticks;
1350 pdata->rx_sec_period = ticks;
1351 pdata->rx_ded_period = ticks;
1352 pdata->desc_sec_period = ticks;
1353 pdata->desc_ded_period = ticks;
1354
1355 /* Reset the hardware */
1356 ret = hw_if->exit(&sc->pdata);
1357 if (ret)
1358 axgbe_error("%s: exit error %d\n", __func__, ret);
1359
1360 /* Configure the defaults */
1361 xgbe_default_config(pdata);
1362
1363 /* Set default max values if not provided */
1364 if (!pdata->tx_max_fifo_size)
1365 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1366 if (!pdata->rx_max_fifo_size)
1367 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1368
1369 DBGPR("%s: tx fifo 0x%x rx fifo 0x%x\n", __func__,
1370 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
1371
1372 /* Set and validate the number of descriptors for a ring */
1373 MPASS(powerof2(XGBE_TX_DESC_CNT));
1374 pdata->tx_desc_count = XGBE_TX_DESC_CNT;
1375 MPASS(powerof2(XGBE_RX_DESC_CNT));
1376 pdata->rx_desc_count = XGBE_RX_DESC_CNT;
1377
1378 /* Adjust the number of queues based on interrupts assigned */
1379 if (pdata->channel_irq_count) {
1380 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
1381 pdata->channel_irq_count);
1382 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
1383 pdata->channel_irq_count);
1384
1385 DBGPR("adjusted TX %u/%u RX %u/%u\n",
1386 pdata->tx_ring_count, pdata->tx_q_count,
1387 pdata->rx_ring_count, pdata->rx_q_count);
1388 }
1389
1390 /* Set channel count based on interrupts assigned */
1391 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets,
1392 scctx->isc_nrxqsets);
1393 DBGPR("Channel count set to: %u\n", pdata->channel_count);
1394
1395 /* Get RSS key */
1396 #ifdef RSS
1397 rss_getkey((uint8_t *)pdata->rss_key);
1398 #else
1399 arc4rand(&pdata->rss_key, ARRAY_SIZE(pdata->rss_key), 0);
1400 #endif
1401 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
1402 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
1403 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
1404
1405 /* Initialize the PHY device */
1406 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
1407 phy_if->phy_init(pdata);
1408
1409 /* Set the coalescing */
1410 xgbe_init_rx_coalesce(&sc->pdata);
1411 xgbe_init_tx_coalesce(&sc->pdata);
1412
1413 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
1414 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
1415 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SFI, 0, NULL);
1416 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1417 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
1418 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
1419 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1420 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1421 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SGMII, 0, NULL);
1422 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1423 ifmedia_add(sc->media, IFM_ETHER | IFM_100_SGMII, 0, NULL);
1424 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1425 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1426
1427 /* Initialize the phy */
1428 pdata->phy_link = -1;
1429 pdata->phy_speed = SPEED_UNKNOWN;
1430 ret = phy_if->phy_reset(pdata);
1431 if (ret)
1432 return (ret);
1433
1434 /* Calculate the Rx buffer size before allocating rings */
1435 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev));
1436 pdata->rx_buf_size = ret;
1437 DBGPR("%s: rx_buf_size %d\n", __func__, ret);
1438
1439 /* Setup RSS lookup table */
1440 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1441 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1442 i % pdata->rx_ring_count);
1443
1444 /*
1445 * Mark the device down until it is initialized, which happens
1446 * when the device is accessed first (for configuring the iface,
1447 * eg: setting IP)
1448 */
1449 set_bit(XGBE_DOWN, &pdata->dev_state);
1450
1451 DBGPR("mtu %d\n", if_getmtu(ifp));
1452 scctx->isc_max_frame_size = if_getmtu(ifp) + 18;
1453 scctx->isc_min_frame_size = XGMAC_MIN_PACKET;
1454
1455 axgbe_sysctl_init(pdata);
1456
1457 axgbe_pci_init(pdata);
1458
1459 return (0);
1460 } /* axgbe_if_attach_post */
1461
1462 static void
xgbe_free_intr(struct xgbe_prv_data * pdata,struct resource * res,void * tag,int rid)1463 xgbe_free_intr(struct xgbe_prv_data *pdata, struct resource *res, void *tag,
1464 int rid)
1465 {
1466 if (tag)
1467 bus_teardown_intr(pdata->dev, res, tag);
1468
1469 if (res)
1470 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res);
1471 }
1472
1473 static void
axgbe_interrupts_free(if_ctx_t ctx)1474 axgbe_interrupts_free(if_ctx_t ctx)
1475 {
1476 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1477 struct xgbe_prv_data *pdata = &sc->pdata;
1478 if_softc_ctx_t scctx = sc->scctx;
1479 struct xgbe_channel *channel;
1480 struct if_irq irq;
1481 int i;
1482
1483 axgbe_printf(2, "%s: mode %d\n", __func__, scctx->isc_intr);
1484
1485 /* Free dev_irq */
1486 iflib_irq_free(ctx, &pdata->dev_irq);
1487
1488 /* Free ecc_irq */
1489 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag,
1490 pdata->ecc_rid);
1491
1492 /* Free i2c_irq */
1493 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag,
1494 pdata->i2c_rid);
1495
1496 /* Free an_irq */
1497 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag,
1498 pdata->an_rid);
1499
1500 for (i = 0; i < scctx->isc_nrxqsets; i++) {
1501
1502 channel = pdata->channel[i];
1503 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid);
1504 irq.ii_res = channel->dma_irq_res;
1505 irq.ii_tag = channel->dma_irq_tag;
1506 iflib_irq_free(ctx, &irq);
1507 }
1508 }
1509
1510 static int
axgbe_if_detach(if_ctx_t ctx)1511 axgbe_if_detach(if_ctx_t ctx)
1512 {
1513 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1514 struct xgbe_prv_data *pdata = &sc->pdata;
1515 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1516 struct resource *mac_res[2];
1517
1518 mac_res[0] = pdata->xgmac_res;
1519 mac_res[1] = pdata->xpcs_res;
1520
1521 phy_if->phy_exit(pdata);
1522
1523 /* Free Interrupts */
1524 axgbe_interrupts_free(ctx);
1525
1526 /* Free workqueues */
1527 taskqueue_free(pdata->dev_workqueue);
1528
1529 /* Release bus resources */
1530 bus_release_resources(iflib_get_dev(ctx), axgbe_pci_mac_spec, mac_res);
1531
1532 /* Free VLAN bitmap */
1533 free(pdata->active_vlans, M_AXGBE);
1534
1535 axgbe_sysctl_exit(pdata);
1536
1537 return (0);
1538 } /* axgbe_if_detach */
1539
1540 static void
axgbe_pci_init(struct xgbe_prv_data * pdata)1541 axgbe_pci_init(struct xgbe_prv_data *pdata)
1542 {
1543 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1544 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1545 int ret = 0;
1546
1547 if (!__predict_false((test_bit(XGBE_DOWN, &pdata->dev_state)))) {
1548 axgbe_printf(1, "%s: Starting when XGBE_UP\n", __func__);
1549 return;
1550 }
1551
1552 hw_if->init(pdata);
1553
1554 ret = phy_if->phy_start(pdata);
1555 if (ret) {
1556 axgbe_error("%s: phy start %d\n", __func__, ret);
1557 ret = hw_if->exit(pdata);
1558 if (ret)
1559 axgbe_error("%s: exit error %d\n", __func__, ret);
1560 return;
1561 }
1562
1563 hw_if->enable_tx(pdata);
1564 hw_if->enable_rx(pdata);
1565
1566 xgbe_start_timers(pdata);
1567
1568 clear_bit(XGBE_DOWN, &pdata->dev_state);
1569
1570 xgbe_dump_phy_registers(pdata);
1571 xgbe_dump_prop_registers(pdata);
1572 xgbe_dump_dma_registers(pdata, -1);
1573 xgbe_dump_mtl_registers(pdata);
1574 xgbe_dump_mac_registers(pdata);
1575 xgbe_dump_rmon_counters(pdata);
1576 }
1577
1578 static void
axgbe_if_init(if_ctx_t ctx)1579 axgbe_if_init(if_ctx_t ctx)
1580 {
1581 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1582 struct xgbe_prv_data *pdata = &sc->pdata;
1583
1584 axgbe_pci_init(pdata);
1585 }
1586
1587 static void
axgbe_pci_stop(if_ctx_t ctx)1588 axgbe_pci_stop(if_ctx_t ctx)
1589 {
1590 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1591 struct xgbe_prv_data *pdata = &sc->pdata;
1592 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1593 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1594 int ret;
1595
1596 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
1597 axgbe_printf(1, "%s: Stopping when XGBE_DOWN\n", __func__);
1598 return;
1599 }
1600
1601 xgbe_stop_timers(pdata);
1602 taskqueue_drain_all(pdata->dev_workqueue);
1603
1604 hw_if->disable_tx(pdata);
1605 hw_if->disable_rx(pdata);
1606
1607 phy_if->phy_stop(pdata);
1608
1609 ret = hw_if->exit(pdata);
1610 if (ret)
1611 axgbe_error("%s: exit error %d\n", __func__, ret);
1612
1613 set_bit(XGBE_DOWN, &pdata->dev_state);
1614 }
1615
1616 static void
axgbe_if_stop(if_ctx_t ctx)1617 axgbe_if_stop(if_ctx_t ctx)
1618 {
1619 axgbe_pci_stop(ctx);
1620 }
1621
1622 static void
axgbe_if_disable_intr(if_ctx_t ctx)1623 axgbe_if_disable_intr(if_ctx_t ctx)
1624 {
1625 /* TODO - implement */
1626 }
1627
1628 static void
axgbe_if_enable_intr(if_ctx_t ctx)1629 axgbe_if_enable_intr(if_ctx_t ctx)
1630 {
1631 /* TODO - implement */
1632 }
1633
1634 static int
axgbe_if_tx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int ntxqs,int ntxqsets)1635 axgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int ntxqs,
1636 int ntxqsets)
1637 {
1638 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1639 struct xgbe_prv_data *pdata = &sc->pdata;
1640 if_softc_ctx_t scctx = sc->scctx;
1641 struct xgbe_channel *channel;
1642 struct xgbe_ring *tx_ring;
1643 int i, j, k;
1644
1645 MPASS(scctx->isc_ntxqsets > 0);
1646 MPASS(scctx->isc_ntxqsets == ntxqsets);
1647 MPASS(ntxqs == 1);
1648
1649 axgbe_printf(1, "%s: txqsets %d/%d txqs %d\n", __func__,
1650 scctx->isc_ntxqsets, ntxqsets, ntxqs);
1651
1652 for (i = 0 ; i < ntxqsets; i++) {
1653
1654 channel = pdata->channel[i];
1655
1656 tx_ring = (struct xgbe_ring*)malloc(ntxqs *
1657 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1658
1659 if (tx_ring == NULL) {
1660 axgbe_error("Unable to allocate TX ring memory\n");
1661 goto tx_ring_fail;
1662 }
1663
1664 channel->tx_ring = tx_ring;
1665
1666 for (j = 0; j < ntxqs; j++, tx_ring++) {
1667 tx_ring->rdata =
1668 (struct xgbe_ring_data*)malloc(scctx->isc_ntxd[j] *
1669 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1670
1671 /* Get the virtual & physical address of hw queues */
1672 tx_ring->rdesc = (struct xgbe_ring_desc *)va[i*ntxqs + j];
1673 tx_ring->rdesc_paddr = pa[i*ntxqs + j];
1674 tx_ring->rdesc_count = scctx->isc_ntxd[j];
1675 spin_lock_init(&tx_ring->lock);
1676 }
1677 }
1678
1679 axgbe_printf(1, "allocated for %d tx queues\n", scctx->isc_ntxqsets);
1680
1681 return (0);
1682
1683 tx_ring_fail:
1684
1685 for (j = 0; j < i ; j++) {
1686
1687 channel = pdata->channel[j];
1688
1689 tx_ring = channel->tx_ring;
1690 for (k = 0; k < ntxqs ; k++, tx_ring++) {
1691 if (tx_ring && tx_ring->rdata)
1692 free(tx_ring->rdata, M_AXGBE);
1693 }
1694 free(channel->tx_ring, M_AXGBE);
1695
1696 channel->tx_ring = NULL;
1697 }
1698
1699 return (ENOMEM);
1700
1701 } /* axgbe_if_tx_queues_alloc */
1702
1703 static int
axgbe_if_rx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int nrxqs,int nrxqsets)1704 axgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int nrxqs,
1705 int nrxqsets)
1706 {
1707 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1708 struct xgbe_prv_data *pdata = &sc->pdata;
1709 if_softc_ctx_t scctx = sc->scctx;
1710 struct xgbe_channel *channel;
1711 struct xgbe_ring *rx_ring;
1712 int i, j, k;
1713
1714 MPASS(scctx->isc_nrxqsets > 0);
1715 MPASS(scctx->isc_nrxqsets == nrxqsets);
1716 if (!pdata->sph_enable) {
1717 MPASS(nrxqs == 1);
1718 } else {
1719 MPASS(nrxqs == 2);
1720 }
1721
1722 axgbe_printf(1, "%s: rxqsets %d/%d rxqs %d\n", __func__,
1723 scctx->isc_nrxqsets, nrxqsets, nrxqs);
1724
1725 for (i = 0 ; i < nrxqsets; i++) {
1726
1727 channel = pdata->channel[i];
1728
1729 rx_ring = (struct xgbe_ring*)malloc(nrxqs *
1730 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1731
1732 if (rx_ring == NULL) {
1733 axgbe_error("Unable to allocate RX ring memory\n");
1734 goto rx_ring_fail;
1735 }
1736
1737 channel->rx_ring = rx_ring;
1738
1739 for (j = 0; j < nrxqs; j++, rx_ring++) {
1740 rx_ring->rdata =
1741 (struct xgbe_ring_data*)malloc(scctx->isc_nrxd[j] *
1742 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1743
1744 /* Get the virtual and physical address of the hw queues */
1745 rx_ring->rdesc = (struct xgbe_ring_desc *)va[i*nrxqs + j];
1746 rx_ring->rdesc_paddr = pa[i*nrxqs + j];
1747 rx_ring->rdesc_count = scctx->isc_nrxd[j];
1748 spin_lock_init(&rx_ring->lock);
1749 }
1750 }
1751
1752 axgbe_printf(2, "allocated for %d rx queues\n", scctx->isc_nrxqsets);
1753
1754 return (0);
1755
1756 rx_ring_fail:
1757
1758 for (j = 0 ; j < i ; j++) {
1759
1760 channel = pdata->channel[j];
1761
1762 rx_ring = channel->rx_ring;
1763 for (k = 0; k < nrxqs ; k++, rx_ring++) {
1764 if (rx_ring && rx_ring->rdata)
1765 free(rx_ring->rdata, M_AXGBE);
1766 }
1767 free(channel->rx_ring, M_AXGBE);
1768
1769 channel->rx_ring = NULL;
1770 }
1771
1772 return (ENOMEM);
1773
1774 } /* axgbe_if_rx_queues_alloc */
1775
1776 static void
axgbe_if_queues_free(if_ctx_t ctx)1777 axgbe_if_queues_free(if_ctx_t ctx)
1778 {
1779 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1780 struct xgbe_prv_data *pdata = &sc->pdata;
1781 if_softc_ctx_t scctx = sc->scctx;
1782 if_shared_ctx_t sctx = sc->sctx;
1783 struct xgbe_channel *channel;
1784 struct xgbe_ring *tx_ring;
1785 struct xgbe_ring *rx_ring;
1786 int i, j;
1787
1788 for (i = 0 ; i < scctx->isc_ntxqsets; i++) {
1789
1790 channel = pdata->channel[i];
1791
1792 tx_ring = channel->tx_ring;
1793 for (j = 0; j < sctx->isc_ntxqs ; j++, tx_ring++) {
1794 if (tx_ring && tx_ring->rdata)
1795 free(tx_ring->rdata, M_AXGBE);
1796 }
1797 free(channel->tx_ring, M_AXGBE);
1798 channel->tx_ring = NULL;
1799 }
1800
1801 for (i = 0 ; i < scctx->isc_nrxqsets; i++) {
1802
1803 channel = pdata->channel[i];
1804
1805 rx_ring = channel->rx_ring;
1806 for (j = 0; j < sctx->isc_nrxqs ; j++, rx_ring++) {
1807 if (rx_ring && rx_ring->rdata)
1808 free(rx_ring->rdata, M_AXGBE);
1809 }
1810 free(channel->rx_ring, M_AXGBE);
1811 channel->rx_ring = NULL;
1812 }
1813
1814 axgbe_free_channels(sc);
1815 } /* axgbe_if_queues_free */
1816
1817 static void
axgbe_if_vlan_register(if_ctx_t ctx,uint16_t vtag)1818 axgbe_if_vlan_register(if_ctx_t ctx, uint16_t vtag)
1819 {
1820 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1821 struct xgbe_prv_data *pdata = &sc->pdata;
1822 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1823
1824 if (!bit_test(pdata->active_vlans, vtag)) {
1825 axgbe_printf(0, "Registering VLAN %d\n", vtag);
1826
1827 bit_set(pdata->active_vlans, vtag);
1828 hw_if->update_vlan_hash_table(pdata);
1829 pdata->num_active_vlans++;
1830
1831 axgbe_printf(1, "Total active vlans: %d\n",
1832 pdata->num_active_vlans);
1833 } else
1834 axgbe_printf(0, "VLAN %d already registered\n", vtag);
1835
1836 xgbe_dump_active_vlans(pdata);
1837 }
1838
1839 static void
axgbe_if_vlan_unregister(if_ctx_t ctx,uint16_t vtag)1840 axgbe_if_vlan_unregister(if_ctx_t ctx, uint16_t vtag)
1841 {
1842 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1843 struct xgbe_prv_data *pdata = &sc->pdata;
1844 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1845
1846 if (pdata->num_active_vlans == 0) {
1847 axgbe_printf(1, "No active VLANs to unregister\n");
1848 return;
1849 }
1850
1851 if (bit_test(pdata->active_vlans, vtag)){
1852 axgbe_printf(0, "Un-Registering VLAN %d\n", vtag);
1853
1854 bit_clear(pdata->active_vlans, vtag);
1855 hw_if->update_vlan_hash_table(pdata);
1856 pdata->num_active_vlans--;
1857
1858 axgbe_printf(1, "Total active vlans: %d\n",
1859 pdata->num_active_vlans);
1860 } else
1861 axgbe_printf(0, "VLAN %d already unregistered\n", vtag);
1862
1863 xgbe_dump_active_vlans(pdata);
1864 }
1865
1866 #if __FreeBSD_version >= 1300000
1867 static bool
axgbe_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)1868 axgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
1869 {
1870 switch (event) {
1871 case IFLIB_RESTART_VLAN_CONFIG:
1872 default:
1873 return (true);
1874 }
1875 }
1876 #endif
1877
1878 static int
axgbe_if_msix_intr_assign(if_ctx_t ctx,int msix)1879 axgbe_if_msix_intr_assign(if_ctx_t ctx, int msix)
1880 {
1881 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1882 struct xgbe_prv_data *pdata = &sc->pdata;
1883 if_softc_ctx_t scctx = sc->scctx;
1884 struct xgbe_channel *channel;
1885 struct if_irq irq;
1886 int i, error, rid = 0, flags;
1887 char buf[16];
1888
1889 MPASS(scctx->isc_intr != IFLIB_INTR_LEGACY);
1890
1891 pdata->isr_as_tasklet = 1;
1892
1893 if (scctx->isc_intr == IFLIB_INTR_MSI) {
1894 pdata->irq_count = 1;
1895 pdata->channel_irq_count = 1;
1896 return (0);
1897 }
1898
1899 axgbe_printf(1, "%s: msix %d txqsets %d rxqsets %d\n", __func__, msix,
1900 scctx->isc_ntxqsets, scctx->isc_nrxqsets);
1901
1902 flags = RF_ACTIVE;
1903
1904 /* DEV INTR SETUP */
1905 rid++;
1906 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid,
1907 IFLIB_INTR_ADMIN, axgbe_dev_isr, sc, 0, "dev_irq");
1908 if (error) {
1909 axgbe_error("Failed to register device interrupt rid %d name %s\n",
1910 rid, "dev_irq");
1911 return (error);
1912 }
1913
1914 /* ECC INTR SETUP */
1915 rid++;
1916 pdata->ecc_rid = rid;
1917 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1918 &rid, flags);
1919 if (!pdata->ecc_irq_res) {
1920 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1921 rid, "ecc_irq");
1922 return (ENOMEM);
1923 }
1924
1925 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE |
1926 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag);
1927 if (error) {
1928 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1929 rid, "ecc_irq", error);
1930 return (error);
1931 }
1932
1933 /* I2C INTR SETUP */
1934 rid++;
1935 pdata->i2c_rid = rid;
1936 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1937 &rid, flags);
1938 if (!pdata->i2c_irq_res) {
1939 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1940 rid, "i2c_irq");
1941 return (ENOMEM);
1942 }
1943
1944 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE |
1945 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag);
1946 if (error) {
1947 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1948 rid, "i2c_irq", error);
1949 return (error);
1950 }
1951
1952 /* AN INTR SETUP */
1953 rid++;
1954 pdata->an_rid = rid;
1955 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1956 &rid, flags);
1957 if (!pdata->an_irq_res) {
1958 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1959 rid, "an_irq");
1960 return (ENOMEM);
1961 }
1962
1963 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE |
1964 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag);
1965 if (error) {
1966 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1967 rid, "an_irq", error);
1968 return (error);
1969 }
1970
1971 pdata->per_channel_irq = 1;
1972 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
1973 rid++;
1974 for (i = 0; i < scctx->isc_nrxqsets; i++, rid++) {
1975
1976 channel = pdata->channel[i];
1977
1978 snprintf(buf, sizeof(buf), "rxq%d", i);
1979 error = iflib_irq_alloc_generic(ctx, &irq, rid, IFLIB_INTR_RXTX,
1980 axgbe_msix_que, channel, channel->queue_index, buf);
1981
1982 if (error) {
1983 axgbe_error("Failed to allocated que int %d err: %d\n",
1984 i, error);
1985 return (error);
1986 }
1987
1988 channel->dma_irq_rid = rid;
1989 channel->dma_irq_res = irq.ii_res;
1990 channel->dma_irq_tag = irq.ii_tag;
1991 axgbe_printf(1, "%s: channel count %d idx %d irq %d\n",
1992 __func__, scctx->isc_nrxqsets, i, rid);
1993 }
1994 pdata->irq_count = msix;
1995 pdata->channel_irq_count = scctx->isc_nrxqsets;
1996
1997 for (i = 0; i < scctx->isc_ntxqsets; i++) {
1998
1999 channel = pdata->channel[i];
2000
2001 snprintf(buf, sizeof(buf), "txq%d", i);
2002 irq.ii_res = channel->dma_irq_res;
2003 iflib_softirq_alloc_generic(ctx, &irq, IFLIB_INTR_TX, channel,
2004 channel->queue_index, buf);
2005 }
2006
2007 return (0);
2008 } /* axgbe_if_msix_intr_assign */
2009
2010 static int
xgbe_enable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2011 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2012 {
2013 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2014 enum xgbe_int int_id;
2015
2016 if (channel->tx_ring && channel->rx_ring)
2017 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2018 else if (channel->tx_ring)
2019 int_id = XGMAC_INT_DMA_CH_SR_TI;
2020 else if (channel->rx_ring)
2021 int_id = XGMAC_INT_DMA_CH_SR_RI;
2022 else
2023 return (-1);
2024
2025 axgbe_printf(1, "%s channel: %d rx_tx interrupt enabled %d\n",
2026 __func__, channel->queue_index, int_id);
2027 return (hw_if->enable_int(channel, int_id));
2028 }
2029
2030 static void
xgbe_disable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2031 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2032 {
2033 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2034 enum xgbe_int int_id;
2035
2036 if (channel->tx_ring && channel->rx_ring)
2037 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2038 else if (channel->tx_ring)
2039 int_id = XGMAC_INT_DMA_CH_SR_TI;
2040 else if (channel->rx_ring)
2041 int_id = XGMAC_INT_DMA_CH_SR_RI;
2042 else
2043 return;
2044
2045 axgbe_printf(1, "%s channel: %d rx_tx interrupt disabled %d\n",
2046 __func__, channel->queue_index, int_id);
2047 hw_if->disable_int(channel, int_id);
2048 }
2049
2050 static void
xgbe_disable_rx_tx_ints(struct xgbe_prv_data * pdata)2051 xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
2052 {
2053 unsigned int i;
2054
2055 for (i = 0; i < pdata->channel_count; i++)
2056 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
2057 }
2058
2059 static int
axgbe_msix_que(void * arg)2060 axgbe_msix_que(void *arg)
2061 {
2062 struct xgbe_channel *channel = (struct xgbe_channel *)arg;
2063 struct xgbe_prv_data *pdata = channel->pdata;
2064 unsigned int dma_status;
2065
2066 axgbe_printf(1, "%s: Channel: %d SR 0x%04x DSR 0x%04x IER:0x%04x D_ISR:0x%04x M_ISR:0x%04x\n",
2067 __func__, channel->queue_index,
2068 XGMAC_DMA_IOREAD(channel, DMA_CH_SR),
2069 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR),
2070 XGMAC_DMA_IOREAD(channel, DMA_CH_IER),
2071 XGMAC_IOREAD(pdata, DMA_ISR),
2072 XGMAC_IOREAD(pdata, MAC_ISR));
2073
2074 (void)XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2075
2076 /* Disable Tx and Rx channel interrupts */
2077 xgbe_disable_rx_tx_int(pdata, channel);
2078
2079 /* Clear the interrupts */
2080 dma_status = 0;
2081 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
2082 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
2083 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
2084
2085 return (FILTER_SCHEDULE_THREAD);
2086 }
2087
2088 static int
axgbe_dev_isr(void * arg)2089 axgbe_dev_isr(void *arg)
2090 {
2091 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2092 struct xgbe_prv_data *pdata = &sc->pdata;
2093 struct xgbe_channel *channel;
2094 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2095 unsigned int i, dma_isr, dma_ch_isr;
2096 unsigned int mac_isr, mac_mdioisr;
2097 int ret = FILTER_HANDLED;
2098
2099 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
2100 axgbe_printf(2, "%s DMA ISR: 0x%x\n", __func__, dma_isr);
2101
2102 if (!dma_isr)
2103 return (FILTER_HANDLED);
2104
2105 for (i = 0; i < pdata->channel_count; i++) {
2106
2107 if (!(dma_isr & (1 << i)))
2108 continue;
2109
2110 channel = pdata->channel[i];
2111
2112 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2113 axgbe_printf(2, "%s: channel %d SR 0x%x DSR 0x%x\n", __func__,
2114 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel,
2115 DMA_CH_DSR));
2116
2117 /*
2118 * The TI or RI interrupt bits may still be set even if using
2119 * per channel DMA interrupts. Check to be sure those are not
2120 * enabled before using the private data napi structure.
2121 */
2122 if (!pdata->per_channel_irq &&
2123 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
2124 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
2125
2126 /* Disable Tx and Rx interrupts */
2127 xgbe_disable_rx_tx_ints(pdata);
2128 } else {
2129
2130 /*
2131 * Don't clear Rx/Tx status if doing per channel DMA
2132 * interrupts, these will be cleared by the ISR for
2133 * per channel DMA interrupts
2134 */
2135 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
2136 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
2137 }
2138
2139 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
2140 pdata->ext_stats.rx_buffer_unavailable++;
2141
2142 /* Restart the device on a Fatal Bus Error */
2143 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
2144 axgbe_error("%s: Fatal bus error reported 0x%x\n",
2145 __func__, dma_ch_isr);
2146
2147 /* Clear all interrupt signals */
2148 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
2149
2150 ret = FILTER_SCHEDULE_THREAD;
2151 }
2152
2153 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
2154
2155 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
2156 axgbe_printf(2, "%s MAC ISR: 0x%x\n", __func__, mac_isr);
2157
2158 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
2159 hw_if->tx_mmc_int(pdata);
2160
2161 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
2162 hw_if->rx_mmc_int(pdata);
2163
2164 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
2165 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
2166
2167 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
2168 SNGLCOMPINT))
2169 wakeup_one(pdata);
2170 }
2171
2172 }
2173
2174 return (ret);
2175 } /* axgbe_dev_isr */
2176
2177 static void
axgbe_i2c_isr(void * arg)2178 axgbe_i2c_isr(void *arg)
2179 {
2180 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2181
2182 sc->pdata.i2c_if.i2c_isr(&sc->pdata);
2183 }
2184
2185 static void
axgbe_ecc_isr(void * arg)2186 axgbe_ecc_isr(void *arg)
2187 {
2188 /* TODO - implement */
2189 }
2190
2191 static void
axgbe_an_isr(void * arg)2192 axgbe_an_isr(void *arg)
2193 {
2194 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2195
2196 sc->pdata.phy_if.an_isr(&sc->pdata);
2197 }
2198
2199 static int
axgbe_if_tx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2200 axgbe_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2201 {
2202 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2203 struct xgbe_prv_data *pdata = &sc->pdata;
2204 int ret;
2205
2206 if (qid < pdata->tx_q_count) {
2207 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2208 if (ret) {
2209 axgbe_error("Enable TX INT failed\n");
2210 return (ret);
2211 }
2212 } else
2213 axgbe_error("Queue ID exceed channel count\n");
2214
2215 return (0);
2216 }
2217
2218 static int
axgbe_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2219 axgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2220 {
2221 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2222 struct xgbe_prv_data *pdata = &sc->pdata;
2223 int ret;
2224
2225 if (qid < pdata->rx_q_count) {
2226 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2227 if (ret) {
2228 axgbe_error("Enable RX INT failed\n");
2229 return (ret);
2230 }
2231 } else
2232 axgbe_error("Queue ID exceed channel count\n");
2233
2234 return (0);
2235 }
2236
2237 static void
axgbe_if_update_admin_status(if_ctx_t ctx)2238 axgbe_if_update_admin_status(if_ctx_t ctx)
2239 {
2240 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2241 struct xgbe_prv_data *pdata = &sc->pdata;
2242
2243 axgbe_printf(1, "%s: phy_link %d status %d speed %d\n", __func__,
2244 pdata->phy_link, sc->link_status, pdata->phy.speed);
2245
2246 if (pdata->phy_link < 0)
2247 return;
2248
2249 if (pdata->phy_link) {
2250 if (sc->link_status == LINK_STATE_DOWN) {
2251 sc->link_status = LINK_STATE_UP;
2252 if (pdata->phy.speed & SPEED_10000)
2253 iflib_link_state_change(ctx, LINK_STATE_UP,
2254 IF_Gbps(10));
2255 else if (pdata->phy.speed & SPEED_2500)
2256 iflib_link_state_change(ctx, LINK_STATE_UP,
2257 IF_Gbps(2.5));
2258 else if (pdata->phy.speed & SPEED_1000)
2259 iflib_link_state_change(ctx, LINK_STATE_UP,
2260 IF_Gbps(1));
2261 else if (pdata->phy.speed & SPEED_100)
2262 iflib_link_state_change(ctx, LINK_STATE_UP,
2263 IF_Mbps(100));
2264 else if (pdata->phy.speed & SPEED_10)
2265 iflib_link_state_change(ctx, LINK_STATE_UP,
2266 IF_Mbps(10));
2267 }
2268 } else {
2269 if (sc->link_status == LINK_STATE_UP) {
2270 sc->link_status = LINK_STATE_DOWN;
2271 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
2272 }
2273 }
2274 }
2275
2276 static int
axgbe_if_media_change(if_ctx_t ctx)2277 axgbe_if_media_change(if_ctx_t ctx)
2278 {
2279 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2280 struct ifmedia *ifm = iflib_get_media(ctx);
2281
2282 sx_xlock(&sc->pdata.an_mutex);
2283 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2284 return (EINVAL);
2285
2286 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2287 case IFM_10G_KR:
2288 sc->pdata.phy.speed = SPEED_10000;
2289 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2290 break;
2291 case IFM_2500_KX:
2292 sc->pdata.phy.speed = SPEED_2500;
2293 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2294 break;
2295 case IFM_1000_KX:
2296 sc->pdata.phy.speed = SPEED_1000;
2297 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2298 break;
2299 case IFM_100_TX:
2300 sc->pdata.phy.speed = SPEED_100;
2301 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2302 break;
2303 case IFM_AUTO:
2304 sc->pdata.phy.autoneg = AUTONEG_ENABLE;
2305 break;
2306 }
2307 sx_xunlock(&sc->pdata.an_mutex);
2308
2309 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata));
2310 }
2311
2312 static int
axgbe_if_promisc_set(if_ctx_t ctx,int flags)2313 axgbe_if_promisc_set(if_ctx_t ctx, int flags)
2314 {
2315 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2316 struct xgbe_prv_data *pdata = &sc->pdata;
2317 if_t ifp = pdata->netdev;
2318
2319 axgbe_printf(1, "%s: MAC_PFR 0x%x drv_flags 0x%x if_flags 0x%x\n",
2320 __func__, XGMAC_IOREAD(pdata, MAC_PFR), if_getdrvflags(ifp),
2321 if_getflags(ifp));
2322
2323 if (if_getflags(ifp) & IFF_PPROMISC) {
2324
2325 axgbe_printf(1, "User requested to enter promisc mode\n");
2326
2327 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 1) {
2328 axgbe_printf(1, "Already in promisc mode\n");
2329 return (0);
2330 }
2331
2332 axgbe_printf(1, "Entering promisc mode\n");
2333 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
2334 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
2335 } else {
2336
2337 axgbe_printf(1, "User requested to leave promisc mode\n");
2338
2339 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 0) {
2340 axgbe_printf(1, "Already not in promisc mode\n");
2341 return (0);
2342 }
2343
2344 axgbe_printf(1, "Leaving promisc mode\n");
2345 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
2346 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
2347 }
2348
2349 return (0);
2350 }
2351
2352 static uint64_t
axgbe_if_get_counter(if_ctx_t ctx,ift_counter cnt)2353 axgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt)
2354 {
2355 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2356 if_t ifp = iflib_get_ifp(ctx);
2357 struct xgbe_prv_data *pdata = &sc->pdata;
2358 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2359
2360 pdata->hw_if.read_mmc_stats(pdata);
2361
2362 switch(cnt) {
2363 case IFCOUNTER_IPACKETS:
2364 return (pstats->rxframecount_gb);
2365 case IFCOUNTER_IERRORS:
2366 return (pstats->rxframecount_gb - pstats->rxbroadcastframes_g -
2367 pstats->rxmulticastframes_g - pstats->rxunicastframes_g);
2368 case IFCOUNTER_OPACKETS:
2369 return (pstats->txframecount_gb);
2370 case IFCOUNTER_OERRORS:
2371 return (pstats->txframecount_gb - pstats->txframecount_g);
2372 case IFCOUNTER_IBYTES:
2373 return (pstats->rxoctetcount_gb);
2374 case IFCOUNTER_OBYTES:
2375 return (pstats->txoctetcount_gb);
2376 default:
2377 return (if_get_counter_default(ifp, cnt));
2378 }
2379 }
2380
2381 static int
axgbe_if_mtu_set(if_ctx_t ctx,uint32_t mtu)2382 axgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
2383 {
2384 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2385 struct xgbe_prv_data *pdata = &sc->pdata;
2386 int ret;
2387
2388 if (mtu > XGMAC_JUMBO_PACKET_MTU)
2389 return (EINVAL);
2390
2391 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu);
2392 pdata->rx_buf_size = ret;
2393 axgbe_printf(1, "%s: rx_buf_size %d\n", __func__, ret);
2394
2395 sc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2396 return (0);
2397 }
2398
2399 static void
axgbe_if_media_status(if_ctx_t ctx,struct ifmediareq * ifmr)2400 axgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
2401 {
2402 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2403 struct xgbe_prv_data *pdata = &sc->pdata;
2404
2405 ifmr->ifm_status = IFM_AVALID;
2406 if (!sc->pdata.phy.link)
2407 return;
2408
2409 ifmr->ifm_active = IFM_ETHER;
2410 ifmr->ifm_status |= IFM_ACTIVE;
2411
2412 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed,
2413 pdata->phy_if.phy_impl.cur_mode(pdata));
2414 pdata->phy_if.phy_impl.get_type(pdata, ifmr);
2415
2416 ifmr->ifm_active |= IFM_FDX;
2417 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2418 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2419 }
2420