1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
3 * All rights reserved.
4 */
5
6 #include <unistd.h>
7
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
14 #include <rte_io.h>
15
16 #include "bnxt.h"
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
19 #include "bnxt_rxq.h"
20 #include "bnxt_rxr.h"
21 #include "bnxt_ring.h"
22 #include "bnxt_txq.h"
23 #include "bnxt_txr.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
26
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
30 #define HWRM_VERSION_1_10_2_13 0x10a020d
31 struct bnxt_plcmodes_cfg {
32 uint32_t flags;
33 uint16_t jumbo_thresh;
34 uint16_t hds_offset;
35 uint16_t hds_threshold;
36 };
37
page_getenum(size_t size)38 static int page_getenum(size_t size)
39 {
40 if (size <= 1 << 4)
41 return 4;
42 if (size <= 1 << 12)
43 return 12;
44 if (size <= 1 << 13)
45 return 13;
46 if (size <= 1 << 16)
47 return 16;
48 if (size <= 1 << 21)
49 return 21;
50 if (size <= 1 << 22)
51 return 22;
52 if (size <= 1 << 30)
53 return 30;
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(int) * 8 - 1;
56 }
57
page_roundup(size_t size)58 static int page_roundup(size_t size)
59 {
60 return 1 << page_getenum(size);
61 }
62
bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info * rmem,uint8_t * pg_attr,uint64_t * pg_dir)63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
64 uint8_t *pg_attr,
65 uint64_t *pg_dir)
66 {
67 if (rmem->nr_pages == 0)
68 return;
69
70 if (rmem->nr_pages > 1) {
71 *pg_attr = 1;
72 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
73 } else {
74 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
75 }
76 }
77
78 static struct bnxt_cp_ring_info*
bnxt_get_ring_info_by_id(struct bnxt * bp,uint16_t rid,uint16_t type)79 bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
80 {
81 struct bnxt_cp_ring_info *cp_ring = NULL;
82 uint16_t i;
83
84 switch (type) {
85 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
86 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
87 /* FALLTHROUGH */
88 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
89 struct bnxt_rx_queue *rxq = bp->rx_queues[i];
90
91 if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
92 rte_cpu_to_le_16(rid)) {
93 return rxq->cp_ring;
94 }
95 }
96 break;
97 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
98 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
99 struct bnxt_tx_queue *txq = bp->tx_queues[i];
100
101 if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
102 rte_cpu_to_le_16(rid)) {
103 return txq->cp_ring;
104 }
105 }
106 break;
107 default:
108 return cp_ring;
109 }
110 return cp_ring;
111 }
112
113 /* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
114 * If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
115 * before timeout, we force the done bit for the cleanup to proceed.
116 * Also if cpr is null, do nothing.. The HWRM command is not for a
117 * Tx/Rx/AGG ring cleanup.
118 */
119 static int
bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info * cpr,bool tx,bool rx,bool timeout)120 bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
121 bool tx, bool rx, bool timeout)
122 {
123 int done = 0;
124
125 if (cpr != NULL) {
126 if (tx)
127 done = bnxt_flush_tx_cmp(cpr);
128
129 if (rx)
130 done = bnxt_flush_rx_cmp(cpr);
131
132 if (done)
133 PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
134 rx ? "Rx" : "Tx");
135
136 /* We are about to timeout and still haven't seen the
137 * HWRM done for the Ring free. Force the cleanup.
138 */
139 if (!done && timeout) {
140 done = 1;
141 PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
142 rx ? "Rx" : "Tx");
143 }
144 } else {
145 /* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
146 * Otherwise the cpr would have been valid. So do nothing.
147 */
148 done = 1;
149 }
150
151 return done;
152 }
153
154 /*
155 * HWRM Functions (sent to HWRM)
156 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
157 * HWRM command times out, or a negative error code if the HWRM
158 * command was failed by the FW.
159 */
160
bnxt_hwrm_send_message(struct bnxt * bp,void * msg,uint32_t msg_len,bool use_kong_mb)161 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
162 uint32_t msg_len, bool use_kong_mb)
163 {
164 unsigned int i;
165 struct input *req = msg;
166 struct output *resp = bp->hwrm_cmd_resp_addr;
167 uint32_t *data = msg;
168 uint8_t *bar;
169 uint8_t *valid;
170 uint16_t max_req_len = bp->max_req_len;
171 struct hwrm_short_input short_input = { 0 };
172 uint16_t bar_offset = use_kong_mb ?
173 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
174 uint16_t mb_trigger_offset = use_kong_mb ?
175 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
176 struct bnxt_cp_ring_info *cpr = NULL;
177 bool is_rx = false;
178 bool is_tx = false;
179 uint32_t timeout;
180
181 /* Do not send HWRM commands to firmware in error state */
182 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
183 return 0;
184
185 timeout = bp->hwrm_cmd_timeout;
186
187 /* Update the message length for backing store config for new FW. */
188 if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
189 rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
190 msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
191
192 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
193 msg_len > bp->max_req_len) {
194 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
195
196 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
197 memcpy(short_cmd_req, req, msg_len);
198
199 short_input.req_type = rte_cpu_to_le_16(req->req_type);
200 short_input.signature = rte_cpu_to_le_16(
201 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
202 short_input.size = rte_cpu_to_le_16(msg_len);
203 short_input.req_addr =
204 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
205
206 data = (uint32_t *)&short_input;
207 msg_len = sizeof(short_input);
208
209 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
210 }
211
212 /* Write request msg to hwrm channel */
213 for (i = 0; i < msg_len; i += 4) {
214 bar = (uint8_t *)bp->bar0 + bar_offset + i;
215 rte_write32(*data, bar);
216 data++;
217 }
218
219 /* Zero the rest of the request space */
220 for (; i < max_req_len; i += 4) {
221 bar = (uint8_t *)bp->bar0 + bar_offset + i;
222 rte_write32(0, bar);
223 }
224
225 /* Ring channel doorbell */
226 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
227 rte_write32(1, bar);
228 /*
229 * Make sure the channel doorbell ring command complete before
230 * reading the response to avoid getting stale or invalid
231 * responses.
232 */
233 rte_io_mb();
234
235 /* Check ring flush is done.
236 * This is valid only for Tx and Rx rings (including AGG rings).
237 * The Tx and Rx rings should be freed once the HW confirms all
238 * the internal buffers and BDs associated with the rings are
239 * consumed and the corresponding DMA is handled.
240 */
241 if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
242 /* Check if the TxCQ matches. If that fails check if RxCQ
243 * matches. And if neither match, is_rx = false, is_tx = false.
244 */
245 cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
246 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
247 if (cpr == NULL) {
248 /* Not a TxCQ. Check if the RxCQ matches. */
249 cpr =
250 bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
251 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
252 if (cpr != NULL)
253 is_rx = true;
254 } else {
255 is_tx = true;
256 }
257 }
258
259 /* Poll for the valid bit */
260 for (i = 0; i < timeout; i++) {
261 int done;
262
263 done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
264 i == timeout - 1);
265 /* Sanity check on the resp->resp_len */
266 rte_io_rmb();
267 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
268 /* Last byte of resp contains the valid key */
269 valid = (uint8_t *)resp + resp->resp_len - 1;
270 if (*valid == HWRM_RESP_VALID_KEY && done)
271 break;
272 }
273 rte_delay_us(1);
274 }
275
276 if (i >= timeout) {
277 /* Suppress VER_GET timeout messages during reset recovery */
278 if (bp->flags & BNXT_FLAG_FW_RESET &&
279 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
280 return -ETIMEDOUT;
281
282 PMD_DRV_LOG(ERR,
283 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
284 req->req_type, req->seq_id);
285 return -ETIMEDOUT;
286 }
287 return 0;
288 }
289
290 /*
291 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
292 * spinlock, and does initial processing.
293 *
294 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
295 * releases the spinlock only if it returns. If the regular int return codes
296 * are not used by the function, HWRM_CHECK_RESULT() should not be used
297 * directly, rather it should be copied and modified to suit the function.
298 *
299 * HWRM_UNLOCK() must be called after all response processing is completed.
300 */
301 #define HWRM_PREP(req, type, kong) do { \
302 rte_spinlock_lock(&bp->hwrm_lock); \
303 if (bp->hwrm_cmd_resp_addr == NULL) { \
304 rte_spinlock_unlock(&bp->hwrm_lock); \
305 return -EACCES; \
306 } \
307 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
308 (req)->req_type = rte_cpu_to_le_16(type); \
309 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
310 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
311 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
312 (req)->target_id = rte_cpu_to_le_16(0xffff); \
313 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
314 } while (0)
315
316 #define HWRM_CHECK_RESULT_SILENT() do {\
317 if (rc) { \
318 rte_spinlock_unlock(&bp->hwrm_lock); \
319 return rc; \
320 } \
321 if (resp->error_code) { \
322 rc = rte_le_to_cpu_16(resp->error_code); \
323 rte_spinlock_unlock(&bp->hwrm_lock); \
324 return rc; \
325 } \
326 } while (0)
327
328 #define HWRM_CHECK_RESULT() do {\
329 if (rc) { \
330 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
331 rte_spinlock_unlock(&bp->hwrm_lock); \
332 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
333 rc = -EACCES; \
334 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
335 rc = -ENOSPC; \
336 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
337 rc = -EINVAL; \
338 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
339 rc = -ENOTSUP; \
340 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
341 rc = -EAGAIN; \
342 else if (rc > 0) \
343 rc = -EIO; \
344 return rc; \
345 } \
346 if (resp->error_code) { \
347 rc = rte_le_to_cpu_16(resp->error_code); \
348 if (resp->resp_len >= 16) { \
349 struct hwrm_err_output *tmp_hwrm_err_op = \
350 (void *)resp; \
351 PMD_DRV_LOG(ERR, \
352 "error %d:%d:%08x:%04x\n", \
353 rc, tmp_hwrm_err_op->cmd_err, \
354 rte_le_to_cpu_32(\
355 tmp_hwrm_err_op->opaque_0), \
356 rte_le_to_cpu_16(\
357 tmp_hwrm_err_op->opaque_1)); \
358 } else { \
359 PMD_DRV_LOG(ERR, "error %d\n", rc); \
360 } \
361 rte_spinlock_unlock(&bp->hwrm_lock); \
362 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
363 rc = -EACCES; \
364 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
365 rc = -ENOSPC; \
366 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
367 rc = -EINVAL; \
368 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
369 rc = -ENOTSUP; \
370 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
371 rc = -EAGAIN; \
372 else if (rc > 0) \
373 rc = -EIO; \
374 return rc; \
375 } \
376 } while (0)
377
378 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
379
bnxt_hwrm_tf_message_direct(struct bnxt * bp,bool use_kong_mb,uint16_t msg_type,void * msg,uint32_t msg_len,void * resp_msg,uint32_t resp_len)380 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
381 bool use_kong_mb,
382 uint16_t msg_type,
383 void *msg,
384 uint32_t msg_len,
385 void *resp_msg,
386 uint32_t resp_len)
387 {
388 int rc = 0;
389 bool mailbox = BNXT_USE_CHIMP_MB;
390 struct input *req = msg;
391 struct output *resp = bp->hwrm_cmd_resp_addr;
392
393 if (use_kong_mb)
394 mailbox = BNXT_USE_KONG(bp);
395
396 HWRM_PREP(req, msg_type, mailbox);
397
398 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
399
400 HWRM_CHECK_RESULT();
401
402 if (resp_msg)
403 memcpy(resp_msg, resp, resp_len);
404
405 HWRM_UNLOCK();
406
407 return rc;
408 }
409
bnxt_hwrm_tf_message_tunneled(struct bnxt * bp,bool use_kong_mb,uint16_t tf_type,uint16_t tf_subtype,uint32_t * tf_response_code,void * msg,uint32_t msg_len,void * response,uint32_t response_len)410 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
411 bool use_kong_mb,
412 uint16_t tf_type,
413 uint16_t tf_subtype,
414 uint32_t *tf_response_code,
415 void *msg,
416 uint32_t msg_len,
417 void *response,
418 uint32_t response_len)
419 {
420 int rc = 0;
421 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
422 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
423 bool mailbox = BNXT_USE_CHIMP_MB;
424
425 if (msg_len > sizeof(req.tf_req))
426 return -ENOMEM;
427
428 if (use_kong_mb)
429 mailbox = BNXT_USE_KONG(bp);
430
431 HWRM_PREP(&req, HWRM_TF, mailbox);
432 /* Build request using the user supplied request payload.
433 * TLV request size is checked at build time against HWRM
434 * request max size, thus no checking required.
435 */
436 req.tf_type = tf_type;
437 req.tf_subtype = tf_subtype;
438 memcpy(req.tf_req, msg, msg_len);
439
440 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
441 HWRM_CHECK_RESULT();
442
443 /* Copy the resp to user provided response buffer */
444 if (response != NULL)
445 /* Post process response data. We need to copy only
446 * the 'payload' as the HWRM data structure really is
447 * HWRM header + msg header + payload and the TFLIB
448 * only provided a payload place holder.
449 */
450 if (response_len != 0) {
451 memcpy(response,
452 resp->tf_resp,
453 response_len);
454 }
455
456 /* Extract the internal tflib response code */
457 *tf_response_code = resp->tf_resp_code;
458 HWRM_UNLOCK();
459
460 return rc;
461 }
462
bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt * bp,struct bnxt_vnic_info * vnic)463 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
464 {
465 int rc = 0;
466 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
467 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
468
469 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
470 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
471 req.mask = 0;
472
473 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
474
475 HWRM_CHECK_RESULT();
476 HWRM_UNLOCK();
477
478 return rc;
479 }
480
bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt * bp,struct bnxt_vnic_info * vnic,uint16_t vlan_count,struct bnxt_vlan_table_entry * vlan_table)481 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
482 struct bnxt_vnic_info *vnic,
483 uint16_t vlan_count,
484 struct bnxt_vlan_table_entry *vlan_table)
485 {
486 int rc = 0;
487 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
488 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
489 uint32_t mask = 0;
490
491 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
492 return rc;
493
494 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
495 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
496
497 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
498 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
499 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
500 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
501
502 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
503 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
504
505 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
506 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
507 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
508 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
509 req.num_mc_entries = rte_cpu_to_le_32(bp->nb_mc_addr);
510 req.mc_tbl_addr = rte_cpu_to_le_64(bp->mc_list_dma_addr);
511 }
512 if (vlan_table) {
513 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
514 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
515 req.vlan_tag_tbl_addr =
516 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
517 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
518 }
519 req.mask = rte_cpu_to_le_32(mask);
520
521 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
522
523 HWRM_CHECK_RESULT();
524 HWRM_UNLOCK();
525
526 return rc;
527 }
528
bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt * bp,uint16_t fid,uint16_t vlan_count,struct bnxt_vlan_antispoof_table_entry * vlan_table)529 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
530 uint16_t vlan_count,
531 struct bnxt_vlan_antispoof_table_entry *vlan_table)
532 {
533 int rc = 0;
534 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
535 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
536 bp->hwrm_cmd_resp_addr;
537
538 /*
539 * Older HWRM versions did not support this command, and the set_rx_mask
540 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
541 * removed from set_rx_mask call, and this command was added.
542 *
543 * This command is also present from 1.7.8.11 and higher,
544 * as well as 1.7.8.0
545 */
546 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
547 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
548 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
549 (11)))
550 return 0;
551 }
552 }
553 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
554 req.fid = rte_cpu_to_le_16(fid);
555
556 req.vlan_tag_mask_tbl_addr =
557 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
558 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
559
560 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
561
562 HWRM_CHECK_RESULT();
563 HWRM_UNLOCK();
564
565 return rc;
566 }
567
bnxt_hwrm_clear_l2_filter(struct bnxt * bp,struct bnxt_filter_info * filter)568 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
569 struct bnxt_filter_info *filter)
570 {
571 int rc = 0;
572 struct bnxt_filter_info *l2_filter = filter;
573 struct bnxt_vnic_info *vnic = NULL;
574 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
575 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
576
577 if (filter->fw_l2_filter_id == UINT64_MAX)
578 return 0;
579
580 if (filter->matching_l2_fltr_ptr)
581 l2_filter = filter->matching_l2_fltr_ptr;
582
583 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
584 filter, l2_filter, l2_filter->l2_ref_cnt);
585
586 if (l2_filter->l2_ref_cnt == 0)
587 return 0;
588
589 if (l2_filter->l2_ref_cnt > 0)
590 l2_filter->l2_ref_cnt--;
591
592 if (l2_filter->l2_ref_cnt > 0)
593 return 0;
594
595 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
596
597 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
598
599 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
600
601 HWRM_CHECK_RESULT();
602 HWRM_UNLOCK();
603
604 filter->fw_l2_filter_id = UINT64_MAX;
605 if (l2_filter->l2_ref_cnt == 0) {
606 vnic = l2_filter->vnic;
607 if (vnic) {
608 STAILQ_REMOVE(&vnic->filter, l2_filter,
609 bnxt_filter_info, next);
610 bnxt_free_filter(bp, l2_filter);
611 }
612 }
613
614 return 0;
615 }
616
bnxt_hwrm_set_l2_filter(struct bnxt * bp,uint16_t dst_id,struct bnxt_filter_info * filter)617 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
618 uint16_t dst_id,
619 struct bnxt_filter_info *filter)
620 {
621 int rc = 0;
622 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
623 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
624 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
625 const struct rte_eth_vmdq_rx_conf *conf =
626 &dev_conf->rx_adv_conf.vmdq_rx_conf;
627 uint32_t enables = 0;
628 uint16_t j = dst_id - 1;
629
630 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
631 if ((dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) &&
632 conf->pool_map[j].pools & (1UL << j)) {
633 PMD_DRV_LOG(DEBUG,
634 "Add vlan %u to vmdq pool %u\n",
635 conf->pool_map[j].vlan_id, j);
636
637 filter->l2_ivlan = conf->pool_map[j].vlan_id;
638 filter->enables |=
639 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
640 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
641 }
642
643 if (filter->fw_l2_filter_id != UINT64_MAX)
644 bnxt_hwrm_clear_l2_filter(bp, filter);
645
646 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
647
648 /* PMD does not support XDP and RoCE */
649 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
650 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
651 req.flags = rte_cpu_to_le_32(filter->flags);
652
653 enables = filter->enables |
654 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
655 req.dst_id = rte_cpu_to_le_16(dst_id);
656
657 if (enables &
658 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
659 memcpy(req.l2_addr, filter->l2_addr,
660 RTE_ETHER_ADDR_LEN);
661 if (enables &
662 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
663 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
664 RTE_ETHER_ADDR_LEN);
665 if (enables &
666 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
667 req.l2_ovlan = filter->l2_ovlan;
668 if (enables &
669 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
670 req.l2_ivlan = filter->l2_ivlan;
671 if (enables &
672 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
673 req.l2_ovlan_mask = filter->l2_ovlan_mask;
674 if (enables &
675 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
676 req.l2_ivlan_mask = filter->l2_ivlan_mask;
677 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
678 req.src_id = rte_cpu_to_le_32(filter->src_id);
679 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
680 req.src_type = filter->src_type;
681 if (filter->pri_hint) {
682 req.pri_hint = filter->pri_hint;
683 req.l2_filter_id_hint =
684 rte_cpu_to_le_64(filter->l2_filter_id_hint);
685 }
686
687 req.enables = rte_cpu_to_le_32(enables);
688
689 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
690
691 HWRM_CHECK_RESULT();
692
693 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
694 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
695 HWRM_UNLOCK();
696
697 filter->l2_ref_cnt++;
698
699 return rc;
700 }
701
bnxt_hwrm_ptp_cfg(struct bnxt * bp)702 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
703 {
704 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
705 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
706 uint32_t flags = 0;
707 int rc;
708
709 if (!ptp)
710 return 0;
711
712 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
713
714 if (ptp->rx_filter)
715 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
716 else
717 flags |=
718 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
719 if (ptp->tx_tstamp_en)
720 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
721 else
722 flags |=
723 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
724 req.flags = rte_cpu_to_le_32(flags);
725 req.enables = rte_cpu_to_le_32
726 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
727 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
728
729 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
730 HWRM_UNLOCK();
731
732 return rc;
733 }
734
bnxt_hwrm_ptp_qcfg(struct bnxt * bp)735 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
736 {
737 int rc = 0;
738 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
739 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
740 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
741
742 if (ptp)
743 return 0;
744
745 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
746
747 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
748
749 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
750
751 HWRM_CHECK_RESULT();
752
753 if (BNXT_CHIP_P5(bp)) {
754 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
755 return 0;
756 } else {
757 if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
758 return 0;
759 }
760
761 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
762 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
763
764 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
765 if (!ptp)
766 return -ENOMEM;
767
768 if (!BNXT_CHIP_P5(bp)) {
769 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
770 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
771 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
772 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
773 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
774 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
775 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
776 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
777 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
778 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
779 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
780 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
781 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
782 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
783 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
784 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
785 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
786 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
787 }
788
789 ptp->bp = bp;
790 bp->ptp_cfg = ptp;
791
792 return 0;
793 }
794
bnxt_free_vf_info(struct bnxt * bp)795 void bnxt_free_vf_info(struct bnxt *bp)
796 {
797 int i;
798
799 if (bp->pf == NULL)
800 return;
801
802 if (bp->pf->vf_info == NULL)
803 return;
804
805 for (i = 0; i < bp->pf->max_vfs; i++) {
806 rte_free(bp->pf->vf_info[i].vlan_table);
807 bp->pf->vf_info[i].vlan_table = NULL;
808 rte_free(bp->pf->vf_info[i].vlan_as_table);
809 bp->pf->vf_info[i].vlan_as_table = NULL;
810 }
811 rte_free(bp->pf->vf_info);
812 bp->pf->vf_info = NULL;
813 }
814
bnxt_alloc_vf_info(struct bnxt * bp,uint16_t max_vfs)815 static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
816 {
817 struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
818 int i;
819
820 if (vf_info)
821 bnxt_free_vf_info(bp);
822
823 vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
824 if (vf_info == NULL) {
825 PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
826 return -ENOMEM;
827 }
828
829 bp->pf->max_vfs = max_vfs;
830 for (i = 0; i < max_vfs; i++) {
831 vf_info[i].fid = bp->pf->first_vf_id + i;
832 vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
833 getpagesize(), getpagesize());
834 if (vf_info[i].vlan_table == NULL) {
835 PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
836 goto err;
837 }
838 rte_mem_lock_page(vf_info[i].vlan_table);
839
840 vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
841 getpagesize(), getpagesize());
842 if (vf_info[i].vlan_as_table == NULL) {
843 PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
844 goto err;
845 }
846 rte_mem_lock_page(vf_info[i].vlan_as_table);
847
848 STAILQ_INIT(&vf_info[i].filter);
849 }
850
851 bp->pf->vf_info = vf_info;
852
853 return 0;
854 err:
855 bnxt_free_vf_info(bp);
856 return -ENOMEM;
857 }
858
__bnxt_hwrm_func_qcaps(struct bnxt * bp)859 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
860 {
861 int rc = 0;
862 struct hwrm_func_qcaps_input req = {.req_type = 0 };
863 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
864 uint16_t new_max_vfs;
865 uint32_t flags;
866
867 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
868
869 req.fid = rte_cpu_to_le_16(0xffff);
870
871 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
872
873 HWRM_CHECK_RESULT();
874
875 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
876 flags = rte_le_to_cpu_32(resp->flags);
877 if (BNXT_PF(bp)) {
878 bp->pf->port_id = resp->port_id;
879 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
880 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
881 new_max_vfs = bp->pdev->max_vfs;
882 if (new_max_vfs != bp->pf->max_vfs) {
883 rc = bnxt_alloc_vf_info(bp, new_max_vfs);
884 if (rc)
885 goto unlock;
886 }
887 }
888
889 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
890 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
891 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
892 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
893 } else {
894 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
895 }
896 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
897 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
898 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
899 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
900 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
901 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
902 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
903 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
904 bp->max_l2_ctx += bp->max_rx_em_flows;
905 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
906 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
907 bp->max_l2_ctx, bp->max_vnics);
908 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
909 bp->max_mcast_addr = rte_le_to_cpu_32(resp->max_mcast_filters);
910
911 if (BNXT_PF(bp)) {
912 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
913 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
914 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
915 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
916 HWRM_UNLOCK();
917 bnxt_hwrm_ptp_qcfg(bp);
918 }
919 }
920
921 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
922 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
923
924 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
925 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
926 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
927 }
928
929 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
930 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
931
932 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
933 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
934
935 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
936 bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
937
938 if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) {
939 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
940 PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
941 }
942
943 bp->tunnel_disable_flag = rte_le_to_cpu_16(resp->tunnel_disable_flag);
944 if (bp->tunnel_disable_flag)
945 PMD_DRV_LOG(DEBUG, "Tunnel parsing capability is disabled, flags : %#x\n",
946 bp->tunnel_disable_flag);
947 unlock:
948 HWRM_UNLOCK();
949
950 return rc;
951 }
952
bnxt_hwrm_func_qcaps(struct bnxt * bp)953 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
954 {
955 int rc;
956
957 rc = __bnxt_hwrm_func_qcaps(bp);
958 if (rc == -ENOMEM)
959 return rc;
960
961 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
962 rc = bnxt_alloc_ctx_mem(bp);
963 if (rc)
964 return rc;
965
966 /* On older FW,
967 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
968 * But the error can be ignored. Return success.
969 */
970 rc = bnxt_hwrm_func_resc_qcaps(bp);
971 if (!rc)
972 bp->flags |= BNXT_FLAG_NEW_RM;
973 }
974
975 return 0;
976 }
977
978 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
bnxt_hwrm_vnic_qcaps(struct bnxt * bp)979 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
980 {
981 int rc = 0;
982 uint32_t flags;
983 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
984 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
985
986 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
987
988 req.target_id = rte_cpu_to_le_16(0xffff);
989
990 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
991
992 HWRM_CHECK_RESULT();
993
994 flags = rte_le_to_cpu_32(resp->flags);
995
996 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
997 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
998 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
999 }
1000
1001 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP)
1002 bp->vnic_cap_flags |= BNXT_VNIC_CAP_OUTER_RSS;
1003
1004 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP)
1005 bp->vnic_cap_flags |= BNXT_VNIC_CAP_RX_CMPL_V2;
1006
1007 if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP) {
1008 bp->vnic_cap_flags |= BNXT_VNIC_CAP_VLAN_RX_STRIP;
1009 PMD_DRV_LOG(DEBUG, "Rx VLAN strip capability enabled\n");
1010 }
1011
1012 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
1013
1014 HWRM_UNLOCK();
1015
1016 return rc;
1017 }
1018
bnxt_hwrm_func_reset(struct bnxt * bp)1019 int bnxt_hwrm_func_reset(struct bnxt *bp)
1020 {
1021 int rc = 0;
1022 struct hwrm_func_reset_input req = {.req_type = 0 };
1023 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
1024
1025 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
1026
1027 req.enables = rte_cpu_to_le_32(0);
1028
1029 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1030
1031 HWRM_CHECK_RESULT();
1032 HWRM_UNLOCK();
1033
1034 return rc;
1035 }
1036
bnxt_hwrm_func_driver_register(struct bnxt * bp)1037 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
1038 {
1039 int rc;
1040 uint32_t flags = 0;
1041 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
1042 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
1043
1044 if (bp->flags & BNXT_FLAG_REGISTERED)
1045 return 0;
1046
1047 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
1048 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
1049 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1050 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
1051
1052 /* PFs and trusted VFs should indicate the support of the
1053 * Master capability on non Stingray platform
1054 */
1055 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
1056 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
1057
1058 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
1059 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
1060 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
1061 req.ver_maj_8b = RTE_VER_YEAR;
1062 req.ver_min_8b = RTE_VER_MONTH;
1063 req.ver_upd_8b = RTE_VER_MINOR;
1064
1065 if (BNXT_PF(bp)) {
1066 req.enables |= rte_cpu_to_le_32(
1067 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
1068 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
1069 RTE_MIN(sizeof(req.vf_req_fwd),
1070 sizeof(bp->pf->vf_req_fwd)));
1071 }
1072
1073 req.flags = rte_cpu_to_le_32(flags);
1074
1075 req.async_event_fwd[0] |=
1076 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
1077 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
1078 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
1079 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
1080 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
1081 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
1082 req.async_event_fwd[0] |=
1083 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
1084 req.async_event_fwd[1] |=
1085 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
1086 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
1087 if (BNXT_PF(bp))
1088 req.async_event_fwd[1] |=
1089 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
1090
1091 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))
1092 req.async_event_fwd[1] |=
1093 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE);
1094
1095 req.async_event_fwd[2] |=
1096 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ECHO_REQUEST |
1097 ASYNC_CMPL_EVENT_ID_ERROR_REPORT);
1098
1099 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1100
1101 HWRM_CHECK_RESULT();
1102
1103 flags = rte_le_to_cpu_32(resp->flags);
1104 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
1105 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
1106
1107 HWRM_UNLOCK();
1108
1109 bp->flags |= BNXT_FLAG_REGISTERED;
1110
1111 return rc;
1112 }
1113
bnxt_hwrm_check_vf_rings(struct bnxt * bp)1114 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
1115 {
1116 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
1117 return 0;
1118
1119 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
1120 }
1121
bnxt_hwrm_func_reserve_vf_resc(struct bnxt * bp,bool test)1122 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
1123 {
1124 int rc;
1125 uint32_t flags = 0;
1126 uint32_t enables;
1127 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1128 struct hwrm_func_vf_cfg_input req = {0};
1129
1130 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
1131
1132 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
1133 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
1134 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
1135 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
1136 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
1137
1138 if (BNXT_HAS_RING_GRPS(bp)) {
1139 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
1140 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
1141 }
1142
1143 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
1144 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
1145 AGG_RING_MULTIPLIER);
1146 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
1147 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
1148 bp->tx_nr_rings +
1149 BNXT_NUM_ASYNC_CPR(bp));
1150 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
1151 if (bp->vf_resv_strategy ==
1152 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
1153 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
1154 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
1155 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1156 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
1157 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
1158 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
1159 } else if (bp->vf_resv_strategy ==
1160 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
1161 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
1162 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
1163 }
1164
1165 if (test)
1166 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
1167 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
1168 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
1169 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
1170 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
1171 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
1172
1173 if (test && BNXT_HAS_RING_GRPS(bp))
1174 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
1175
1176 req.flags = rte_cpu_to_le_32(flags);
1177 req.enables |= rte_cpu_to_le_32(enables);
1178
1179 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1180
1181 if (test)
1182 HWRM_CHECK_RESULT_SILENT();
1183 else
1184 HWRM_CHECK_RESULT();
1185
1186 HWRM_UNLOCK();
1187 return rc;
1188 }
1189
bnxt_hwrm_func_resc_qcaps(struct bnxt * bp)1190 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1191 {
1192 int rc;
1193 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1194 struct hwrm_func_resource_qcaps_input req = {0};
1195
1196 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1197 req.fid = rte_cpu_to_le_16(0xffff);
1198
1199 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1200
1201 HWRM_CHECK_RESULT_SILENT();
1202
1203 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1204 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1205 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1206 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1207 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1208 /* func_resource_qcaps does not return max_rx_em_flows.
1209 * So use the value provided by func_qcaps.
1210 */
1211 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1212 if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
1213 bp->max_l2_ctx += bp->max_rx_em_flows;
1214 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1215 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1216 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1217 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1218 if (bp->vf_resv_strategy >
1219 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1220 bp->vf_resv_strategy =
1221 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1222
1223 HWRM_UNLOCK();
1224 return rc;
1225 }
1226
bnxt_hwrm_ver_get(struct bnxt * bp,uint32_t timeout)1227 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1228 {
1229 int rc = 0;
1230 struct hwrm_ver_get_input req = {.req_type = 0 };
1231 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1232 uint32_t fw_version;
1233 uint16_t max_resp_len;
1234 char type[RTE_MEMZONE_NAMESIZE];
1235 uint32_t dev_caps_cfg;
1236
1237 bp->max_req_len = HWRM_MAX_REQ_LEN;
1238 bp->hwrm_cmd_timeout = timeout;
1239 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1240
1241 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1242 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1243 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1244
1245 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1246
1247 if (bp->flags & BNXT_FLAG_FW_RESET)
1248 HWRM_CHECK_RESULT_SILENT();
1249 else
1250 HWRM_CHECK_RESULT();
1251
1252 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY) {
1253 rc = -EAGAIN;
1254 goto error;
1255 }
1256
1257 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d.%d\n",
1258 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1259 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1260 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b,
1261 resp->hwrm_fw_rsvd_8b);
1262 bp->fw_ver = ((uint32_t)resp->hwrm_fw_maj_8b << 24) |
1263 ((uint32_t)resp->hwrm_fw_min_8b << 16) |
1264 ((uint32_t)resp->hwrm_fw_bld_8b << 8) |
1265 resp->hwrm_fw_rsvd_8b;
1266 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1267 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1268
1269 fw_version = resp->hwrm_intf_maj_8b << 16;
1270 fw_version |= resp->hwrm_intf_min_8b << 8;
1271 fw_version |= resp->hwrm_intf_upd_8b;
1272 bp->hwrm_spec_code = fw_version;
1273
1274 /* def_req_timeout value is in milliseconds */
1275 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1276 /* convert timeout to usec */
1277 bp->hwrm_cmd_timeout *= 1000;
1278 if (!bp->hwrm_cmd_timeout)
1279 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1280
1281 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1282 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1283 rc = -EINVAL;
1284 goto error;
1285 }
1286
1287 if (bp->max_req_len > resp->max_req_win_len) {
1288 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1289 rc = -EINVAL;
1290 goto error;
1291 }
1292
1293 bp->chip_num = rte_le_to_cpu_16(resp->chip_num);
1294
1295 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1296 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1297 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1298 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1299
1300 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1301 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1302
1303 RTE_VERIFY(max_resp_len <= bp->max_resp_len);
1304 bp->max_resp_len = max_resp_len;
1305
1306 if ((dev_caps_cfg &
1307 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1308 (dev_caps_cfg &
1309 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1310 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1311 bp->flags |= BNXT_FLAG_SHORT_CMD;
1312 }
1313
1314 if (((dev_caps_cfg &
1315 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1316 (dev_caps_cfg &
1317 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1318 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1319 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1320 bp->pdev->addr.domain, bp->pdev->addr.bus,
1321 bp->pdev->addr.devid, bp->pdev->addr.function);
1322
1323 rte_free(bp->hwrm_short_cmd_req_addr);
1324
1325 bp->hwrm_short_cmd_req_addr =
1326 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1327 if (bp->hwrm_short_cmd_req_addr == NULL) {
1328 rc = -ENOMEM;
1329 goto error;
1330 }
1331 bp->hwrm_short_cmd_req_dma_addr =
1332 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1333 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1334 rte_free(bp->hwrm_short_cmd_req_addr);
1335 PMD_DRV_LOG(ERR,
1336 "Unable to map buffer to physical memory.\n");
1337 rc = -ENOMEM;
1338 goto error;
1339 }
1340 }
1341 if (dev_caps_cfg &
1342 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1343 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1344 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1345 }
1346 if (dev_caps_cfg &
1347 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1348 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1349 if (dev_caps_cfg &
1350 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1351 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1352 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1353 }
1354
1355 if (dev_caps_cfg &
1356 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1357 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1358 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1359 }
1360
1361 if (dev_caps_cfg &
1362 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED) {
1363 PMD_DRV_LOG(DEBUG, "Host-based truflow feature enabled.\n");
1364 bp->fw_cap |= BNXT_FW_CAP_TRUFLOW_EN;
1365 }
1366
1367 error:
1368 HWRM_UNLOCK();
1369 return rc;
1370 }
1371
bnxt_hwrm_func_driver_unregister(struct bnxt * bp)1372 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp)
1373 {
1374 int rc;
1375 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1376 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1377
1378 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1379 return 0;
1380
1381 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1382
1383 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1384
1385 HWRM_CHECK_RESULT();
1386 HWRM_UNLOCK();
1387
1388 PMD_DRV_LOG(DEBUG, "Port %u: Unregistered with fw\n",
1389 bp->eth_dev->data->port_id);
1390
1391 return rc;
1392 }
1393
bnxt_hwrm_port_phy_cfg(struct bnxt * bp,struct bnxt_link_info * conf)1394 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1395 {
1396 int rc = 0;
1397 struct hwrm_port_phy_cfg_input req = {0};
1398 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1399 uint32_t enables = 0;
1400
1401 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1402
1403 if (conf->link_up) {
1404 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1405 if (bp->link_info->auto_mode && conf->link_speed) {
1406 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1407 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1408 }
1409
1410 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1411 /*
1412 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1413 * any auto mode, even "none".
1414 */
1415 if (!conf->link_speed) {
1416 /* No speeds specified. Enable AutoNeg - all speeds */
1417 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1418 req.auto_mode =
1419 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1420 } else {
1421 if (bp->link_info->link_signal_mode) {
1422 enables |=
1423 HWRM_PORT_PHY_CFG_IN_EN_FORCE_PAM4_LINK_SPEED;
1424 req.force_pam4_link_speed =
1425 rte_cpu_to_le_16(conf->link_speed);
1426 } else {
1427 req.force_link_speed =
1428 rte_cpu_to_le_16(conf->link_speed);
1429 }
1430 }
1431 /* AutoNeg - Advertise speeds specified. */
1432 if ((conf->auto_link_speed_mask || conf->auto_pam4_link_speed_mask) &&
1433 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1434 req.auto_mode =
1435 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1436 if (conf->auto_pam4_link_speed_mask) {
1437 enables |=
1438 HWRM_PORT_PHY_CFG_IN_EN_AUTO_PAM4_LINK_SPD_MASK;
1439 req.auto_link_pam4_speed_mask =
1440 rte_cpu_to_le_16(conf->auto_pam4_link_speed_mask);
1441 }
1442 if (conf->auto_link_speed_mask) {
1443 enables |=
1444 HWRM_PORT_PHY_CFG_IN_EN_AUTO_LINK_SPEED_MASK;
1445 req.auto_link_speed_mask =
1446 rte_cpu_to_le_16(conf->auto_link_speed_mask);
1447 }
1448 }
1449 if (conf->auto_link_speed &&
1450 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE))
1451 enables |=
1452 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
1453
1454 req.auto_duplex = conf->duplex;
1455 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1456 req.auto_pause = conf->auto_pause;
1457 req.force_pause = conf->force_pause;
1458 /* Set force_pause if there is no auto or if there is a force */
1459 if (req.auto_pause && !req.force_pause)
1460 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1461 else
1462 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1463
1464 req.enables = rte_cpu_to_le_32(enables);
1465 } else {
1466 req.flags =
1467 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1468 PMD_DRV_LOG(INFO, "Force Link Down\n");
1469 }
1470
1471 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1472
1473 HWRM_CHECK_RESULT();
1474 HWRM_UNLOCK();
1475
1476 return rc;
1477 }
1478
bnxt_hwrm_port_phy_qcfg(struct bnxt * bp,struct bnxt_link_info * link_info)1479 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1480 struct bnxt_link_info *link_info)
1481 {
1482 int rc = 0;
1483 struct hwrm_port_phy_qcfg_input req = {0};
1484 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1485
1486 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1487
1488 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1489
1490 HWRM_CHECK_RESULT();
1491
1492 link_info->phy_link_status = resp->link;
1493 link_info->link_up =
1494 (link_info->phy_link_status ==
1495 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1496 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1497 link_info->duplex = resp->duplex_cfg;
1498 link_info->pause = resp->pause;
1499 link_info->auto_pause = resp->auto_pause;
1500 link_info->force_pause = resp->force_pause;
1501 link_info->auto_mode = resp->auto_mode;
1502 link_info->phy_type = resp->phy_type;
1503 link_info->media_type = resp->media_type;
1504
1505 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1506 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1507 link_info->auto_link_speed_mask = rte_le_to_cpu_16(resp->auto_link_speed_mask);
1508 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1509 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1510 link_info->phy_ver[0] = resp->phy_maj;
1511 link_info->phy_ver[1] = resp->phy_min;
1512 link_info->phy_ver[2] = resp->phy_bld;
1513 link_info->link_signal_mode =
1514 resp->active_fec_signal_mode & HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK;
1515 link_info->force_pam4_link_speed =
1516 rte_le_to_cpu_16(resp->force_pam4_link_speed);
1517 link_info->support_pam4_speeds =
1518 rte_le_to_cpu_16(resp->support_pam4_speeds);
1519 link_info->auto_pam4_link_speed_mask =
1520 rte_le_to_cpu_16(resp->auto_pam4_link_speed_mask);
1521 link_info->module_status = resp->module_status;
1522 HWRM_UNLOCK();
1523
1524 PMD_DRV_LOG(DEBUG, "Link Speed:%d,Auto:%d:%x:%x,Support:%x,Force:%x\n",
1525 link_info->link_speed, link_info->auto_mode,
1526 link_info->auto_link_speed, link_info->auto_link_speed_mask,
1527 link_info->support_speeds, link_info->force_link_speed);
1528 PMD_DRV_LOG(DEBUG, "Link Signal:%d,PAM::Auto:%x,Support:%x,Force:%x\n",
1529 link_info->link_signal_mode,
1530 link_info->auto_pam4_link_speed_mask,
1531 link_info->support_pam4_speeds,
1532 link_info->force_pam4_link_speed);
1533 return rc;
1534 }
1535
bnxt_hwrm_port_phy_qcaps(struct bnxt * bp)1536 int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp)
1537 {
1538 int rc = 0;
1539 struct hwrm_port_phy_qcaps_input req = {0};
1540 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1541 struct bnxt_link_info *link_info = bp->link_info;
1542
1543 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1544 return 0;
1545
1546 HWRM_PREP(&req, HWRM_PORT_PHY_QCAPS, BNXT_USE_CHIMP_MB);
1547
1548 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1549
1550 HWRM_CHECK_RESULT_SILENT();
1551
1552 bp->port_cnt = resp->port_cnt;
1553 if (resp->supported_speeds_auto_mode)
1554 link_info->support_auto_speeds =
1555 rte_le_to_cpu_16(resp->supported_speeds_auto_mode);
1556 if (resp->supported_pam4_speeds_auto_mode)
1557 link_info->support_pam4_auto_speeds =
1558 rte_le_to_cpu_16(resp->supported_pam4_speeds_auto_mode);
1559
1560 HWRM_UNLOCK();
1561
1562 /* Older firmware does not have supported_auto_speeds, so assume
1563 * that all supported speeds can be autonegotiated.
1564 */
1565 if (link_info->auto_link_speed_mask && !link_info->support_auto_speeds)
1566 link_info->support_auto_speeds = link_info->support_speeds;
1567
1568 return 0;
1569 }
1570
bnxt_find_lossy_profile(struct bnxt * bp)1571 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1572 {
1573 int i = 0;
1574
1575 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1576 if (bp->tx_cos_queue[i].profile ==
1577 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1578 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1579 return true;
1580 }
1581 }
1582 return false;
1583 }
1584
bnxt_find_first_valid_profile(struct bnxt * bp)1585 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1586 {
1587 int i = 0;
1588
1589 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1590 if (bp->tx_cos_queue[i].profile !=
1591 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1592 bp->tx_cos_queue[i].id !=
1593 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1594 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1595 break;
1596 }
1597 }
1598 }
1599
bnxt_hwrm_queue_qportcfg(struct bnxt * bp)1600 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1601 {
1602 int rc = 0;
1603 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1604 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1605 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1606 int i;
1607
1608 get_rx_info:
1609 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1610
1611 req.flags = rte_cpu_to_le_32(dir);
1612 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1613 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1614 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1615 req.drv_qmap_cap =
1616 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1617 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1618
1619 HWRM_CHECK_RESULT();
1620
1621 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1622 GET_TX_QUEUE_INFO(0);
1623 GET_TX_QUEUE_INFO(1);
1624 GET_TX_QUEUE_INFO(2);
1625 GET_TX_QUEUE_INFO(3);
1626 GET_TX_QUEUE_INFO(4);
1627 GET_TX_QUEUE_INFO(5);
1628 GET_TX_QUEUE_INFO(6);
1629 GET_TX_QUEUE_INFO(7);
1630 } else {
1631 GET_RX_QUEUE_INFO(0);
1632 GET_RX_QUEUE_INFO(1);
1633 GET_RX_QUEUE_INFO(2);
1634 GET_RX_QUEUE_INFO(3);
1635 GET_RX_QUEUE_INFO(4);
1636 GET_RX_QUEUE_INFO(5);
1637 GET_RX_QUEUE_INFO(6);
1638 GET_RX_QUEUE_INFO(7);
1639 }
1640
1641 HWRM_UNLOCK();
1642
1643 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1644 goto done;
1645
1646 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1647 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1648 } else {
1649 int j;
1650
1651 /* iterate and find the COSq profile to use for Tx */
1652 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1653 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1654 if (bp->tx_cos_queue[i].id != 0xff)
1655 bp->tx_cosq_id[j++] =
1656 bp->tx_cos_queue[i].id;
1657 }
1658 } else {
1659 /* When CoS classification is disabled, for normal NIC
1660 * operations, ideally we should look to use LOSSY.
1661 * If not found, fallback to the first valid profile
1662 */
1663 if (!bnxt_find_lossy_profile(bp))
1664 bnxt_find_first_valid_profile(bp);
1665
1666 }
1667 }
1668
1669 bp->max_tc = resp->max_configurable_queues;
1670 bp->max_lltc = resp->max_configurable_lossless_queues;
1671 if (bp->max_tc > BNXT_MAX_QUEUE)
1672 bp->max_tc = BNXT_MAX_QUEUE;
1673 bp->max_q = bp->max_tc;
1674
1675 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1676 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1677 goto get_rx_info;
1678 }
1679
1680 done:
1681 return rc;
1682 }
1683
bnxt_hwrm_ring_alloc(struct bnxt * bp,struct bnxt_ring * ring,uint32_t ring_type,uint32_t map_index,uint32_t stats_ctx_id,uint32_t cmpl_ring_id,uint16_t tx_cosq_id)1684 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1685 struct bnxt_ring *ring,
1686 uint32_t ring_type, uint32_t map_index,
1687 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1688 uint16_t tx_cosq_id)
1689 {
1690 int rc = 0;
1691 uint32_t enables = 0;
1692 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1693 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1694 struct rte_mempool *mb_pool;
1695 uint16_t rx_buf_size;
1696
1697 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1698
1699 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1700 req.fbo = rte_cpu_to_le_32(0);
1701 /* Association of ring index with doorbell index */
1702 req.logical_id = rte_cpu_to_le_16(map_index);
1703 req.length = rte_cpu_to_le_32(ring->ring_size);
1704
1705 switch (ring_type) {
1706 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1707 req.ring_type = ring_type;
1708 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1709 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1710 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1711 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1712 enables |=
1713 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1714 break;
1715 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1716 req.ring_type = ring_type;
1717 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1718 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1719 if (BNXT_CHIP_P5(bp)) {
1720 mb_pool = bp->rx_queues[0]->mb_pool;
1721 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1722 RTE_PKTMBUF_HEADROOM;
1723 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1724 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1725 enables |=
1726 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1727 }
1728 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1729 enables |=
1730 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1731 break;
1732 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1733 req.ring_type = ring_type;
1734 if (BNXT_HAS_NQ(bp)) {
1735 /* Association of cp ring with nq */
1736 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1737 enables |=
1738 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1739 }
1740 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1741 break;
1742 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1743 req.ring_type = ring_type;
1744 req.page_size = BNXT_PAGE_SHFT;
1745 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1746 break;
1747 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1748 req.ring_type = ring_type;
1749 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1750
1751 mb_pool = bp->rx_queues[0]->mb_pool;
1752 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1753 RTE_PKTMBUF_HEADROOM;
1754 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1755 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1756
1757 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1758 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1759 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1760 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1761 break;
1762 default:
1763 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1764 ring_type);
1765 HWRM_UNLOCK();
1766 return -EINVAL;
1767 }
1768 req.enables = rte_cpu_to_le_32(enables);
1769
1770 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1771
1772 if (rc || resp->error_code) {
1773 if (rc == 0 && resp->error_code)
1774 rc = rte_le_to_cpu_16(resp->error_code);
1775 switch (ring_type) {
1776 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1777 PMD_DRV_LOG(ERR,
1778 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1779 HWRM_UNLOCK();
1780 return rc;
1781 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1782 PMD_DRV_LOG(ERR,
1783 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1784 HWRM_UNLOCK();
1785 return rc;
1786 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1787 PMD_DRV_LOG(ERR,
1788 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1789 rc);
1790 HWRM_UNLOCK();
1791 return rc;
1792 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1793 PMD_DRV_LOG(ERR,
1794 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1795 HWRM_UNLOCK();
1796 return rc;
1797 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1798 PMD_DRV_LOG(ERR,
1799 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1800 HWRM_UNLOCK();
1801 return rc;
1802 default:
1803 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1804 HWRM_UNLOCK();
1805 return rc;
1806 }
1807 }
1808
1809 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1810 HWRM_UNLOCK();
1811 return rc;
1812 }
1813
bnxt_hwrm_ring_free(struct bnxt * bp,struct bnxt_ring * ring,uint32_t ring_type,uint16_t cp_ring_id)1814 int bnxt_hwrm_ring_free(struct bnxt *bp,
1815 struct bnxt_ring *ring, uint32_t ring_type,
1816 uint16_t cp_ring_id)
1817 {
1818 int rc;
1819 struct hwrm_ring_free_input req = {.req_type = 0 };
1820 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1821
1822 if (ring->fw_ring_id == INVALID_HW_RING_ID)
1823 return -EINVAL;
1824
1825 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1826
1827 req.ring_type = ring_type;
1828 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1829 req.cmpl_ring = rte_cpu_to_le_16(cp_ring_id);
1830
1831 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1832 ring->fw_ring_id = INVALID_HW_RING_ID;
1833
1834 if (rc || resp->error_code) {
1835 if (rc == 0 && resp->error_code)
1836 rc = rte_le_to_cpu_16(resp->error_code);
1837 HWRM_UNLOCK();
1838
1839 switch (ring_type) {
1840 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1841 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1842 rc);
1843 return rc;
1844 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1845 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1846 rc);
1847 return rc;
1848 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1849 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1850 rc);
1851 return rc;
1852 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1853 PMD_DRV_LOG(ERR,
1854 "hwrm_ring_free nq failed. rc:%d\n", rc);
1855 return rc;
1856 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1857 PMD_DRV_LOG(ERR,
1858 "hwrm_ring_free agg failed. rc:%d\n", rc);
1859 return rc;
1860 default:
1861 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1862 return rc;
1863 }
1864 }
1865 HWRM_UNLOCK();
1866 return 0;
1867 }
1868
bnxt_hwrm_ring_grp_alloc(struct bnxt * bp,unsigned int idx)1869 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1870 {
1871 int rc = 0;
1872 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1873 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1874
1875 /* Don't attempt to re-create the ring group if it is already created */
1876 if (bp->grp_info[idx].fw_grp_id != INVALID_HW_RING_ID)
1877 return 0;
1878
1879 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1880
1881 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1882 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1883 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1884 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1885
1886 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1887
1888 HWRM_CHECK_RESULT();
1889
1890 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1891
1892 HWRM_UNLOCK();
1893
1894 return rc;
1895 }
1896
bnxt_hwrm_ring_grp_free(struct bnxt * bp,unsigned int idx)1897 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1898 {
1899 int rc;
1900 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1901 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1902
1903 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
1904 return 0;
1905
1906 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1907
1908 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1909
1910 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1911
1912 HWRM_CHECK_RESULT();
1913 HWRM_UNLOCK();
1914
1915 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1916 return rc;
1917 }
1918
bnxt_hwrm_stat_clear(struct bnxt * bp,struct bnxt_cp_ring_info * cpr)1919 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1920 {
1921 int rc = 0;
1922 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1923 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1924
1925 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1926 return rc;
1927
1928 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1929
1930 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1931
1932 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933
1934 HWRM_CHECK_RESULT();
1935 HWRM_UNLOCK();
1936
1937 return rc;
1938 }
1939
bnxt_hwrm_stat_ctx_alloc(struct bnxt * bp,struct bnxt_cp_ring_info * cpr)1940 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1941 {
1942 int rc;
1943 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1944 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1945
1946 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE)
1947 return 0;
1948
1949 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1950
1951 req.update_period_ms = rte_cpu_to_le_32(0);
1952
1953 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1954
1955 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1956
1957 HWRM_CHECK_RESULT();
1958
1959 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1960
1961 HWRM_UNLOCK();
1962
1963 return rc;
1964 }
1965
bnxt_hwrm_stat_ctx_free(struct bnxt * bp,struct bnxt_cp_ring_info * cpr)1966 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1967 {
1968 int rc;
1969 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1970 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1971
1972 if (cpr->hw_stats_ctx_id == HWRM_NA_SIGNATURE)
1973 return 0;
1974
1975 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1976
1977 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1978
1979 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1980
1981 HWRM_CHECK_RESULT();
1982 HWRM_UNLOCK();
1983
1984 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
1985
1986 return rc;
1987 }
1988
bnxt_hwrm_vnic_alloc(struct bnxt * bp,struct bnxt_vnic_info * vnic)1989 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1990 {
1991 int rc = 0, i, j;
1992 struct hwrm_vnic_alloc_input req = { 0 };
1993 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1994
1995 if (!BNXT_HAS_RING_GRPS(bp))
1996 goto skip_ring_grps;
1997
1998 /* map ring groups to this vnic */
1999 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
2000 vnic->start_grp_id, vnic->end_grp_id);
2001 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
2002 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
2003
2004 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
2005 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
2006 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
2007 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
2008
2009 skip_ring_grps:
2010 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
2011 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
2012
2013 if (vnic->func_default)
2014 req.flags =
2015 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
2016 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2017
2018 HWRM_CHECK_RESULT();
2019
2020 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
2021 HWRM_UNLOCK();
2022 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2023 return rc;
2024 }
2025
bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt * bp,struct bnxt_vnic_info * vnic,struct bnxt_plcmodes_cfg * pmode)2026 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
2027 struct bnxt_vnic_info *vnic,
2028 struct bnxt_plcmodes_cfg *pmode)
2029 {
2030 int rc = 0;
2031 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
2032 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2033
2034 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
2035
2036 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2037
2038 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2039
2040 HWRM_CHECK_RESULT();
2041
2042 pmode->flags = rte_le_to_cpu_32(resp->flags);
2043 /* dflt_vnic bit doesn't exist in the _cfg command */
2044 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
2045 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
2046 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
2047 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
2048
2049 HWRM_UNLOCK();
2050
2051 return rc;
2052 }
2053
bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt * bp,struct bnxt_vnic_info * vnic,struct bnxt_plcmodes_cfg * pmode)2054 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
2055 struct bnxt_vnic_info *vnic,
2056 struct bnxt_plcmodes_cfg *pmode)
2057 {
2058 int rc = 0;
2059 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2060 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2061
2062 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2063 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2064 return rc;
2065 }
2066
2067 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2068
2069 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2070 req.flags = rte_cpu_to_le_32(pmode->flags);
2071 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
2072 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
2073 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
2074 req.enables = rte_cpu_to_le_32(
2075 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
2076 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
2077 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
2078 );
2079
2080 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2081
2082 HWRM_CHECK_RESULT();
2083 HWRM_UNLOCK();
2084
2085 return rc;
2086 }
2087
bnxt_hwrm_vnic_cfg(struct bnxt * bp,struct bnxt_vnic_info * vnic)2088 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2089 {
2090 int rc = 0;
2091 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
2092 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2093 struct bnxt_plcmodes_cfg pmodes = { 0 };
2094 uint32_t ctx_enable_flag = 0;
2095 uint32_t enables = 0;
2096
2097 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2098 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2099 return rc;
2100 }
2101
2102 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
2103 if (rc)
2104 return rc;
2105
2106 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
2107
2108 if (BNXT_CHIP_P5(bp)) {
2109 int dflt_rxq = vnic->start_grp_id;
2110 struct bnxt_rx_ring_info *rxr;
2111 struct bnxt_cp_ring_info *cpr;
2112 struct bnxt_rx_queue *rxq;
2113 int i;
2114
2115 /*
2116 * The first active receive ring is used as the VNIC
2117 * default receive ring. If there are no active receive
2118 * rings (all corresponding receive queues are stopped),
2119 * the first receive ring is used.
2120 */
2121 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
2122 rxq = bp->eth_dev->data->rx_queues[i];
2123 if (rxq->rx_started) {
2124 dflt_rxq = i;
2125 break;
2126 }
2127 }
2128
2129 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
2130 rxr = rxq->rx_ring;
2131 cpr = rxq->cp_ring;
2132
2133 req.default_rx_ring_id =
2134 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
2135 req.default_cmpl_ring_id =
2136 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
2137 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
2138 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
2139 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_RX_CMPL_V2) {
2140 enables |= HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE;
2141 req.rx_csum_v2_mode =
2142 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK;
2143 }
2144 goto config_mru;
2145 }
2146
2147 /* Only RSS support for now TBD: COS & LB */
2148 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
2149 if (vnic->lb_rule != 0xffff)
2150 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
2151 if (vnic->cos_rule != 0xffff)
2152 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
2153 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
2154 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
2155 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
2156 }
2157 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
2158 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
2159 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
2160 }
2161
2162 enables |= ctx_enable_flag;
2163 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
2164 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
2165 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
2166 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
2167
2168 config_mru:
2169 req.enables = rte_cpu_to_le_32(enables);
2170 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2171 req.mru = rte_cpu_to_le_16(vnic->mru);
2172 /* Configure default VNIC only once. */
2173 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
2174 req.flags |=
2175 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
2176 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
2177 }
2178 if (vnic->vlan_strip)
2179 req.flags |=
2180 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
2181 if (vnic->bd_stall)
2182 req.flags |=
2183 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
2184 if (vnic->rss_dflt_cr)
2185 req.flags |= rte_cpu_to_le_32(
2186 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
2187
2188 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2189
2190 HWRM_CHECK_RESULT();
2191 HWRM_UNLOCK();
2192
2193 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
2194
2195 return rc;
2196 }
2197
bnxt_hwrm_vnic_qcfg(struct bnxt * bp,struct bnxt_vnic_info * vnic,int16_t fw_vf_id)2198 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
2199 int16_t fw_vf_id)
2200 {
2201 int rc = 0;
2202 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
2203 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
2204
2205 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2206 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
2207 return rc;
2208 }
2209 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
2210
2211 req.enables =
2212 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
2213 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2214 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
2215
2216 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2217
2218 HWRM_CHECK_RESULT();
2219
2220 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
2221 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
2222 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
2223 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
2224 vnic->mru = rte_le_to_cpu_16(resp->mru);
2225 vnic->func_default = rte_le_to_cpu_32(
2226 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
2227 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
2228 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
2229 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
2230 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
2231 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
2232 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
2233
2234 HWRM_UNLOCK();
2235
2236 return rc;
2237 }
2238
bnxt_hwrm_vnic_ctx_alloc(struct bnxt * bp,struct bnxt_vnic_info * vnic,uint16_t ctx_idx)2239 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
2240 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2241 {
2242 int rc = 0;
2243 uint16_t ctx_id;
2244 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
2245 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
2246 bp->hwrm_cmd_resp_addr;
2247
2248 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
2249
2250 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2251 HWRM_CHECK_RESULT();
2252
2253 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2254 if (!BNXT_HAS_RING_GRPS(bp))
2255 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2256 else if (ctx_idx == 0)
2257 vnic->rss_rule = ctx_id;
2258
2259 HWRM_UNLOCK();
2260
2261 return rc;
2262 }
2263
2264 static
_bnxt_hwrm_vnic_ctx_free(struct bnxt * bp,struct bnxt_vnic_info * vnic,uint16_t ctx_idx)2265 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2266 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2267 {
2268 int rc = 0;
2269 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2270 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2271 bp->hwrm_cmd_resp_addr;
2272
2273 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2274 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2275 return rc;
2276 }
2277 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2278
2279 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2280
2281 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2282
2283 HWRM_CHECK_RESULT();
2284 HWRM_UNLOCK();
2285
2286 return rc;
2287 }
2288
bnxt_hwrm_vnic_ctx_free(struct bnxt * bp,struct bnxt_vnic_info * vnic)2289 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2290 {
2291 int rc = 0;
2292
2293 if (BNXT_CHIP_P5(bp)) {
2294 int j;
2295
2296 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2297 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2298 vnic,
2299 vnic->fw_grp_ids[j]);
2300 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2301 }
2302 vnic->num_lb_ctxts = 0;
2303 } else {
2304 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2305 vnic->rss_rule = INVALID_HW_RING_ID;
2306 }
2307
2308 return rc;
2309 }
2310
bnxt_hwrm_vnic_free(struct bnxt * bp,struct bnxt_vnic_info * vnic)2311 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2312 {
2313 int rc = 0;
2314 struct hwrm_vnic_free_input req = {.req_type = 0 };
2315 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2316
2317 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2318 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2319 return rc;
2320 }
2321
2322 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2323
2324 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2325
2326 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2327
2328 HWRM_CHECK_RESULT();
2329 HWRM_UNLOCK();
2330
2331 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2332 /* Configure default VNIC again if necessary. */
2333 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2334 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2335
2336 return rc;
2337 }
2338
2339 static int
bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt * bp,struct bnxt_vnic_info * vnic)2340 bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2341 {
2342 int i;
2343 int rc = 0;
2344 int nr_ctxs = vnic->num_lb_ctxts;
2345 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2346 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2347
2348 for (i = 0; i < nr_ctxs; i++) {
2349 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2350
2351 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2352 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2353 req.hash_mode_flags = vnic->hash_mode;
2354
2355 req.hash_key_tbl_addr =
2356 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2357
2358 req.ring_grp_tbl_addr =
2359 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2360 i * HW_HASH_INDEX_SIZE);
2361 req.ring_table_pair_index = i;
2362 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2363
2364 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2365 BNXT_USE_CHIMP_MB);
2366
2367 HWRM_CHECK_RESULT();
2368 HWRM_UNLOCK();
2369 }
2370
2371 return rc;
2372 }
2373
bnxt_hwrm_vnic_rss_cfg(struct bnxt * bp,struct bnxt_vnic_info * vnic)2374 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2375 struct bnxt_vnic_info *vnic)
2376 {
2377 int rc = 0;
2378 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2379 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2380
2381 if (!vnic->rss_table)
2382 return 0;
2383
2384 if (BNXT_CHIP_P5(bp))
2385 return bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);
2386
2387 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2388
2389 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2390 req.hash_mode_flags = vnic->hash_mode;
2391
2392 req.ring_grp_tbl_addr =
2393 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2394 req.hash_key_tbl_addr =
2395 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2396 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2397 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2398
2399 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2400
2401 HWRM_CHECK_RESULT();
2402 HWRM_UNLOCK();
2403
2404 return rc;
2405 }
2406
bnxt_hwrm_vnic_plcmode_cfg(struct bnxt * bp,struct bnxt_vnic_info * vnic)2407 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2408 struct bnxt_vnic_info *vnic)
2409 {
2410 int rc = 0;
2411 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2412 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2413 uint16_t size;
2414
2415 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2416 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2417 return rc;
2418 }
2419
2420 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2421
2422 req.flags = rte_cpu_to_le_32(
2423 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2424
2425 req.enables = rte_cpu_to_le_32(
2426 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2427
2428 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2429 size -= RTE_PKTMBUF_HEADROOM;
2430 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2431
2432 req.jumbo_thresh = rte_cpu_to_le_16(size);
2433 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2434
2435 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2436
2437 HWRM_CHECK_RESULT();
2438 HWRM_UNLOCK();
2439
2440 return rc;
2441 }
2442
bnxt_hwrm_vnic_tpa_cfg(struct bnxt * bp,struct bnxt_vnic_info * vnic,bool enable)2443 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2444 struct bnxt_vnic_info *vnic, bool enable)
2445 {
2446 int rc = 0;
2447 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2448 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2449
2450 if (BNXT_CHIP_P5(bp) && !bp->max_tpa_v2) {
2451 if (enable)
2452 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2453 return -ENOTSUP;
2454 }
2455
2456 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2457 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2458 return 0;
2459 }
2460
2461 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2462
2463 if (enable) {
2464 req.enables = rte_cpu_to_le_32(
2465 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2466 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2467 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2468 req.flags = rte_cpu_to_le_32(
2469 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2470 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2471 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2472 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2473 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2474 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2475 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2476 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2477 req.min_agg_len = rte_cpu_to_le_32(512);
2478 }
2479 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2480
2481 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2482
2483 HWRM_CHECK_RESULT();
2484 HWRM_UNLOCK();
2485
2486 return rc;
2487 }
2488
bnxt_hwrm_func_vf_mac(struct bnxt * bp,uint16_t vf,const uint8_t * mac_addr)2489 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2490 {
2491 struct hwrm_func_cfg_input req = {0};
2492 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2493 int rc;
2494
2495 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2496 req.enables = rte_cpu_to_le_32(
2497 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2498 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2499 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2500
2501 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2502
2503 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2504 HWRM_CHECK_RESULT();
2505 HWRM_UNLOCK();
2506
2507 bp->pf->vf_info[vf].random_mac = false;
2508
2509 return rc;
2510 }
2511
bnxt_hwrm_func_qstats_tx_drop(struct bnxt * bp,uint16_t fid,uint64_t * dropped)2512 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2513 uint64_t *dropped)
2514 {
2515 int rc = 0;
2516 struct hwrm_func_qstats_input req = {.req_type = 0};
2517 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2518
2519 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2520
2521 req.fid = rte_cpu_to_le_16(fid);
2522
2523 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2524
2525 HWRM_CHECK_RESULT();
2526
2527 if (dropped)
2528 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2529
2530 HWRM_UNLOCK();
2531
2532 return rc;
2533 }
2534
bnxt_hwrm_func_qstats(struct bnxt * bp,uint16_t fid,struct rte_eth_stats * stats,struct hwrm_func_qstats_output * func_qstats)2535 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2536 struct rte_eth_stats *stats,
2537 struct hwrm_func_qstats_output *func_qstats)
2538 {
2539 int rc = 0;
2540 struct hwrm_func_qstats_input req = {.req_type = 0};
2541 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2542
2543 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2544
2545 req.fid = rte_cpu_to_le_16(fid);
2546
2547 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2548
2549 HWRM_CHECK_RESULT();
2550 if (func_qstats)
2551 memcpy(func_qstats, resp,
2552 sizeof(struct hwrm_func_qstats_output));
2553
2554 if (!stats)
2555 goto exit;
2556
2557 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2558 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2559 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2560 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2561 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2562 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2563
2564 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2565 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2566 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2567 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2568 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2569 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2570
2571 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2572 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2573 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2574
2575 exit:
2576 HWRM_UNLOCK();
2577
2578 return rc;
2579 }
2580
bnxt_hwrm_func_clr_stats(struct bnxt * bp,uint16_t fid)2581 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2582 {
2583 int rc = 0;
2584 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2585 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2586
2587 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2588
2589 req.fid = rte_cpu_to_le_16(fid);
2590
2591 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2592
2593 HWRM_CHECK_RESULT();
2594 HWRM_UNLOCK();
2595
2596 return rc;
2597 }
2598
bnxt_clear_all_hwrm_stat_ctxs(struct bnxt * bp)2599 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2600 {
2601 unsigned int i;
2602 int rc = 0;
2603
2604 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2605 struct bnxt_tx_queue *txq;
2606 struct bnxt_rx_queue *rxq;
2607 struct bnxt_cp_ring_info *cpr;
2608
2609 if (i >= bp->rx_cp_nr_rings) {
2610 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2611 cpr = txq->cp_ring;
2612 } else {
2613 rxq = bp->rx_queues[i];
2614 cpr = rxq->cp_ring;
2615 }
2616
2617 rc = bnxt_hwrm_stat_clear(bp, cpr);
2618 if (rc)
2619 return rc;
2620 }
2621 return 0;
2622 }
2623
2624 static int
bnxt_free_all_hwrm_stat_ctxs(struct bnxt * bp)2625 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2626 {
2627 int rc;
2628 unsigned int i;
2629 struct bnxt_cp_ring_info *cpr;
2630
2631 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2632
2633 cpr = bp->rx_queues[i]->cp_ring;
2634 if (BNXT_HAS_RING_GRPS(bp))
2635 bp->grp_info[i].fw_stats_ctx = -1;
2636 if (cpr == NULL)
2637 continue;
2638 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2639 if (rc)
2640 return rc;
2641 }
2642
2643 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2644 cpr = bp->tx_queues[i]->cp_ring;
2645 if (cpr == NULL)
2646 continue;
2647 rc = bnxt_hwrm_stat_ctx_free(bp, cpr);
2648 if (rc)
2649 return rc;
2650 }
2651
2652 return 0;
2653 }
2654
2655 static int
bnxt_free_all_hwrm_ring_grps(struct bnxt * bp)2656 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2657 {
2658 uint16_t idx;
2659 uint32_t rc = 0;
2660
2661 if (!BNXT_HAS_RING_GRPS(bp))
2662 return 0;
2663
2664 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2665
2666 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2667 continue;
2668
2669 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2670
2671 if (rc)
2672 return rc;
2673 }
2674 return rc;
2675 }
2676
bnxt_free_nq_ring(struct bnxt * bp,struct bnxt_cp_ring_info * cpr)2677 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2678 {
2679 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2680
2681 bnxt_hwrm_ring_free(bp, cp_ring,
2682 HWRM_RING_FREE_INPUT_RING_TYPE_NQ,
2683 INVALID_HW_RING_ID);
2684 memset(cpr->cp_desc_ring, 0,
2685 cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2686 cpr->cp_raw_cons = 0;
2687 }
2688
bnxt_free_cp_ring(struct bnxt * bp,struct bnxt_cp_ring_info * cpr)2689 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2690 {
2691 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2692
2693 bnxt_hwrm_ring_free(bp, cp_ring,
2694 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL,
2695 INVALID_HW_RING_ID);
2696 memset(cpr->cp_desc_ring, 0,
2697 cpr->cp_ring_struct->ring_size * sizeof(*cpr->cp_desc_ring));
2698 cpr->cp_raw_cons = 0;
2699 }
2700
bnxt_free_hwrm_rx_ring(struct bnxt * bp,int queue_index)2701 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2702 {
2703 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2704 struct bnxt_rx_ring_info *rxr = rxq ? rxq->rx_ring : NULL;
2705 struct bnxt_ring *ring = rxr ? rxr->rx_ring_struct : NULL;
2706 struct bnxt_cp_ring_info *cpr = rxq ? rxq->cp_ring : NULL;
2707
2708 if (BNXT_HAS_RING_GRPS(bp))
2709 bnxt_hwrm_ring_grp_free(bp, queue_index);
2710
2711 if (ring != NULL && cpr != NULL)
2712 bnxt_hwrm_ring_free(bp, ring,
2713 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2714 cpr->cp_ring_struct->fw_ring_id);
2715 if (BNXT_HAS_RING_GRPS(bp))
2716 bp->grp_info[queue_index].rx_fw_ring_id = INVALID_HW_RING_ID;
2717
2718 /* Check agg ring struct explicitly.
2719 * bnxt_need_agg_ring() returns the current state of offload flags,
2720 * but we may have to deal with agg ring struct before the offload
2721 * flags are updated.
2722 */
2723 if (!bnxt_need_agg_ring(bp->eth_dev) ||
2724 (rxr && rxr->ag_ring_struct == NULL))
2725 goto no_agg;
2726
2727 ring = rxr ? rxr->ag_ring_struct : NULL;
2728 if (ring != NULL && cpr != NULL) {
2729 bnxt_hwrm_ring_free(bp, ring,
2730 BNXT_CHIP_P5(bp) ?
2731 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2732 HWRM_RING_FREE_INPUT_RING_TYPE_RX,
2733 cpr->cp_ring_struct->fw_ring_id);
2734 }
2735 if (BNXT_HAS_RING_GRPS(bp))
2736 bp->grp_info[queue_index].ag_fw_ring_id = INVALID_HW_RING_ID;
2737
2738 no_agg:
2739 if (cpr != NULL) {
2740 bnxt_hwrm_stat_ctx_free(bp, cpr);
2741 bnxt_free_cp_ring(bp, cpr);
2742 }
2743
2744 if (BNXT_HAS_RING_GRPS(bp))
2745 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2746 }
2747
bnxt_hwrm_rx_ring_reset(struct bnxt * bp,int queue_index)2748 int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int queue_index)
2749 {
2750 int rc;
2751 struct hwrm_ring_reset_input req = {.req_type = 0 };
2752 struct hwrm_ring_reset_output *resp = bp->hwrm_cmd_resp_addr;
2753
2754 HWRM_PREP(&req, HWRM_RING_RESET, BNXT_USE_CHIMP_MB);
2755
2756 req.ring_type = HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP;
2757 req.ring_id = rte_cpu_to_le_16(bp->grp_info[queue_index].fw_grp_id);
2758 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2759
2760 HWRM_CHECK_RESULT();
2761
2762 HWRM_UNLOCK();
2763
2764 return rc;
2765 }
2766
2767 static int
bnxt_free_all_hwrm_rings(struct bnxt * bp)2768 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2769 {
2770 unsigned int i;
2771
2772 for (i = 0; i < bp->tx_cp_nr_rings; i++)
2773 bnxt_free_hwrm_tx_ring(bp, i);
2774
2775 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2776 bnxt_free_hwrm_rx_ring(bp, i);
2777
2778 return 0;
2779 }
2780
bnxt_alloc_all_hwrm_ring_grps(struct bnxt * bp)2781 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2782 {
2783 uint16_t i;
2784 uint32_t rc = 0;
2785
2786 if (!BNXT_HAS_RING_GRPS(bp))
2787 return 0;
2788
2789 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2790 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2791 if (rc)
2792 return rc;
2793 }
2794 return rc;
2795 }
2796
2797 /*
2798 * HWRM utility functions
2799 */
2800
bnxt_free_hwrm_resources(struct bnxt * bp)2801 void bnxt_free_hwrm_resources(struct bnxt *bp)
2802 {
2803 /* Release memzone */
2804 rte_free(bp->hwrm_cmd_resp_addr);
2805 rte_free(bp->hwrm_short_cmd_req_addr);
2806 bp->hwrm_cmd_resp_addr = NULL;
2807 bp->hwrm_short_cmd_req_addr = NULL;
2808 bp->hwrm_cmd_resp_dma_addr = 0;
2809 bp->hwrm_short_cmd_req_dma_addr = 0;
2810 }
2811
bnxt_alloc_hwrm_resources(struct bnxt * bp)2812 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2813 {
2814 struct rte_pci_device *pdev = bp->pdev;
2815 char type[RTE_MEMZONE_NAMESIZE];
2816
2817 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2818 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2819 bp->max_resp_len = BNXT_PAGE_SIZE;
2820 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2821 if (bp->hwrm_cmd_resp_addr == NULL)
2822 return -ENOMEM;
2823 bp->hwrm_cmd_resp_dma_addr =
2824 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2825 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2826 PMD_DRV_LOG(ERR,
2827 "unable to map response address to physical memory\n");
2828 return -ENOMEM;
2829 }
2830 rte_spinlock_init(&bp->hwrm_lock);
2831
2832 return 0;
2833 }
2834
2835 int
bnxt_clear_one_vnic_filter(struct bnxt * bp,struct bnxt_filter_info * filter)2836 bnxt_clear_one_vnic_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
2837 {
2838 int rc = 0;
2839
2840 if (filter->filter_type == HWRM_CFA_EM_FILTER) {
2841 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2842 if (rc)
2843 return rc;
2844 } else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER) {
2845 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2846 if (rc)
2847 return rc;
2848 }
2849
2850 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2851 return rc;
2852 }
2853
2854 static int
bnxt_clear_hwrm_vnic_filters(struct bnxt * bp,struct bnxt_vnic_info * vnic)2855 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2856 {
2857 struct bnxt_filter_info *filter;
2858 int rc = 0;
2859
2860 STAILQ_FOREACH(filter, &vnic->filter, next) {
2861 rc = bnxt_clear_one_vnic_filter(bp, filter);
2862 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2863 bnxt_free_filter(bp, filter);
2864 }
2865 return rc;
2866 }
2867
2868 static int
bnxt_clear_hwrm_vnic_flows(struct bnxt * bp,struct bnxt_vnic_info * vnic)2869 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2870 {
2871 struct bnxt_filter_info *filter;
2872 struct rte_flow *flow;
2873 int rc = 0;
2874
2875 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2876 flow = STAILQ_FIRST(&vnic->flow_list);
2877 filter = flow->filter;
2878 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2879 rc = bnxt_clear_one_vnic_filter(bp, filter);
2880
2881 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2882 rte_free(flow);
2883 }
2884 return rc;
2885 }
2886
bnxt_set_hwrm_vnic_filters(struct bnxt * bp,struct bnxt_vnic_info * vnic)2887 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2888 {
2889 struct bnxt_filter_info *filter;
2890 int rc = 0;
2891
2892 STAILQ_FOREACH(filter, &vnic->filter, next) {
2893 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2894 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2895 filter);
2896 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2897 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2898 filter);
2899 else
2900 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2901 filter);
2902 if (rc)
2903 break;
2904 }
2905 return rc;
2906 }
2907
2908 static void
bnxt_free_tunnel_ports(struct bnxt * bp)2909 bnxt_free_tunnel_ports(struct bnxt *bp)
2910 {
2911 if (bp->vxlan_port_cnt)
2912 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2913 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2914
2915 if (bp->geneve_port_cnt)
2916 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2917 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2918 }
2919
bnxt_free_all_hwrm_resources(struct bnxt * bp)2920 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2921 {
2922 int i;
2923
2924 if (bp->vnic_info == NULL)
2925 return;
2926
2927 /*
2928 * Cleanup VNICs in reverse order, to make sure the L2 filter
2929 * from vnic0 is last to be cleaned up.
2930 */
2931 for (i = bp->max_vnics - 1; i >= 0; i--) {
2932 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2933
2934 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2935 continue;
2936
2937 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2938
2939 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2940
2941 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2942
2943 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2944
2945 bnxt_hwrm_vnic_free(bp, vnic);
2946
2947 rte_free(vnic->fw_grp_ids);
2948 }
2949 /* Ring resources */
2950 bnxt_free_all_hwrm_rings(bp);
2951 bnxt_free_all_hwrm_ring_grps(bp);
2952 bnxt_free_all_hwrm_stat_ctxs(bp);
2953 bnxt_free_tunnel_ports(bp);
2954 }
2955
bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)2956 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2957 {
2958 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2959
2960 if ((conf_link_speed & RTE_ETH_LINK_SPEED_FIXED) == RTE_ETH_LINK_SPEED_AUTONEG)
2961 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2962
2963 switch (conf_link_speed) {
2964 case RTE_ETH_LINK_SPEED_10M_HD:
2965 case RTE_ETH_LINK_SPEED_100M_HD:
2966 /* FALLTHROUGH */
2967 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2968 }
2969 return hw_link_duplex;
2970 }
2971
bnxt_check_eth_link_autoneg(uint32_t conf_link)2972 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2973 {
2974 return !conf_link;
2975 }
2976
bnxt_parse_eth_link_speed(uint32_t conf_link_speed,uint16_t pam4_link)2977 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed,
2978 uint16_t pam4_link)
2979 {
2980 uint16_t eth_link_speed = 0;
2981
2982 if (conf_link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
2983 return RTE_ETH_LINK_SPEED_AUTONEG;
2984
2985 switch (conf_link_speed & ~RTE_ETH_LINK_SPEED_FIXED) {
2986 case RTE_ETH_LINK_SPEED_100M:
2987 case RTE_ETH_LINK_SPEED_100M_HD:
2988 /* FALLTHROUGH */
2989 eth_link_speed =
2990 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2991 break;
2992 case RTE_ETH_LINK_SPEED_1G:
2993 eth_link_speed =
2994 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2995 break;
2996 case RTE_ETH_LINK_SPEED_2_5G:
2997 eth_link_speed =
2998 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2999 break;
3000 case RTE_ETH_LINK_SPEED_10G:
3001 eth_link_speed =
3002 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
3003 break;
3004 case RTE_ETH_LINK_SPEED_20G:
3005 eth_link_speed =
3006 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
3007 break;
3008 case RTE_ETH_LINK_SPEED_25G:
3009 eth_link_speed =
3010 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
3011 break;
3012 case RTE_ETH_LINK_SPEED_40G:
3013 eth_link_speed =
3014 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
3015 break;
3016 case RTE_ETH_LINK_SPEED_50G:
3017 eth_link_speed = pam4_link ?
3018 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB :
3019 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
3020 break;
3021 case RTE_ETH_LINK_SPEED_100G:
3022 eth_link_speed = pam4_link ?
3023 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB :
3024 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
3025 break;
3026 case RTE_ETH_LINK_SPEED_200G:
3027 eth_link_speed =
3028 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3029 break;
3030 default:
3031 PMD_DRV_LOG(ERR,
3032 "Unsupported link speed %d; default to AUTO\n",
3033 conf_link_speed);
3034 break;
3035 }
3036 return eth_link_speed;
3037 }
3038
3039 #define BNXT_SUPPORTED_SPEEDS (RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_100M_HD | \
3040 RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_2_5G | \
3041 RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_20G | RTE_ETH_LINK_SPEED_25G | \
3042 RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_50G | \
3043 RTE_ETH_LINK_SPEED_100G | RTE_ETH_LINK_SPEED_200G)
3044
bnxt_validate_link_speed(struct bnxt * bp)3045 static int bnxt_validate_link_speed(struct bnxt *bp)
3046 {
3047 uint32_t link_speed = bp->eth_dev->data->dev_conf.link_speeds;
3048 uint16_t port_id = bp->eth_dev->data->port_id;
3049 uint32_t link_speed_capa;
3050 uint32_t one_speed;
3051
3052 if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG)
3053 return 0;
3054
3055 link_speed_capa = bnxt_get_speed_capabilities(bp);
3056
3057 if (link_speed & RTE_ETH_LINK_SPEED_FIXED) {
3058 one_speed = link_speed & ~RTE_ETH_LINK_SPEED_FIXED;
3059
3060 if (one_speed & (one_speed - 1)) {
3061 PMD_DRV_LOG(ERR,
3062 "Invalid advertised speeds (%u) for port %u\n",
3063 link_speed, port_id);
3064 return -EINVAL;
3065 }
3066 if ((one_speed & link_speed_capa) != one_speed) {
3067 PMD_DRV_LOG(ERR,
3068 "Unsupported advertised speed (%u) for port %u\n",
3069 link_speed, port_id);
3070 return -EINVAL;
3071 }
3072 } else {
3073 if (!(link_speed & link_speed_capa)) {
3074 PMD_DRV_LOG(ERR,
3075 "Unsupported advertised speeds (%u) for port %u\n",
3076 link_speed, port_id);
3077 return -EINVAL;
3078 }
3079 }
3080 return 0;
3081 }
3082
3083 static uint16_t
bnxt_parse_eth_link_speed_mask(struct bnxt * bp,uint32_t link_speed)3084 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
3085 {
3086 uint16_t ret = 0;
3087
3088 if (link_speed == RTE_ETH_LINK_SPEED_AUTONEG) {
3089 if (bp->link_info->support_speeds)
3090 return bp->link_info->support_speeds;
3091 link_speed = BNXT_SUPPORTED_SPEEDS;
3092 }
3093
3094 if (link_speed & RTE_ETH_LINK_SPEED_100M)
3095 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3096 if (link_speed & RTE_ETH_LINK_SPEED_100M_HD)
3097 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
3098 if (link_speed & RTE_ETH_LINK_SPEED_1G)
3099 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
3100 if (link_speed & RTE_ETH_LINK_SPEED_2_5G)
3101 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
3102 if (link_speed & RTE_ETH_LINK_SPEED_10G)
3103 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
3104 if (link_speed & RTE_ETH_LINK_SPEED_20G)
3105 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
3106 if (link_speed & RTE_ETH_LINK_SPEED_25G)
3107 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
3108 if (link_speed & RTE_ETH_LINK_SPEED_40G)
3109 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
3110 if (link_speed & RTE_ETH_LINK_SPEED_50G)
3111 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
3112 if (link_speed & RTE_ETH_LINK_SPEED_100G)
3113 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
3114 if (link_speed & RTE_ETH_LINK_SPEED_200G)
3115 ret |= HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB;
3116 return ret;
3117 }
3118
bnxt_parse_hw_link_speed(uint16_t hw_link_speed)3119 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
3120 {
3121 uint32_t eth_link_speed = RTE_ETH_SPEED_NUM_NONE;
3122
3123 switch (hw_link_speed) {
3124 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
3125 eth_link_speed = RTE_ETH_SPEED_NUM_100M;
3126 break;
3127 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
3128 eth_link_speed = RTE_ETH_SPEED_NUM_1G;
3129 break;
3130 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
3131 eth_link_speed = RTE_ETH_SPEED_NUM_2_5G;
3132 break;
3133 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
3134 eth_link_speed = RTE_ETH_SPEED_NUM_10G;
3135 break;
3136 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
3137 eth_link_speed = RTE_ETH_SPEED_NUM_20G;
3138 break;
3139 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
3140 eth_link_speed = RTE_ETH_SPEED_NUM_25G;
3141 break;
3142 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
3143 eth_link_speed = RTE_ETH_SPEED_NUM_40G;
3144 break;
3145 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
3146 eth_link_speed = RTE_ETH_SPEED_NUM_50G;
3147 break;
3148 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
3149 eth_link_speed = RTE_ETH_SPEED_NUM_100G;
3150 break;
3151 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
3152 eth_link_speed = RTE_ETH_SPEED_NUM_200G;
3153 break;
3154 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
3155 default:
3156 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
3157 hw_link_speed);
3158 break;
3159 }
3160 return eth_link_speed;
3161 }
3162
bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)3163 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
3164 {
3165 uint16_t eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3166
3167 switch (hw_link_duplex) {
3168 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
3169 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
3170 /* FALLTHROUGH */
3171 eth_link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3172 break;
3173 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
3174 eth_link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
3175 break;
3176 default:
3177 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
3178 hw_link_duplex);
3179 break;
3180 }
3181 return eth_link_duplex;
3182 }
3183
bnxt_get_hwrm_link_config(struct bnxt * bp,struct rte_eth_link * link)3184 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
3185 {
3186 int rc = 0;
3187 struct bnxt_link_info *link_info = bp->link_info;
3188
3189 rc = bnxt_hwrm_port_phy_qcaps(bp);
3190 if (rc)
3191 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3192
3193 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
3194 if (rc) {
3195 PMD_DRV_LOG(ERR, "Get link config failed with rc %d\n", rc);
3196 goto exit;
3197 }
3198
3199 if (link_info->link_speed)
3200 link->link_speed =
3201 bnxt_parse_hw_link_speed(link_info->link_speed);
3202 else
3203 link->link_speed = RTE_ETH_SPEED_NUM_NONE;
3204 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
3205 link->link_status = link_info->link_up;
3206 link->link_autoneg = link_info->auto_mode ==
3207 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
3208 RTE_ETH_LINK_FIXED : RTE_ETH_LINK_AUTONEG;
3209 exit:
3210 return rc;
3211 }
3212
bnxt_set_hwrm_link_config(struct bnxt * bp,bool link_up)3213 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
3214 {
3215 int rc = 0;
3216 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
3217 struct bnxt_link_info link_req;
3218 uint16_t speed, autoneg;
3219
3220 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
3221 return 0;
3222
3223 rc = bnxt_validate_link_speed(bp);
3224 if (rc)
3225 goto error;
3226
3227 memset(&link_req, 0, sizeof(link_req));
3228 link_req.link_up = link_up;
3229 if (!link_up)
3230 goto port_phy_cfg;
3231
3232 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
3233 if (BNXT_CHIP_P5(bp) &&
3234 dev_conf->link_speeds == RTE_ETH_LINK_SPEED_40G) {
3235 /* 40G is not supported as part of media auto detect.
3236 * The speed should be forced and autoneg disabled
3237 * to configure 40G speed.
3238 */
3239 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
3240 autoneg = 0;
3241 }
3242
3243 /* No auto speeds and no auto_pam4_link. Disable autoneg */
3244 if (bp->link_info->auto_link_speed == 0 &&
3245 bp->link_info->link_signal_mode &&
3246 bp->link_info->auto_pam4_link_speed_mask == 0)
3247 autoneg = 0;
3248
3249 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds,
3250 bp->link_info->link_signal_mode);
3251 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
3252 /* Autoneg can be done only when the FW allows. */
3253 if (autoneg == 1 &&
3254 (bp->link_info->support_auto_speeds || bp->link_info->support_pam4_auto_speeds)) {
3255 link_req.phy_flags |=
3256 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
3257 link_req.auto_link_speed_mask =
3258 bnxt_parse_eth_link_speed_mask(bp,
3259 dev_conf->link_speeds);
3260 link_req.auto_pam4_link_speed_mask =
3261 bp->link_info->auto_pam4_link_speed_mask;
3262 } else {
3263 if (bp->link_info->phy_type ==
3264 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3265 bp->link_info->phy_type ==
3266 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3267 bp->link_info->media_type ==
3268 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3269 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3270 return -EINVAL;
3271 }
3272
3273 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3274 /* If user wants a particular speed try that first. */
3275 if (speed)
3276 link_req.link_speed = speed;
3277 else if (bp->link_info->force_pam4_link_speed)
3278 link_req.link_speed =
3279 bp->link_info->force_pam4_link_speed;
3280 else if (bp->link_info->auto_pam4_link_speed_mask)
3281 link_req.link_speed =
3282 bp->link_info->auto_pam4_link_speed_mask;
3283 else if (bp->link_info->support_pam4_speeds)
3284 link_req.link_speed =
3285 bp->link_info->support_pam4_speeds;
3286 else if (bp->link_info->force_link_speed)
3287 link_req.link_speed = bp->link_info->force_link_speed;
3288 else
3289 link_req.link_speed = bp->link_info->auto_link_speed;
3290 /* Auto PAM4 link speed is zero, but auto_link_speed is not
3291 * zero. Use the auto_link_speed.
3292 */
3293 if (bp->link_info->auto_link_speed != 0 &&
3294 bp->link_info->auto_pam4_link_speed_mask == 0)
3295 link_req.link_speed = bp->link_info->auto_link_speed;
3296 }
3297 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3298 link_req.auto_pause = bp->link_info->auto_pause;
3299 link_req.force_pause = bp->link_info->force_pause;
3300
3301 port_phy_cfg:
3302 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3303 if (rc) {
3304 PMD_DRV_LOG(ERR,
3305 "Set link config failed with rc %d\n", rc);
3306 }
3307
3308 error:
3309 return rc;
3310 }
3311
bnxt_hwrm_func_qcfg(struct bnxt * bp,uint16_t * mtu)3312 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3313 {
3314 struct hwrm_func_qcfg_input req = {0};
3315 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3316 uint16_t flags;
3317 int rc = 0;
3318 bp->func_svif = BNXT_SVIF_INVALID;
3319 uint16_t svif_info;
3320
3321 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3322 req.fid = rte_cpu_to_le_16(0xffff);
3323
3324 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3325
3326 HWRM_CHECK_RESULT();
3327
3328 bp->vlan = rte_le_to_cpu_16(resp->vlan) & RTE_ETH_VLAN_ID_MAX;
3329
3330 svif_info = rte_le_to_cpu_16(resp->svif_info);
3331 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3332 bp->func_svif = svif_info &
3333 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3334
3335 flags = rte_le_to_cpu_16(resp->flags);
3336 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3337 bp->flags |= BNXT_FLAG_MULTI_HOST;
3338
3339 if (BNXT_VF(bp) &&
3340 !BNXT_VF_IS_TRUSTED(bp) &&
3341 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3342 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3343 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3344 } else if (BNXT_VF(bp) &&
3345 BNXT_VF_IS_TRUSTED(bp) &&
3346 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3347 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3348 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3349 }
3350
3351 if (mtu)
3352 *mtu = rte_le_to_cpu_16(resp->admin_mtu);
3353
3354 switch (resp->port_partition_type) {
3355 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3356 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3357 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3358 /* FALLTHROUGH */
3359 bp->flags |= BNXT_FLAG_NPAR_PF;
3360 break;
3361 default:
3362 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3363 break;
3364 }
3365
3366 bp->legacy_db_size =
3367 rte_le_to_cpu_16(resp->legacy_l2_db_size_kb) * 1024;
3368
3369 HWRM_UNLOCK();
3370
3371 return rc;
3372 }
3373
bnxt_hwrm_parent_pf_qcfg(struct bnxt * bp)3374 int bnxt_hwrm_parent_pf_qcfg(struct bnxt *bp)
3375 {
3376 struct hwrm_func_qcfg_input req = {0};
3377 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3378 uint16_t flags;
3379 int rc;
3380
3381 if (!BNXT_VF_IS_TRUSTED(bp))
3382 return 0;
3383
3384 if (!bp->parent)
3385 return -EINVAL;
3386
3387 bp->parent->fid = BNXT_PF_FID_INVALID;
3388
3389 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3390
3391 req.fid = rte_cpu_to_le_16(0xfffe); /* Request parent PF information. */
3392
3393 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3394
3395 HWRM_CHECK_RESULT_SILENT();
3396
3397 memcpy(bp->parent->mac_addr, resp->mac_address, RTE_ETHER_ADDR_LEN);
3398 bp->parent->vnic = rte_le_to_cpu_16(resp->dflt_vnic_id);
3399 bp->parent->fid = rte_le_to_cpu_16(resp->fid);
3400 bp->parent->port_id = rte_le_to_cpu_16(resp->port_id);
3401
3402 flags = rte_le_to_cpu_16(resp->flags);
3403 /* check for the multi-root support */
3404 if (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT) {
3405 bp->flags2 |= BNXT_FLAGS2_MULTIROOT_EN;
3406 PMD_DRV_LOG(DEBUG, "PF enabled with multi root capability\n");
3407 }
3408
3409 HWRM_UNLOCK();
3410
3411 return 0;
3412 }
3413
bnxt_hwrm_get_dflt_vnic_svif(struct bnxt * bp,uint16_t fid,uint16_t * vnic_id,uint16_t * svif)3414 int bnxt_hwrm_get_dflt_vnic_svif(struct bnxt *bp, uint16_t fid,
3415 uint16_t *vnic_id, uint16_t *svif)
3416 {
3417 struct hwrm_func_qcfg_input req = {0};
3418 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3419 uint16_t svif_info;
3420 int rc = 0;
3421
3422 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3423 req.fid = rte_cpu_to_le_16(fid);
3424
3425 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3426
3427 HWRM_CHECK_RESULT();
3428
3429 if (vnic_id)
3430 *vnic_id = rte_le_to_cpu_16(resp->dflt_vnic_id);
3431
3432 svif_info = rte_le_to_cpu_16(resp->svif_info);
3433 if (svif && (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID))
3434 *svif = svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3435
3436 HWRM_UNLOCK();
3437
3438 return rc;
3439 }
3440
bnxt_hwrm_port_mac_qcfg(struct bnxt * bp)3441 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3442 {
3443 struct hwrm_port_mac_qcfg_input req = {0};
3444 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3445 uint16_t port_svif_info;
3446 int rc;
3447
3448 bp->port_svif = BNXT_SVIF_INVALID;
3449
3450 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3451 return 0;
3452
3453 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3454
3455 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3456
3457 HWRM_CHECK_RESULT_SILENT();
3458
3459 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3460 if (port_svif_info &
3461 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3462 bp->port_svif = port_svif_info &
3463 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3464
3465 HWRM_UNLOCK();
3466
3467 return 0;
3468 }
3469
bnxt_hwrm_pf_func_cfg(struct bnxt * bp,struct bnxt_pf_resource_info * pf_resc)3470 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp,
3471 struct bnxt_pf_resource_info *pf_resc)
3472 {
3473 struct hwrm_func_cfg_input req = {0};
3474 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3475 uint32_t enables;
3476 int rc;
3477
3478 enables = HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3479 HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU |
3480 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3481 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3482 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3483 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3484 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3485 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3486 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3487 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3488
3489 if (BNXT_HAS_RING_GRPS(bp)) {
3490 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3491 req.num_hw_ring_grps =
3492 rte_cpu_to_le_16(pf_resc->num_hw_ring_grps);
3493 } else if (BNXT_HAS_NQ(bp)) {
3494 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3495 req.num_msix = rte_cpu_to_le_16(pf_resc->num_nq_rings);
3496 }
3497
3498 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3499 req.admin_mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3500 req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
3501 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3502 req.num_rsscos_ctxs = rte_cpu_to_le_16(pf_resc->num_rsscos_ctxs);
3503 req.num_stat_ctxs = rte_cpu_to_le_16(pf_resc->num_stat_ctxs);
3504 req.num_cmpl_rings = rte_cpu_to_le_16(pf_resc->num_cp_rings);
3505 req.num_tx_rings = rte_cpu_to_le_16(pf_resc->num_tx_rings);
3506 req.num_rx_rings = rte_cpu_to_le_16(pf_resc->num_rx_rings);
3507 req.num_l2_ctxs = rte_cpu_to_le_16(pf_resc->num_l2_ctxs);
3508 req.num_vnics = rte_cpu_to_le_16(pf_resc->num_vnics);
3509 req.fid = rte_cpu_to_le_16(0xffff);
3510 req.enables = rte_cpu_to_le_32(enables);
3511
3512 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3513
3514 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3515
3516 HWRM_CHECK_RESULT();
3517 HWRM_UNLOCK();
3518
3519 return rc;
3520 }
3521
3522 /* min values are the guaranteed resources and max values are subject
3523 * to availability. The strategy for now is to keep both min & max
3524 * values the same.
3525 */
3526 static void
bnxt_fill_vf_func_cfg_req_new(struct bnxt * bp,struct hwrm_func_vf_resource_cfg_input * req,int num_vfs)3527 bnxt_fill_vf_func_cfg_req_new(struct bnxt *bp,
3528 struct hwrm_func_vf_resource_cfg_input *req,
3529 int num_vfs)
3530 {
3531 req->max_rsscos_ctx = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3532 (num_vfs + 1));
3533 req->min_rsscos_ctx = req->max_rsscos_ctx;
3534 req->max_stat_ctx = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3535 req->min_stat_ctx = req->max_stat_ctx;
3536 req->max_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3537 (num_vfs + 1));
3538 req->min_cmpl_rings = req->max_cmpl_rings;
3539 req->max_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3540 req->min_tx_rings = req->max_tx_rings;
3541 req->max_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3542 req->min_rx_rings = req->max_rx_rings;
3543 req->max_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3544 req->min_l2_ctxs = req->max_l2_ctxs;
3545 req->max_vnics = rte_cpu_to_le_16(bp->max_vnics / (num_vfs + 1));
3546 req->min_vnics = req->max_vnics;
3547 req->max_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3548 (num_vfs + 1));
3549 req->min_hw_ring_grps = req->max_hw_ring_grps;
3550 req->max_msix = rte_cpu_to_le_16(bp->max_nq_rings / (num_vfs + 1));
3551 }
3552
3553 static void
bnxt_fill_vf_func_cfg_req_old(struct bnxt * bp,struct hwrm_func_cfg_input * req,int num_vfs)3554 bnxt_fill_vf_func_cfg_req_old(struct bnxt *bp,
3555 struct hwrm_func_cfg_input *req,
3556 int num_vfs)
3557 {
3558 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU |
3559 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3560 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3561 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3562 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3563 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3564 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3565 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3566 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3567 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3568
3569 req->admin_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3570 RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN *
3571 BNXT_NUM_VLANS);
3572 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3573 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3574 (num_vfs + 1));
3575 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3576 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3577 (num_vfs + 1));
3578 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3579 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3580 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3581 /* TODO: For now, do not support VMDq/RFS on VFs. */
3582 req->num_vnics = rte_cpu_to_le_16(1);
3583 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3584 (num_vfs + 1));
3585 }
3586
3587 /* Update the port wide resource values based on how many resources
3588 * got allocated to the VF.
3589 */
bnxt_update_max_resources(struct bnxt * bp,int vf)3590 static int bnxt_update_max_resources(struct bnxt *bp,
3591 int vf)
3592 {
3593 struct hwrm_func_qcfg_input req = {0};
3594 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3595 int rc;
3596
3597 /* Get the actual allocated values now */
3598 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3599 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3600 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3601 HWRM_CHECK_RESULT();
3602
3603 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3604 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->alloc_stat_ctx);
3605 bp->max_cp_rings -= rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3606 bp->max_tx_rings -= rte_le_to_cpu_16(resp->alloc_tx_rings);
3607 bp->max_rx_rings -= rte_le_to_cpu_16(resp->alloc_rx_rings);
3608 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->alloc_l2_ctx);
3609 bp->max_ring_grps -= rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3610 bp->max_nq_rings -= rte_le_to_cpu_16(resp->alloc_msix);
3611 bp->max_vnics -= rte_le_to_cpu_16(resp->alloc_vnics);
3612
3613 HWRM_UNLOCK();
3614
3615 return 0;
3616 }
3617
3618 /* Update the PF resource values based on how many resources
3619 * got allocated to it.
3620 */
bnxt_update_max_resources_pf_only(struct bnxt * bp)3621 static int bnxt_update_max_resources_pf_only(struct bnxt *bp)
3622 {
3623 struct hwrm_func_qcfg_input req = {0};
3624 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3625 int rc;
3626
3627 /* Get the actual allocated values now */
3628 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3629 req.fid = rte_cpu_to_le_16(0xffff);
3630 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3631 HWRM_CHECK_RESULT();
3632
3633 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3634 bp->max_stat_ctx = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3635 bp->max_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3636 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3637 bp->max_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3638 bp->max_l2_ctx = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3639 bp->max_ring_grps = rte_le_to_cpu_16(resp->alloc_hw_ring_grps);
3640 bp->max_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3641
3642 HWRM_UNLOCK();
3643
3644 return 0;
3645 }
3646
bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt * bp,int vf)3647 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3648 {
3649 struct hwrm_func_qcfg_input req = {0};
3650 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3651 int rc;
3652
3653 /* Check for zero MAC address */
3654 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3655 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3656 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3657 HWRM_CHECK_RESULT();
3658 rc = rte_le_to_cpu_16(resp->vlan);
3659
3660 HWRM_UNLOCK();
3661
3662 return rc;
3663 }
3664
bnxt_query_pf_resources(struct bnxt * bp,struct bnxt_pf_resource_info * pf_resc)3665 static int bnxt_query_pf_resources(struct bnxt *bp,
3666 struct bnxt_pf_resource_info *pf_resc)
3667 {
3668 struct hwrm_func_qcfg_input req = {0};
3669 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3670 int rc;
3671
3672 /* And copy the allocated numbers into the pf struct */
3673 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3674 req.fid = rte_cpu_to_le_16(0xffff);
3675 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3676 HWRM_CHECK_RESULT();
3677
3678 pf_resc->num_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3679 pf_resc->num_rsscos_ctxs = rte_le_to_cpu_16(resp->alloc_rsscos_ctx);
3680 pf_resc->num_stat_ctxs = rte_le_to_cpu_16(resp->alloc_stat_ctx);
3681 pf_resc->num_cp_rings = rte_le_to_cpu_16(resp->alloc_cmpl_rings);
3682 pf_resc->num_rx_rings = rte_le_to_cpu_16(resp->alloc_rx_rings);
3683 pf_resc->num_l2_ctxs = rte_le_to_cpu_16(resp->alloc_l2_ctx);
3684 pf_resc->num_hw_ring_grps = rte_le_to_cpu_32(resp->alloc_hw_ring_grps);
3685 pf_resc->num_nq_rings = rte_le_to_cpu_32(resp->alloc_msix);
3686 pf_resc->num_vnics = rte_le_to_cpu_16(resp->alloc_vnics);
3687 bp->pf->evb_mode = resp->evb_mode;
3688
3689 HWRM_UNLOCK();
3690
3691 return rc;
3692 }
3693
3694 static void
bnxt_calculate_pf_resources(struct bnxt * bp,struct bnxt_pf_resource_info * pf_resc,int num_vfs)3695 bnxt_calculate_pf_resources(struct bnxt *bp,
3696 struct bnxt_pf_resource_info *pf_resc,
3697 int num_vfs)
3698 {
3699 if (!num_vfs) {
3700 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx;
3701 pf_resc->num_stat_ctxs = bp->max_stat_ctx;
3702 pf_resc->num_cp_rings = bp->max_cp_rings;
3703 pf_resc->num_tx_rings = bp->max_tx_rings;
3704 pf_resc->num_rx_rings = bp->max_rx_rings;
3705 pf_resc->num_l2_ctxs = bp->max_l2_ctx;
3706 pf_resc->num_hw_ring_grps = bp->max_ring_grps;
3707 pf_resc->num_nq_rings = bp->max_nq_rings;
3708 pf_resc->num_vnics = bp->max_vnics;
3709
3710 return;
3711 }
3712
3713 pf_resc->num_rsscos_ctxs = bp->max_rsscos_ctx / (num_vfs + 1) +
3714 bp->max_rsscos_ctx % (num_vfs + 1);
3715 pf_resc->num_stat_ctxs = bp->max_stat_ctx / (num_vfs + 1) +
3716 bp->max_stat_ctx % (num_vfs + 1);
3717 pf_resc->num_cp_rings = bp->max_cp_rings / (num_vfs + 1) +
3718 bp->max_cp_rings % (num_vfs + 1);
3719 pf_resc->num_tx_rings = bp->max_tx_rings / (num_vfs + 1) +
3720 bp->max_tx_rings % (num_vfs + 1);
3721 pf_resc->num_rx_rings = bp->max_rx_rings / (num_vfs + 1) +
3722 bp->max_rx_rings % (num_vfs + 1);
3723 pf_resc->num_l2_ctxs = bp->max_l2_ctx / (num_vfs + 1) +
3724 bp->max_l2_ctx % (num_vfs + 1);
3725 pf_resc->num_hw_ring_grps = bp->max_ring_grps / (num_vfs + 1) +
3726 bp->max_ring_grps % (num_vfs + 1);
3727 pf_resc->num_nq_rings = bp->max_nq_rings / (num_vfs + 1) +
3728 bp->max_nq_rings % (num_vfs + 1);
3729 pf_resc->num_vnics = bp->max_vnics / (num_vfs + 1) +
3730 bp->max_vnics % (num_vfs + 1);
3731 }
3732
bnxt_hwrm_allocate_pf_only(struct bnxt * bp)3733 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3734 {
3735 struct bnxt_pf_resource_info pf_resc = { 0 };
3736 int rc;
3737
3738 if (!BNXT_PF(bp)) {
3739 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3740 return -EINVAL;
3741 }
3742
3743 rc = bnxt_hwrm_func_qcaps(bp);
3744 if (rc)
3745 return rc;
3746
3747 bnxt_calculate_pf_resources(bp, &pf_resc, 0);
3748
3749 bp->pf->func_cfg_flags &=
3750 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3751 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3752 bp->pf->func_cfg_flags |=
3753 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3754
3755 rc = bnxt_hwrm_pf_func_cfg(bp, &pf_resc);
3756 if (rc)
3757 return rc;
3758
3759 rc = bnxt_update_max_resources_pf_only(bp);
3760
3761 return rc;
3762 }
3763
3764 static int
bnxt_configure_vf_req_buf(struct bnxt * bp,int num_vfs)3765 bnxt_configure_vf_req_buf(struct bnxt *bp, int num_vfs)
3766 {
3767 size_t req_buf_sz, sz;
3768 int i, rc;
3769
3770 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3771 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3772 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3773 if (bp->pf->vf_req_buf == NULL) {
3774 return -ENOMEM;
3775 }
3776
3777 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3778 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3779
3780 for (i = 0; i < num_vfs; i++)
3781 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3782 (i * HWRM_MAX_REQ_LEN);
3783
3784 rc = bnxt_hwrm_func_buf_rgtr(bp, num_vfs);
3785 if (rc)
3786 rte_free(bp->pf->vf_req_buf);
3787
3788 return rc;
3789 }
3790
3791 static int
bnxt_process_vf_resc_config_new(struct bnxt * bp,int num_vfs)3792 bnxt_process_vf_resc_config_new(struct bnxt *bp, int num_vfs)
3793 {
3794 struct hwrm_func_vf_resource_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3795 struct hwrm_func_vf_resource_cfg_input req = {0};
3796 int i, rc = 0;
3797
3798 bnxt_fill_vf_func_cfg_req_new(bp, &req, num_vfs);
3799 bp->pf->active_vfs = 0;
3800 for (i = 0; i < num_vfs; i++) {
3801 HWRM_PREP(&req, HWRM_FUNC_VF_RESOURCE_CFG, BNXT_USE_CHIMP_MB);
3802 req.vf_id = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3803 rc = bnxt_hwrm_send_message(bp,
3804 &req,
3805 sizeof(req),
3806 BNXT_USE_CHIMP_MB);
3807 if (rc || resp->error_code) {
3808 PMD_DRV_LOG(ERR,
3809 "Failed to initialize VF %d\n", i);
3810 PMD_DRV_LOG(ERR,
3811 "Not all VFs available. (%d, %d)\n",
3812 rc, resp->error_code);
3813 HWRM_UNLOCK();
3814
3815 /* If the first VF configuration itself fails,
3816 * unregister the vf_fwd_request buffer.
3817 */
3818 if (i == 0)
3819 bnxt_hwrm_func_buf_unrgtr(bp);
3820 break;
3821 }
3822 HWRM_UNLOCK();
3823
3824 /* Update the max resource values based on the resource values
3825 * allocated to the VF.
3826 */
3827 bnxt_update_max_resources(bp, i);
3828 bp->pf->active_vfs++;
3829 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3830 }
3831
3832 return 0;
3833 }
3834
3835 static int
bnxt_process_vf_resc_config_old(struct bnxt * bp,int num_vfs)3836 bnxt_process_vf_resc_config_old(struct bnxt *bp, int num_vfs)
3837 {
3838 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3839 struct hwrm_func_cfg_input req = {0};
3840 int i, rc;
3841
3842 bnxt_fill_vf_func_cfg_req_old(bp, &req, num_vfs);
3843
3844 bp->pf->active_vfs = 0;
3845 for (i = 0; i < num_vfs; i++) {
3846 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3847 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3848 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3849 rc = bnxt_hwrm_send_message(bp,
3850 &req,
3851 sizeof(req),
3852 BNXT_USE_CHIMP_MB);
3853
3854 /* Clear enable flag for next pass */
3855 req.enables &= ~rte_cpu_to_le_32(
3856 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3857
3858 if (rc || resp->error_code) {
3859 PMD_DRV_LOG(ERR,
3860 "Failed to initialize VF %d\n", i);
3861 PMD_DRV_LOG(ERR,
3862 "Not all VFs available. (%d, %d)\n",
3863 rc, resp->error_code);
3864 HWRM_UNLOCK();
3865
3866 /* If the first VF configuration itself fails,
3867 * unregister the vf_fwd_request buffer.
3868 */
3869 if (i == 0)
3870 bnxt_hwrm_func_buf_unrgtr(bp);
3871 break;
3872 }
3873
3874 HWRM_UNLOCK();
3875
3876 /* Update the max resource values based on the resource values
3877 * allocated to the VF.
3878 */
3879 bnxt_update_max_resources(bp, i);
3880 bp->pf->active_vfs++;
3881 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3882 }
3883
3884 return 0;
3885 }
3886
3887 static void
bnxt_configure_vf_resources(struct bnxt * bp,int num_vfs)3888 bnxt_configure_vf_resources(struct bnxt *bp, int num_vfs)
3889 {
3890 if (bp->flags & BNXT_FLAG_NEW_RM)
3891 bnxt_process_vf_resc_config_new(bp, num_vfs);
3892 else
3893 bnxt_process_vf_resc_config_old(bp, num_vfs);
3894 }
3895
3896 static void
bnxt_update_pf_resources(struct bnxt * bp,struct bnxt_pf_resource_info * pf_resc)3897 bnxt_update_pf_resources(struct bnxt *bp,
3898 struct bnxt_pf_resource_info *pf_resc)
3899 {
3900 bp->max_rsscos_ctx = pf_resc->num_rsscos_ctxs;
3901 bp->max_stat_ctx = pf_resc->num_stat_ctxs;
3902 bp->max_cp_rings = pf_resc->num_cp_rings;
3903 bp->max_tx_rings = pf_resc->num_tx_rings;
3904 bp->max_rx_rings = pf_resc->num_rx_rings;
3905 bp->max_ring_grps = pf_resc->num_hw_ring_grps;
3906 bp->max_nq_rings = pf_resc->num_nq_rings;
3907 bp->max_vnics = pf_resc->num_vnics;
3908 }
3909
3910 static int32_t
bnxt_configure_pf_resources(struct bnxt * bp,struct bnxt_pf_resource_info * pf_resc)3911 bnxt_configure_pf_resources(struct bnxt *bp,
3912 struct bnxt_pf_resource_info *pf_resc)
3913 {
3914 /*
3915 * We're using STD_TX_RING_MODE here which will limit the TX
3916 * rings. This will allow QoS to function properly. Not setting this
3917 * will cause PF rings to break bandwidth settings.
3918 */
3919 bp->pf->func_cfg_flags &=
3920 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3921 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3922 bp->pf->func_cfg_flags |=
3923 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3924 return bnxt_hwrm_pf_func_cfg(bp, pf_resc);
3925 }
3926
bnxt_hwrm_allocate_vfs(struct bnxt * bp,int num_vfs)3927 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3928 {
3929 struct bnxt_pf_resource_info pf_resc = { 0 };
3930 int rc;
3931
3932 if (!BNXT_PF(bp)) {
3933 PMD_DRV_LOG(ERR, "Attempt to allocate VFs on a VF!\n");
3934 return -EINVAL;
3935 }
3936
3937 rc = bnxt_hwrm_func_qcaps(bp);
3938 if (rc)
3939 return rc;
3940
3941 bnxt_calculate_pf_resources(bp, &pf_resc, num_vfs);
3942
3943 rc = bnxt_configure_pf_resources(bp, &pf_resc);
3944 if (rc)
3945 return rc;
3946
3947 rc = bnxt_query_pf_resources(bp, &pf_resc);
3948 if (rc)
3949 return rc;
3950
3951 /*
3952 * Now, create and register a buffer to hold forwarded VF requests
3953 */
3954 rc = bnxt_configure_vf_req_buf(bp, num_vfs);
3955 if (rc)
3956 return rc;
3957
3958 bnxt_configure_vf_resources(bp, num_vfs);
3959
3960 bnxt_update_pf_resources(bp, &pf_resc);
3961
3962 return 0;
3963 }
3964
bnxt_hwrm_pf_evb_mode(struct bnxt * bp)3965 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3966 {
3967 struct hwrm_func_cfg_input req = {0};
3968 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3969 int rc;
3970
3971 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3972
3973 req.fid = rte_cpu_to_le_16(0xffff);
3974 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3975 req.evb_mode = bp->pf->evb_mode;
3976
3977 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3978 HWRM_CHECK_RESULT();
3979 HWRM_UNLOCK();
3980
3981 return rc;
3982 }
3983
bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt * bp,uint16_t port,uint8_t tunnel_type)3984 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3985 uint8_t tunnel_type)
3986 {
3987 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3988 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3989 int rc = 0;
3990
3991 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3992 req.tunnel_type = tunnel_type;
3993 req.tunnel_dst_port_val = rte_cpu_to_be_16(port);
3994 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3995 HWRM_CHECK_RESULT();
3996
3997 switch (tunnel_type) {
3998 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3999 bp->vxlan_fw_dst_port_id =
4000 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
4001 bp->vxlan_port = port;
4002 break;
4003 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
4004 bp->geneve_fw_dst_port_id =
4005 rte_le_to_cpu_16(resp->tunnel_dst_port_id);
4006 bp->geneve_port = port;
4007 break;
4008 default:
4009 break;
4010 }
4011
4012 HWRM_UNLOCK();
4013
4014 return rc;
4015 }
4016
bnxt_hwrm_tunnel_dst_port_free(struct bnxt * bp,uint16_t port,uint8_t tunnel_type)4017 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
4018 uint8_t tunnel_type)
4019 {
4020 struct hwrm_tunnel_dst_port_free_input req = {0};
4021 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
4022 int rc = 0;
4023
4024 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
4025
4026 req.tunnel_type = tunnel_type;
4027 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
4028 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4029
4030 HWRM_CHECK_RESULT();
4031 HWRM_UNLOCK();
4032
4033 if (tunnel_type ==
4034 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) {
4035 bp->vxlan_port = 0;
4036 bp->vxlan_port_cnt = 0;
4037 }
4038
4039 if (tunnel_type ==
4040 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) {
4041 bp->geneve_port = 0;
4042 bp->geneve_port_cnt = 0;
4043 }
4044
4045 return rc;
4046 }
4047
bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt * bp,uint16_t vf,uint32_t flags)4048 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
4049 uint32_t flags)
4050 {
4051 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4052 struct hwrm_func_cfg_input req = {0};
4053 int rc;
4054
4055 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4056
4057 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4058 req.flags = rte_cpu_to_le_32(flags);
4059 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4060
4061 HWRM_CHECK_RESULT();
4062 HWRM_UNLOCK();
4063
4064 return rc;
4065 }
4066
vf_vnic_set_rxmask_cb(struct bnxt_vnic_info * vnic,void * flagp)4067 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
4068 {
4069 uint32_t *flag = flagp;
4070
4071 vnic->flags = *flag;
4072 }
4073
bnxt_set_rx_mask_no_vlan(struct bnxt * bp,struct bnxt_vnic_info * vnic)4074 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4075 {
4076 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
4077 }
4078
bnxt_hwrm_func_buf_rgtr(struct bnxt * bp,int num_vfs)4079 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp, int num_vfs)
4080 {
4081 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4082 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
4083 int rc;
4084
4085 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
4086
4087 req.req_buf_num_pages = rte_cpu_to_le_16(1);
4088 req.req_buf_page_size =
4089 rte_cpu_to_le_16(page_getenum(num_vfs * HWRM_MAX_REQ_LEN));
4090 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
4091 req.req_buf_page_addr0 =
4092 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
4093 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
4094 PMD_DRV_LOG(ERR,
4095 "unable to map buffer address to physical memory\n");
4096 HWRM_UNLOCK();
4097 return -ENOMEM;
4098 }
4099
4100 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4101
4102 HWRM_CHECK_RESULT();
4103 HWRM_UNLOCK();
4104
4105 return rc;
4106 }
4107
bnxt_hwrm_func_buf_unrgtr(struct bnxt * bp)4108 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
4109 {
4110 int rc = 0;
4111 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
4112 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
4113
4114 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
4115 return 0;
4116
4117 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
4118
4119 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4120
4121 HWRM_CHECK_RESULT();
4122 HWRM_UNLOCK();
4123
4124 return rc;
4125 }
4126
bnxt_hwrm_func_cfg_def_cp(struct bnxt * bp)4127 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
4128 {
4129 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4130 struct hwrm_func_cfg_input req = {0};
4131 int rc;
4132
4133 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4134
4135 req.fid = rte_cpu_to_le_16(0xffff);
4136 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
4137 req.enables = rte_cpu_to_le_32(
4138 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4139 req.async_event_cr = rte_cpu_to_le_16(
4140 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4141 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4142
4143 HWRM_CHECK_RESULT();
4144 HWRM_UNLOCK();
4145
4146 return rc;
4147 }
4148
bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt * bp)4149 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
4150 {
4151 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4152 struct hwrm_func_vf_cfg_input req = {0};
4153 int rc;
4154
4155 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
4156
4157 req.enables = rte_cpu_to_le_32(
4158 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
4159 req.async_event_cr = rte_cpu_to_le_16(
4160 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
4161 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4162
4163 HWRM_CHECK_RESULT();
4164 HWRM_UNLOCK();
4165
4166 return rc;
4167 }
4168
bnxt_hwrm_set_default_vlan(struct bnxt * bp,int vf,uint8_t is_vf)4169 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
4170 {
4171 struct hwrm_func_cfg_input req = {0};
4172 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4173 uint16_t dflt_vlan, fid;
4174 uint32_t func_cfg_flags;
4175 int rc = 0;
4176
4177 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4178
4179 if (is_vf) {
4180 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
4181 fid = bp->pf->vf_info[vf].fid;
4182 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
4183 } else {
4184 fid = rte_cpu_to_le_16(0xffff);
4185 func_cfg_flags = bp->pf->func_cfg_flags;
4186 dflt_vlan = bp->vlan;
4187 }
4188
4189 req.flags = rte_cpu_to_le_32(func_cfg_flags);
4190 req.fid = rte_cpu_to_le_16(fid);
4191 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4192 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
4193
4194 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4195
4196 HWRM_CHECK_RESULT();
4197 HWRM_UNLOCK();
4198
4199 return rc;
4200 }
4201
bnxt_hwrm_func_bw_cfg(struct bnxt * bp,uint16_t vf,uint16_t max_bw,uint16_t enables)4202 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
4203 uint16_t max_bw, uint16_t enables)
4204 {
4205 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4206 struct hwrm_func_cfg_input req = {0};
4207 int rc;
4208
4209 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4210
4211 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4212 req.enables |= rte_cpu_to_le_32(enables);
4213 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4214 req.max_bw = rte_cpu_to_le_32(max_bw);
4215 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4216
4217 HWRM_CHECK_RESULT();
4218 HWRM_UNLOCK();
4219
4220 return rc;
4221 }
4222
bnxt_hwrm_set_vf_vlan(struct bnxt * bp,int vf)4223 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
4224 {
4225 struct hwrm_func_cfg_input req = {0};
4226 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4227 int rc = 0;
4228
4229 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4230
4231 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
4232 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4233 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
4234 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
4235
4236 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4237
4238 HWRM_CHECK_RESULT();
4239 HWRM_UNLOCK();
4240
4241 return rc;
4242 }
4243
bnxt_hwrm_set_async_event_cr(struct bnxt * bp)4244 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
4245 {
4246 int rc;
4247
4248 if (BNXT_PF(bp))
4249 rc = bnxt_hwrm_func_cfg_def_cp(bp);
4250 else
4251 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
4252
4253 return rc;
4254 }
4255
bnxt_hwrm_reject_fwd_resp(struct bnxt * bp,uint16_t target_id,void * encaped,size_t ec_size)4256 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
4257 void *encaped, size_t ec_size)
4258 {
4259 int rc = 0;
4260 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
4261 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4262
4263 if (ec_size > sizeof(req.encap_request))
4264 return -1;
4265
4266 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
4267
4268 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4269 memcpy(req.encap_request, encaped, ec_size);
4270
4271 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4272
4273 HWRM_CHECK_RESULT();
4274 HWRM_UNLOCK();
4275
4276 return rc;
4277 }
4278
bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt * bp,uint16_t vf,struct rte_ether_addr * mac)4279 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
4280 struct rte_ether_addr *mac)
4281 {
4282 struct hwrm_func_qcfg_input req = {0};
4283 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4284 int rc;
4285
4286 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
4287
4288 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4289 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4290
4291 HWRM_CHECK_RESULT();
4292
4293 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
4294
4295 HWRM_UNLOCK();
4296
4297 return rc;
4298 }
4299
bnxt_hwrm_exec_fwd_resp(struct bnxt * bp,uint16_t target_id,void * encaped,size_t ec_size)4300 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
4301 void *encaped, size_t ec_size)
4302 {
4303 int rc = 0;
4304 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
4305 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
4306
4307 if (ec_size > sizeof(req.encap_request))
4308 return -1;
4309
4310 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
4311
4312 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
4313 memcpy(req.encap_request, encaped, ec_size);
4314
4315 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4316
4317 HWRM_CHECK_RESULT();
4318 HWRM_UNLOCK();
4319
4320 return rc;
4321 }
4322
bnxt_update_prev_stat(uint64_t * cntr,uint64_t * prev_cntr)4323 static void bnxt_update_prev_stat(uint64_t *cntr, uint64_t *prev_cntr)
4324 {
4325 /* One of the HW stat values that make up this counter was zero as
4326 * returned by HW in this iteration, so use the previous
4327 * iteration's counter value
4328 */
4329 if (*prev_cntr && *cntr == 0)
4330 *cntr = *prev_cntr;
4331 else
4332 *prev_cntr = *cntr;
4333 }
4334
bnxt_hwrm_ring_stats(struct bnxt * bp,uint32_t cid,int idx,struct bnxt_ring_stats * ring_stats,bool rx)4335 int bnxt_hwrm_ring_stats(struct bnxt *bp, uint32_t cid, int idx,
4336 struct bnxt_ring_stats *ring_stats, bool rx)
4337 {
4338 int rc = 0;
4339 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
4340 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
4341
4342 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
4343
4344 req.stat_ctx_id = rte_cpu_to_le_32(cid);
4345
4346 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4347
4348 HWRM_CHECK_RESULT();
4349
4350 if (rx) {
4351 struct bnxt_ring_stats *prev_stats = &bp->prev_rx_ring_stats[idx];
4352
4353 ring_stats->rx_ucast_pkts = rte_le_to_cpu_64(resp->rx_ucast_pkts);
4354 bnxt_update_prev_stat(&ring_stats->rx_ucast_pkts,
4355 &prev_stats->rx_ucast_pkts);
4356
4357 ring_stats->rx_mcast_pkts = rte_le_to_cpu_64(resp->rx_mcast_pkts);
4358 bnxt_update_prev_stat(&ring_stats->rx_mcast_pkts,
4359 &prev_stats->rx_mcast_pkts);
4360
4361 ring_stats->rx_bcast_pkts = rte_le_to_cpu_64(resp->rx_bcast_pkts);
4362 bnxt_update_prev_stat(&ring_stats->rx_bcast_pkts,
4363 &prev_stats->rx_bcast_pkts);
4364
4365 ring_stats->rx_ucast_bytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
4366 bnxt_update_prev_stat(&ring_stats->rx_ucast_bytes,
4367 &prev_stats->rx_ucast_bytes);
4368
4369 ring_stats->rx_mcast_bytes = rte_le_to_cpu_64(resp->rx_mcast_bytes);
4370 bnxt_update_prev_stat(&ring_stats->rx_mcast_bytes,
4371 &prev_stats->rx_mcast_bytes);
4372
4373 ring_stats->rx_bcast_bytes = rte_le_to_cpu_64(resp->rx_bcast_bytes);
4374 bnxt_update_prev_stat(&ring_stats->rx_bcast_bytes,
4375 &prev_stats->rx_bcast_bytes);
4376
4377 ring_stats->rx_discard_pkts = rte_le_to_cpu_64(resp->rx_discard_pkts);
4378 bnxt_update_prev_stat(&ring_stats->rx_discard_pkts,
4379 &prev_stats->rx_discard_pkts);
4380
4381 ring_stats->rx_error_pkts = rte_le_to_cpu_64(resp->rx_error_pkts);
4382 bnxt_update_prev_stat(&ring_stats->rx_error_pkts,
4383 &prev_stats->rx_error_pkts);
4384
4385 ring_stats->rx_agg_pkts = rte_le_to_cpu_64(resp->rx_agg_pkts);
4386 bnxt_update_prev_stat(&ring_stats->rx_agg_pkts,
4387 &prev_stats->rx_agg_pkts);
4388
4389 ring_stats->rx_agg_bytes = rte_le_to_cpu_64(resp->rx_agg_bytes);
4390 bnxt_update_prev_stat(&ring_stats->rx_agg_bytes,
4391 &prev_stats->rx_agg_bytes);
4392
4393 ring_stats->rx_agg_events = rte_le_to_cpu_64(resp->rx_agg_events);
4394 bnxt_update_prev_stat(&ring_stats->rx_agg_events,
4395 &prev_stats->rx_agg_events);
4396
4397 ring_stats->rx_agg_aborts = rte_le_to_cpu_64(resp->rx_agg_aborts);
4398 bnxt_update_prev_stat(&ring_stats->rx_agg_aborts,
4399 &prev_stats->rx_agg_aborts);
4400 } else {
4401 struct bnxt_ring_stats *prev_stats = &bp->prev_tx_ring_stats[idx];
4402
4403 ring_stats->tx_ucast_pkts = rte_le_to_cpu_64(resp->tx_ucast_pkts);
4404 bnxt_update_prev_stat(&ring_stats->tx_ucast_pkts,
4405 &prev_stats->tx_ucast_pkts);
4406
4407 ring_stats->tx_mcast_pkts = rte_le_to_cpu_64(resp->tx_mcast_pkts);
4408 bnxt_update_prev_stat(&ring_stats->tx_mcast_pkts,
4409 &prev_stats->tx_mcast_pkts);
4410
4411 ring_stats->tx_bcast_pkts = rte_le_to_cpu_64(resp->tx_bcast_pkts);
4412 bnxt_update_prev_stat(&ring_stats->tx_bcast_pkts,
4413 &prev_stats->tx_bcast_pkts);
4414
4415 ring_stats->tx_ucast_bytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
4416 bnxt_update_prev_stat(&ring_stats->tx_ucast_bytes,
4417 &prev_stats->tx_ucast_bytes);
4418
4419 ring_stats->tx_mcast_bytes = rte_le_to_cpu_64(resp->tx_mcast_bytes);
4420 bnxt_update_prev_stat(&ring_stats->tx_mcast_bytes,
4421 &prev_stats->tx_mcast_bytes);
4422
4423 ring_stats->tx_bcast_bytes = rte_le_to_cpu_64(resp->tx_bcast_bytes);
4424 bnxt_update_prev_stat(&ring_stats->tx_bcast_bytes,
4425 &prev_stats->tx_bcast_bytes);
4426
4427 ring_stats->tx_discard_pkts = rte_le_to_cpu_64(resp->tx_discard_pkts);
4428 bnxt_update_prev_stat(&ring_stats->tx_discard_pkts,
4429 &prev_stats->tx_discard_pkts);
4430 }
4431
4432 HWRM_UNLOCK();
4433
4434 return rc;
4435 }
4436
bnxt_hwrm_port_qstats(struct bnxt * bp)4437 int bnxt_hwrm_port_qstats(struct bnxt *bp)
4438 {
4439 struct hwrm_port_qstats_input req = {0};
4440 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
4441 struct bnxt_pf_info *pf = bp->pf;
4442 int rc;
4443
4444 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
4445
4446 req.port_id = rte_cpu_to_le_16(pf->port_id);
4447 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
4448 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
4449 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4450
4451 HWRM_CHECK_RESULT();
4452 HWRM_UNLOCK();
4453
4454 return rc;
4455 }
4456
bnxt_hwrm_port_clr_stats(struct bnxt * bp)4457 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
4458 {
4459 struct hwrm_port_clr_stats_input req = {0};
4460 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
4461 struct bnxt_pf_info *pf = bp->pf;
4462 int rc;
4463
4464 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
4465 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
4466 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
4467 return 0;
4468
4469 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
4470
4471 req.port_id = rte_cpu_to_le_16(pf->port_id);
4472 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4473
4474 HWRM_CHECK_RESULT();
4475 HWRM_UNLOCK();
4476
4477 return rc;
4478 }
4479
bnxt_hwrm_port_led_qcaps(struct bnxt * bp)4480 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
4481 {
4482 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4483 struct hwrm_port_led_qcaps_input req = {0};
4484 int rc;
4485
4486 if (BNXT_VF(bp))
4487 return 0;
4488
4489 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
4490 req.port_id = bp->pf->port_id;
4491 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4492
4493 HWRM_CHECK_RESULT_SILENT();
4494
4495 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
4496 unsigned int i;
4497
4498 bp->leds->num_leds = resp->num_leds;
4499 memcpy(bp->leds, &resp->led0_id,
4500 sizeof(bp->leds[0]) * bp->leds->num_leds);
4501 for (i = 0; i < bp->leds->num_leds; i++) {
4502 struct bnxt_led_info *led = &bp->leds[i];
4503
4504 uint16_t caps = led->led_state_caps;
4505
4506 if (!led->led_group_id ||
4507 !BNXT_LED_ALT_BLINK_CAP(caps)) {
4508 bp->leds->num_leds = 0;
4509 break;
4510 }
4511 }
4512 }
4513
4514 HWRM_UNLOCK();
4515
4516 return rc;
4517 }
4518
bnxt_hwrm_port_led_cfg(struct bnxt * bp,bool led_on)4519 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
4520 {
4521 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4522 struct hwrm_port_led_cfg_input req = {0};
4523 struct bnxt_led_cfg *led_cfg;
4524 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
4525 uint16_t duration = 0;
4526 int rc, i;
4527
4528 if (!bp->leds->num_leds || BNXT_VF(bp))
4529 return -EOPNOTSUPP;
4530
4531 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
4532
4533 if (led_on) {
4534 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
4535 duration = rte_cpu_to_le_16(500);
4536 }
4537 req.port_id = bp->pf->port_id;
4538 req.num_leds = bp->leds->num_leds;
4539 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
4540 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
4541 req.enables |= BNXT_LED_DFLT_ENABLES(i);
4542 led_cfg->led_id = bp->leds[i].led_id;
4543 led_cfg->led_state = led_state;
4544 led_cfg->led_blink_on = duration;
4545 led_cfg->led_blink_off = duration;
4546 led_cfg->led_group_id = bp->leds[i].led_group_id;
4547 }
4548
4549 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4550
4551 HWRM_CHECK_RESULT();
4552 HWRM_UNLOCK();
4553
4554 return rc;
4555 }
4556
bnxt_hwrm_nvm_get_dir_info(struct bnxt * bp,uint32_t * entries,uint32_t * length)4557 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
4558 uint32_t *length)
4559 {
4560 int rc;
4561 struct hwrm_nvm_get_dir_info_input req = {0};
4562 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
4563
4564 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
4565
4566 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4567
4568 HWRM_CHECK_RESULT();
4569
4570 *entries = rte_le_to_cpu_32(resp->entries);
4571 *length = rte_le_to_cpu_32(resp->entry_length);
4572
4573 HWRM_UNLOCK();
4574 return rc;
4575 }
4576
bnxt_get_nvram_directory(struct bnxt * bp,uint32_t len,uint8_t * data)4577 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
4578 {
4579 int rc;
4580 uint32_t dir_entries;
4581 uint32_t entry_length;
4582 uint8_t *buf;
4583 size_t buflen;
4584 rte_iova_t dma_handle;
4585 struct hwrm_nvm_get_dir_entries_input req = {0};
4586 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
4587
4588 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4589 if (rc != 0)
4590 return rc;
4591
4592 *data++ = dir_entries;
4593 *data++ = entry_length;
4594 len -= 2;
4595 memset(data, 0xff, len);
4596
4597 buflen = dir_entries * entry_length;
4598 buf = rte_malloc("nvm_dir", buflen, 0);
4599 if (buf == NULL)
4600 return -ENOMEM;
4601 dma_handle = rte_malloc_virt2iova(buf);
4602 if (dma_handle == RTE_BAD_IOVA) {
4603 rte_free(buf);
4604 PMD_DRV_LOG(ERR,
4605 "unable to map response address to physical memory\n");
4606 return -ENOMEM;
4607 }
4608 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4609 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4610 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4611
4612 if (rc == 0)
4613 memcpy(data, buf, len > buflen ? buflen : len);
4614
4615 rte_free(buf);
4616 HWRM_CHECK_RESULT();
4617 HWRM_UNLOCK();
4618
4619 return rc;
4620 }
4621
bnxt_hwrm_get_nvram_item(struct bnxt * bp,uint32_t index,uint32_t offset,uint32_t length,uint8_t * data)4622 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4623 uint32_t offset, uint32_t length,
4624 uint8_t *data)
4625 {
4626 int rc;
4627 uint8_t *buf;
4628 rte_iova_t dma_handle;
4629 struct hwrm_nvm_read_input req = {0};
4630 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4631
4632 buf = rte_malloc("nvm_item", length, 0);
4633 if (!buf)
4634 return -ENOMEM;
4635
4636 dma_handle = rte_malloc_virt2iova(buf);
4637 if (dma_handle == RTE_BAD_IOVA) {
4638 rte_free(buf);
4639 PMD_DRV_LOG(ERR,
4640 "unable to map response address to physical memory\n");
4641 return -ENOMEM;
4642 }
4643 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4644 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4645 req.dir_idx = rte_cpu_to_le_16(index);
4646 req.offset = rte_cpu_to_le_32(offset);
4647 req.len = rte_cpu_to_le_32(length);
4648 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4649 if (rc == 0)
4650 memcpy(data, buf, length);
4651
4652 rte_free(buf);
4653 HWRM_CHECK_RESULT();
4654 HWRM_UNLOCK();
4655
4656 return rc;
4657 }
4658
bnxt_hwrm_erase_nvram_directory(struct bnxt * bp,uint8_t index)4659 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4660 {
4661 int rc;
4662 struct hwrm_nvm_erase_dir_entry_input req = {0};
4663 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4664
4665 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4666 req.dir_idx = rte_cpu_to_le_16(index);
4667 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4668 HWRM_CHECK_RESULT();
4669 HWRM_UNLOCK();
4670
4671 return rc;
4672 }
4673
bnxt_hwrm_flash_nvram(struct bnxt * bp,uint16_t dir_type,uint16_t dir_ordinal,uint16_t dir_ext,uint16_t dir_attr,const uint8_t * data,size_t data_len)4674 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4675 uint16_t dir_ordinal, uint16_t dir_ext,
4676 uint16_t dir_attr, const uint8_t *data,
4677 size_t data_len)
4678 {
4679 int rc;
4680 struct hwrm_nvm_write_input req = {0};
4681 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4682 rte_iova_t dma_handle;
4683 uint8_t *buf;
4684
4685 buf = rte_malloc("nvm_write", data_len, 0);
4686 if (!buf)
4687 return -ENOMEM;
4688
4689 dma_handle = rte_malloc_virt2iova(buf);
4690 if (dma_handle == RTE_BAD_IOVA) {
4691 rte_free(buf);
4692 PMD_DRV_LOG(ERR,
4693 "unable to map response address to physical memory\n");
4694 return -ENOMEM;
4695 }
4696 memcpy(buf, data, data_len);
4697
4698 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4699
4700 req.dir_type = rte_cpu_to_le_16(dir_type);
4701 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4702 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4703 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4704 req.dir_data_length = rte_cpu_to_le_32(data_len);
4705 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4706
4707 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4708
4709 rte_free(buf);
4710 HWRM_CHECK_RESULT();
4711 HWRM_UNLOCK();
4712
4713 return rc;
4714 }
4715
4716 static void
bnxt_vnic_count(struct bnxt_vnic_info * vnic __rte_unused,void * cbdata)4717 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4718 {
4719 uint32_t *count = cbdata;
4720
4721 *count = *count + 1;
4722 }
4723
bnxt_vnic_count_hwrm_stub(struct bnxt * bp __rte_unused,struct bnxt_vnic_info * vnic __rte_unused)4724 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4725 struct bnxt_vnic_info *vnic __rte_unused)
4726 {
4727 return 0;
4728 }
4729
bnxt_vf_vnic_count(struct bnxt * bp,uint16_t vf)4730 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4731 {
4732 uint32_t count = 0;
4733
4734 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4735 &count, bnxt_vnic_count_hwrm_stub);
4736
4737 return count;
4738 }
4739
bnxt_hwrm_func_vf_vnic_query(struct bnxt * bp,uint16_t vf,uint16_t * vnic_ids)4740 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4741 uint16_t *vnic_ids)
4742 {
4743 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4744 struct hwrm_func_vf_vnic_ids_query_output *resp =
4745 bp->hwrm_cmd_resp_addr;
4746 int rc;
4747
4748 /* First query all VNIC ids */
4749 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4750
4751 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4752 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4753 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4754
4755 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4756 HWRM_UNLOCK();
4757 PMD_DRV_LOG(ERR,
4758 "unable to map VNIC ID table address to physical memory\n");
4759 return -ENOMEM;
4760 }
4761 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4762 HWRM_CHECK_RESULT();
4763 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4764
4765 HWRM_UNLOCK();
4766
4767 return rc;
4768 }
4769
4770 /*
4771 * This function queries the VNIC IDs for a specified VF. It then calls
4772 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4773 * Then it calls the hwrm_cb function to program this new vnic configuration.
4774 */
bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt * bp,uint16_t vf,void (* vnic_cb)(struct bnxt_vnic_info *,void *),void * cbdata,int (* hwrm_cb)(struct bnxt * bp,struct bnxt_vnic_info * vnic))4775 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4776 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4777 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4778 {
4779 struct bnxt_vnic_info vnic;
4780 int rc = 0;
4781 int i, num_vnic_ids;
4782 uint16_t *vnic_ids;
4783 size_t vnic_id_sz;
4784 size_t sz;
4785
4786 /* First query all VNIC ids */
4787 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4788 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4789 RTE_CACHE_LINE_SIZE);
4790 if (vnic_ids == NULL)
4791 return -ENOMEM;
4792
4793 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4794 rte_mem_lock_page(((char *)vnic_ids) + sz);
4795
4796 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4797
4798 if (num_vnic_ids < 0)
4799 return num_vnic_ids;
4800
4801 /* Retrieve VNIC, update bd_stall then update */
4802
4803 for (i = 0; i < num_vnic_ids; i++) {
4804 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4805 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4806 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4807 if (rc)
4808 break;
4809 if (vnic.mru <= 4) /* Indicates unallocated */
4810 continue;
4811
4812 vnic_cb(&vnic, cbdata);
4813
4814 rc = hwrm_cb(bp, &vnic);
4815 if (rc)
4816 break;
4817 }
4818
4819 rte_free(vnic_ids);
4820
4821 return rc;
4822 }
4823
bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt * bp,uint16_t vf,bool on)4824 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4825 bool on)
4826 {
4827 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4828 struct hwrm_func_cfg_input req = {0};
4829 int rc;
4830
4831 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4832
4833 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4834 req.enables |= rte_cpu_to_le_32(
4835 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4836 req.vlan_antispoof_mode = on ?
4837 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4838 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4839 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4840
4841 HWRM_CHECK_RESULT();
4842 HWRM_UNLOCK();
4843
4844 return rc;
4845 }
4846
bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt * bp,int vf)4847 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4848 {
4849 struct bnxt_vnic_info vnic;
4850 uint16_t *vnic_ids;
4851 size_t vnic_id_sz;
4852 int num_vnic_ids, i;
4853 size_t sz;
4854 int rc;
4855
4856 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4857 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4858 RTE_CACHE_LINE_SIZE);
4859 if (vnic_ids == NULL)
4860 return -ENOMEM;
4861
4862 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4863 rte_mem_lock_page(((char *)vnic_ids) + sz);
4864
4865 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4866 if (rc <= 0)
4867 goto exit;
4868 num_vnic_ids = rc;
4869
4870 /*
4871 * Loop through to find the default VNIC ID.
4872 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4873 * by sending the hwrm_func_qcfg command to the firmware.
4874 */
4875 for (i = 0; i < num_vnic_ids; i++) {
4876 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4877 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4878 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4879 bp->pf->first_vf_id + vf);
4880 if (rc)
4881 goto exit;
4882 if (vnic.func_default) {
4883 rte_free(vnic_ids);
4884 return vnic.fw_vnic_id;
4885 }
4886 }
4887 /* Could not find a default VNIC. */
4888 PMD_DRV_LOG(ERR, "No default VNIC\n");
4889 exit:
4890 rte_free(vnic_ids);
4891 return rc;
4892 }
4893
bnxt_hwrm_set_em_filter(struct bnxt * bp,uint16_t dst_id,struct bnxt_filter_info * filter)4894 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4895 uint16_t dst_id,
4896 struct bnxt_filter_info *filter)
4897 {
4898 int rc = 0;
4899 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4900 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4901 uint32_t enables = 0;
4902
4903 if (filter->fw_em_filter_id != UINT64_MAX)
4904 bnxt_hwrm_clear_em_filter(bp, filter);
4905
4906 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4907
4908 req.flags = rte_cpu_to_le_32(filter->flags);
4909
4910 enables = filter->enables |
4911 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4912 req.dst_id = rte_cpu_to_le_16(dst_id);
4913
4914 if (filter->ip_addr_type) {
4915 req.ip_addr_type = filter->ip_addr_type;
4916 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4917 }
4918 if (enables &
4919 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4920 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4921 if (enables &
4922 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4923 memcpy(req.src_macaddr, filter->src_macaddr,
4924 RTE_ETHER_ADDR_LEN);
4925 if (enables &
4926 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4927 memcpy(req.dst_macaddr, filter->dst_macaddr,
4928 RTE_ETHER_ADDR_LEN);
4929 if (enables &
4930 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4931 req.ovlan_vid = filter->l2_ovlan;
4932 if (enables &
4933 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4934 req.ivlan_vid = filter->l2_ivlan;
4935 if (enables &
4936 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4937 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4938 if (enables &
4939 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4940 req.ip_protocol = filter->ip_protocol;
4941 if (enables &
4942 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4943 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4944 if (enables &
4945 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4946 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4947 if (enables &
4948 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4949 req.src_port = rte_cpu_to_be_16(filter->src_port);
4950 if (enables &
4951 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4952 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4953 if (enables &
4954 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4955 req.mirror_vnic_id = filter->mirror_vnic_id;
4956
4957 req.enables = rte_cpu_to_le_32(enables);
4958
4959 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4960
4961 HWRM_CHECK_RESULT();
4962
4963 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4964 HWRM_UNLOCK();
4965
4966 return rc;
4967 }
4968
bnxt_hwrm_clear_em_filter(struct bnxt * bp,struct bnxt_filter_info * filter)4969 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4970 {
4971 int rc = 0;
4972 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4973 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4974
4975 if (filter->fw_em_filter_id == UINT64_MAX)
4976 return 0;
4977
4978 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4979
4980 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4981
4982 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4983
4984 HWRM_CHECK_RESULT();
4985 HWRM_UNLOCK();
4986
4987 filter->fw_em_filter_id = UINT64_MAX;
4988 filter->fw_l2_filter_id = UINT64_MAX;
4989
4990 return 0;
4991 }
4992
bnxt_hwrm_set_ntuple_filter(struct bnxt * bp,uint16_t dst_id,struct bnxt_filter_info * filter)4993 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4994 uint16_t dst_id,
4995 struct bnxt_filter_info *filter)
4996 {
4997 int rc = 0;
4998 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4999 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
5000 bp->hwrm_cmd_resp_addr;
5001 uint32_t enables = 0;
5002
5003 if (filter->fw_ntuple_filter_id != UINT64_MAX)
5004 bnxt_hwrm_clear_ntuple_filter(bp, filter);
5005
5006 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
5007
5008 req.flags = rte_cpu_to_le_32(filter->flags);
5009
5010 enables = filter->enables |
5011 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
5012 req.dst_id = rte_cpu_to_le_16(dst_id);
5013
5014 if (filter->ip_addr_type) {
5015 req.ip_addr_type = filter->ip_addr_type;
5016 enables |=
5017 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
5018 }
5019 if (enables &
5020 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
5021 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
5022 if (enables &
5023 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
5024 memcpy(req.src_macaddr, filter->src_macaddr,
5025 RTE_ETHER_ADDR_LEN);
5026 if (enables &
5027 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
5028 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
5029 if (enables &
5030 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
5031 req.ip_protocol = filter->ip_protocol;
5032 if (enables &
5033 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
5034 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
5035 if (enables &
5036 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
5037 req.src_ipaddr_mask[0] =
5038 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
5039 if (enables &
5040 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
5041 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
5042 if (enables &
5043 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
5044 req.dst_ipaddr_mask[0] =
5045 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
5046 if (enables &
5047 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
5048 req.src_port = rte_cpu_to_le_16(filter->src_port);
5049 if (enables &
5050 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
5051 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
5052 if (enables &
5053 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
5054 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
5055 if (enables &
5056 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
5057 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
5058 if (enables &
5059 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
5060 req.mirror_vnic_id = filter->mirror_vnic_id;
5061
5062 req.enables = rte_cpu_to_le_32(enables);
5063
5064 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5065
5066 HWRM_CHECK_RESULT();
5067
5068 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
5069 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
5070 HWRM_UNLOCK();
5071
5072 return rc;
5073 }
5074
bnxt_hwrm_clear_ntuple_filter(struct bnxt * bp,struct bnxt_filter_info * filter)5075 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
5076 struct bnxt_filter_info *filter)
5077 {
5078 int rc = 0;
5079 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
5080 struct hwrm_cfa_ntuple_filter_free_output *resp =
5081 bp->hwrm_cmd_resp_addr;
5082
5083 if (filter->fw_ntuple_filter_id == UINT64_MAX)
5084 return 0;
5085
5086 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
5087
5088 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
5089
5090 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5091
5092 HWRM_CHECK_RESULT();
5093 HWRM_UNLOCK();
5094
5095 filter->fw_ntuple_filter_id = UINT64_MAX;
5096
5097 return 0;
5098 }
5099
5100 static int
bnxt_vnic_rss_configure_p5(struct bnxt * bp,struct bnxt_vnic_info * vnic)5101 bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5102 {
5103 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5104 uint8_t *rxq_state = bp->eth_dev->data->rx_queue_state;
5105 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
5106 struct bnxt_rx_queue **rxqs = bp->rx_queues;
5107 uint16_t *ring_tbl = vnic->rss_table;
5108 int nr_ctxs = vnic->num_lb_ctxts;
5109 int max_rings = bp->rx_nr_rings;
5110 int i, j, k, cnt;
5111 int rc = 0;
5112
5113 for (i = 0, k = 0; i < nr_ctxs; i++) {
5114 struct bnxt_rx_ring_info *rxr;
5115 struct bnxt_cp_ring_info *cpr;
5116
5117 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
5118
5119 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
5120 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
5121 req.hash_mode_flags = vnic->hash_mode;
5122
5123 req.ring_grp_tbl_addr =
5124 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
5125 i * BNXT_RSS_ENTRIES_PER_CTX_P5 *
5126 2 * sizeof(*ring_tbl));
5127 req.hash_key_tbl_addr =
5128 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
5129
5130 req.ring_table_pair_index = i;
5131 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
5132
5133 for (j = 0; j < 64; j++) {
5134 uint16_t ring_id;
5135
5136 /* Find next active ring. */
5137 for (cnt = 0; cnt < max_rings; cnt++) {
5138 if (rxq_state[k] != RTE_ETH_QUEUE_STATE_STOPPED)
5139 break;
5140 if (++k == max_rings)
5141 k = 0;
5142 }
5143
5144 /* Return if no rings are active. */
5145 if (cnt == max_rings) {
5146 HWRM_UNLOCK();
5147 return 0;
5148 }
5149
5150 /* Add rx/cp ring pair to RSS table. */
5151 rxr = rxqs[k]->rx_ring;
5152 cpr = rxqs[k]->cp_ring;
5153
5154 ring_id = rxr->rx_ring_struct->fw_ring_id;
5155 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5156 ring_id = cpr->cp_ring_struct->fw_ring_id;
5157 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
5158
5159 if (++k == max_rings)
5160 k = 0;
5161 }
5162 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5163 BNXT_USE_CHIMP_MB);
5164
5165 HWRM_CHECK_RESULT();
5166 HWRM_UNLOCK();
5167 }
5168
5169 return rc;
5170 }
5171
bnxt_vnic_rss_configure(struct bnxt * bp,struct bnxt_vnic_info * vnic)5172 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5173 {
5174 unsigned int rss_idx, fw_idx, i;
5175
5176 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
5177 return 0;
5178
5179 if (!(vnic->rss_table && vnic->hash_type))
5180 return 0;
5181
5182 if (BNXT_CHIP_P5(bp))
5183 return bnxt_vnic_rss_configure_p5(bp, vnic);
5184
5185 /*
5186 * Fill the RSS hash & redirection table with
5187 * ring group ids for all VNICs
5188 */
5189 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
5190 rss_idx++, fw_idx++) {
5191 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
5192 fw_idx %= bp->rx_cp_nr_rings;
5193 if (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)
5194 break;
5195 fw_idx++;
5196 }
5197
5198 if (i == bp->rx_cp_nr_rings)
5199 return 0;
5200
5201 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
5202 }
5203
5204 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
5205 }
5206
bnxt_hwrm_set_coal_params(struct bnxt_coal * hw_coal,struct hwrm_ring_cmpl_ring_cfg_aggint_params_input * req)5207 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
5208 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
5209 {
5210 uint16_t flags;
5211
5212 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
5213
5214 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5215 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
5216
5217 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
5218 req->num_cmpl_dma_aggr_during_int =
5219 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
5220
5221 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
5222
5223 /* min timer set to 1/2 of interrupt timer */
5224 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
5225
5226 /* buf timer set to 1/4 of interrupt timer */
5227 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
5228
5229 req->cmpl_aggr_dma_tmr_during_int =
5230 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
5231
5232 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5233 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5234 req->flags = rte_cpu_to_le_16(flags);
5235 }
5236
bnxt_hwrm_set_coal_params_p5(struct bnxt * bp,struct hwrm_ring_cmpl_ring_cfg_aggint_params_input * agg_req)5237 static int bnxt_hwrm_set_coal_params_p5(struct bnxt *bp,
5238 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
5239 {
5240 struct hwrm_ring_aggint_qcaps_input req = {0};
5241 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5242 uint32_t enables;
5243 uint16_t flags;
5244 int rc;
5245
5246 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
5247 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5248 HWRM_CHECK_RESULT();
5249
5250 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
5251 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
5252
5253 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
5254 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
5255 agg_req->flags = rte_cpu_to_le_16(flags);
5256 enables =
5257 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
5258 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
5259 agg_req->enables = rte_cpu_to_le_32(enables);
5260
5261 HWRM_UNLOCK();
5262 return rc;
5263 }
5264
bnxt_hwrm_set_ring_coal(struct bnxt * bp,struct bnxt_coal * coal,uint16_t ring_id)5265 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
5266 struct bnxt_coal *coal, uint16_t ring_id)
5267 {
5268 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
5269 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
5270 bp->hwrm_cmd_resp_addr;
5271 int rc;
5272
5273 /* Set ring coalesce parameters only for 100G NICs */
5274 if (BNXT_CHIP_P5(bp)) {
5275 if (bnxt_hwrm_set_coal_params_p5(bp, &req))
5276 return -1;
5277 } else if (bnxt_stratus_device(bp)) {
5278 bnxt_hwrm_set_coal_params(coal, &req);
5279 } else {
5280 return 0;
5281 }
5282
5283 HWRM_PREP(&req,
5284 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
5285 BNXT_USE_CHIMP_MB);
5286 req.ring_id = rte_cpu_to_le_16(ring_id);
5287 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5288 HWRM_CHECK_RESULT();
5289 HWRM_UNLOCK();
5290 return 0;
5291 }
5292
5293 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
bnxt_hwrm_func_backing_store_qcaps(struct bnxt * bp)5294 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
5295 {
5296 struct hwrm_func_backing_store_qcaps_input req = {0};
5297 struct hwrm_func_backing_store_qcaps_output *resp =
5298 bp->hwrm_cmd_resp_addr;
5299 struct bnxt_ctx_pg_info *ctx_pg;
5300 struct bnxt_ctx_mem_info *ctx;
5301 int total_alloc_len;
5302 int rc, i, tqm_rings;
5303
5304 if (!BNXT_CHIP_P5(bp) ||
5305 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
5306 BNXT_VF(bp) ||
5307 bp->ctx)
5308 return 0;
5309
5310 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
5311 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5312 HWRM_CHECK_RESULT_SILENT();
5313
5314 total_alloc_len = sizeof(*ctx);
5315 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
5316 RTE_CACHE_LINE_SIZE);
5317 if (!ctx) {
5318 rc = -ENOMEM;
5319 goto ctx_err;
5320 }
5321
5322 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
5323 ctx->qp_min_qp1_entries =
5324 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
5325 ctx->qp_max_l2_entries =
5326 rte_le_to_cpu_16(resp->qp_max_l2_entries);
5327 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
5328 ctx->srq_max_l2_entries =
5329 rte_le_to_cpu_16(resp->srq_max_l2_entries);
5330 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
5331 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
5332 ctx->cq_max_l2_entries =
5333 rte_le_to_cpu_16(resp->cq_max_l2_entries);
5334 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
5335 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
5336 ctx->vnic_max_vnic_entries =
5337 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
5338 ctx->vnic_max_ring_table_entries =
5339 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
5340 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
5341 ctx->stat_max_entries =
5342 rte_le_to_cpu_32(resp->stat_max_entries);
5343 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
5344 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
5345 ctx->tqm_min_entries_per_ring =
5346 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
5347 ctx->tqm_max_entries_per_ring =
5348 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
5349 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
5350 if (!ctx->tqm_entries_multiple)
5351 ctx->tqm_entries_multiple = 1;
5352 ctx->mrav_max_entries =
5353 rte_le_to_cpu_32(resp->mrav_max_entries);
5354 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
5355 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
5356 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
5357 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
5358
5359 ctx->tqm_fp_rings_count = ctx->tqm_fp_rings_count ?
5360 RTE_MIN(ctx->tqm_fp_rings_count,
5361 BNXT_MAX_TQM_FP_LEGACY_RINGS) :
5362 bp->max_q;
5363
5364 /* Check if the ext ring count needs to be counted.
5365 * Ext ring count is available only with new FW so we should not
5366 * look at the field on older FW.
5367 */
5368 if (ctx->tqm_fp_rings_count == BNXT_MAX_TQM_FP_LEGACY_RINGS &&
5369 bp->hwrm_max_ext_req_len >= BNXT_BACKING_STORE_CFG_LEN) {
5370 ctx->tqm_fp_rings_count += resp->tqm_fp_rings_count_ext;
5371 ctx->tqm_fp_rings_count = RTE_MIN(BNXT_MAX_TQM_FP_RINGS,
5372 ctx->tqm_fp_rings_count);
5373 }
5374
5375 tqm_rings = ctx->tqm_fp_rings_count + 1;
5376
5377 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
5378 sizeof(*ctx_pg) * tqm_rings,
5379 RTE_CACHE_LINE_SIZE);
5380 if (!ctx_pg) {
5381 rc = -ENOMEM;
5382 goto ctx_err;
5383 }
5384 for (i = 0; i < tqm_rings; i++, ctx_pg++)
5385 ctx->tqm_mem[i] = ctx_pg;
5386
5387 bp->ctx = ctx;
5388 ctx_err:
5389 HWRM_UNLOCK();
5390 return rc;
5391 }
5392
bnxt_hwrm_func_backing_store_cfg(struct bnxt * bp,uint32_t enables)5393 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
5394 {
5395 struct hwrm_func_backing_store_cfg_input req = {0};
5396 struct hwrm_func_backing_store_cfg_output *resp =
5397 bp->hwrm_cmd_resp_addr;
5398 struct bnxt_ctx_mem_info *ctx = bp->ctx;
5399 struct bnxt_ctx_pg_info *ctx_pg;
5400 uint32_t *num_entries;
5401 uint64_t *pg_dir;
5402 uint8_t *pg_attr;
5403 uint32_t ena;
5404 int i, rc;
5405
5406 if (!ctx)
5407 return 0;
5408
5409 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
5410 req.enables = rte_cpu_to_le_32(enables);
5411
5412 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
5413 ctx_pg = &ctx->qp_mem;
5414 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5415 req.qp_num_qp1_entries =
5416 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
5417 req.qp_num_l2_entries =
5418 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
5419 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
5420 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5421 &req.qpc_pg_size_qpc_lvl,
5422 &req.qpc_page_dir);
5423 }
5424
5425 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
5426 ctx_pg = &ctx->srq_mem;
5427 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5428 req.srq_num_l2_entries =
5429 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
5430 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
5431 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5432 &req.srq_pg_size_srq_lvl,
5433 &req.srq_page_dir);
5434 }
5435
5436 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
5437 ctx_pg = &ctx->cq_mem;
5438 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
5439 req.cq_num_l2_entries =
5440 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
5441 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
5442 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5443 &req.cq_pg_size_cq_lvl,
5444 &req.cq_page_dir);
5445 }
5446
5447 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
5448 ctx_pg = &ctx->vnic_mem;
5449 req.vnic_num_vnic_entries =
5450 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
5451 req.vnic_num_ring_table_entries =
5452 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
5453 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
5454 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5455 &req.vnic_pg_size_vnic_lvl,
5456 &req.vnic_page_dir);
5457 }
5458
5459 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
5460 ctx_pg = &ctx->stat_mem;
5461 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
5462 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
5463 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5464 &req.stat_pg_size_stat_lvl,
5465 &req.stat_page_dir);
5466 }
5467
5468 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5469 num_entries = &req.tqm_sp_num_entries;
5470 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
5471 pg_dir = &req.tqm_sp_page_dir;
5472 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
5473 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
5474 if (!(enables & ena))
5475 continue;
5476
5477 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
5478
5479 ctx_pg = ctx->tqm_mem[i];
5480 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5481 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
5482 }
5483
5484 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8) {
5485 /* DPDK does not need to configure MRAV and TIM type.
5486 * So we are skipping over MRAV and TIM. Skip to configure
5487 * HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8.
5488 */
5489 ctx_pg = ctx->tqm_mem[BNXT_MAX_TQM_LEGACY_RINGS];
5490 req.tqm_ring8_num_entries = rte_cpu_to_le_16(ctx_pg->entries);
5491 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
5492 &req.tqm_ring8_pg_size_tqm_ring_lvl,
5493 &req.tqm_ring8_page_dir);
5494 }
5495
5496 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5497 HWRM_CHECK_RESULT();
5498 HWRM_UNLOCK();
5499
5500 return rc;
5501 }
5502
bnxt_hwrm_ext_port_qstats(struct bnxt * bp)5503 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
5504 {
5505 struct hwrm_port_qstats_ext_input req = {0};
5506 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
5507 struct bnxt_pf_info *pf = bp->pf;
5508 int rc;
5509
5510 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
5511 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
5512 return 0;
5513
5514 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
5515
5516 req.port_id = rte_cpu_to_le_16(pf->port_id);
5517 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
5518 req.tx_stat_host_addr =
5519 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
5520 req.tx_stat_size =
5521 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
5522 }
5523 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
5524 req.rx_stat_host_addr =
5525 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
5526 req.rx_stat_size =
5527 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
5528 }
5529 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5530
5531 if (rc) {
5532 bp->fw_rx_port_stats_ext_size = 0;
5533 bp->fw_tx_port_stats_ext_size = 0;
5534 } else {
5535 bp->fw_rx_port_stats_ext_size =
5536 rte_le_to_cpu_16(resp->rx_stat_size);
5537 bp->fw_tx_port_stats_ext_size =
5538 rte_le_to_cpu_16(resp->tx_stat_size);
5539 }
5540
5541 HWRM_CHECK_RESULT();
5542 HWRM_UNLOCK();
5543
5544 return rc;
5545 }
5546
5547 int
bnxt_hwrm_tunnel_redirect(struct bnxt * bp,uint8_t type)5548 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
5549 {
5550 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
5551 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
5552 bp->hwrm_cmd_resp_addr;
5553 int rc = 0;
5554
5555 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
5556 req.tunnel_type = type;
5557 req.dest_fid = bp->fw_fid;
5558 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5559 HWRM_CHECK_RESULT();
5560
5561 HWRM_UNLOCK();
5562
5563 return rc;
5564 }
5565
5566 int
bnxt_hwrm_tunnel_redirect_free(struct bnxt * bp,uint8_t type)5567 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
5568 {
5569 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
5570 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
5571 bp->hwrm_cmd_resp_addr;
5572 int rc = 0;
5573
5574 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
5575 req.tunnel_type = type;
5576 req.dest_fid = bp->fw_fid;
5577 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5578 HWRM_CHECK_RESULT();
5579
5580 HWRM_UNLOCK();
5581
5582 return rc;
5583 }
5584
bnxt_hwrm_tunnel_redirect_query(struct bnxt * bp,uint32_t * type)5585 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
5586 {
5587 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
5588 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
5589 bp->hwrm_cmd_resp_addr;
5590 int rc = 0;
5591
5592 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
5593 req.src_fid = bp->fw_fid;
5594 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5595 HWRM_CHECK_RESULT();
5596
5597 if (type)
5598 *type = rte_le_to_cpu_32(resp->tunnel_mask);
5599
5600 HWRM_UNLOCK();
5601
5602 return rc;
5603 }
5604
bnxt_hwrm_tunnel_redirect_info(struct bnxt * bp,uint8_t tun_type,uint16_t * dst_fid)5605 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
5606 uint16_t *dst_fid)
5607 {
5608 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
5609 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
5610 bp->hwrm_cmd_resp_addr;
5611 int rc = 0;
5612
5613 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5614 req.src_fid = bp->fw_fid;
5615 req.tunnel_type = tun_type;
5616 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5617 HWRM_CHECK_RESULT();
5618
5619 if (dst_fid)
5620 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5621
5622 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5623
5624 HWRM_UNLOCK();
5625
5626 return rc;
5627 }
5628
bnxt_hwrm_set_mac(struct bnxt * bp)5629 int bnxt_hwrm_set_mac(struct bnxt *bp)
5630 {
5631 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5632 struct hwrm_func_vf_cfg_input req = {0};
5633 int rc = 0;
5634
5635 if (!BNXT_VF(bp))
5636 return 0;
5637
5638 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5639
5640 req.enables =
5641 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5642 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5643
5644 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5645
5646 HWRM_CHECK_RESULT();
5647
5648 HWRM_UNLOCK();
5649
5650 return rc;
5651 }
5652
bnxt_hwrm_if_change(struct bnxt * bp,bool up)5653 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5654 {
5655 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5656 struct hwrm_func_drv_if_change_input req = {0};
5657 uint32_t flags;
5658 int rc;
5659
5660 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5661 return 0;
5662
5663 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5664 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5665 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5666 */
5667 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5668 return 0;
5669
5670 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5671
5672 if (up)
5673 req.flags =
5674 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5675
5676 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5677
5678 HWRM_CHECK_RESULT();
5679 flags = rte_le_to_cpu_32(resp->flags);
5680 HWRM_UNLOCK();
5681
5682 if (!up)
5683 return 0;
5684
5685 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5686 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5687 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5688 }
5689
5690 return 0;
5691 }
5692
bnxt_hwrm_error_recovery_qcfg(struct bnxt * bp)5693 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5694 {
5695 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5696 struct bnxt_error_recovery_info *info = bp->recovery_info;
5697 struct hwrm_error_recovery_qcfg_input req = {0};
5698 uint32_t flags = 0;
5699 unsigned int i;
5700 int rc;
5701
5702 /* Older FW does not have error recovery support */
5703 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5704 return 0;
5705
5706 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5707
5708 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5709
5710 HWRM_CHECK_RESULT();
5711
5712 flags = rte_le_to_cpu_32(resp->flags);
5713 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5714 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5715 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5716 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5717
5718 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5719 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5720 rc = -EINVAL;
5721 goto err;
5722 }
5723
5724 /* FW returned values are in units of 100msec */
5725 info->driver_polling_freq =
5726 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5727 info->primary_func_wait_period =
5728 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5729 info->normal_func_wait_period =
5730 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5731 info->primary_func_wait_period_after_reset =
5732 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5733 info->max_bailout_time_after_reset =
5734 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5735 info->status_regs[BNXT_FW_STATUS_REG] =
5736 rte_le_to_cpu_32(resp->fw_health_status_reg);
5737 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5738 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5739 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5740 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5741 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5742 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5743 info->reg_array_cnt =
5744 rte_le_to_cpu_32(resp->reg_array_cnt);
5745
5746 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5747 rc = -EINVAL;
5748 goto err;
5749 }
5750
5751 for (i = 0; i < info->reg_array_cnt; i++) {
5752 info->reset_reg[i] =
5753 rte_le_to_cpu_32(resp->reset_reg[i]);
5754 info->reset_reg_val[i] =
5755 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5756 info->delay_after_reset[i] =
5757 resp->delay_after_reset[i];
5758 }
5759 err:
5760 HWRM_UNLOCK();
5761
5762 /* Map the FW status registers */
5763 if (!rc)
5764 rc = bnxt_map_fw_health_status_regs(bp);
5765
5766 if (rc) {
5767 rte_free(bp->recovery_info);
5768 bp->recovery_info = NULL;
5769 }
5770 return rc;
5771 }
5772
bnxt_hwrm_fw_reset(struct bnxt * bp)5773 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5774 {
5775 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5776 struct hwrm_fw_reset_input req = {0};
5777 int rc;
5778
5779 if (!BNXT_PF(bp))
5780 return -EOPNOTSUPP;
5781
5782 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5783
5784 req.embedded_proc_type =
5785 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5786 req.selfrst_status =
5787 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5788 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5789
5790 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5791 BNXT_USE_KONG(bp));
5792
5793 HWRM_CHECK_RESULT();
5794 HWRM_UNLOCK();
5795
5796 return rc;
5797 }
5798
bnxt_hwrm_port_ts_query(struct bnxt * bp,uint8_t path,uint64_t * timestamp)5799 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5800 {
5801 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5802 struct hwrm_port_ts_query_input req = {0};
5803 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5804 uint32_t flags = 0;
5805 int rc;
5806
5807 if (!ptp)
5808 return 0;
5809
5810 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5811
5812 switch (path) {
5813 case BNXT_PTP_FLAGS_PATH_TX:
5814 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5815 break;
5816 case BNXT_PTP_FLAGS_PATH_RX:
5817 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5818 break;
5819 case BNXT_PTP_FLAGS_CURRENT_TIME:
5820 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5821 break;
5822 }
5823
5824 req.flags = rte_cpu_to_le_32(flags);
5825 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5826
5827 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5828
5829 HWRM_CHECK_RESULT();
5830
5831 if (timestamp) {
5832 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5833 *timestamp |=
5834 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5835 }
5836 HWRM_UNLOCK();
5837
5838 return rc;
5839 }
5840
bnxt_hwrm_cfa_counter_qcaps(struct bnxt * bp,uint16_t * max_fc)5841 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5842 {
5843 int rc = 0;
5844
5845 struct hwrm_cfa_counter_qcaps_input req = {0};
5846 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5847
5848 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5849 PMD_DRV_LOG(DEBUG,
5850 "Not a PF or trusted VF. Command not supported\n");
5851 return 0;
5852 }
5853
5854 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5855 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5856 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5857
5858 HWRM_CHECK_RESULT();
5859 if (max_fc)
5860 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5861 HWRM_UNLOCK();
5862
5863 return 0;
5864 }
5865
bnxt_hwrm_ctx_rgtr(struct bnxt * bp,rte_iova_t dma_addr,uint16_t * ctx_id)5866 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5867 {
5868 int rc = 0;
5869 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5870 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5871
5872 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5873 PMD_DRV_LOG(DEBUG,
5874 "Not a PF or trusted VF. Command not supported\n");
5875 return 0;
5876 }
5877
5878 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5879
5880 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5881 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5882 req.page_dir = rte_cpu_to_le_64(dma_addr);
5883
5884 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5885
5886 HWRM_CHECK_RESULT();
5887 if (ctx_id) {
5888 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5889 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5890 }
5891 HWRM_UNLOCK();
5892
5893 return 0;
5894 }
5895
bnxt_hwrm_ctx_unrgtr(struct bnxt * bp,uint16_t ctx_id)5896 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5897 {
5898 int rc = 0;
5899 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5900 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5901
5902 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5903 PMD_DRV_LOG(DEBUG,
5904 "Not a PF or trusted VF. Command not supported\n");
5905 return 0;
5906 }
5907
5908 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5909
5910 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5911
5912 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5913
5914 HWRM_CHECK_RESULT();
5915 HWRM_UNLOCK();
5916
5917 return rc;
5918 }
5919
bnxt_hwrm_cfa_counter_cfg(struct bnxt * bp,enum bnxt_flow_dir dir,uint16_t cntr,uint16_t ctx_id,uint32_t num_entries,bool enable)5920 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5921 uint16_t cntr, uint16_t ctx_id,
5922 uint32_t num_entries, bool enable)
5923 {
5924 struct hwrm_cfa_counter_cfg_input req = {0};
5925 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5926 uint16_t flags = 0;
5927 int rc;
5928
5929 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5930 PMD_DRV_LOG(DEBUG,
5931 "Not a PF or trusted VF. Command not supported\n");
5932 return 0;
5933 }
5934
5935 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5936
5937 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5938 req.counter_type = rte_cpu_to_le_16(cntr);
5939 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5940 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5941 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5942 if (dir == BNXT_DIR_RX)
5943 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5944 else if (dir == BNXT_DIR_TX)
5945 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5946 req.flags = rte_cpu_to_le_16(flags);
5947 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5948 req.num_entries = rte_cpu_to_le_32(num_entries);
5949
5950 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5951 HWRM_CHECK_RESULT();
5952 HWRM_UNLOCK();
5953
5954 return 0;
5955 }
5956
bnxt_hwrm_cfa_counter_qstats(struct bnxt * bp,enum bnxt_flow_dir dir,uint16_t cntr,uint16_t num_entries)5957 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5958 enum bnxt_flow_dir dir,
5959 uint16_t cntr,
5960 uint16_t num_entries)
5961 {
5962 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5963 struct hwrm_cfa_counter_qstats_input req = {0};
5964 uint16_t flow_ctx_id = 0;
5965 uint16_t flags = 0;
5966 int rc = 0;
5967
5968 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5969 PMD_DRV_LOG(DEBUG,
5970 "Not a PF or trusted VF. Command not supported\n");
5971 return 0;
5972 }
5973
5974 if (dir == BNXT_DIR_RX) {
5975 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5976 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5977 } else if (dir == BNXT_DIR_TX) {
5978 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5979 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5980 }
5981
5982 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5983 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5984 req.counter_type = rte_cpu_to_le_16(cntr);
5985 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5986 req.num_entries = rte_cpu_to_le_16(num_entries);
5987 req.flags = rte_cpu_to_le_16(flags);
5988 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5989
5990 HWRM_CHECK_RESULT();
5991 HWRM_UNLOCK();
5992
5993 return 0;
5994 }
5995
bnxt_hwrm_first_vf_id_query(struct bnxt * bp,uint16_t fid,uint16_t * first_vf_id)5996 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
5997 uint16_t *first_vf_id)
5998 {
5999 int rc = 0;
6000 struct hwrm_func_qcaps_input req = {.req_type = 0 };
6001 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6002
6003 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
6004
6005 req.fid = rte_cpu_to_le_16(fid);
6006
6007 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6008
6009 HWRM_CHECK_RESULT();
6010
6011 if (first_vf_id)
6012 *first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
6013
6014 HWRM_UNLOCK();
6015
6016 return rc;
6017 }
6018
bnxt_hwrm_cfa_pair_exists(struct bnxt * bp,struct bnxt_representor * rep_bp)6019 int bnxt_hwrm_cfa_pair_exists(struct bnxt *bp, struct bnxt_representor *rep_bp)
6020 {
6021 struct hwrm_cfa_pair_info_output *resp = bp->hwrm_cmd_resp_addr;
6022 struct hwrm_cfa_pair_info_input req = {0};
6023 int rc = 0;
6024
6025 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6026 PMD_DRV_LOG(DEBUG,
6027 "Not a PF or trusted VF. Command not supported\n");
6028 return 0;
6029 }
6030
6031 HWRM_PREP(&req, HWRM_CFA_PAIR_INFO, BNXT_USE_CHIMP_MB);
6032 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6033 bp->eth_dev->data->name, rep_bp->vf_id);
6034 req.flags =
6035 rte_cpu_to_le_32(HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE);
6036
6037 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6038 HWRM_CHECK_RESULT();
6039 if (rc == HWRM_ERR_CODE_SUCCESS && strlen(resp->pair_name)) {
6040 HWRM_UNLOCK();
6041 return !rc;
6042 }
6043 HWRM_UNLOCK();
6044 return rc;
6045 }
6046
bnxt_hwrm_cfa_pair_alloc(struct bnxt * bp,struct bnxt_representor * rep_bp)6047 int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
6048 {
6049 struct hwrm_cfa_pair_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6050 struct hwrm_cfa_pair_alloc_input req = {0};
6051 int rc;
6052
6053 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6054 PMD_DRV_LOG(DEBUG,
6055 "Not a PF or trusted VF. Command not supported\n");
6056 return 0;
6057 }
6058
6059 HWRM_PREP(&req, HWRM_CFA_PAIR_ALLOC, BNXT_USE_CHIMP_MB);
6060 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6061 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6062 bp->eth_dev->data->name, rep_bp->vf_id);
6063
6064 req.pf_b_id = rep_bp->parent_pf_idx;
6065 req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6066 rte_cpu_to_le_16(rep_bp->vf_id);
6067 req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
6068 req.host_b_id = 1; /* TBD - Confirm if this is OK */
6069
6070 req.enables |= rep_bp->flags & BNXT_REP_Q_R2F_VALID ?
6071 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID : 0;
6072 req.enables |= rep_bp->flags & BNXT_REP_Q_F2R_VALID ?
6073 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID : 0;
6074 req.enables |= rep_bp->flags & BNXT_REP_FC_R2F_VALID ?
6075 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID : 0;
6076 req.enables |= rep_bp->flags & BNXT_REP_FC_F2R_VALID ?
6077 HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID : 0;
6078
6079 req.q_ab = rep_bp->rep_q_r2f;
6080 req.q_ba = rep_bp->rep_q_f2r;
6081 req.fc_ab = rep_bp->rep_fc_r2f;
6082 req.fc_ba = rep_bp->rep_fc_f2r;
6083
6084 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6085 HWRM_CHECK_RESULT();
6086
6087 HWRM_UNLOCK();
6088 PMD_DRV_LOG(DEBUG, "%s %d allocated\n",
6089 BNXT_REP_PF(rep_bp) ? "PFR" : "VFR", rep_bp->vf_id);
6090 return rc;
6091 }
6092
bnxt_hwrm_cfa_pair_free(struct bnxt * bp,struct bnxt_representor * rep_bp)6093 int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
6094 {
6095 struct hwrm_cfa_pair_free_output *resp = bp->hwrm_cmd_resp_addr;
6096 struct hwrm_cfa_pair_free_input req = {0};
6097 int rc;
6098
6099 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
6100 PMD_DRV_LOG(DEBUG,
6101 "Not a PF or trusted VF. Command not supported\n");
6102 return 0;
6103 }
6104
6105 HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
6106 snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
6107 bp->eth_dev->data->name, rep_bp->vf_id);
6108 req.pf_b_id = rep_bp->parent_pf_idx;
6109 req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
6110 req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
6111 rte_cpu_to_le_16(rep_bp->vf_id);
6112 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6113 HWRM_CHECK_RESULT();
6114 HWRM_UNLOCK();
6115 PMD_DRV_LOG(DEBUG, "%s %d freed\n", BNXT_REP_PF(rep_bp) ? "PFR" : "VFR",
6116 rep_bp->vf_id);
6117 return rc;
6118 }
6119
bnxt_hwrm_fw_echo_reply(struct bnxt * bp,uint32_t echo_req_data1,uint32_t echo_req_data2)6120 int bnxt_hwrm_fw_echo_reply(struct bnxt *bp, uint32_t echo_req_data1,
6121 uint32_t echo_req_data2)
6122 {
6123 struct hwrm_func_echo_response_input req = {0};
6124 struct hwrm_func_echo_response_output *resp = bp->hwrm_cmd_resp_addr;
6125 int rc;
6126
6127 HWRM_PREP(&req, HWRM_FUNC_ECHO_RESPONSE, BNXT_USE_CHIMP_MB);
6128 req.event_data1 = rte_cpu_to_le_32(echo_req_data1);
6129 req.event_data2 = rte_cpu_to_le_32(echo_req_data2);
6130
6131 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6132
6133 HWRM_CHECK_RESULT();
6134 HWRM_UNLOCK();
6135
6136 return rc;
6137 }
6138
bnxt_hwrm_poll_ver_get(struct bnxt * bp)6139 int bnxt_hwrm_poll_ver_get(struct bnxt *bp)
6140 {
6141 struct hwrm_ver_get_input req = {.req_type = 0 };
6142 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
6143 int rc = 0;
6144
6145 bp->max_req_len = HWRM_MAX_REQ_LEN;
6146 bp->max_resp_len = BNXT_PAGE_SIZE;
6147 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
6148
6149 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
6150 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
6151 req.hwrm_intf_min = HWRM_VERSION_MINOR;
6152 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
6153
6154 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6155
6156 HWRM_CHECK_RESULT_SILENT();
6157
6158 if (resp->flags & HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY)
6159 rc = -EAGAIN;
6160
6161 HWRM_UNLOCK();
6162
6163 return rc;
6164 }
6165
bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt * bp,uint16_t i2c_addr,uint16_t page_number,uint16_t start_addr,uint16_t data_length,uint8_t * buf)6166 int bnxt_hwrm_read_sfp_module_eeprom_info(struct bnxt *bp, uint16_t i2c_addr,
6167 uint16_t page_number, uint16_t start_addr,
6168 uint16_t data_length, uint8_t *buf)
6169 {
6170 struct hwrm_port_phy_i2c_read_output *resp = bp->hwrm_cmd_resp_addr;
6171 struct hwrm_port_phy_i2c_read_input req = {0};
6172 uint32_t enables = HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET;
6173 int rc, byte_offset = 0;
6174
6175 do {
6176 uint16_t xfer_size;
6177
6178 HWRM_PREP(&req, HWRM_PORT_PHY_I2C_READ, BNXT_USE_CHIMP_MB);
6179 req.i2c_slave_addr = i2c_addr;
6180 req.page_number = rte_cpu_to_le_16(page_number);
6181 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
6182
6183 xfer_size = RTE_MIN(data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
6184 req.page_offset = rte_cpu_to_le_16(start_addr + byte_offset);
6185 req.data_length = xfer_size;
6186 req.enables = rte_cpu_to_le_32(start_addr + byte_offset ? enables : 0);
6187 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6188 HWRM_CHECK_RESULT();
6189
6190 memcpy(buf + byte_offset, resp->data, xfer_size);
6191
6192 data_length -= xfer_size;
6193 byte_offset += xfer_size;
6194
6195 HWRM_UNLOCK();
6196 } while (data_length > 0);
6197
6198 return rc;
6199 }
6200
bnxt_free_hwrm_tx_ring(struct bnxt * bp,int queue_index)6201 void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index)
6202 {
6203 struct bnxt_tx_queue *txq = bp->tx_queues[queue_index];
6204 struct bnxt_tx_ring_info *txr = txq->tx_ring;
6205 struct bnxt_ring *ring = txr->tx_ring_struct;
6206 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
6207
6208 bnxt_hwrm_ring_free(bp, ring,
6209 HWRM_RING_FREE_INPUT_RING_TYPE_TX,
6210 cpr->cp_ring_struct->fw_ring_id);
6211 txr->tx_raw_prod = 0;
6212 txr->tx_raw_cons = 0;
6213 memset(txr->tx_desc_ring, 0,
6214 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_desc_ring));
6215 memset(txr->tx_buf_ring, 0,
6216 txr->tx_ring_struct->ring_size * sizeof(*txr->tx_buf_ring));
6217
6218 bnxt_hwrm_stat_ctx_free(bp, cpr);
6219
6220 bnxt_free_cp_ring(bp, cpr);
6221 }
6222
bnxt_hwrm_config_host_mtu(struct bnxt * bp)6223 int bnxt_hwrm_config_host_mtu(struct bnxt *bp)
6224 {
6225 struct hwrm_func_cfg_input req = {0};
6226 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6227 int rc;
6228
6229 if (!BNXT_PF(bp))
6230 return 0;
6231
6232 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
6233
6234 req.fid = rte_cpu_to_le_16(0xffff);
6235 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU);
6236 req.host_mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu);
6237
6238 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6239 HWRM_CHECK_RESULT();
6240 HWRM_UNLOCK();
6241
6242 return rc;
6243 }
6244
6245 int
bnxt_vnic_rss_clear_p5(struct bnxt * bp,struct bnxt_vnic_info * vnic)6246 bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)
6247 {
6248 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
6249 struct hwrm_vnic_rss_cfg_input req = {0};
6250 int nr_ctxs = vnic->num_lb_ctxts;
6251 int i, rc = 0;
6252
6253 for (i = 0; i < nr_ctxs; i++) {
6254 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
6255
6256 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
6257 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
6258
6259 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
6260
6261 HWRM_CHECK_RESULT();
6262 HWRM_UNLOCK();
6263 }
6264
6265 return rc;
6266 }
6267