1 /* $OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $ */
2
3 /*
4 * Copyright (c) 2014 genua mbh <[email protected]>
5 * Copyright (c) 2014 Fixup Software Ltd.
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /*-
21 * Based on BSD-licensed source modules in the Linux iwlwifi driver,
22 * which were used as the reference documentation for this implementation.
23 *
24 * Driver version we are currently based off of is
25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd)
26 *
27 ***********************************************************************
28 *
29 * This file is provided under a dual BSD/GPLv2 license. When using or
30 * redistributing this file, you may do so under either license.
31 *
32 * GPL LICENSE SUMMARY
33 *
34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
35 *
36 * This program is free software; you can redistribute it and/or modify
37 * it under the terms of version 2 of the GNU General Public License as
38 * published by the Free Software Foundation.
39 *
40 * This program is distributed in the hope that it will be useful, but
41 * WITHOUT ANY WARRANTY; without even the implied warranty of
42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
43 * General Public License for more details.
44 *
45 * You should have received a copy of the GNU General Public License
46 * along with this program; if not, write to the Free Software
47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
48 * USA
49 *
50 * The full GNU General Public License is included in this distribution
51 * in the file called COPYING.
52 *
53 * Contact Information:
54 * Intel Linux Wireless <[email protected]>
55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
56 *
57 *
58 * BSD LICENSE
59 *
60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
61 * All rights reserved.
62 *
63 * Redistribution and use in source and binary forms, with or without
64 * modification, are permitted provided that the following conditions
65 * are met:
66 *
67 * * Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * * Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in
71 * the documentation and/or other materials provided with the
72 * distribution.
73 * * Neither the name Intel Corporation nor the names of its
74 * contributors may be used to endorse or promote products derived
75 * from this software without specific prior written permission.
76 *
77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
88 */
89
90 /*-
91 * Copyright (c) 2007-2010 Damien Bergamini <[email protected]>
92 *
93 * Permission to use, copy, modify, and distribute this software for any
94 * purpose with or without fee is hereby granted, provided that the above
95 * copyright notice and this permission notice appear in all copies.
96 *
97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
104 */
105 #include <sys/cdefs.h>
106 __FBSDID("$FreeBSD$");
107
108 #include "opt_wlan.h"
109 #include "opt_iwm.h"
110
111 #include <sys/param.h>
112 #include <sys/bus.h>
113 #include <sys/conf.h>
114 #include <sys/endian.h>
115 #include <sys/firmware.h>
116 #include <sys/kernel.h>
117 #include <sys/malloc.h>
118 #include <sys/mbuf.h>
119 #include <sys/mutex.h>
120 #include <sys/module.h>
121 #include <sys/proc.h>
122 #include <sys/rman.h>
123 #include <sys/socket.h>
124 #include <sys/sockio.h>
125 #include <sys/sysctl.h>
126 #include <sys/linker.h>
127
128 #include <machine/bus.h>
129 #include <machine/endian.h>
130 #include <machine/resource.h>
131
132 #include <dev/pci/pcivar.h>
133 #include <dev/pci/pcireg.h>
134
135 #include <net/bpf.h>
136
137 #include <net/if.h>
138 #include <net/if_var.h>
139 #include <net/if_arp.h>
140 #include <net/if_dl.h>
141 #include <net/if_media.h>
142 #include <net/if_types.h>
143
144 #include <netinet/in.h>
145 #include <netinet/in_systm.h>
146 #include <netinet/if_ether.h>
147 #include <netinet/ip.h>
148
149 #include <net80211/ieee80211_var.h>
150 #include <net80211/ieee80211_regdomain.h>
151 #include <net80211/ieee80211_ratectl.h>
152 #include <net80211/ieee80211_radiotap.h>
153
154 #include <dev/iwm/if_iwmreg.h>
155 #include <dev/iwm/if_iwmvar.h>
156 #include <dev/iwm/if_iwm_config.h>
157 #include <dev/iwm/if_iwm_debug.h>
158 #include <dev/iwm/if_iwm_pcie_trans.h>
159
160 /*
161 * This is a subset of what's in linux iwlwifi/pcie/trans.c.
162 * The rest can be migrated out into here once they're no longer in
163 * if_iwm.c.
164 */
165
166 /*
167 * basic device access
168 */
169
170 uint32_t
iwm_read_prph(struct iwm_softc * sc,uint32_t addr)171 iwm_read_prph(struct iwm_softc *sc, uint32_t addr)
172 {
173 IWM_WRITE(sc,
174 IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24)));
175 IWM_BARRIER_READ_WRITE(sc);
176 return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT);
177 }
178
179 void
iwm_write_prph(struct iwm_softc * sc,uint32_t addr,uint32_t val)180 iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val)
181 {
182 IWM_WRITE(sc,
183 IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24)));
184 IWM_BARRIER_WRITE(sc);
185 IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val);
186 }
187
188 #ifdef IWM_DEBUG
189 /* iwlwifi: pcie/trans.c */
190 int
iwm_read_mem(struct iwm_softc * sc,uint32_t addr,void * buf,int dwords)191 iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords)
192 {
193 int offs, ret = 0;
194 uint32_t *vals = buf;
195
196 if (iwm_nic_lock(sc)) {
197 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr);
198 for (offs = 0; offs < dwords; offs++)
199 vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT);
200 iwm_nic_unlock(sc);
201 } else {
202 ret = EBUSY;
203 }
204 return ret;
205 }
206 #endif
207
208 /* iwlwifi: pcie/trans.c */
209 int
iwm_write_mem(struct iwm_softc * sc,uint32_t addr,const void * buf,int dwords)210 iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords)
211 {
212 int offs;
213 const uint32_t *vals = buf;
214
215 if (iwm_nic_lock(sc)) {
216 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr);
217 /* WADDR auto-increments */
218 for (offs = 0; offs < dwords; offs++) {
219 uint32_t val = vals ? vals[offs] : 0;
220 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val);
221 }
222 iwm_nic_unlock(sc);
223 } else {
224 IWM_DPRINTF(sc, IWM_DEBUG_TRANS,
225 "%s: write_mem failed\n", __func__);
226 return EBUSY;
227 }
228 return 0;
229 }
230
231 int
iwm_write_mem32(struct iwm_softc * sc,uint32_t addr,uint32_t val)232 iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val)
233 {
234 return iwm_write_mem(sc, addr, &val, 1);
235 }
236
237 int
iwm_poll_bit(struct iwm_softc * sc,int reg,uint32_t bits,uint32_t mask,int timo)238 iwm_poll_bit(struct iwm_softc *sc, int reg,
239 uint32_t bits, uint32_t mask, int timo)
240 {
241 for (;;) {
242 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {
243 return 1;
244 }
245 if (timo < 10) {
246 return 0;
247 }
248 timo -= 10;
249 DELAY(10);
250 }
251 }
252
253 int
iwm_nic_lock(struct iwm_softc * sc)254 iwm_nic_lock(struct iwm_softc *sc)
255 {
256 int rv = 0;
257
258 if (sc->cmd_hold_nic_awake)
259 return 1;
260
261 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
262 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
263
264 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_8000)
265 DELAY(2);
266
267 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
268 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
269 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
270 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) {
271 rv = 1;
272 } else {
273 /* jolt */
274 IWM_DPRINTF(sc, IWM_DEBUG_RESET,
275 "%s: resetting device via NMI\n", __func__);
276 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI);
277 }
278
279 return rv;
280 }
281
282 void
iwm_nic_unlock(struct iwm_softc * sc)283 iwm_nic_unlock(struct iwm_softc *sc)
284 {
285 if (sc->cmd_hold_nic_awake)
286 return;
287
288 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
289 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
290 }
291
292 void
iwm_set_bits_mask_prph(struct iwm_softc * sc,uint32_t reg,uint32_t bits,uint32_t mask)293 iwm_set_bits_mask_prph(struct iwm_softc *sc,
294 uint32_t reg, uint32_t bits, uint32_t mask)
295 {
296 uint32_t val;
297
298 /* XXX: no error path? */
299 if (iwm_nic_lock(sc)) {
300 val = iwm_read_prph(sc, reg) & mask;
301 val |= bits;
302 iwm_write_prph(sc, reg, val);
303 iwm_nic_unlock(sc);
304 }
305 }
306
307 void
iwm_set_bits_prph(struct iwm_softc * sc,uint32_t reg,uint32_t bits)308 iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
309 {
310 iwm_set_bits_mask_prph(sc, reg, bits, ~0);
311 }
312
313 void
iwm_clear_bits_prph(struct iwm_softc * sc,uint32_t reg,uint32_t bits)314 iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
315 {
316 iwm_set_bits_mask_prph(sc, reg, 0, ~bits);
317 }
318
319 /*
320 * High-level hardware frobbing routines
321 */
322
323 void
iwm_enable_rfkill_int(struct iwm_softc * sc)324 iwm_enable_rfkill_int(struct iwm_softc *sc)
325 {
326 sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL;
327 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask);
328 }
329
330 int
iwm_check_rfkill(struct iwm_softc * sc)331 iwm_check_rfkill(struct iwm_softc *sc)
332 {
333 uint32_t v;
334 int rv;
335
336 /*
337 * "documentation" is not really helpful here:
338 * 27: HW_RF_KILL_SW
339 * Indicates state of (platform's) hardware RF-Kill switch
340 *
341 * But apparently when it's off, it's on ...
342 */
343 v = IWM_READ(sc, IWM_CSR_GP_CNTRL);
344 rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0;
345 if (rv) {
346 sc->sc_flags |= IWM_FLAG_RFKILL;
347 } else {
348 sc->sc_flags &= ~IWM_FLAG_RFKILL;
349 }
350
351 return rv;
352 }
353
354
355 #define IWM_HW_READY_TIMEOUT 50
356 int
iwm_set_hw_ready(struct iwm_softc * sc)357 iwm_set_hw_ready(struct iwm_softc *sc)
358 {
359 int ready;
360
361 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
362 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
363
364 ready = iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG,
365 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
366 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
367 IWM_HW_READY_TIMEOUT);
368 if (ready) {
369 IWM_SETBITS(sc, IWM_CSR_MBOX_SET_REG,
370 IWM_CSR_MBOX_SET_REG_OS_ALIVE);
371 }
372 return ready;
373 }
374 #undef IWM_HW_READY_TIMEOUT
375
376 int
iwm_prepare_card_hw(struct iwm_softc * sc)377 iwm_prepare_card_hw(struct iwm_softc *sc)
378 {
379 int rv = 0;
380 int t = 0;
381
382 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__);
383 if (iwm_set_hw_ready(sc))
384 goto out;
385
386 DELAY(100);
387
388 /* If HW is not ready, prepare the conditions to check again */
389 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
390 IWM_CSR_HW_IF_CONFIG_REG_PREPARE);
391
392 do {
393 if (iwm_set_hw_ready(sc))
394 goto out;
395 DELAY(200);
396 t += 200;
397 } while (t < 150000);
398
399 rv = ETIMEDOUT;
400
401 out:
402 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__);
403 return rv;
404 }
405
406 void
iwm_apm_config(struct iwm_softc * sc)407 iwm_apm_config(struct iwm_softc *sc)
408 {
409 uint16_t lctl, cap;
410 int pcie_ptr;
411
412 /*
413 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
414 * Check if BIOS (or OS) enabled L1-ASPM on this device.
415 * If so (likely), disable L0S, so device moves directly L0->L1;
416 * costs negligible amount of power savings.
417 * If not (unlikely), enable L0S, so there is at least some
418 * power savings, even without L1.
419 */
420 int error;
421
422 error = pci_find_cap(sc->sc_dev, PCIY_EXPRESS, &pcie_ptr);
423 if (error != 0)
424 return;
425 lctl = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_LINK_CTL,
426 sizeof(lctl));
427 if (lctl & PCIEM_LINK_CTL_ASPMC_L1) {
428 IWM_SETBITS(sc, IWM_CSR_GIO_REG,
429 IWM_CSR_GIO_REG_VAL_L0S_ENABLED);
430 } else {
431 IWM_CLRBITS(sc, IWM_CSR_GIO_REG,
432 IWM_CSR_GIO_REG_VAL_L0S_ENABLED);
433 }
434
435 cap = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_DEVICE_CTL2,
436 sizeof(cap));
437 sc->sc_ltr_enabled = (cap & PCIEM_CTL2_LTR_ENABLE) ? 1 : 0;
438 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_PWRSAVE,
439 "L1 %sabled - LTR %sabled\n",
440 (lctl & PCIEM_LINK_CTL_ASPMC_L1) ? "En" : "Dis",
441 sc->sc_ltr_enabled ? "En" : "Dis");
442 }
443
444 /*
445 * Start up NIC's basic functionality after it has been reset
446 * (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop())
447 * NOTE: This does not load uCode nor start the embedded processor
448 */
449 int
iwm_apm_init(struct iwm_softc * sc)450 iwm_apm_init(struct iwm_softc *sc)
451 {
452 int error = 0;
453
454 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n");
455
456 /* Disable L0S exit timer (platform NMI Work/Around) */
457 if (sc->cfg->device_family != IWM_DEVICE_FAMILY_8000) {
458 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS,
459 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
460 }
461
462 /*
463 * Disable L0s without affecting L1;
464 * don't wait for ICH L0s (ICH bug W/A)
465 */
466 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS,
467 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
468
469 /* Set FH wait threshold to maximum (HW error during stress W/A) */
470 IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL);
471
472 /*
473 * Enable HAP INTA (interrupt from management bus) to
474 * wake device's PCI Express link L1a -> L0s
475 */
476 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
477 IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
478
479 iwm_apm_config(sc);
480
481 #if 0 /* not for 7k/8k */
482 /* Configure analog phase-lock-loop before activating to D0A */
483 if (trans->cfg->base_params->pll_cfg_val)
484 IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG,
485 trans->cfg->base_params->pll_cfg_val);
486 #endif
487
488 /*
489 * Set "initialization complete" bit to move adapter from
490 * D0U* --> D0A* (powered-up active) state.
491 */
492 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
493
494 /*
495 * Wait for clock stabilization; once stabilized, access to
496 * device-internal resources is supported, e.g. iwm_write_prph()
497 * and accesses to uCode SRAM.
498 */
499 if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
500 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
501 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) {
502 device_printf(sc->sc_dev,
503 "timeout waiting for clock stabilization\n");
504 error = ETIMEDOUT;
505 goto out;
506 }
507
508 if (sc->cfg->host_interrupt_operation_mode) {
509 /*
510 * This is a bit of an abuse - This is needed for 7260 / 3160
511 * only check host_interrupt_operation_mode even if this is
512 * not related to host_interrupt_operation_mode.
513 *
514 * Enable the oscillator to count wake up time for L1 exit. This
515 * consumes slightly more power (100uA) - but allows to be sure
516 * that we wake up from L1 on time.
517 *
518 * This looks weird: read twice the same register, discard the
519 * value, set a bit, and yet again, read that same register
520 * just to discard the value. But that's the way the hardware
521 * seems to like it.
522 */
523 if (iwm_nic_lock(sc)) {
524 iwm_read_prph(sc, IWM_OSC_CLK);
525 iwm_read_prph(sc, IWM_OSC_CLK);
526 iwm_nic_unlock(sc);
527 }
528 iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL);
529 if (iwm_nic_lock(sc)) {
530 iwm_read_prph(sc, IWM_OSC_CLK);
531 iwm_read_prph(sc, IWM_OSC_CLK);
532 iwm_nic_unlock(sc);
533 }
534 }
535
536 /*
537 * Enable DMA clock and wait for it to stabilize.
538 *
539 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
540 * do not disable clocks. This preserves any hardware bits already
541 * set by default in "CLK_CTRL_REG" after reset.
542 */
543 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) {
544 if (iwm_nic_lock(sc)) {
545 iwm_write_prph(sc, IWM_APMG_CLK_EN_REG,
546 IWM_APMG_CLK_VAL_DMA_CLK_RQT);
547 iwm_nic_unlock(sc);
548 }
549 DELAY(20);
550
551 /* Disable L1-Active */
552 iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG,
553 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
554
555 /* Clear the interrupt in APMG if the NIC is in RFKILL */
556 if (iwm_nic_lock(sc)) {
557 iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG,
558 IWM_APMG_RTC_INT_STT_RFKILL);
559 iwm_nic_unlock(sc);
560 }
561 }
562 out:
563 if (error)
564 device_printf(sc->sc_dev, "apm init error %d\n", error);
565 return error;
566 }
567
568 /* iwlwifi/pcie/trans.c */
569 void
iwm_apm_stop(struct iwm_softc * sc)570 iwm_apm_stop(struct iwm_softc *sc)
571 {
572 /* stop device's busmaster DMA activity */
573 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER);
574
575 if (!iwm_poll_bit(sc, IWM_CSR_RESET,
576 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED,
577 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100))
578 device_printf(sc->sc_dev, "timeout waiting for master\n");
579 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__);
580 }
581
582 /* iwlwifi pcie/trans.c */
583 int
iwm_start_hw(struct iwm_softc * sc)584 iwm_start_hw(struct iwm_softc *sc)
585 {
586 int error;
587
588 if ((error = iwm_prepare_card_hw(sc)) != 0)
589 return error;
590
591 /* Reset the entire device */
592 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET);
593 DELAY(10);
594
595 if ((error = iwm_apm_init(sc)) != 0)
596 return error;
597
598 iwm_enable_rfkill_int(sc);
599 iwm_check_rfkill(sc);
600
601 return 0;
602 }
603
604 /* iwlwifi pcie/trans.c (always main power) */
605 void
iwm_set_pwr(struct iwm_softc * sc)606 iwm_set_pwr(struct iwm_softc *sc)
607 {
608 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG,
609 IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC);
610 }
611
612 /* iwlwifi pcie/rx.c */
613 int
iwm_pcie_rx_stop(struct iwm_softc * sc)614 iwm_pcie_rx_stop(struct iwm_softc *sc)
615 {
616 int ret = 0;
617 if (iwm_nic_lock(sc)) {
618 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
619 ret = iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG,
620 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
621 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
622 1000);
623 iwm_nic_unlock(sc);
624 }
625 return ret;
626 }
627
628 void
iwm_pcie_clear_cmd_in_flight(struct iwm_softc * sc)629 iwm_pcie_clear_cmd_in_flight(struct iwm_softc *sc)
630 {
631 if (!sc->cfg->apmg_wake_up_wa)
632 return;
633
634 if (!sc->cmd_hold_nic_awake) {
635 device_printf(sc->sc_dev,
636 "%s: cmd_hold_nic_awake not set\n", __func__);
637 return;
638 }
639
640 sc->cmd_hold_nic_awake = 0;
641 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
642 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
643 }
644
645 int
iwm_pcie_set_cmd_in_flight(struct iwm_softc * sc)646 iwm_pcie_set_cmd_in_flight(struct iwm_softc *sc)
647 {
648 int ret;
649
650 /*
651 * wake up the NIC to make sure that the firmware will see the host
652 * command - we will let the NIC sleep once all the host commands
653 * returned. This needs to be done only on NICs that have
654 * apmg_wake_up_wa set.
655 */
656 if (sc->cfg->apmg_wake_up_wa &&
657 !sc->cmd_hold_nic_awake) {
658
659 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
660 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
661
662 ret = iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
663 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
664 (IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
665 IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
666 15000);
667 if (ret == 0) {
668 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
669 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
670 device_printf(sc->sc_dev,
671 "%s: Failed to wake NIC for hcmd\n", __func__);
672 return EIO;
673 }
674 sc->cmd_hold_nic_awake = 1;
675 }
676
677 return 0;
678 }
679