xref: /freebsd-12.1/sys/gnu/dts/arm/aspeed-g5.dtsi (revision 43faf498) 
1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/clock/aspeed-clock.h>
3
4/ {
5	model = "Aspeed BMC";
6	compatible = "aspeed,ast2500";
7	#address-cells = <1>;
8	#size-cells = <1>;
9	interrupt-parent = <&vic>;
10
11	aliases {
12		i2c0 = &i2c0;
13		i2c1 = &i2c1;
14		i2c2 = &i2c2;
15		i2c3 = &i2c3;
16		i2c4 = &i2c4;
17		i2c5 = &i2c5;
18		i2c6 = &i2c6;
19		i2c7 = &i2c7;
20		i2c8 = &i2c8;
21		i2c9 = &i2c9;
22		i2c10 = &i2c10;
23		i2c11 = &i2c11;
24		i2c12 = &i2c12;
25		i2c13 = &i2c13;
26		serial0 = &uart1;
27		serial1 = &uart2;
28		serial2 = &uart3;
29		serial3 = &uart4;
30		serial4 = &uart5;
31		serial5 = &vuart;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		cpu@0 {
39			compatible = "arm,arm1176jzf-s";
40			device_type = "cpu";
41			reg = <0>;
42		};
43	};
44
45	memory@80000000 {
46		device_type = "memory";
47		reg = <0x80000000 0>;
48	};
49
50	edac: sdram@1e6e0000 {
51		compatible = "aspeed,ast2500-sdram-edac";
52		reg = <0x1e6e0000 0x174>;
53		interrupts = <0>;
54		status = "disabled";
55	};
56
57	ahb {
58		compatible = "simple-bus";
59		#address-cells = <1>;
60		#size-cells = <1>;
61		ranges;
62
63		fmc: flash-controller@1e620000 {
64			reg = < 0x1e620000 0xc4
65				0x20000000 0x10000000 >;
66			#address-cells = <1>;
67			#size-cells = <0>;
68			compatible = "aspeed,ast2500-fmc";
69			clocks = <&syscon ASPEED_CLK_AHB>;
70			status = "disabled";
71			interrupts = <19>;
72			flash@0 {
73				reg = < 0 >;
74				compatible = "jedec,spi-nor";
75				status = "disabled";
76			};
77			flash@1 {
78				reg = < 1 >;
79				compatible = "jedec,spi-nor";
80				status = "disabled";
81			};
82			flash@2 {
83				reg = < 2 >;
84				compatible = "jedec,spi-nor";
85				status = "disabled";
86			};
87		};
88
89		spi1: flash-controller@1e630000 {
90			reg = < 0x1e630000 0xc4
91				0x30000000 0x08000000 >;
92			#address-cells = <1>;
93			#size-cells = <0>;
94			compatible = "aspeed,ast2500-spi";
95			clocks = <&syscon ASPEED_CLK_AHB>;
96			status = "disabled";
97			flash@0 {
98				reg = < 0 >;
99				compatible = "jedec,spi-nor";
100				status = "disabled";
101			};
102			flash@1 {
103				reg = < 1 >;
104				compatible = "jedec,spi-nor";
105				status = "disabled";
106			};
107		};
108
109		spi2: flash-controller@1e631000 {
110			reg = < 0x1e631000 0xc4
111				0x38000000 0x08000000 >;
112			#address-cells = <1>;
113			#size-cells = <0>;
114			compatible = "aspeed,ast2500-spi";
115			clocks = <&syscon ASPEED_CLK_AHB>;
116			status = "disabled";
117			flash@0 {
118				reg = < 0 >;
119				compatible = "jedec,spi-nor";
120				status = "disabled";
121			};
122			flash@1 {
123				reg = < 1 >;
124				compatible = "jedec,spi-nor";
125				status = "disabled";
126			};
127		};
128
129		vic: interrupt-controller@1e6c0080 {
130			compatible = "aspeed,ast2400-vic";
131			interrupt-controller;
132			#interrupt-cells = <1>;
133			valid-sources = <0xfefff7ff 0x0807ffff>;
134			reg = <0x1e6c0080 0x80>;
135		};
136
137		cvic: copro-interrupt-controller@1e6c2000 {
138			compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
139			valid-sources = <0xffffffff>;
140			copro-sw-interrupts = <1>;
141			reg = <0x1e6c2000 0x80>;
142		};
143
144		mac0: ethernet@1e660000 {
145			compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
146			reg = <0x1e660000 0x180>;
147			interrupts = <2>;
148			clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
149			status = "disabled";
150		};
151
152		mac1: ethernet@1e680000 {
153			compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
154			reg = <0x1e680000 0x180>;
155			interrupts = <3>;
156			clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
157			status = "disabled";
158		};
159
160		ehci0: usb@1e6a1000 {
161			compatible = "aspeed,ast2500-ehci", "generic-ehci";
162			reg = <0x1e6a1000 0x100>;
163			interrupts = <5>;
164			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
165			pinctrl-names = "default";
166			pinctrl-0 = <&pinctrl_usb2ah_default>;
167			status = "disabled";
168		};
169
170		ehci1: usb@1e6a3000 {
171			compatible = "aspeed,ast2500-ehci", "generic-ehci";
172			reg = <0x1e6a3000 0x100>;
173			interrupts = <13>;
174			clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
175			pinctrl-names = "default";
176			pinctrl-0 = <&pinctrl_usb2bh_default>;
177			status = "disabled";
178		};
179
180		uhci: usb@1e6b0000 {
181			compatible = "aspeed,ast2500-uhci", "generic-uhci";
182			reg = <0x1e6b0000 0x100>;
183			interrupts = <14>;
184			#ports = <2>;
185			clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
186			status = "disabled";
187			/*
188			 * No default pinmux, it will follow EHCI, use an explicit pinmux
189			 * override if you don't enable EHCI
190			 */
191		};
192
193		vhub: usb-vhub@1e6a0000 {
194			compatible = "aspeed,ast2500-usb-vhub";
195			reg = <0x1e6a0000 0x300>;
196			interrupts = <5>;
197			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
198			pinctrl-names = "default";
199			pinctrl-0 = <&pinctrl_usb2ad_default>;
200			status = "disabled";
201		};
202
203		apb {
204			compatible = "simple-bus";
205			#address-cells = <1>;
206			#size-cells = <1>;
207			ranges;
208
209			syscon: syscon@1e6e2000 {
210				compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
211				reg = <0x1e6e2000 0x1a8>;
212				#address-cells = <1>;
213				#size-cells = <0>;
214				#clock-cells = <1>;
215				#reset-cells = <1>;
216
217				pinctrl: pinctrl {
218					compatible = "aspeed,g5-pinctrl";
219					aspeed,external-nodes = <&gfx &lhc>;
220
221				};
222			};
223
224			rng: hwrng@1e6e2078 {
225				compatible = "timeriomem_rng";
226				reg = <0x1e6e2078 0x4>;
227				period = <1>;
228				quality = <100>;
229			};
230
231			gfx: display@1e6e6000 {
232				compatible = "aspeed,ast2500-gfx", "syscon";
233				reg = <0x1e6e6000 0x1000>;
234				reg-io-width = <4>;
235			};
236
237			adc: adc@1e6e9000 {
238				compatible = "aspeed,ast2500-adc";
239				reg = <0x1e6e9000 0xb0>;
240				clocks = <&syscon ASPEED_CLK_APB>;
241				resets = <&syscon ASPEED_RESET_ADC>;
242				#io-channel-cells = <1>;
243				status = "disabled";
244			};
245
246			sram: sram@1e720000 {
247				compatible = "mmio-sram";
248				reg = <0x1e720000 0x9000>;	// 36K
249			};
250
251			gpio: gpio@1e780000 {
252				#gpio-cells = <2>;
253				gpio-controller;
254				compatible = "aspeed,ast2500-gpio";
255				reg = <0x1e780000 0x1000>;
256				interrupts = <20>;
257				gpio-ranges = <&pinctrl 0 0 220>;
258				clocks = <&syscon ASPEED_CLK_APB>;
259				interrupt-controller;
260				#interrupt-cells = <2>;
261			};
262
263			timer: timer@1e782000 {
264				/* This timer is a Faraday FTTMR010 derivative */
265				compatible = "aspeed,ast2400-timer";
266				reg = <0x1e782000 0x90>;
267				interrupts = <16 17 18 35 36 37 38 39>;
268				clocks = <&syscon ASPEED_CLK_APB>;
269				clock-names = "PCLK";
270			};
271
272			uart1: serial@1e783000 {
273				compatible = "ns16550a";
274				reg = <0x1e783000 0x20>;
275				reg-shift = <2>;
276				interrupts = <9>;
277				clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
278				resets = <&lpc_reset 4>;
279				no-loopback-test;
280				status = "disabled";
281			};
282
283			uart5: serial@1e784000 {
284				compatible = "ns16550a";
285				reg = <0x1e784000 0x20>;
286				reg-shift = <2>;
287				interrupts = <10>;
288				clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
289				no-loopback-test;
290				status = "disabled";
291			};
292
293			wdt1: watchdog@1e785000 {
294				compatible = "aspeed,ast2500-wdt";
295				reg = <0x1e785000 0x20>;
296				clocks = <&syscon ASPEED_CLK_APB>;
297			};
298
299			wdt2: watchdog@1e785020 {
300				compatible = "aspeed,ast2500-wdt";
301				reg = <0x1e785020 0x20>;
302				clocks = <&syscon ASPEED_CLK_APB>;
303			};
304
305			wdt3: watchdog@1e785040 {
306				compatible = "aspeed,ast2500-wdt";
307				reg = <0x1e785040 0x20>;
308				clocks = <&syscon ASPEED_CLK_APB>;
309				status = "disabled";
310			};
311
312			pwm_tacho: pwm-tacho-controller@1e786000 {
313				compatible = "aspeed,ast2500-pwm-tacho";
314				#address-cells = <1>;
315				#size-cells = <0>;
316				reg = <0x1e786000 0x1000>;
317				clocks = <&syscon ASPEED_CLK_24M>;
318				resets = <&syscon ASPEED_RESET_PWM>;
319				status = "disabled";
320			};
321
322			vuart: serial@1e787000 {
323				compatible = "aspeed,ast2500-vuart";
324				reg = <0x1e787000 0x40>;
325				reg-shift = <2>;
326				interrupts = <8>;
327				clocks = <&syscon ASPEED_CLK_APB>;
328				no-loopback-test;
329				status = "disabled";
330			};
331
332			lpc: lpc@1e789000 {
333				compatible = "aspeed,ast2500-lpc", "simple-mfd";
334				reg = <0x1e789000 0x1000>;
335
336				#address-cells = <1>;
337				#size-cells = <1>;
338				ranges = <0x0 0x1e789000 0x1000>;
339
340				lpc_bmc: lpc-bmc@0 {
341					compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
342					reg = <0x0 0x80>;
343					reg-io-width = <4>;
344
345					#address-cells = <1>;
346					#size-cells = <1>;
347					ranges = <0x0 0x0 0x80>;
348
349					kcs1: kcs1@0 {
350						compatible = "aspeed,ast2500-kcs-bmc";
351						interrupts = <8>;
352						kcs_chan = <1>;
353						status = "disabled";
354					};
355					kcs2: kcs2@0 {
356						compatible = "aspeed,ast2500-kcs-bmc";
357						interrupts = <8>;
358						kcs_chan = <2>;
359						status = "disabled";
360					};
361					kcs3: kcs3@0 {
362						compatible = "aspeed,ast2500-kcs-bmc";
363						interrupts = <8>;
364						kcs_chan = <3>;
365						status = "disabled";
366					};
367				};
368
369				lpc_host: lpc-host@80 {
370					compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
371					reg = <0x80 0x1e0>;
372					reg-io-width = <4>;
373
374					#address-cells = <1>;
375					#size-cells = <1>;
376					ranges = <0x0 0x80 0x1e0>;
377
378					kcs4: kcs4@0 {
379						compatible = "aspeed,ast2500-kcs-bmc";
380						interrupts = <8>;
381						kcs_chan = <4>;
382						status = "disabled";
383					};
384
385					lpc_ctrl: lpc-ctrl@0 {
386						compatible = "aspeed,ast2500-lpc-ctrl";
387						reg = <0x0 0x80>;
388						clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
389						status = "disabled";
390					};
391
392					lpc_snoop: lpc-snoop@0 {
393						compatible = "aspeed,ast2500-lpc-snoop";
394						reg = <0x0 0x80>;
395						interrupts = <8>;
396						status = "disabled";
397					};
398
399					lhc: lhc@20 {
400						compatible = "aspeed,ast2500-lhc";
401						reg = <0x20 0x24 0x48 0x8>;
402					};
403
404					lpc_reset: reset-controller@18 {
405						compatible = "aspeed,ast2500-lpc-reset";
406						reg = <0x18 0x4>;
407						#reset-cells = <1>;
408					};
409
410					ibt: ibt@c0 {
411						compatible = "aspeed,ast2500-ibt-bmc";
412						reg = <0xc0 0x18>;
413						interrupts = <8>;
414						status = "disabled";
415					};
416				};
417			};
418
419			uart2: serial@1e78d000 {
420				compatible = "ns16550a";
421				reg = <0x1e78d000 0x20>;
422				reg-shift = <2>;
423				interrupts = <32>;
424				clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
425				resets = <&lpc_reset 5>;
426				no-loopback-test;
427				status = "disabled";
428			};
429
430			uart3: serial@1e78e000 {
431				compatible = "ns16550a";
432				reg = <0x1e78e000 0x20>;
433				reg-shift = <2>;
434				interrupts = <33>;
435				clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
436				resets = <&lpc_reset 6>;
437				no-loopback-test;
438				status = "disabled";
439			};
440
441			uart4: serial@1e78f000 {
442				compatible = "ns16550a";
443				reg = <0x1e78f000 0x20>;
444				reg-shift = <2>;
445				interrupts = <34>;
446				clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
447				resets = <&lpc_reset 7>;
448				no-loopback-test;
449				status = "disabled";
450			};
451
452			i2c: bus@1e78a000 {
453				compatible = "simple-bus";
454				#address-cells = <1>;
455				#size-cells = <1>;
456				ranges = <0 0x1e78a000 0x1000>;
457			};
458		};
459	};
460};
461
462&i2c {
463	i2c_ic: interrupt-controller@0 {
464		#interrupt-cells = <1>;
465		compatible = "aspeed,ast2500-i2c-ic";
466		reg = <0x0 0x40>;
467		interrupts = <12>;
468		interrupt-controller;
469	};
470
471	i2c0: i2c-bus@40 {
472		#address-cells = <1>;
473		#size-cells = <0>;
474		#interrupt-cells = <1>;
475
476		reg = <0x40 0x40>;
477		compatible = "aspeed,ast2500-i2c-bus";
478		clocks = <&syscon ASPEED_CLK_APB>;
479		resets = <&syscon ASPEED_RESET_I2C>;
480		bus-frequency = <100000>;
481		interrupts = <0>;
482		interrupt-parent = <&i2c_ic>;
483		status = "disabled";
484		/* Does not need pinctrl properties */
485	};
486
487	i2c1: i2c-bus@80 {
488		#address-cells = <1>;
489		#size-cells = <0>;
490		#interrupt-cells = <1>;
491
492		reg = <0x80 0x40>;
493		compatible = "aspeed,ast2500-i2c-bus";
494		clocks = <&syscon ASPEED_CLK_APB>;
495		resets = <&syscon ASPEED_RESET_I2C>;
496		bus-frequency = <100000>;
497		interrupts = <1>;
498		interrupt-parent = <&i2c_ic>;
499		status = "disabled";
500		/* Does not need pinctrl properties */
501	};
502
503	i2c2: i2c-bus@c0 {
504		#address-cells = <1>;
505		#size-cells = <0>;
506		#interrupt-cells = <1>;
507
508		reg = <0xc0 0x40>;
509		compatible = "aspeed,ast2500-i2c-bus";
510		clocks = <&syscon ASPEED_CLK_APB>;
511		resets = <&syscon ASPEED_RESET_I2C>;
512		bus-frequency = <100000>;
513		interrupts = <2>;
514		interrupt-parent = <&i2c_ic>;
515		pinctrl-names = "default";
516		pinctrl-0 = <&pinctrl_i2c3_default>;
517		status = "disabled";
518	};
519
520	i2c3: i2c-bus@100 {
521		#address-cells = <1>;
522		#size-cells = <0>;
523		#interrupt-cells = <1>;
524
525		reg = <0x100 0x40>;
526		compatible = "aspeed,ast2500-i2c-bus";
527		clocks = <&syscon ASPEED_CLK_APB>;
528		resets = <&syscon ASPEED_RESET_I2C>;
529		bus-frequency = <100000>;
530		interrupts = <3>;
531		interrupt-parent = <&i2c_ic>;
532		pinctrl-names = "default";
533		pinctrl-0 = <&pinctrl_i2c4_default>;
534		status = "disabled";
535	};
536
537	i2c4: i2c-bus@140 {
538		#address-cells = <1>;
539		#size-cells = <0>;
540		#interrupt-cells = <1>;
541
542		reg = <0x140 0x40>;
543		compatible = "aspeed,ast2500-i2c-bus";
544		clocks = <&syscon ASPEED_CLK_APB>;
545		resets = <&syscon ASPEED_RESET_I2C>;
546		bus-frequency = <100000>;
547		interrupts = <4>;
548		interrupt-parent = <&i2c_ic>;
549		pinctrl-names = "default";
550		pinctrl-0 = <&pinctrl_i2c5_default>;
551		status = "disabled";
552	};
553
554	i2c5: i2c-bus@180 {
555		#address-cells = <1>;
556		#size-cells = <0>;
557		#interrupt-cells = <1>;
558
559		reg = <0x180 0x40>;
560		compatible = "aspeed,ast2500-i2c-bus";
561		clocks = <&syscon ASPEED_CLK_APB>;
562		resets = <&syscon ASPEED_RESET_I2C>;
563		bus-frequency = <100000>;
564		interrupts = <5>;
565		interrupt-parent = <&i2c_ic>;
566		pinctrl-names = "default";
567		pinctrl-0 = <&pinctrl_i2c6_default>;
568		status = "disabled";
569	};
570
571	i2c6: i2c-bus@1c0 {
572		#address-cells = <1>;
573		#size-cells = <0>;
574		#interrupt-cells = <1>;
575
576		reg = <0x1c0 0x40>;
577		compatible = "aspeed,ast2500-i2c-bus";
578		clocks = <&syscon ASPEED_CLK_APB>;
579		resets = <&syscon ASPEED_RESET_I2C>;
580		bus-frequency = <100000>;
581		interrupts = <6>;
582		interrupt-parent = <&i2c_ic>;
583		pinctrl-names = "default";
584		pinctrl-0 = <&pinctrl_i2c7_default>;
585		status = "disabled";
586	};
587
588	i2c7: i2c-bus@300 {
589		#address-cells = <1>;
590		#size-cells = <0>;
591		#interrupt-cells = <1>;
592
593		reg = <0x300 0x40>;
594		compatible = "aspeed,ast2500-i2c-bus";
595		clocks = <&syscon ASPEED_CLK_APB>;
596		resets = <&syscon ASPEED_RESET_I2C>;
597		bus-frequency = <100000>;
598		interrupts = <7>;
599		interrupt-parent = <&i2c_ic>;
600		pinctrl-names = "default";
601		pinctrl-0 = <&pinctrl_i2c8_default>;
602		status = "disabled";
603	};
604
605	i2c8: i2c-bus@340 {
606		#address-cells = <1>;
607		#size-cells = <0>;
608		#interrupt-cells = <1>;
609
610		reg = <0x340 0x40>;
611		compatible = "aspeed,ast2500-i2c-bus";
612		clocks = <&syscon ASPEED_CLK_APB>;
613		resets = <&syscon ASPEED_RESET_I2C>;
614		bus-frequency = <100000>;
615		interrupts = <8>;
616		interrupt-parent = <&i2c_ic>;
617		pinctrl-names = "default";
618		pinctrl-0 = <&pinctrl_i2c9_default>;
619		status = "disabled";
620	};
621
622	i2c9: i2c-bus@380 {
623		#address-cells = <1>;
624		#size-cells = <0>;
625		#interrupt-cells = <1>;
626
627		reg = <0x380 0x40>;
628		compatible = "aspeed,ast2500-i2c-bus";
629		clocks = <&syscon ASPEED_CLK_APB>;
630		resets = <&syscon ASPEED_RESET_I2C>;
631		bus-frequency = <100000>;
632		interrupts = <9>;
633		interrupt-parent = <&i2c_ic>;
634		pinctrl-names = "default";
635		pinctrl-0 = <&pinctrl_i2c10_default>;
636		status = "disabled";
637	};
638
639	i2c10: i2c-bus@3c0 {
640		#address-cells = <1>;
641		#size-cells = <0>;
642		#interrupt-cells = <1>;
643
644		reg = <0x3c0 0x40>;
645		compatible = "aspeed,ast2500-i2c-bus";
646		clocks = <&syscon ASPEED_CLK_APB>;
647		resets = <&syscon ASPEED_RESET_I2C>;
648		bus-frequency = <100000>;
649		interrupts = <10>;
650		interrupt-parent = <&i2c_ic>;
651		pinctrl-names = "default";
652		pinctrl-0 = <&pinctrl_i2c11_default>;
653		status = "disabled";
654	};
655
656	i2c11: i2c-bus@400 {
657		#address-cells = <1>;
658		#size-cells = <0>;
659		#interrupt-cells = <1>;
660
661		reg = <0x400 0x40>;
662		compatible = "aspeed,ast2500-i2c-bus";
663		clocks = <&syscon ASPEED_CLK_APB>;
664		resets = <&syscon ASPEED_RESET_I2C>;
665		bus-frequency = <100000>;
666		interrupts = <11>;
667		interrupt-parent = <&i2c_ic>;
668		pinctrl-names = "default";
669		pinctrl-0 = <&pinctrl_i2c12_default>;
670		status = "disabled";
671	};
672
673	i2c12: i2c-bus@440 {
674		#address-cells = <1>;
675		#size-cells = <0>;
676		#interrupt-cells = <1>;
677
678		reg = <0x440 0x40>;
679		compatible = "aspeed,ast2500-i2c-bus";
680		clocks = <&syscon ASPEED_CLK_APB>;
681		resets = <&syscon ASPEED_RESET_I2C>;
682		bus-frequency = <100000>;
683		interrupts = <12>;
684		interrupt-parent = <&i2c_ic>;
685		pinctrl-names = "default";
686		pinctrl-0 = <&pinctrl_i2c13_default>;
687		status = "disabled";
688	};
689
690	i2c13: i2c-bus@480 {
691		#address-cells = <1>;
692		#size-cells = <0>;
693		#interrupt-cells = <1>;
694
695		reg = <0x480 0x40>;
696		compatible = "aspeed,ast2500-i2c-bus";
697		clocks = <&syscon ASPEED_CLK_APB>;
698		resets = <&syscon ASPEED_RESET_I2C>;
699		bus-frequency = <100000>;
700		interrupts = <13>;
701		interrupt-parent = <&i2c_ic>;
702		pinctrl-names = "default";
703		pinctrl-0 = <&pinctrl_i2c14_default>;
704		status = "disabled";
705	};
706};
707
708&pinctrl {
709	pinctrl_acpi_default: acpi_default {
710		function = "ACPI";
711		groups = "ACPI";
712	};
713
714	pinctrl_adc0_default: adc0_default {
715		function = "ADC0";
716		groups = "ADC0";
717	};
718
719	pinctrl_adc1_default: adc1_default {
720		function = "ADC1";
721		groups = "ADC1";
722	};
723
724	pinctrl_adc10_default: adc10_default {
725		function = "ADC10";
726		groups = "ADC10";
727	};
728
729	pinctrl_adc11_default: adc11_default {
730		function = "ADC11";
731		groups = "ADC11";
732	};
733
734	pinctrl_adc12_default: adc12_default {
735		function = "ADC12";
736		groups = "ADC12";
737	};
738
739	pinctrl_adc13_default: adc13_default {
740		function = "ADC13";
741		groups = "ADC13";
742	};
743
744	pinctrl_adc14_default: adc14_default {
745		function = "ADC14";
746		groups = "ADC14";
747	};
748
749	pinctrl_adc15_default: adc15_default {
750		function = "ADC15";
751		groups = "ADC15";
752	};
753
754	pinctrl_adc2_default: adc2_default {
755		function = "ADC2";
756		groups = "ADC2";
757	};
758
759	pinctrl_adc3_default: adc3_default {
760		function = "ADC3";
761		groups = "ADC3";
762	};
763
764	pinctrl_adc4_default: adc4_default {
765		function = "ADC4";
766		groups = "ADC4";
767	};
768
769	pinctrl_adc5_default: adc5_default {
770		function = "ADC5";
771		groups = "ADC5";
772	};
773
774	pinctrl_adc6_default: adc6_default {
775		function = "ADC6";
776		groups = "ADC6";
777	};
778
779	pinctrl_adc7_default: adc7_default {
780		function = "ADC7";
781		groups = "ADC7";
782	};
783
784	pinctrl_adc8_default: adc8_default {
785		function = "ADC8";
786		groups = "ADC8";
787	};
788
789	pinctrl_adc9_default: adc9_default {
790		function = "ADC9";
791		groups = "ADC9";
792	};
793
794	pinctrl_bmcint_default: bmcint_default {
795		function = "BMCINT";
796		groups = "BMCINT";
797	};
798
799	pinctrl_ddcclk_default: ddcclk_default {
800		function = "DDCCLK";
801		groups = "DDCCLK";
802	};
803
804	pinctrl_ddcdat_default: ddcdat_default {
805		function = "DDCDAT";
806		groups = "DDCDAT";
807	};
808
809	pinctrl_espi_default: espi_default {
810		function = "ESPI";
811		groups = "ESPI";
812	};
813
814	pinctrl_fwspics1_default: fwspics1_default {
815		function = "FWSPICS1";
816		groups = "FWSPICS1";
817	};
818
819	pinctrl_fwspics2_default: fwspics2_default {
820		function = "FWSPICS2";
821		groups = "FWSPICS2";
822	};
823
824	pinctrl_gpid0_default: gpid0_default {
825		function = "GPID0";
826		groups = "GPID0";
827	};
828
829	pinctrl_gpid2_default: gpid2_default {
830		function = "GPID2";
831		groups = "GPID2";
832	};
833
834	pinctrl_gpid4_default: gpid4_default {
835		function = "GPID4";
836		groups = "GPID4";
837	};
838
839	pinctrl_gpid6_default: gpid6_default {
840		function = "GPID6";
841		groups = "GPID6";
842	};
843
844	pinctrl_gpie0_default: gpie0_default {
845		function = "GPIE0";
846		groups = "GPIE0";
847	};
848
849	pinctrl_gpie2_default: gpie2_default {
850		function = "GPIE2";
851		groups = "GPIE2";
852	};
853
854	pinctrl_gpie4_default: gpie4_default {
855		function = "GPIE4";
856		groups = "GPIE4";
857	};
858
859	pinctrl_gpie6_default: gpie6_default {
860		function = "GPIE6";
861		groups = "GPIE6";
862	};
863
864	pinctrl_i2c10_default: i2c10_default {
865		function = "I2C10";
866		groups = "I2C10";
867	};
868
869	pinctrl_i2c11_default: i2c11_default {
870		function = "I2C11";
871		groups = "I2C11";
872	};
873
874	pinctrl_i2c12_default: i2c12_default {
875		function = "I2C12";
876		groups = "I2C12";
877	};
878
879	pinctrl_i2c13_default: i2c13_default {
880		function = "I2C13";
881		groups = "I2C13";
882	};
883
884	pinctrl_i2c14_default: i2c14_default {
885		function = "I2C14";
886		groups = "I2C14";
887	};
888
889	pinctrl_i2c3_default: i2c3_default {
890		function = "I2C3";
891		groups = "I2C3";
892	};
893
894	pinctrl_i2c4_default: i2c4_default {
895		function = "I2C4";
896		groups = "I2C4";
897	};
898
899	pinctrl_i2c5_default: i2c5_default {
900		function = "I2C5";
901		groups = "I2C5";
902	};
903
904	pinctrl_i2c6_default: i2c6_default {
905		function = "I2C6";
906		groups = "I2C6";
907	};
908
909	pinctrl_i2c7_default: i2c7_default {
910		function = "I2C7";
911		groups = "I2C7";
912	};
913
914	pinctrl_i2c8_default: i2c8_default {
915		function = "I2C8";
916		groups = "I2C8";
917	};
918
919	pinctrl_i2c9_default: i2c9_default {
920		function = "I2C9";
921		groups = "I2C9";
922	};
923
924	pinctrl_lad0_default: lad0_default {
925		function = "LAD0";
926		groups = "LAD0";
927	};
928
929	pinctrl_lad1_default: lad1_default {
930		function = "LAD1";
931		groups = "LAD1";
932	};
933
934	pinctrl_lad2_default: lad2_default {
935		function = "LAD2";
936		groups = "LAD2";
937	};
938
939	pinctrl_lad3_default: lad3_default {
940		function = "LAD3";
941		groups = "LAD3";
942	};
943
944	pinctrl_lclk_default: lclk_default {
945		function = "LCLK";
946		groups = "LCLK";
947	};
948
949	pinctrl_lframe_default: lframe_default {
950		function = "LFRAME";
951		groups = "LFRAME";
952	};
953
954	pinctrl_lpchc_default: lpchc_default {
955		function = "LPCHC";
956		groups = "LPCHC";
957	};
958
959	pinctrl_lpcpd_default: lpcpd_default {
960		function = "LPCPD";
961		groups = "LPCPD";
962	};
963
964	pinctrl_lpcplus_default: lpcplus_default {
965		function = "LPCPLUS";
966		groups = "LPCPLUS";
967	};
968
969	pinctrl_lpcpme_default: lpcpme_default {
970		function = "LPCPME";
971		groups = "LPCPME";
972	};
973
974	pinctrl_lpcrst_default: lpcrst_default {
975		function = "LPCRST";
976		groups = "LPCRST";
977	};
978
979	pinctrl_lpcsmi_default: lpcsmi_default {
980		function = "LPCSMI";
981		groups = "LPCSMI";
982	};
983
984	pinctrl_lsirq_default: lsirq_default {
985		function = "LSIRQ";
986		groups = "LSIRQ";
987	};
988
989	pinctrl_mac1link_default: mac1link_default {
990		function = "MAC1LINK";
991		groups = "MAC1LINK";
992	};
993
994	pinctrl_mac2link_default: mac2link_default {
995		function = "MAC2LINK";
996		groups = "MAC2LINK";
997	};
998
999	pinctrl_mdio1_default: mdio1_default {
1000		function = "MDIO1";
1001		groups = "MDIO1";
1002	};
1003
1004	pinctrl_mdio2_default: mdio2_default {
1005		function = "MDIO2";
1006		groups = "MDIO2";
1007	};
1008
1009	pinctrl_ncts1_default: ncts1_default {
1010		function = "NCTS1";
1011		groups = "NCTS1";
1012	};
1013
1014	pinctrl_ncts2_default: ncts2_default {
1015		function = "NCTS2";
1016		groups = "NCTS2";
1017	};
1018
1019	pinctrl_ncts3_default: ncts3_default {
1020		function = "NCTS3";
1021		groups = "NCTS3";
1022	};
1023
1024	pinctrl_ncts4_default: ncts4_default {
1025		function = "NCTS4";
1026		groups = "NCTS4";
1027	};
1028
1029	pinctrl_ndcd1_default: ndcd1_default {
1030		function = "NDCD1";
1031		groups = "NDCD1";
1032	};
1033
1034	pinctrl_ndcd2_default: ndcd2_default {
1035		function = "NDCD2";
1036		groups = "NDCD2";
1037	};
1038
1039	pinctrl_ndcd3_default: ndcd3_default {
1040		function = "NDCD3";
1041		groups = "NDCD3";
1042	};
1043
1044	pinctrl_ndcd4_default: ndcd4_default {
1045		function = "NDCD4";
1046		groups = "NDCD4";
1047	};
1048
1049	pinctrl_ndsr1_default: ndsr1_default {
1050		function = "NDSR1";
1051		groups = "NDSR1";
1052	};
1053
1054	pinctrl_ndsr2_default: ndsr2_default {
1055		function = "NDSR2";
1056		groups = "NDSR2";
1057	};
1058
1059	pinctrl_ndsr3_default: ndsr3_default {
1060		function = "NDSR3";
1061		groups = "NDSR3";
1062	};
1063
1064	pinctrl_ndsr4_default: ndsr4_default {
1065		function = "NDSR4";
1066		groups = "NDSR4";
1067	};
1068
1069	pinctrl_ndtr1_default: ndtr1_default {
1070		function = "NDTR1";
1071		groups = "NDTR1";
1072	};
1073
1074	pinctrl_ndtr2_default: ndtr2_default {
1075		function = "NDTR2";
1076		groups = "NDTR2";
1077	};
1078
1079	pinctrl_ndtr3_default: ndtr3_default {
1080		function = "NDTR3";
1081		groups = "NDTR3";
1082	};
1083
1084	pinctrl_ndtr4_default: ndtr4_default {
1085		function = "NDTR4";
1086		groups = "NDTR4";
1087	};
1088
1089	pinctrl_nri1_default: nri1_default {
1090		function = "NRI1";
1091		groups = "NRI1";
1092	};
1093
1094	pinctrl_nri2_default: nri2_default {
1095		function = "NRI2";
1096		groups = "NRI2";
1097	};
1098
1099	pinctrl_nri3_default: nri3_default {
1100		function = "NRI3";
1101		groups = "NRI3";
1102	};
1103
1104	pinctrl_nri4_default: nri4_default {
1105		function = "NRI4";
1106		groups = "NRI4";
1107	};
1108
1109	pinctrl_nrts1_default: nrts1_default {
1110		function = "NRTS1";
1111		groups = "NRTS1";
1112	};
1113
1114	pinctrl_nrts2_default: nrts2_default {
1115		function = "NRTS2";
1116		groups = "NRTS2";
1117	};
1118
1119	pinctrl_nrts3_default: nrts3_default {
1120		function = "NRTS3";
1121		groups = "NRTS3";
1122	};
1123
1124	pinctrl_nrts4_default: nrts4_default {
1125		function = "NRTS4";
1126		groups = "NRTS4";
1127	};
1128
1129	pinctrl_oscclk_default: oscclk_default {
1130		function = "OSCCLK";
1131		groups = "OSCCLK";
1132	};
1133
1134	pinctrl_pewake_default: pewake_default {
1135		function = "PEWAKE";
1136		groups = "PEWAKE";
1137	};
1138
1139	pinctrl_pnor_default: pnor_default {
1140		function = "PNOR";
1141		groups = "PNOR";
1142	};
1143
1144	pinctrl_pwm0_default: pwm0_default {
1145		function = "PWM0";
1146		groups = "PWM0";
1147	};
1148
1149	pinctrl_pwm1_default: pwm1_default {
1150		function = "PWM1";
1151		groups = "PWM1";
1152	};
1153
1154	pinctrl_pwm2_default: pwm2_default {
1155		function = "PWM2";
1156		groups = "PWM2";
1157	};
1158
1159	pinctrl_pwm3_default: pwm3_default {
1160		function = "PWM3";
1161		groups = "PWM3";
1162	};
1163
1164	pinctrl_pwm4_default: pwm4_default {
1165		function = "PWM4";
1166		groups = "PWM4";
1167	};
1168
1169	pinctrl_pwm5_default: pwm5_default {
1170		function = "PWM5";
1171		groups = "PWM5";
1172	};
1173
1174	pinctrl_pwm6_default: pwm6_default {
1175		function = "PWM6";
1176		groups = "PWM6";
1177	};
1178
1179	pinctrl_pwm7_default: pwm7_default {
1180		function = "PWM7";
1181		groups = "PWM7";
1182	};
1183
1184	pinctrl_rgmii1_default: rgmii1_default {
1185		function = "RGMII1";
1186		groups = "RGMII1";
1187	};
1188
1189	pinctrl_rgmii2_default: rgmii2_default {
1190		function = "RGMII2";
1191		groups = "RGMII2";
1192	};
1193
1194	pinctrl_rmii1_default: rmii1_default {
1195		function = "RMII1";
1196		groups = "RMII1";
1197	};
1198
1199	pinctrl_rmii2_default: rmii2_default {
1200		function = "RMII2";
1201		groups = "RMII2";
1202	};
1203
1204	pinctrl_rxd1_default: rxd1_default {
1205		function = "RXD1";
1206		groups = "RXD1";
1207	};
1208
1209	pinctrl_rxd2_default: rxd2_default {
1210		function = "RXD2";
1211		groups = "RXD2";
1212	};
1213
1214	pinctrl_rxd3_default: rxd3_default {
1215		function = "RXD3";
1216		groups = "RXD3";
1217	};
1218
1219	pinctrl_rxd4_default: rxd4_default {
1220		function = "RXD4";
1221		groups = "RXD4";
1222	};
1223
1224	pinctrl_salt1_default: salt1_default {
1225		function = "SALT1";
1226		groups = "SALT1";
1227	};
1228
1229	pinctrl_salt10_default: salt10_default {
1230		function = "SALT10";
1231		groups = "SALT10";
1232	};
1233
1234	pinctrl_salt11_default: salt11_default {
1235		function = "SALT11";
1236		groups = "SALT11";
1237	};
1238
1239	pinctrl_salt12_default: salt12_default {
1240		function = "SALT12";
1241		groups = "SALT12";
1242	};
1243
1244	pinctrl_salt13_default: salt13_default {
1245		function = "SALT13";
1246		groups = "SALT13";
1247	};
1248
1249	pinctrl_salt14_default: salt14_default {
1250		function = "SALT14";
1251		groups = "SALT14";
1252	};
1253
1254	pinctrl_salt2_default: salt2_default {
1255		function = "SALT2";
1256		groups = "SALT2";
1257	};
1258
1259	pinctrl_salt3_default: salt3_default {
1260		function = "SALT3";
1261		groups = "SALT3";
1262	};
1263
1264	pinctrl_salt4_default: salt4_default {
1265		function = "SALT4";
1266		groups = "SALT4";
1267	};
1268
1269	pinctrl_salt5_default: salt5_default {
1270		function = "SALT5";
1271		groups = "SALT5";
1272	};
1273
1274	pinctrl_salt6_default: salt6_default {
1275		function = "SALT6";
1276		groups = "SALT6";
1277	};
1278
1279	pinctrl_salt7_default: salt7_default {
1280		function = "SALT7";
1281		groups = "SALT7";
1282	};
1283
1284	pinctrl_salt8_default: salt8_default {
1285		function = "SALT8";
1286		groups = "SALT8";
1287	};
1288
1289	pinctrl_salt9_default: salt9_default {
1290		function = "SALT9";
1291		groups = "SALT9";
1292	};
1293
1294	pinctrl_scl1_default: scl1_default {
1295		function = "SCL1";
1296		groups = "SCL1";
1297	};
1298
1299	pinctrl_scl2_default: scl2_default {
1300		function = "SCL2";
1301		groups = "SCL2";
1302	};
1303
1304	pinctrl_sd1_default: sd1_default {
1305		function = "SD1";
1306		groups = "SD1";
1307	};
1308
1309	pinctrl_sd2_default: sd2_default {
1310		function = "SD2";
1311		groups = "SD2";
1312	};
1313
1314	pinctrl_sda1_default: sda1_default {
1315		function = "SDA1";
1316		groups = "SDA1";
1317	};
1318
1319	pinctrl_sda2_default: sda2_default {
1320		function = "SDA2";
1321		groups = "SDA2";
1322	};
1323
1324	pinctrl_sgps1_default: sgps1_default {
1325		function = "SGPS1";
1326		groups = "SGPS1";
1327	};
1328
1329	pinctrl_sgps2_default: sgps2_default {
1330		function = "SGPS2";
1331		groups = "SGPS2";
1332	};
1333
1334	pinctrl_sioonctrl_default: sioonctrl_default {
1335		function = "SIOONCTRL";
1336		groups = "SIOONCTRL";
1337	};
1338
1339	pinctrl_siopbi_default: siopbi_default {
1340		function = "SIOPBI";
1341		groups = "SIOPBI";
1342	};
1343
1344	pinctrl_siopbo_default: siopbo_default {
1345		function = "SIOPBO";
1346		groups = "SIOPBO";
1347	};
1348
1349	pinctrl_siopwreq_default: siopwreq_default {
1350		function = "SIOPWREQ";
1351		groups = "SIOPWREQ";
1352	};
1353
1354	pinctrl_siopwrgd_default: siopwrgd_default {
1355		function = "SIOPWRGD";
1356		groups = "SIOPWRGD";
1357	};
1358
1359	pinctrl_sios3_default: sios3_default {
1360		function = "SIOS3";
1361		groups = "SIOS3";
1362	};
1363
1364	pinctrl_sios5_default: sios5_default {
1365		function = "SIOS5";
1366		groups = "SIOS5";
1367	};
1368
1369	pinctrl_siosci_default: siosci_default {
1370		function = "SIOSCI";
1371		groups = "SIOSCI";
1372	};
1373
1374	pinctrl_spi1_default: spi1_default {
1375		function = "SPI1";
1376		groups = "SPI1";
1377	};
1378
1379	pinctrl_spi1cs1_default: spi1cs1_default {
1380		function = "SPI1CS1";
1381		groups = "SPI1CS1";
1382	};
1383
1384	pinctrl_spi1debug_default: spi1debug_default {
1385		function = "SPI1DEBUG";
1386		groups = "SPI1DEBUG";
1387	};
1388
1389	pinctrl_spi1passthru_default: spi1passthru_default {
1390		function = "SPI1PASSTHRU";
1391		groups = "SPI1PASSTHRU";
1392	};
1393
1394	pinctrl_spi2ck_default: spi2ck_default {
1395		function = "SPI2CK";
1396		groups = "SPI2CK";
1397	};
1398
1399	pinctrl_spi2cs0_default: spi2cs0_default {
1400		function = "SPI2CS0";
1401		groups = "SPI2CS0";
1402	};
1403
1404	pinctrl_spi2cs1_default: spi2cs1_default {
1405		function = "SPI2CS1";
1406		groups = "SPI2CS1";
1407	};
1408
1409	pinctrl_spi2miso_default: spi2miso_default {
1410		function = "SPI2MISO";
1411		groups = "SPI2MISO";
1412	};
1413
1414	pinctrl_spi2mosi_default: spi2mosi_default {
1415		function = "SPI2MOSI";
1416		groups = "SPI2MOSI";
1417	};
1418
1419	pinctrl_timer3_default: timer3_default {
1420		function = "TIMER3";
1421		groups = "TIMER3";
1422	};
1423
1424	pinctrl_timer4_default: timer4_default {
1425		function = "TIMER4";
1426		groups = "TIMER4";
1427	};
1428
1429	pinctrl_timer5_default: timer5_default {
1430		function = "TIMER5";
1431		groups = "TIMER5";
1432	};
1433
1434	pinctrl_timer6_default: timer6_default {
1435		function = "TIMER6";
1436		groups = "TIMER6";
1437	};
1438
1439	pinctrl_timer7_default: timer7_default {
1440		function = "TIMER7";
1441		groups = "TIMER7";
1442	};
1443
1444	pinctrl_timer8_default: timer8_default {
1445		function = "TIMER8";
1446		groups = "TIMER8";
1447	};
1448
1449	pinctrl_txd1_default: txd1_default {
1450		function = "TXD1";
1451		groups = "TXD1";
1452	};
1453
1454	pinctrl_txd2_default: txd2_default {
1455		function = "TXD2";
1456		groups = "TXD2";
1457	};
1458
1459	pinctrl_txd3_default: txd3_default {
1460		function = "TXD3";
1461		groups = "TXD3";
1462	};
1463
1464	pinctrl_txd4_default: txd4_default {
1465		function = "TXD4";
1466		groups = "TXD4";
1467	};
1468
1469	pinctrl_uart6_default: uart6_default {
1470		function = "UART6";
1471		groups = "UART6";
1472	};
1473
1474	pinctrl_usbcki_default: usbcki_default {
1475		function = "USBCKI";
1476		groups = "USBCKI";
1477	};
1478
1479	pinctrl_usb2ah_default: usb2ah_default {
1480		function = "USB2AH";
1481		groups = "USB2AH";
1482	};
1483
1484	pinctrl_usb2ad_default: usb2ad_default {
1485		function = "USB2AD";
1486		groups = "USB2AD";
1487	};
1488
1489	pinctrl_usb11bhid_default: usb11bhid_default {
1490		function = "USB11BHID";
1491		groups = "USB11BHID";
1492	};
1493
1494	pinctrl_usb2bh_default: usb2bh_default {
1495		function = "USB2BH";
1496		groups = "USB2BH";
1497	};
1498
1499	pinctrl_vgabiosrom_default: vgabiosrom_default {
1500		function = "VGABIOSROM";
1501		groups = "VGABIOSROM";
1502	};
1503
1504	pinctrl_vgahs_default: vgahs_default {
1505		function = "VGAHS";
1506		groups = "VGAHS";
1507	};
1508
1509	pinctrl_vgavs_default: vgavs_default {
1510		function = "VGAVS";
1511		groups = "VGAVS";
1512	};
1513
1514	pinctrl_vpi24_default: vpi24_default {
1515		function = "VPI24";
1516		groups = "VPI24";
1517	};
1518
1519	pinctrl_vpo_default: vpo_default {
1520		function = "VPO";
1521		groups = "VPO";
1522	};
1523
1524	pinctrl_wdtrst1_default: wdtrst1_default {
1525		function = "WDTRST1";
1526		groups = "WDTRST1";
1527	};
1528
1529	pinctrl_wdtrst2_default: wdtrst2_default {
1530		function = "WDTRST2";
1531		groups = "WDTRST2";
1532	};
1533};
1534