1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4412 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 *		http://www.samsung.com
7 *
8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
14 * nodes can be added to this file.
15 */
16
17#include "exynos4.dtsi"
18
19#include "exynos4-cpu-thermal.dtsi"
20
21/ {
22	compatible = "samsung,exynos4412", "samsung,exynos4";
23
24	aliases {
25		pinctrl0 = &pinctrl_0;
26		pinctrl1 = &pinctrl_1;
27		pinctrl2 = &pinctrl_2;
28		pinctrl3 = &pinctrl_3;
29		fimc-lite0 = &fimc_lite_0;
30		fimc-lite1 = &fimc_lite_1;
31	};
32
33	bus_acp: bus-acp {
34		compatible = "samsung,exynos-bus";
35		clocks = <&clock CLK_DIV_ACP>;
36		clock-names = "bus";
37		operating-points-v2 = <&bus_acp_opp_table>;
38		status = "disabled";
39
40		bus_acp_opp_table: opp-table {
41			compatible = "operating-points-v2";
42
43			opp-100000000 {
44				opp-hz = /bits/ 64 <100000000>;
45			};
46			opp-134000000 {
47				opp-hz = /bits/ 64 <134000000>;
48			};
49			opp-160000000 {
50				opp-hz = /bits/ 64 <160000000>;
51			};
52			opp-267000000 {
53				opp-hz = /bits/ 64 <267000000>;
54			};
55		};
56	};
57
58	bus_c2c: bus-c2c {
59		compatible = "samsung,exynos-bus";
60		clocks = <&clock CLK_DIV_C2C>;
61		clock-names = "bus";
62		operating-points-v2 = <&bus_dmc_opp_table>;
63		status = "disabled";
64	};
65
66	bus_dmc: bus-dmc {
67		compatible = "samsung,exynos-bus";
68		clocks = <&clock CLK_DIV_DMC>;
69		clock-names = "bus";
70		operating-points-v2 = <&bus_dmc_opp_table>;
71		samsung,data-clock-ratio = <4>;
72		#interconnect-cells = <0>;
73		status = "disabled";
74	};
75
76	bus_display: bus-display {
77		compatible = "samsung,exynos-bus";
78		clocks = <&clock CLK_ACLK160>;
79		clock-names = "bus";
80		operating-points-v2 = <&bus_display_opp_table>;
81		interconnects = <&bus_leftbus &bus_dmc>;
82		#interconnect-cells = <0>;
83		status = "disabled";
84
85		bus_display_opp_table: opp-table {
86			compatible = "operating-points-v2";
87
88			opp-160000000 {
89				opp-hz = /bits/ 64 <160000000>;
90			};
91			opp-200000000 {
92				opp-hz = /bits/ 64 <200000000>;
93			};
94		};
95	};
96
97	bus_fsys: bus-fsys {
98		compatible = "samsung,exynos-bus";
99		clocks = <&clock CLK_ACLK133>;
100		clock-names = "bus";
101		operating-points-v2 = <&bus_fsys_opp_table>;
102		status = "disabled";
103
104		bus_fsys_opp_table: opp-table {
105			compatible = "operating-points-v2";
106
107			opp-100000000 {
108				opp-hz = /bits/ 64 <100000000>;
109			};
110			opp-134000000 {
111				opp-hz = /bits/ 64 <134000000>;
112			};
113		};
114	};
115
116	bus_leftbus: bus-leftbus {
117		compatible = "samsung,exynos-bus";
118		clocks = <&clock CLK_DIV_GDL>;
119		clock-names = "bus";
120		operating-points-v2 = <&bus_leftbus_opp_table>;
121		interconnects = <&bus_dmc>;
122		#interconnect-cells = <0>;
123		status = "disabled";
124	};
125
126	bus_mfc: bus-mfc {
127		compatible = "samsung,exynos-bus";
128		clocks = <&clock CLK_SCLK_MFC>;
129		clock-names = "bus";
130		operating-points-v2 = <&bus_leftbus_opp_table>;
131		status = "disabled";
132	};
133
134	bus_peri: bus-peri {
135		compatible = "samsung,exynos-bus";
136		clocks = <&clock CLK_ACLK100>;
137		clock-names = "bus";
138		operating-points-v2 = <&bus_peri_opp_table>;
139		status = "disabled";
140
141		bus_peri_opp_table: opp-table {
142			compatible = "operating-points-v2";
143
144			opp-50000000 {
145				opp-hz = /bits/ 64 <50000000>;
146			};
147			opp-100000000 {
148				opp-hz = /bits/ 64 <100000000>;
149			};
150		};
151	};
152
153	bus_rightbus: bus-rightbus {
154		compatible = "samsung,exynos-bus";
155		clocks = <&clock CLK_DIV_GDR>;
156		clock-names = "bus";
157		operating-points-v2 = <&bus_leftbus_opp_table>;
158		status = "disabled";
159	};
160
161	cpus {
162		#address-cells = <1>;
163		#size-cells = <0>;
164
165		cpu-map {
166			cluster0 {
167				core0 {
168					cpu = <&cpu0>;
169				};
170				core1 {
171					cpu = <&cpu1>;
172				};
173				core2 {
174					cpu = <&cpu2>;
175				};
176				core3 {
177					cpu = <&cpu3>;
178				};
179			};
180		};
181
182		cpu0: cpu@a00 {
183			device_type = "cpu";
184			compatible = "arm,cortex-a9";
185			reg = <0xa00>;
186			clocks = <&clock CLK_ARM_CLK>;
187			clock-names = "cpu";
188			operating-points-v2 = <&cpu0_opp_table>;
189			#cooling-cells = <2>; /* min followed by max */
190		};
191
192		cpu1: cpu@a01 {
193			device_type = "cpu";
194			compatible = "arm,cortex-a9";
195			reg = <0xa01>;
196			clocks = <&clock CLK_ARM_CLK>;
197			clock-names = "cpu";
198			operating-points-v2 = <&cpu0_opp_table>;
199			#cooling-cells = <2>; /* min followed by max */
200		};
201
202		cpu2: cpu@a02 {
203			device_type = "cpu";
204			compatible = "arm,cortex-a9";
205			reg = <0xa02>;
206			clocks = <&clock CLK_ARM_CLK>;
207			clock-names = "cpu";
208			operating-points-v2 = <&cpu0_opp_table>;
209			#cooling-cells = <2>; /* min followed by max */
210		};
211
212		cpu3: cpu@a03 {
213			device_type = "cpu";
214			compatible = "arm,cortex-a9";
215			reg = <0xa03>;
216			clocks = <&clock CLK_ARM_CLK>;
217			clock-names = "cpu";
218			operating-points-v2 = <&cpu0_opp_table>;
219			#cooling-cells = <2>; /* min followed by max */
220		};
221	};
222
223	cpu0_opp_table: opp-table-0 {
224		compatible = "operating-points-v2";
225		opp-shared;
226
227		opp-200000000 {
228			opp-hz = /bits/ 64 <200000000>;
229			opp-microvolt = <900000>;
230			clock-latency-ns = <200000>;
231		};
232		opp-300000000 {
233			opp-hz = /bits/ 64 <300000000>;
234			opp-microvolt = <900000>;
235			clock-latency-ns = <200000>;
236		};
237		opp-400000000 {
238			opp-hz = /bits/ 64 <400000000>;
239			opp-microvolt = <925000>;
240			clock-latency-ns = <200000>;
241		};
242		opp-500000000 {
243			opp-hz = /bits/ 64 <500000000>;
244			opp-microvolt = <950000>;
245			clock-latency-ns = <200000>;
246		};
247		opp-600000000 {
248			opp-hz = /bits/ 64 <600000000>;
249			opp-microvolt = <975000>;
250			clock-latency-ns = <200000>;
251		};
252		opp-700000000 {
253			opp-hz = /bits/ 64 <700000000>;
254			opp-microvolt = <987500>;
255			clock-latency-ns = <200000>;
256		};
257		opp-800000000 {
258			opp-hz = /bits/ 64 <800000000>;
259			opp-microvolt = <1000000>;
260			clock-latency-ns = <200000>;
261			opp-suspend;
262		};
263		opp-900000000 {
264			opp-hz = /bits/ 64 <900000000>;
265			opp-microvolt = <1037500>;
266			clock-latency-ns = <200000>;
267		};
268		opp-1000000000 {
269			opp-hz = /bits/ 64 <1000000000>;
270			opp-microvolt = <1087500>;
271			clock-latency-ns = <200000>;
272		};
273		opp-1100000000 {
274			opp-hz = /bits/ 64 <1100000000>;
275			opp-microvolt = <1137500>;
276			clock-latency-ns = <200000>;
277		};
278		opp-1200000000 {
279			opp-hz = /bits/ 64 <1200000000>;
280			opp-microvolt = <1187500>;
281			clock-latency-ns = <200000>;
282		};
283		opp-1300000000 {
284			opp-hz = /bits/ 64 <1300000000>;
285			opp-microvolt = <1250000>;
286			clock-latency-ns = <200000>;
287		};
288		opp-1400000000 {
289			opp-hz = /bits/ 64 <1400000000>;
290			opp-microvolt = <1287500>;
291			clock-latency-ns = <200000>;
292		};
293		cpu0_opp_1500: opp-1500000000 {
294			opp-hz = /bits/ 64 <1500000000>;
295			opp-microvolt = <1350000>;
296			clock-latency-ns = <200000>;
297			turbo-mode;
298		};
299	};
300
301	bus_dmc_opp_table: opp-table-1 {
302		compatible = "operating-points-v2";
303
304		opp-100000000 {
305			opp-hz = /bits/ 64 <100000000>;
306			opp-microvolt = <900000>;
307		};
308		opp-134000000 {
309			opp-hz = /bits/ 64 <134000000>;
310			opp-microvolt = <900000>;
311		};
312		opp-160000000 {
313			opp-hz = /bits/ 64 <160000000>;
314			opp-microvolt = <900000>;
315		};
316		opp-267000000 {
317			opp-hz = /bits/ 64 <267000000>;
318			opp-microvolt = <950000>;
319		};
320		opp-400000000 {
321			opp-hz = /bits/ 64 <400000000>;
322			opp-microvolt = <1050000>;
323			opp-suspend;
324		};
325	};
326
327	bus_leftbus_opp_table: opp-table-2 {
328		compatible = "operating-points-v2";
329
330		opp-100000000 {
331			opp-hz = /bits/ 64 <100000000>;
332			opp-microvolt = <900000>;
333		};
334		opp-134000000 {
335			opp-hz = /bits/ 64 <134000000>;
336			opp-microvolt = <925000>;
337		};
338		opp-160000000 {
339			opp-hz = /bits/ 64 <160000000>;
340			opp-microvolt = <950000>;
341		};
342		opp-200000000 {
343			opp-hz = /bits/ 64 <200000000>;
344			opp-microvolt = <1000000>;
345			opp-suspend;
346		};
347	};
348
349	soc: soc {
350
351		pinctrl_0: pinctrl@11400000 {
352			compatible = "samsung,exynos4x12-pinctrl";
353			reg = <0x11400000 0x1000>;
354			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
355		};
356
357		pinctrl_1: pinctrl@11000000 {
358			compatible = "samsung,exynos4x12-pinctrl";
359			reg = <0x11000000 0x1000>;
360			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
361
362			wakup_eint: wakeup-interrupt-controller {
363				compatible = "samsung,exynos4210-wakeup-eint";
364				interrupt-parent = <&gic>;
365				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
366			};
367		};
368
369		pinctrl_2: pinctrl@3860000 {
370			compatible = "samsung,exynos4x12-pinctrl";
371			reg = <0x03860000 0x1000>;
372			interrupt-parent = <&combiner>;
373			interrupts = <10 0>;
374		};
375
376		pinctrl_3: pinctrl@106e0000 {
377			compatible = "samsung,exynos4x12-pinctrl";
378			reg = <0x106e0000 0x1000>;
379			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
380		};
381
382		sram@2020000 {
383			compatible = "mmio-sram";
384			reg = <0x02020000 0x40000>;
385			#address-cells = <1>;
386			#size-cells = <1>;
387			ranges = <0 0x02020000 0x40000>;
388
389			smp-sram@0 {
390				compatible = "samsung,exynos4210-sysram";
391				reg = <0x0 0x1000>;
392			};
393
394			smp-sram@2f000 {
395				compatible = "samsung,exynos4210-sysram-ns";
396				reg = <0x2f000 0x1000>;
397			};
398		};
399
400		pd_isp: power-domain@10023ca0 {
401			compatible = "samsung,exynos4210-pd";
402			reg = <0x10023ca0 0x20>;
403			#power-domain-cells = <0>;
404			label = "ISP";
405		};
406
407		l2c: cache-controller@10502000 {
408			compatible = "arm,pl310-cache";
409			reg = <0x10502000 0x1000>;
410			cache-unified;
411			cache-level = <2>;
412			prefetch-data = <1>;
413			prefetch-instr = <1>;
414			arm,tag-latency = <2 2 1>;
415			arm,data-latency = <3 2 1>;
416			arm,double-linefill = <1>;
417			arm,double-linefill-incr = <0>;
418			arm,double-linefill-wrap = <1>;
419			arm,prefetch-drop = <1>;
420			arm,prefetch-offset = <7>;
421		};
422
423		clock: clock-controller@10030000 {
424			compatible = "samsung,exynos4412-clock";
425			reg = <0x10030000 0x18000>;
426			#clock-cells = <1>;
427		};
428
429		isp_clock: clock-controller@10048000 {
430			compatible = "samsung,exynos4412-isp-clock";
431			reg = <0x10048000 0x1000>;
432			#clock-cells = <1>;
433			power-domains = <&pd_isp>;
434			clocks = <&clock CLK_ACLK200>,
435				 <&clock CLK_ACLK400_MCUISP>;
436			clock-names = "aclk200", "aclk400_mcuisp";
437		};
438
439		timer@10050000 {
440			compatible = "samsung,exynos4412-mct";
441			reg = <0x10050000 0x800>;
442			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
443			clock-names = "fin_pll", "mct";
444			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
445					      <&combiner 12 5>,
446					      <&combiner 12 6>,
447					      <&combiner 12 7>,
448					      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
449		};
450
451		watchdog: watchdog@10060000 {
452			compatible = "samsung,exynos5250-wdt";
453			reg = <0x10060000 0x100>;
454			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
455			clocks = <&clock CLK_WDT>;
456			clock-names = "watchdog";
457			samsung,syscon-phandle = <&pmu_system_controller>;
458		};
459
460		adc: adc@126c0000 {
461			compatible = "samsung,exynos4212-adc";
462			reg = <0x126c0000 0x100>;
463			interrupt-parent = <&combiner>;
464			interrupts = <10 3>;
465			clocks = <&clock CLK_TSADC>;
466			clock-names = "adc";
467			#io-channel-cells = <1>;
468			samsung,syscon-phandle = <&pmu_system_controller>;
469			status = "disabled";
470		};
471
472		g2d: g2d@10800000 {
473			compatible = "samsung,exynos4212-g2d";
474			reg = <0x10800000 0x1000>;
475			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
476			clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
477			clock-names = "sclk_fimg2d", "fimg2d";
478			iommus = <&sysmmu_g2d>;
479		};
480
481		mshc_0: mmc@12550000 {
482			compatible = "samsung,exynos4412-dw-mshc";
483			reg = <0x12550000 0x1000>;
484			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
485			#address-cells = <1>;
486			#size-cells = <0>;
487			fifo-depth = <0x80>;
488			clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
489			clock-names = "biu", "ciu";
490			status = "disabled";
491		};
492
493		sysmmu_g2d: sysmmu@10a40000 {
494			compatible = "samsung,exynos-sysmmu";
495			reg = <0x10a40000 0x1000>;
496			interrupt-parent = <&combiner>;
497			interrupts = <4 7>;
498			clock-names = "sysmmu", "master";
499			clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
500			#iommu-cells = <0>;
501		};
502
503		sysmmu_fimc_isp: sysmmu@12260000 {
504			compatible = "samsung,exynos-sysmmu";
505			reg = <0x12260000 0x1000>;
506			interrupt-parent = <&combiner>;
507			interrupts = <16 2>;
508			power-domains = <&pd_isp>;
509			clock-names = "sysmmu";
510			clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
511			#iommu-cells = <0>;
512		};
513
514		sysmmu_fimc_drc: sysmmu@12270000 {
515			compatible = "samsung,exynos-sysmmu";
516			reg = <0x12270000 0x1000>;
517			interrupt-parent = <&combiner>;
518			interrupts = <16 3>;
519			power-domains = <&pd_isp>;
520			clock-names = "sysmmu";
521			clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
522			#iommu-cells = <0>;
523		};
524
525		sysmmu_fimc_fd: sysmmu@122a0000 {
526			compatible = "samsung,exynos-sysmmu";
527			reg = <0x122a0000 0x1000>;
528			interrupt-parent = <&combiner>;
529			interrupts = <16 4>;
530			power-domains = <&pd_isp>;
531			clock-names = "sysmmu";
532			clocks = <&isp_clock CLK_ISP_SMMU_FD>;
533			#iommu-cells = <0>;
534		};
535
536		sysmmu_fimc_mcuctl: sysmmu@122b0000 {
537			compatible = "samsung,exynos-sysmmu";
538			reg = <0x122b0000 0x1000>;
539			interrupt-parent = <&combiner>;
540			interrupts = <16 5>;
541			power-domains = <&pd_isp>;
542			clock-names = "sysmmu";
543			clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
544			#iommu-cells = <0>;
545		};
546
547		sysmmu_fimc_lite0: sysmmu@123b0000 {
548			compatible = "samsung,exynos-sysmmu";
549			reg = <0x123b0000 0x1000>;
550			interrupt-parent = <&combiner>;
551			interrupts = <16 0>;
552			power-domains = <&pd_isp>;
553			clock-names = "sysmmu", "master";
554			clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
555				 <&isp_clock CLK_ISP_FIMC_LITE0>;
556			#iommu-cells = <0>;
557		};
558
559		sysmmu_fimc_lite1: sysmmu@123c0000 {
560			compatible = "samsung,exynos-sysmmu";
561			reg = <0x123c0000 0x1000>;
562			interrupt-parent = <&combiner>;
563			interrupts = <16 1>;
564			power-domains = <&pd_isp>;
565			clock-names = "sysmmu", "master";
566			clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
567				 <&isp_clock CLK_ISP_FIMC_LITE1>;
568			#iommu-cells = <0>;
569		};
570	};
571};
572
573&combiner {
574	samsung,combiner-nr = <20>;
575	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
576		     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
577		     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
578		     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
579		     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
580		     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
581		     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
582		     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
583		     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
584		     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
585		     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
586		     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
587		     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
588		     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
589		     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
590		     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
591		     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
592		     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
593		     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
594		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
595};
596
597&camera {
598	clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
599		 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
600	clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
601
602	/* fimc_[0-3] are configured outside, under phandles */
603	fimc_lite_0: fimc-lite@12390000 {
604		compatible = "samsung,exynos4212-fimc-lite";
605		reg = <0x12390000 0x1000>;
606		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
607		power-domains = <&pd_isp>;
608		clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
609		clock-names = "flite";
610		iommus = <&sysmmu_fimc_lite0>;
611		status = "disabled";
612	};
613
614	fimc_lite_1: fimc-lite@123a0000 {
615		compatible = "samsung,exynos4212-fimc-lite";
616		reg = <0x123a0000 0x1000>;
617		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
618		power-domains = <&pd_isp>;
619		clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
620		clock-names = "flite";
621		iommus = <&sysmmu_fimc_lite1>;
622		status = "disabled";
623	};
624
625	fimc_is: fimc-is@12000000 {
626		compatible = "samsung,exynos4212-fimc-is";
627		reg = <0x12000000 0x260000>;
628		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
629			     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
630		power-domains = <&pd_isp>;
631		clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
632			 <&isp_clock CLK_ISP_FIMC_LITE1>,
633			 <&isp_clock CLK_ISP_PPMUISPX>,
634			 <&isp_clock CLK_ISP_PPMUISPMX>,
635			 <&isp_clock CLK_ISP_FIMC_ISP>,
636			 <&isp_clock CLK_ISP_FIMC_DRC>,
637			 <&isp_clock CLK_ISP_FIMC_FD>,
638			 <&isp_clock CLK_ISP_MCUISP>,
639			 <&isp_clock CLK_ISP_GICISP>,
640			 <&isp_clock CLK_ISP_MCUCTL_ISP>,
641			 <&isp_clock CLK_ISP_PWM_ISP>,
642			 <&isp_clock CLK_ISP_DIV_ISP0>,
643			 <&isp_clock CLK_ISP_DIV_ISP1>,
644			 <&isp_clock CLK_ISP_DIV_MCUISP0>,
645			 <&isp_clock CLK_ISP_DIV_MCUISP1>,
646			 <&clock CLK_MOUT_MPLL_USER_T>,
647			 <&clock CLK_ACLK200>,
648			 <&clock CLK_ACLK400_MCUISP>,
649			 <&clock CLK_DIV_ACLK200>,
650			 <&clock CLK_DIV_ACLK400_MCUISP>,
651			 <&clock CLK_UART_ISP_SCLK>;
652		clock-names = "lite0", "lite1", "ppmuispx",
653			      "ppmuispmx", "isp",
654			      "drc", "fd", "mcuisp",
655			      "gicisp", "mcuctl_isp", "pwm_isp",
656			      "ispdiv0", "ispdiv1", "mcuispdiv0",
657			      "mcuispdiv1", "mpll", "aclk200",
658			      "aclk400mcuisp", "div_aclk200",
659			      "div_aclk400mcuisp", "uart";
660		iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
661			 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
662		iommu-names = "isp", "drc", "fd", "mcuctl";
663		#address-cells = <1>;
664		#size-cells = <1>;
665		ranges;
666		status = "disabled";
667
668		pmu@10020000 {
669			reg = <0x10020000 0x3000>;
670		};
671
672		i2c1_isp: i2c-isp@12140000 {
673			compatible = "samsung,exynos4212-i2c-isp";
674			reg = <0x12140000 0x100>;
675			clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
676			clock-names = "i2c_isp";
677			#address-cells = <1>;
678			#size-cells = <0>;
679		};
680	};
681};
682
683&exynos_usbphy {
684	compatible = "samsung,exynos4x12-usb2-phy";
685	samsung,sysreg-phandle = <&sys_reg>;
686};
687
688&fimc_0 {
689	compatible = "samsung,exynos4212-fimc";
690	samsung,pix-limits = <4224 8192 1920 4224>;
691	samsung,mainscaler-ext;
692	samsung,isp-wb;
693	samsung,cam-if;
694};
695
696&fimc_1 {
697	compatible = "samsung,exynos4212-fimc";
698	samsung,pix-limits = <4224 8192 1920 4224>;
699	samsung,mainscaler-ext;
700	samsung,isp-wb;
701	samsung,cam-if;
702};
703
704&fimc_2 {
705	compatible = "samsung,exynos4212-fimc";
706	samsung,pix-limits = <4224 8192 1920 4224>;
707	samsung,mainscaler-ext;
708	samsung,isp-wb;
709	samsung,lcd-wb;
710	samsung,cam-if;
711};
712
713&fimc_3 {
714	compatible = "samsung,exynos4212-fimc";
715	samsung,pix-limits = <1920 8192 1366 1920>;
716	samsung,rotators = <0>;
717	samsung,mainscaler-ext;
718	samsung,isp-wb;
719	samsung,lcd-wb;
720};
721
722&gic {
723	cpu-offset = <0x4000>;
724};
725
726&gpu {
727	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
728		     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
729		     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
730		     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
731		     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
732		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
733		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
734		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
735		     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
736		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
737		     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
738	interrupt-names = "gp",
739			  "gpmmu",
740			  "pp0",
741			  "ppmmu0",
742			  "pp1",
743			  "ppmmu1",
744			  "pp2",
745			  "ppmmu2",
746			  "pp3",
747			  "ppmmu3",
748			  "pmu";
749	operating-points-v2 = <&gpu_opp_table>;
750
751	gpu_opp_table: opp-table {
752		compatible = "operating-points-v2";
753
754		opp-160000000 {
755			opp-hz = /bits/ 64 <160000000>;
756			opp-microvolt = <875000>;
757		};
758		opp-267000000 {
759			opp-hz = /bits/ 64 <267000000>;
760			opp-microvolt = <900000>;
761		};
762		opp-350000000 {
763			opp-hz = /bits/ 64 <350000000>;
764			opp-microvolt = <950000>;
765		};
766		opp-440000000 {
767			opp-hz = /bits/ 64 <440000000>;
768			opp-microvolt = <1025000>;
769		};
770	};
771};
772
773&hdmi {
774	compatible = "samsung,exynos4212-hdmi";
775};
776
777&jpeg_codec {
778	compatible = "samsung,exynos4212-jpeg";
779};
780
781&rotator {
782	compatible = "samsung,exynos4212-rotator";
783};
784
785&mixer {
786	compatible = "samsung,exynos4212-mixer";
787	clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
788	clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
789		 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
790	interconnects = <&bus_display &bus_dmc>;
791};
792
793&pmu {
794	interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
795	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
796	status = "okay";
797};
798
799&pmu_system_controller {
800	compatible = "samsung,exynos4412-pmu", "simple-mfd", "syscon";
801	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
802			"clkout4", "clkout8", "clkout9";
803	clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
804		<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
805		<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
806	#clock-cells = <1>;
807};
808
809&tmu {
810	compatible = "samsung,exynos4412-tmu";
811	interrupt-parent = <&combiner>;
812	interrupts = <2 4>;
813	reg = <0x100c0000 0x100>;
814	clocks = <&clock CLK_TMU_APBIF>;
815	clock-names = "tmu_apbif";
816	status = "disabled";
817};
818
819#include "exynos4412-pinctrl.dtsi"
820