1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
3 */
4
5 #include <sys/queue.h>
6 #include <stdio.h>
7 #include <errno.h>
8 #include <stdint.h>
9 #include <string.h>
10 #include <unistd.h>
11 #include <stdarg.h>
12 #include <inttypes.h>
13
14 #include <rte_string_fns.h>
15 #include <rte_pci.h>
16 #include <rte_ether.h>
17 #include <ethdev_driver.h>
18 #include <rte_malloc.h>
19 #include <rte_memcpy.h>
20
21 #include "i40e_logs.h"
22 #include "base/i40e_prototype.h"
23 #include "base/i40e_adminq_cmd.h"
24 #include "base/i40e_type.h"
25 #include "i40e_ethdev.h"
26 #include "i40e_rxtx.h"
27 #include "i40e_pf.h"
28 #include "rte_pmd_i40e.h"
29
30 #define I40E_CFG_CRCSTRIP_DEFAULT 1
31
32 /* Supported RSS offloads */
33 #define I40E_DEFAULT_RSS_HENA ( \
34 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
35 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
36 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
37 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
38 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \
39 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
40 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
41 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
42 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
43 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \
44 BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))
45
46 #define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \
47 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
48 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
49 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
50 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
51 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
52 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
53
54 static int
55 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
56 struct virtchnl_queue_select *qsel,
57 bool on);
58
59 /**
60 * Bind PF queues with VSI and VF.
61 **/
62 static int
i40e_pf_vf_queues_mapping(struct i40e_pf_vf * vf)63 i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
64 {
65 int i;
66 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
67 uint16_t vsi_id = vf->vsi->vsi_id;
68 uint16_t vf_id = vf->vf_idx;
69 uint16_t nb_qps = vf->vsi->nb_qps;
70 uint16_t qbase = vf->vsi->base_queue;
71 uint16_t q1, q2;
72 uint32_t val;
73
74 /*
75 * VF should use scatter range queues. So, it needn't
76 * to set QBASE in this register.
77 */
78 i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vsi_id),
79 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
80
81 /* Set to enable VFLAN_QTABLE[] registers valid */
82 I40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),
83 I40E_VPLAN_MAPENA_TXRX_ENA_MASK);
84
85 /* map PF queues to VF */
86 for (i = 0; i < nb_qps; i++) {
87 val = ((qbase + i) & I40E_VPLAN_QTABLE_QINDEX_MASK);
88 I40E_WRITE_REG(hw, I40E_VPLAN_QTABLE(i, vf_id), val);
89 }
90
91 /* map PF queues to VSI */
92 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF / 2; i++) {
93 if (2 * i > nb_qps - 1)
94 q1 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
95 else
96 q1 = qbase + 2 * i;
97
98 if (2 * i + 1 > nb_qps - 1)
99 q2 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
100 else
101 q2 = qbase + 2 * i + 1;
102
103 val = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;
104 i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
105 }
106 I40E_WRITE_FLUSH(hw);
107
108 return I40E_SUCCESS;
109 }
110
111
112 /**
113 * Proceed VF reset operation.
114 */
115 int
i40e_pf_host_vf_reset(struct i40e_pf_vf * vf,bool do_hw_reset)116 i40e_pf_host_vf_reset(struct i40e_pf_vf *vf, bool do_hw_reset)
117 {
118 uint32_t val, i;
119 struct i40e_hw *hw;
120 struct i40e_pf *pf;
121 uint16_t vf_id, abs_vf_id, vf_msix_num;
122 int ret;
123 struct virtchnl_queue_select qsel;
124
125 if (vf == NULL)
126 return -EINVAL;
127
128 pf = vf->pf;
129 hw = I40E_PF_TO_HW(vf->pf);
130 vf_id = vf->vf_idx;
131 abs_vf_id = vf_id + hw->func_caps.vf_base_id;
132
133 /* Notify VF that we are in VFR progress */
134 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_INPROGRESS);
135
136 /*
137 * If require a SW VF reset, a VFLR interrupt will be generated,
138 * this function will be called again. To avoid it,
139 * disable interrupt first.
140 */
141 if (do_hw_reset) {
142 vf->state = I40E_VF_INRESET;
143 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
144 val |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;
145 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
146 I40E_WRITE_FLUSH(hw);
147 }
148
149 #define VFRESET_MAX_WAIT_CNT 100
150 /* Wait until VF reset is done */
151 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
152 rte_delay_us(10);
153 val = I40E_READ_REG(hw, I40E_VPGEN_VFRSTAT(vf_id));
154 if (val & I40E_VPGEN_VFRSTAT_VFRD_MASK)
155 break;
156 }
157
158 if (i >= VFRESET_MAX_WAIT_CNT) {
159 PMD_DRV_LOG(ERR, "VF reset timeout");
160 return -ETIMEDOUT;
161 }
162 /* This is not first time to do reset, do cleanup job first */
163 if (vf->vsi) {
164 /* Disable queues */
165 memset(&qsel, 0, sizeof(qsel));
166 for (i = 0; i < vf->vsi->nb_qps; i++)
167 qsel.rx_queues |= 1 << i;
168 qsel.tx_queues = qsel.rx_queues;
169 ret = i40e_pf_host_switch_queues(vf, &qsel, false);
170 if (ret != I40E_SUCCESS) {
171 PMD_DRV_LOG(ERR, "Disable VF queues failed");
172 return -EFAULT;
173 }
174
175 /* Disable VF interrupt setting */
176 vf_msix_num = hw->func_caps.num_msix_vectors_vf;
177 for (i = 0; i < vf_msix_num; i++) {
178 if (!i)
179 val = I40E_VFINT_DYN_CTL0(vf_id);
180 else
181 val = I40E_VFINT_DYN_CTLN(((vf_msix_num - 1) *
182 (vf_id)) + (i - 1));
183 I40E_WRITE_REG(hw, val, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
184 }
185 I40E_WRITE_FLUSH(hw);
186
187 /* remove VSI */
188 ret = i40e_vsi_release(vf->vsi);
189 if (ret != I40E_SUCCESS) {
190 PMD_DRV_LOG(ERR, "Release VSI failed");
191 return -EFAULT;
192 }
193 }
194
195 #define I40E_VF_PCI_ADDR 0xAA
196 #define I40E_VF_PEND_MASK 0x20
197 /* Check the pending transactions of this VF */
198 /* Use absolute VF id, refer to datasheet for details */
199 I40E_WRITE_REG(hw, I40E_PF_PCI_CIAA, I40E_VF_PCI_ADDR |
200 (abs_vf_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT));
201 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
202 rte_delay_us(1);
203 val = I40E_READ_REG(hw, I40E_PF_PCI_CIAD);
204 if ((val & I40E_VF_PEND_MASK) == 0)
205 break;
206 }
207
208 if (i >= VFRESET_MAX_WAIT_CNT) {
209 PMD_DRV_LOG(ERR, "Wait VF PCI transaction end timeout");
210 return -ETIMEDOUT;
211 }
212
213 /* Reset done, Set COMPLETE flag and clear reset bit */
214 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_COMPLETED);
215 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
216 val &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;
217 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
218 vf->reset_cnt++;
219 I40E_WRITE_FLUSH(hw);
220
221 /* Allocate resource again */
222 if (pf->floating_veb && pf->floating_veb_list[vf_id]) {
223 vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
224 NULL, vf->vf_idx);
225 } else {
226 vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
227 vf->pf->main_vsi, vf->vf_idx);
228 }
229
230 if (vf->vsi == NULL) {
231 PMD_DRV_LOG(ERR, "Add vsi failed");
232 return -EFAULT;
233 }
234
235 ret = i40e_pf_vf_queues_mapping(vf);
236 if (ret != I40E_SUCCESS) {
237 PMD_DRV_LOG(ERR, "queue mapping error");
238 i40e_vsi_release(vf->vsi);
239 return -EFAULT;
240 }
241
242 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), VIRTCHNL_VFR_VFACTIVE);
243
244 return ret;
245 }
246
247 int
i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf * vf,uint32_t opcode,uint32_t retval,uint8_t * msg,uint16_t msglen)248 i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf,
249 uint32_t opcode,
250 uint32_t retval,
251 uint8_t *msg,
252 uint16_t msglen)
253 {
254 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
255 uint16_t abs_vf_id = hw->func_caps.vf_base_id + vf->vf_idx;
256 int ret;
257
258 ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, opcode, retval,
259 msg, msglen, NULL);
260 if (ret) {
261 PMD_INIT_LOG(ERR, "Fail to send message to VF, err %u",
262 hw->aq.asq_last_status);
263 }
264
265 return ret;
266 }
267
268 static void
i40e_pf_host_process_cmd_version(struct i40e_pf_vf * vf,uint8_t * msg,bool b_op)269 i40e_pf_host_process_cmd_version(struct i40e_pf_vf *vf, uint8_t *msg,
270 bool b_op)
271 {
272 struct virtchnl_version_info info;
273
274 /* VF and PF drivers need to follow the Virtchnl definition, No matter
275 * it's DPDK or other kernel drivers.
276 * The original DPDK host specific feature
277 * like CFG_VLAN_PVID and CONFIG_VSI_QUEUES_EXT will not available.
278 */
279
280 info.major = VIRTCHNL_VERSION_MAJOR;
281 vf->version = *(struct virtchnl_version_info *)msg;
282 if (VF_IS_V10(&vf->version))
283 info.minor = VIRTCHNL_VERSION_MINOR_NO_VF_CAPS;
284 else
285 info.minor = VIRTCHNL_VERSION_MINOR;
286
287 if (b_op)
288 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_VERSION,
289 I40E_SUCCESS,
290 (uint8_t *)&info,
291 sizeof(info));
292 else
293 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_VERSION,
294 I40E_NOT_SUPPORTED,
295 (uint8_t *)&info,
296 sizeof(info));
297 }
298
299 static int
i40e_pf_host_process_cmd_reset_vf(struct i40e_pf_vf * vf)300 i40e_pf_host_process_cmd_reset_vf(struct i40e_pf_vf *vf)
301 {
302 i40e_pf_host_vf_reset(vf, 1);
303
304 /* No feedback will be sent to VF for VFLR */
305 return I40E_SUCCESS;
306 }
307
308 static int
i40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf * vf,uint8_t * msg,bool b_op)309 i40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf *vf, uint8_t *msg,
310 bool b_op)
311 {
312 struct virtchnl_vf_resource *vf_res = NULL;
313 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
314 uint32_t len = 0;
315 uint64_t default_hena = I40E_RSS_HENA_ALL;
316 int ret = I40E_SUCCESS;
317
318 if (!b_op) {
319 i40e_pf_host_send_msg_to_vf(vf,
320 VIRTCHNL_OP_GET_VF_RESOURCES,
321 I40E_NOT_SUPPORTED, NULL, 0);
322 return ret;
323 }
324
325 /* only have 1 VSI by default */
326 len = sizeof(struct virtchnl_vf_resource) +
327 I40E_DEFAULT_VF_VSI_NUM *
328 sizeof(struct virtchnl_vsi_resource);
329
330 vf_res = rte_zmalloc("i40e_vf_res", len, 0);
331 if (vf_res == NULL) {
332 PMD_DRV_LOG(ERR, "failed to allocate mem");
333 ret = I40E_ERR_NO_MEMORY;
334 vf_res = NULL;
335 len = 0;
336 goto send_msg;
337 }
338
339 if (VF_IS_V10(&vf->version)) /* doesn't support offload negotiate */
340 vf->request_caps = VIRTCHNL_VF_OFFLOAD_L2 |
341 VIRTCHNL_VF_OFFLOAD_VLAN;
342 else
343 vf->request_caps = *(uint32_t *)msg;
344
345 /* enable all RSS by default,
346 * doesn't support hena setting by virtchnl yet.
347 */
348 if (vf->request_caps & VIRTCHNL_VF_OFFLOAD_RSS_PF) {
349 I40E_WRITE_REG(hw, I40E_VFQF_HENA1(0, vf->vf_idx),
350 (uint32_t)default_hena);
351 I40E_WRITE_REG(hw, I40E_VFQF_HENA1(1, vf->vf_idx),
352 (uint32_t)(default_hena >> 32));
353 I40E_WRITE_FLUSH(hw);
354 }
355
356 vf_res->vf_cap_flags = vf->request_caps &
357 I40E_VIRTCHNL_OFFLOAD_CAPS;
358
359 if (vf->request_caps & VIRTCHNL_VF_OFFLOAD_REQ_QUEUES)
360 vf_res->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_REQ_QUEUES;
361
362 /* For X722, it supports write back on ITR
363 * without binding queue to interrupt vector.
364 */
365 if (hw->mac.type == I40E_MAC_X722)
366 vf_res->vf_cap_flags |= VIRTCHNL_VF_OFFLOAD_WB_ON_ITR;
367 vf_res->max_vectors = hw->func_caps.num_msix_vectors_vf;
368 vf_res->num_queue_pairs = vf->vsi->nb_qps;
369 vf_res->num_vsis = I40E_DEFAULT_VF_VSI_NUM;
370 vf_res->rss_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) * 4;
371 vf_res->rss_lut_size = (I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4;
372
373 /* Change below setting if PF host can support more VSIs for VF */
374 vf_res->vsi_res[0].vsi_type = VIRTCHNL_VSI_SRIOV;
375 vf_res->vsi_res[0].vsi_id = vf->vsi->vsi_id;
376 vf_res->vsi_res[0].num_queue_pairs = vf->vsi->nb_qps;
377 rte_ether_addr_copy(&vf->mac_addr,
378 (struct rte_ether_addr *)vf_res->vsi_res[0].default_mac_addr);
379
380 send_msg:
381 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_VF_RESOURCES,
382 ret, (uint8_t *)vf_res, len);
383 rte_free(vf_res);
384
385 return ret;
386 }
387
388 static int
i40e_pf_host_hmc_config_rxq(struct i40e_hw * hw,struct i40e_pf_vf * vf,struct virtchnl_rxq_info * rxq,uint8_t crcstrip)389 i40e_pf_host_hmc_config_rxq(struct i40e_hw *hw,
390 struct i40e_pf_vf *vf,
391 struct virtchnl_rxq_info *rxq,
392 uint8_t crcstrip)
393 {
394 int err = I40E_SUCCESS;
395 struct i40e_hmc_obj_rxq rx_ctx;
396 uint16_t abs_queue_id = vf->vsi->base_queue + rxq->queue_id;
397
398 /* Clear the context structure first */
399 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
400 rx_ctx.dbuff = rxq->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT;
401 rx_ctx.hbuff = rxq->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT;
402 rx_ctx.base = rxq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
403 rx_ctx.qlen = rxq->ring_len;
404 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
405 rx_ctx.dsize = 1;
406 #endif
407
408 if (rxq->splithdr_enabled) {
409 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
410 rx_ctx.dtype = i40e_header_split_enabled;
411 } else {
412 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
413 rx_ctx.dtype = i40e_header_split_none;
414 }
415 rx_ctx.rxmax = rxq->max_pkt_size;
416 rx_ctx.tphrdesc_ena = 1;
417 rx_ctx.tphwdesc_ena = 1;
418 rx_ctx.tphdata_ena = 1;
419 rx_ctx.tphhead_ena = 1;
420 rx_ctx.lrxqthresh = 2;
421 rx_ctx.crcstrip = crcstrip;
422 rx_ctx.l2tsel = 1;
423 rx_ctx.prefena = 1;
424
425 err = i40e_clear_lan_rx_queue_context(hw, abs_queue_id);
426 if (err != I40E_SUCCESS)
427 return err;
428 err = i40e_set_lan_rx_queue_context(hw, abs_queue_id, &rx_ctx);
429
430 return err;
431 }
432
433 static inline uint8_t
i40e_vsi_get_tc_of_queue(struct i40e_vsi * vsi,uint16_t queue_id)434 i40e_vsi_get_tc_of_queue(struct i40e_vsi *vsi,
435 uint16_t queue_id)
436 {
437 struct i40e_aqc_vsi_properties_data *info = &vsi->info;
438 uint16_t bsf, qp_idx;
439 uint8_t i;
440
441 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
442 if (vsi->enabled_tc & (1 << i)) {
443 qp_idx = rte_le_to_cpu_16((info->tc_mapping[i] &
444 I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
445 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT);
446 bsf = rte_le_to_cpu_16((info->tc_mapping[i] &
447 I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
448 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
449 if (queue_id >= qp_idx && queue_id < qp_idx + (1 << bsf))
450 return i;
451 }
452 }
453 return 0;
454 }
455
456 static int
i40e_pf_host_hmc_config_txq(struct i40e_hw * hw,struct i40e_pf_vf * vf,struct virtchnl_txq_info * txq)457 i40e_pf_host_hmc_config_txq(struct i40e_hw *hw,
458 struct i40e_pf_vf *vf,
459 struct virtchnl_txq_info *txq)
460 {
461 int err = I40E_SUCCESS;
462 struct i40e_hmc_obj_txq tx_ctx;
463 struct i40e_vsi *vsi = vf->vsi;
464 uint32_t qtx_ctl;
465 uint16_t abs_queue_id = vsi->base_queue + txq->queue_id;
466 uint8_t dcb_tc;
467
468 /* clear the context structure first */
469 memset(&tx_ctx, 0, sizeof(tx_ctx));
470 tx_ctx.base = txq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
471 tx_ctx.qlen = txq->ring_len;
472 dcb_tc = i40e_vsi_get_tc_of_queue(vsi, txq->queue_id);
473 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[dcb_tc]);
474 tx_ctx.head_wb_ena = txq->headwb_enabled;
475 tx_ctx.head_wb_addr = txq->dma_headwb_addr;
476
477 err = i40e_clear_lan_tx_queue_context(hw, abs_queue_id);
478 if (err != I40E_SUCCESS)
479 return err;
480
481 err = i40e_set_lan_tx_queue_context(hw, abs_queue_id, &tx_ctx);
482 if (err != I40E_SUCCESS)
483 return err;
484
485 /* bind queue with VF function, since TX/QX will appear in pair,
486 * so only has QTX_CTL to set.
487 */
488 qtx_ctl = (I40E_QTX_CTL_VF_QUEUE << I40E_QTX_CTL_PFVF_Q_SHIFT) |
489 ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
490 I40E_QTX_CTL_PF_INDX_MASK) |
491 (((vf->vf_idx + hw->func_caps.vf_base_id) <<
492 I40E_QTX_CTL_VFVM_INDX_SHIFT) &
493 I40E_QTX_CTL_VFVM_INDX_MASK);
494 I40E_WRITE_REG(hw, I40E_QTX_CTL(abs_queue_id), qtx_ctl);
495 I40E_WRITE_FLUSH(hw);
496
497 return I40E_SUCCESS;
498 }
499
500 static int
i40e_pf_host_process_cmd_config_vsi_queues(struct i40e_pf_vf * vf,uint8_t * msg,uint16_t msglen,bool b_op)501 i40e_pf_host_process_cmd_config_vsi_queues(struct i40e_pf_vf *vf,
502 uint8_t *msg,
503 uint16_t msglen,
504 bool b_op)
505 {
506 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
507 struct i40e_vsi *vsi = vf->vsi;
508 struct virtchnl_vsi_queue_config_info *vc_vqci =
509 (struct virtchnl_vsi_queue_config_info *)msg;
510 struct virtchnl_queue_pair_info *vc_qpi;
511 int i, ret = I40E_SUCCESS;
512
513 if (!b_op) {
514 i40e_pf_host_send_msg_to_vf(vf,
515 VIRTCHNL_OP_CONFIG_VSI_QUEUES,
516 I40E_NOT_SUPPORTED, NULL, 0);
517 return ret;
518 }
519
520 if (!msg || vc_vqci->num_queue_pairs > vsi->nb_qps ||
521 vc_vqci->num_queue_pairs > I40E_MAX_VSI_QP ||
522 msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci,
523 vc_vqci->num_queue_pairs)) {
524 PMD_DRV_LOG(ERR, "vsi_queue_config_info argument wrong");
525 ret = I40E_ERR_PARAM;
526 goto send_msg;
527 }
528
529 vc_qpi = vc_vqci->qpair;
530 for (i = 0; i < vc_vqci->num_queue_pairs; i++) {
531 if (vc_qpi[i].rxq.queue_id > vsi->nb_qps - 1 ||
532 vc_qpi[i].txq.queue_id > vsi->nb_qps - 1) {
533 ret = I40E_ERR_PARAM;
534 goto send_msg;
535 }
536
537 /*
538 * Apply VF RX queue setting to HMC.
539 * If the opcode is VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
540 * then the extra information of
541 * 'struct virtchnl_queue_pair_extra_info' is needed,
542 * otherwise set the last parameter to NULL.
543 */
544 if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpi[i].rxq,
545 I40E_CFG_CRCSTRIP_DEFAULT) != I40E_SUCCESS) {
546 PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
547 ret = I40E_ERR_PARAM;
548 goto send_msg;
549 }
550
551 /* Apply VF TX queue setting to HMC */
552 if (i40e_pf_host_hmc_config_txq(hw, vf,
553 &vc_qpi[i].txq) != I40E_SUCCESS) {
554 PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
555 ret = I40E_ERR_PARAM;
556 goto send_msg;
557 }
558 }
559
560 send_msg:
561 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_VSI_QUEUES,
562 ret, NULL, 0);
563
564 return ret;
565 }
566
567 static void
i40e_pf_config_irq_link_list(struct i40e_pf_vf * vf,struct virtchnl_vector_map * vvm)568 i40e_pf_config_irq_link_list(struct i40e_pf_vf *vf,
569 struct virtchnl_vector_map *vvm)
570 {
571 #define BITS_PER_CHAR 8
572 uint64_t linklistmap = 0, tempmap;
573 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
574 uint16_t qid;
575 bool b_first_q = true;
576 enum i40e_queue_type qtype;
577 uint16_t vector_id;
578 uint32_t reg, reg_idx;
579 uint16_t itr_idx = 0, i;
580
581 vector_id = vvm->vector_id;
582 /* setup the head */
583 if (!vector_id)
584 reg_idx = I40E_VPINT_LNKLST0(vf->vf_idx);
585 else
586 reg_idx = I40E_VPINT_LNKLSTN(
587 ((hw->func_caps.num_msix_vectors_vf - 1) * vf->vf_idx)
588 + (vector_id - 1));
589
590 if (vvm->rxq_map == 0 && vvm->txq_map == 0) {
591 I40E_WRITE_REG(hw, reg_idx,
592 I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK);
593 goto cfg_irq_done;
594 }
595
596 /* sort all rx and tx queues */
597 tempmap = vvm->rxq_map;
598 for (i = 0; i < sizeof(vvm->rxq_map) * BITS_PER_CHAR; i++) {
599 if (tempmap & 0x1)
600 linklistmap |= RTE_BIT64(2 * i);
601 tempmap >>= 1;
602 }
603
604 tempmap = vvm->txq_map;
605 for (i = 0; i < sizeof(vvm->txq_map) * BITS_PER_CHAR; i++) {
606 if (tempmap & 0x1)
607 linklistmap |= RTE_BIT64(2 * i + 1);
608 tempmap >>= 1;
609 }
610
611 /* Link all rx and tx queues into a chained list */
612 tempmap = linklistmap;
613 i = 0;
614 b_first_q = true;
615 do {
616 if (tempmap & 0x1) {
617 qtype = (enum i40e_queue_type)(i % 2);
618 qid = vf->vsi->base_queue + i / 2;
619 if (b_first_q) {
620 /* This is header */
621 b_first_q = false;
622 reg = ((qtype <<
623 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
624 | qid);
625 } else {
626 /* element in the link list */
627 reg = (vector_id) |
628 (qtype << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
629 (qid << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
630 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
631 (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
632 }
633 I40E_WRITE_REG(hw, reg_idx, reg);
634 /* find next register to program */
635 switch (qtype) {
636 case I40E_QUEUE_TYPE_RX:
637 reg_idx = I40E_QINT_RQCTL(qid);
638 itr_idx = vvm->rxitr_idx;
639 break;
640 case I40E_QUEUE_TYPE_TX:
641 reg_idx = I40E_QINT_TQCTL(qid);
642 itr_idx = vvm->txitr_idx;
643 break;
644 default:
645 break;
646 }
647 }
648 i++;
649 tempmap >>= 1;
650 } while (tempmap);
651
652 /* Terminate the link list */
653 reg = (vector_id) |
654 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
655 (0x7FF << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
656 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
657 (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
658 I40E_WRITE_REG(hw, reg_idx, reg);
659
660 cfg_irq_done:
661 I40E_WRITE_FLUSH(hw);
662 }
663
664 static int
i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf * vf,uint8_t * msg,uint16_t msglen,bool b_op)665 i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,
666 uint8_t *msg, uint16_t msglen,
667 bool b_op)
668 {
669 int ret = I40E_SUCCESS;
670 struct i40e_pf *pf = vf->pf;
671 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
672 struct virtchnl_irq_map_info *irqmap =
673 (struct virtchnl_irq_map_info *)msg;
674 struct virtchnl_vector_map *map;
675 int i;
676 uint16_t vector_id, itr_idx;
677 unsigned long qbit_max;
678
679 if (!b_op) {
680 i40e_pf_host_send_msg_to_vf(
681 vf,
682 VIRTCHNL_OP_CONFIG_IRQ_MAP,
683 I40E_NOT_SUPPORTED, NULL, 0);
684 return ret;
685 }
686
687 if (msg == NULL || msglen < sizeof(struct virtchnl_irq_map_info)) {
688 PMD_DRV_LOG(ERR, "buffer too short");
689 ret = I40E_ERR_PARAM;
690 goto send_msg;
691 }
692
693 /* PF host will support both DPDK VF or Linux VF driver, identify by
694 * number of vectors requested.
695 */
696
697 /* DPDK VF only requires single vector */
698 if (irqmap->num_vectors == 1) {
699 /* This MSIX intr store the intr in VF range */
700 vf->vsi->msix_intr = irqmap->vecmap[0].vector_id;
701 vf->vsi->nb_msix = irqmap->num_vectors;
702 vf->vsi->nb_used_qps = vf->vsi->nb_qps;
703 itr_idx = irqmap->vecmap[0].rxitr_idx;
704
705 /* Don't care how the TX/RX queue mapping with this vector.
706 * Link all VF RX queues together. Only did mapping work.
707 * VF can disable/enable the intr by itself.
708 */
709 i40e_vsi_queues_bind_intr(vf->vsi, itr_idx);
710 goto send_msg;
711 }
712
713 /* Then, it's Linux VF driver */
714 qbit_max = 1 << pf->vf_nb_qp_max;
715 for (i = 0; i < irqmap->num_vectors; i++) {
716 map = &irqmap->vecmap[i];
717
718 vector_id = map->vector_id;
719 /* validate msg params */
720 if (vector_id >= hw->func_caps.num_msix_vectors_vf) {
721 ret = I40E_ERR_PARAM;
722 goto send_msg;
723 }
724
725 if ((map->rxq_map < qbit_max) && (map->txq_map < qbit_max)) {
726 i40e_pf_config_irq_link_list(vf, map);
727 } else {
728 /* configured queue size exceed limit */
729 ret = I40E_ERR_PARAM;
730 goto send_msg;
731 }
732 }
733
734 send_msg:
735 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_IRQ_MAP,
736 ret, NULL, 0);
737
738 return ret;
739 }
740
741 static int
i40e_pf_host_switch_queues(struct i40e_pf_vf * vf,struct virtchnl_queue_select * qsel,bool on)742 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
743 struct virtchnl_queue_select *qsel,
744 bool on)
745 {
746 int ret = I40E_SUCCESS;
747 int i;
748 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
749 uint16_t baseq = vf->vsi->base_queue;
750
751 if (qsel->rx_queues + qsel->tx_queues == 0)
752 return I40E_ERR_PARAM;
753
754 /* always enable RX first and disable last */
755 /* Enable RX if it's enable */
756 if (on) {
757 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
758 if (qsel->rx_queues & (1 << i)) {
759 ret = i40e_switch_rx_queue(hw, baseq + i, on);
760 if (ret != I40E_SUCCESS)
761 return ret;
762 }
763 }
764
765 /* Enable/Disable TX */
766 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
767 if (qsel->tx_queues & (1 << i)) {
768 ret = i40e_switch_tx_queue(hw, baseq + i, on);
769 if (ret != I40E_SUCCESS)
770 return ret;
771 }
772
773 /* disable RX last if it's disable */
774 if (!on) {
775 /* disable RX */
776 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
777 if (qsel->rx_queues & (1 << i)) {
778 ret = i40e_switch_rx_queue(hw, baseq + i, on);
779 if (ret != I40E_SUCCESS)
780 return ret;
781 }
782 }
783
784 return ret;
785 }
786
787 static int
i40e_pf_host_process_cmd_enable_queues(struct i40e_pf_vf * vf,uint8_t * msg,uint16_t msglen)788 i40e_pf_host_process_cmd_enable_queues(struct i40e_pf_vf *vf,
789 uint8_t *msg,
790 uint16_t msglen)
791 {
792 int ret = I40E_SUCCESS;
793 struct virtchnl_queue_select *q_sel =
794 (struct virtchnl_queue_select *)msg;
795
796 if (msg == NULL || msglen != sizeof(*q_sel)) {
797 ret = I40E_ERR_PARAM;
798 goto send_msg;
799 }
800 ret = i40e_pf_host_switch_queues(vf, q_sel, true);
801
802 send_msg:
803 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ENABLE_QUEUES,
804 ret, NULL, 0);
805
806 return ret;
807 }
808
809 static int
i40e_pf_host_process_cmd_disable_queues(struct i40e_pf_vf * vf,uint8_t * msg,uint16_t msglen,bool b_op)810 i40e_pf_host_process_cmd_disable_queues(struct i40e_pf_vf *vf,
811 uint8_t *msg,
812 uint16_t msglen,
813 bool b_op)
814 {
815 int ret = I40E_SUCCESS;
816 struct virtchnl_queue_select *q_sel =
817 (struct virtchnl_queue_select *)msg;
818
819 if (!b_op) {
820 i40e_pf_host_send_msg_to_vf(
821 vf,
822 VIRTCHNL_OP_DISABLE_QUEUES,
823 I40E_NOT_SUPPORTED, NULL, 0);
824 return ret;
825 }
826
827 if (msg == NULL || msglen != sizeof(*q_sel)) {
828 ret = I40E_ERR_PARAM;
829 goto send_msg;
830 }
831 ret = i40e_pf_host_switch_queues(vf, q_sel, false);
832
833 send_msg:
834 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DISABLE_QUEUES,
835 ret, NULL, 0);
836
837 return ret;
838 }
839
840
841 static int
i40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf * vf,uint8_t * msg,uint16_t msglen,bool b_op)842 i40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf *vf,
843 uint8_t *msg,
844 uint16_t msglen,
845 bool b_op)
846 {
847 int ret = I40E_SUCCESS;
848 struct virtchnl_ether_addr_list *addr_list =
849 (struct virtchnl_ether_addr_list *)msg;
850 struct i40e_mac_filter_info filter;
851 int i;
852 struct rte_ether_addr *mac;
853
854 if (!b_op) {
855 i40e_pf_host_send_msg_to_vf(
856 vf,
857 VIRTCHNL_OP_ADD_ETH_ADDR,
858 I40E_NOT_SUPPORTED, NULL, 0);
859 return ret;
860 }
861
862 memset(&filter, 0 , sizeof(struct i40e_mac_filter_info));
863
864 if (msg == NULL || msglen <= sizeof(*addr_list)) {
865 PMD_DRV_LOG(ERR, "add_ether_address argument too short");
866 ret = I40E_ERR_PARAM;
867 goto send_msg;
868 }
869
870 for (i = 0; i < addr_list->num_elements; i++) {
871 mac = (struct rte_ether_addr *)(addr_list->list[i].addr);
872 rte_memcpy(&filter.mac_addr, mac, RTE_ETHER_ADDR_LEN);
873 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
874 if (rte_is_zero_ether_addr(mac) ||
875 i40e_vsi_add_mac(vf->vsi, &filter)) {
876 ret = I40E_ERR_INVALID_MAC_ADDR;
877 goto send_msg;
878 }
879 }
880
881 send_msg:
882 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ADD_ETH_ADDR,
883 ret, NULL, 0);
884
885 return ret;
886 }
887
888 static int
i40e_pf_host_process_cmd_del_ether_address(struct i40e_pf_vf * vf,uint8_t * msg,uint16_t msglen,bool b_op)889 i40e_pf_host_process_cmd_del_ether_address(struct i40e_pf_vf *vf,
890 uint8_t *msg,
891 uint16_t msglen,
892 bool b_op)
893 {
894 int ret = I40E_SUCCESS;
895 struct virtchnl_ether_addr_list *addr_list =
896 (struct virtchnl_ether_addr_list *)msg;
897 int i;
898 struct rte_ether_addr *mac;
899
900 if (!b_op) {
901 i40e_pf_host_send_msg_to_vf(
902 vf,
903 VIRTCHNL_OP_DEL_ETH_ADDR,
904 I40E_NOT_SUPPORTED, NULL, 0);
905 return ret;
906 }
907
908 if (msg == NULL || msglen <= sizeof(*addr_list)) {
909 PMD_DRV_LOG(ERR, "delete_ether_address argument too short");
910 ret = I40E_ERR_PARAM;
911 goto send_msg;
912 }
913
914 for (i = 0; i < addr_list->num_elements; i++) {
915 mac = (struct rte_ether_addr *)(addr_list->list[i].addr);
916 if (rte_is_zero_ether_addr(mac) ||
917 i40e_vsi_delete_mac(vf->vsi, mac)) {
918 ret = I40E_ERR_INVALID_MAC_ADDR;
919 goto send_msg;
920 }
921 }
922
923 send_msg:
924 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DEL_ETH_ADDR,
925 ret, NULL, 0);
926
927 return ret;
928 }
929
930 static int
i40e_pf_host_process_cmd_add_vlan(struct i40e_pf_vf * vf,uint8_t * msg,uint16_t msglen,bool b_op)931 i40e_pf_host_process_cmd_add_vlan(struct i40e_pf_vf *vf,
932 uint8_t *msg, uint16_t msglen,
933 bool b_op)
934 {
935 int ret = I40E_SUCCESS;
936 struct virtchnl_vlan_filter_list *vlan_filter_list =
937 (struct virtchnl_vlan_filter_list *)msg;
938 int i;
939 uint16_t *vid;
940
941 if (!b_op) {
942 i40e_pf_host_send_msg_to_vf(
943 vf,
944 VIRTCHNL_OP_ADD_VLAN,
945 I40E_NOT_SUPPORTED, NULL, 0);
946 return ret;
947 }
948
949 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
950 PMD_DRV_LOG(ERR, "add_vlan argument too short");
951 ret = I40E_ERR_PARAM;
952 goto send_msg;
953 }
954
955 vid = vlan_filter_list->vlan_id;
956
957 for (i = 0; i < vlan_filter_list->num_elements; i++) {
958 ret = i40e_vsi_add_vlan(vf->vsi, vid[i]);
959 if(ret != I40E_SUCCESS)
960 goto send_msg;
961 }
962
963 send_msg:
964 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ADD_VLAN,
965 ret, NULL, 0);
966
967 return ret;
968 }
969
970 static int
i40e_pf_host_process_cmd_del_vlan(struct i40e_pf_vf * vf,uint8_t * msg,uint16_t msglen,bool b_op)971 i40e_pf_host_process_cmd_del_vlan(struct i40e_pf_vf *vf,
972 uint8_t *msg,
973 uint16_t msglen,
974 bool b_op)
975 {
976 int ret = I40E_SUCCESS;
977 struct virtchnl_vlan_filter_list *vlan_filter_list =
978 (struct virtchnl_vlan_filter_list *)msg;
979 int i;
980 uint16_t *vid;
981
982 if (!b_op) {
983 i40e_pf_host_send_msg_to_vf(
984 vf,
985 VIRTCHNL_OP_DEL_VLAN,
986 I40E_NOT_SUPPORTED, NULL, 0);
987 return ret;
988 }
989
990 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
991 PMD_DRV_LOG(ERR, "delete_vlan argument too short");
992 ret = I40E_ERR_PARAM;
993 goto send_msg;
994 }
995
996 vid = vlan_filter_list->vlan_id;
997 for (i = 0; i < vlan_filter_list->num_elements; i++) {
998 ret = i40e_vsi_delete_vlan(vf->vsi, vid[i]);
999 if(ret != I40E_SUCCESS)
1000 goto send_msg;
1001 }
1002
1003 send_msg:
1004 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DEL_VLAN,
1005 ret, NULL, 0);
1006
1007 return ret;
1008 }
1009
1010 static int
i40e_pf_host_process_cmd_config_promisc_mode(struct i40e_pf_vf * vf,uint8_t * msg,uint16_t msglen,bool b_op)1011 i40e_pf_host_process_cmd_config_promisc_mode(
1012 struct i40e_pf_vf *vf,
1013 uint8_t *msg,
1014 uint16_t msglen,
1015 bool b_op)
1016 {
1017 int ret = I40E_SUCCESS;
1018 struct virtchnl_promisc_info *promisc =
1019 (struct virtchnl_promisc_info *)msg;
1020 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
1021 bool unicast = FALSE, multicast = FALSE;
1022
1023 if (!b_op) {
1024 i40e_pf_host_send_msg_to_vf(
1025 vf,
1026 VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE,
1027 I40E_NOT_SUPPORTED, NULL, 0);
1028 return ret;
1029 }
1030
1031 if (msg == NULL || msglen != sizeof(*promisc)) {
1032 ret = I40E_ERR_PARAM;
1033 goto send_msg;
1034 }
1035
1036 if (promisc->flags & FLAG_VF_UNICAST_PROMISC)
1037 unicast = TRUE;
1038 ret = i40e_aq_set_vsi_unicast_promiscuous(hw,
1039 vf->vsi->seid, unicast, NULL, true);
1040 if (ret != I40E_SUCCESS)
1041 goto send_msg;
1042
1043 if (promisc->flags & FLAG_VF_MULTICAST_PROMISC)
1044 multicast = TRUE;
1045 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vf->vsi->seid,
1046 multicast, NULL);
1047
1048 send_msg:
1049 i40e_pf_host_send_msg_to_vf(vf,
1050 VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, ret, NULL, 0);
1051
1052 return ret;
1053 }
1054
1055 static int
i40e_pf_host_process_cmd_get_stats(struct i40e_pf_vf * vf,bool b_op)1056 i40e_pf_host_process_cmd_get_stats(struct i40e_pf_vf *vf, bool b_op)
1057 {
1058 i40e_update_vsi_stats(vf->vsi);
1059
1060 if (b_op)
1061 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_STATS,
1062 I40E_SUCCESS,
1063 (uint8_t *)&vf->vsi->eth_stats,
1064 sizeof(vf->vsi->eth_stats));
1065 else
1066 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_STATS,
1067 I40E_NOT_SUPPORTED,
1068 (uint8_t *)&vf->vsi->eth_stats,
1069 sizeof(vf->vsi->eth_stats));
1070
1071 return I40E_SUCCESS;
1072 }
1073
1074 static int
i40e_pf_host_process_cmd_enable_vlan_strip(struct i40e_pf_vf * vf,bool b_op)1075 i40e_pf_host_process_cmd_enable_vlan_strip(struct i40e_pf_vf *vf, bool b_op)
1076 {
1077 int ret = I40E_SUCCESS;
1078
1079 if (!b_op) {
1080 i40e_pf_host_send_msg_to_vf(
1081 vf,
1082 VIRTCHNL_OP_ENABLE_VLAN_STRIPPING,
1083 I40E_NOT_SUPPORTED, NULL, 0);
1084 return ret;
1085 }
1086
1087 ret = i40e_vsi_config_vlan_stripping(vf->vsi, TRUE);
1088 if (ret != 0)
1089 PMD_DRV_LOG(ERR, "Failed to enable vlan stripping");
1090
1091 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_ENABLE_VLAN_STRIPPING,
1092 ret, NULL, 0);
1093
1094 return ret;
1095 }
1096
1097 static int
i40e_pf_host_process_cmd_disable_vlan_strip(struct i40e_pf_vf * vf,bool b_op)1098 i40e_pf_host_process_cmd_disable_vlan_strip(struct i40e_pf_vf *vf, bool b_op)
1099 {
1100 int ret = I40E_SUCCESS;
1101
1102 if (!b_op) {
1103 i40e_pf_host_send_msg_to_vf(
1104 vf,
1105 VIRTCHNL_OP_DISABLE_VLAN_STRIPPING,
1106 I40E_NOT_SUPPORTED, NULL, 0);
1107 return ret;
1108 }
1109
1110 ret = i40e_vsi_config_vlan_stripping(vf->vsi, FALSE);
1111 if (ret != 0)
1112 PMD_DRV_LOG(ERR, "Failed to disable vlan stripping");
1113
1114 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_DISABLE_VLAN_STRIPPING,
1115 ret, NULL, 0);
1116
1117 return ret;
1118 }
1119
1120 static int
i40e_pf_host_process_cmd_set_rss_lut(struct i40e_pf_vf * vf,uint8_t * msg,uint16_t msglen,bool b_op)1121 i40e_pf_host_process_cmd_set_rss_lut(struct i40e_pf_vf *vf,
1122 uint8_t *msg,
1123 uint16_t msglen,
1124 bool b_op)
1125 {
1126 struct virtchnl_rss_lut *rss_lut = (struct virtchnl_rss_lut *)msg;
1127 uint16_t valid_len;
1128 int ret = I40E_SUCCESS;
1129
1130 if (!b_op) {
1131 i40e_pf_host_send_msg_to_vf(
1132 vf,
1133 VIRTCHNL_OP_CONFIG_RSS_LUT,
1134 I40E_NOT_SUPPORTED, NULL, 0);
1135 return ret;
1136 }
1137
1138 if (!msg || msglen <= sizeof(struct virtchnl_rss_lut)) {
1139 PMD_DRV_LOG(ERR, "set_rss_lut argument too short");
1140 ret = I40E_ERR_PARAM;
1141 goto send_msg;
1142 }
1143 valid_len = sizeof(struct virtchnl_rss_lut) + rss_lut->lut_entries - 1;
1144 if (msglen < valid_len) {
1145 PMD_DRV_LOG(ERR, "set_rss_lut length mismatch");
1146 ret = I40E_ERR_PARAM;
1147 goto send_msg;
1148 }
1149
1150 ret = i40e_set_rss_lut(vf->vsi, rss_lut->lut, rss_lut->lut_entries);
1151
1152 send_msg:
1153 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_RSS_LUT,
1154 ret, NULL, 0);
1155
1156 return ret;
1157 }
1158
1159 static int
i40e_pf_host_process_cmd_set_rss_key(struct i40e_pf_vf * vf,uint8_t * msg,uint16_t msglen,bool b_op)1160 i40e_pf_host_process_cmd_set_rss_key(struct i40e_pf_vf *vf,
1161 uint8_t *msg,
1162 uint16_t msglen,
1163 bool b_op)
1164 {
1165 struct virtchnl_rss_key *rss_key = (struct virtchnl_rss_key *)msg;
1166 uint16_t valid_len;
1167 int ret = I40E_SUCCESS;
1168
1169 if (!b_op) {
1170 i40e_pf_host_send_msg_to_vf(
1171 vf,
1172 VIRTCHNL_OP_DEL_VLAN,
1173 VIRTCHNL_OP_CONFIG_RSS_KEY, NULL, 0);
1174 return ret;
1175 }
1176
1177 if (!msg || msglen <= sizeof(struct virtchnl_rss_key)) {
1178 PMD_DRV_LOG(ERR, "set_rss_key argument too short");
1179 ret = I40E_ERR_PARAM;
1180 goto send_msg;
1181 }
1182 valid_len = sizeof(struct virtchnl_rss_key) + rss_key->key_len - 1;
1183 if (msglen < valid_len) {
1184 PMD_DRV_LOG(ERR, "set_rss_key length mismatch");
1185 ret = I40E_ERR_PARAM;
1186 goto send_msg;
1187 }
1188
1189 ret = i40e_set_rss_key(vf->vsi, rss_key->key, rss_key->key_len);
1190
1191 send_msg:
1192 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_CONFIG_RSS_KEY,
1193 ret, NULL, 0);
1194
1195 return ret;
1196 }
1197
1198 void
i40e_notify_vf_link_status(struct rte_eth_dev * dev,struct i40e_pf_vf * vf)1199 i40e_notify_vf_link_status(struct rte_eth_dev *dev, struct i40e_pf_vf *vf)
1200 {
1201 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
1202 struct virtchnl_pf_event event;
1203 uint16_t vf_id = vf->vf_idx;
1204 uint32_t tval, rval;
1205
1206 event.event = VIRTCHNL_EVENT_LINK_CHANGE;
1207 event.event_data.link_event.link_status =
1208 dev->data->dev_link.link_status;
1209
1210 /* need to convert the RTE_ETH_SPEED_xxx into VIRTCHNL_LINK_SPEED_xxx */
1211 switch (dev->data->dev_link.link_speed) {
1212 case RTE_ETH_SPEED_NUM_100M:
1213 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_100MB;
1214 break;
1215 case RTE_ETH_SPEED_NUM_1G:
1216 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_1GB;
1217 break;
1218 case RTE_ETH_SPEED_NUM_10G:
1219 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_10GB;
1220 break;
1221 case RTE_ETH_SPEED_NUM_20G:
1222 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_20GB;
1223 break;
1224 case RTE_ETH_SPEED_NUM_25G:
1225 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_25GB;
1226 break;
1227 case RTE_ETH_SPEED_NUM_40G:
1228 event.event_data.link_event.link_speed = VIRTCHNL_LINK_SPEED_40GB;
1229 break;
1230 default:
1231 event.event_data.link_event.link_speed =
1232 VIRTCHNL_LINK_SPEED_UNKNOWN;
1233 break;
1234 }
1235
1236 tval = I40E_READ_REG(hw, I40E_VF_ATQLEN(vf_id));
1237 rval = I40E_READ_REG(hw, I40E_VF_ARQLEN(vf_id));
1238
1239 if (tval & I40E_VF_ATQLEN_ATQLEN_MASK ||
1240 tval & I40E_VF_ATQLEN_ATQENABLE_MASK ||
1241 rval & I40E_VF_ARQLEN_ARQLEN_MASK ||
1242 rval & I40E_VF_ARQLEN_ARQENABLE_MASK)
1243 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_EVENT,
1244 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
1245 }
1246
1247 /**
1248 * i40e_vc_notify_vf_reset
1249 * @vf: pointer to the VF structure
1250 *
1251 * indicate a pending reset to the given VF
1252 **/
1253 static void
i40e_vc_notify_vf_reset(struct i40e_pf_vf * vf)1254 i40e_vc_notify_vf_reset(struct i40e_pf_vf *vf)
1255 {
1256 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
1257 struct virtchnl_pf_event pfe;
1258 int abs_vf_id;
1259 uint16_t vf_id = vf->vf_idx;
1260
1261 abs_vf_id = vf_id + hw->func_caps.vf_base_id;
1262 pfe.event = VIRTCHNL_EVENT_RESET_IMPENDING;
1263 pfe.severity = PF_EVENT_SEVERITY_CERTAIN_DOOM;
1264 i40e_aq_send_msg_to_vf(hw, abs_vf_id, VIRTCHNL_OP_EVENT, 0, (u8 *)&pfe,
1265 sizeof(struct virtchnl_pf_event), NULL);
1266 }
1267
1268 static int
i40e_pf_host_process_cmd_request_queues(struct i40e_pf_vf * vf,uint8_t * msg)1269 i40e_pf_host_process_cmd_request_queues(struct i40e_pf_vf *vf, uint8_t *msg)
1270 {
1271 struct virtchnl_vf_res_request *vfres =
1272 (struct virtchnl_vf_res_request *)msg;
1273 struct i40e_pf *pf;
1274 uint32_t req_pairs = vfres->num_queue_pairs;
1275 uint32_t cur_pairs = vf->vsi->nb_used_qps;
1276
1277 pf = vf->pf;
1278
1279 if (!rte_is_power_of_2(req_pairs))
1280 req_pairs = i40e_align_floor(req_pairs) << 1;
1281
1282 if (req_pairs == 0) {
1283 PMD_DRV_LOG(ERR, "VF %d tried to request 0 queues. Ignoring.\n",
1284 vf->vf_idx);
1285 } else if (req_pairs > I40E_MAX_QP_NUM_PER_VF) {
1286 PMD_DRV_LOG(ERR,
1287 "VF %d tried to request more than %d queues.\n",
1288 vf->vf_idx,
1289 I40E_MAX_QP_NUM_PER_VF);
1290 vfres->num_queue_pairs = I40E_MAX_QP_NUM_PER_VF;
1291 } else if (req_pairs > cur_pairs + pf->qp_pool.num_free) {
1292 PMD_DRV_LOG(ERR, "VF %d requested %d queues (rounded to %d) "
1293 "but only %d available\n",
1294 vf->vf_idx,
1295 vfres->num_queue_pairs,
1296 req_pairs,
1297 cur_pairs + pf->qp_pool.num_free);
1298 vfres->num_queue_pairs = i40e_align_floor(pf->qp_pool.num_free +
1299 cur_pairs);
1300 } else {
1301 i40e_vc_notify_vf_reset(vf);
1302 vf->vsi->nb_qps = req_pairs;
1303 pf->vf_nb_qps = req_pairs;
1304 i40e_pf_host_process_cmd_reset_vf(vf);
1305
1306 return 0;
1307 }
1308
1309 return i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_REQUEST_QUEUES, 0,
1310 (u8 *)vfres, sizeof(*vfres));
1311 }
1312
1313 static void
i40e_pf_host_process_cmd_get_rss_hena(struct i40e_pf_vf * vf)1314 i40e_pf_host_process_cmd_get_rss_hena(struct i40e_pf_vf *vf)
1315 {
1316 struct virtchnl_rss_hena vrh = {0};
1317 struct i40e_pf *pf = vf->pf;
1318
1319 if (pf->adapter->hw.mac.type == I40E_MAC_X722)
1320 vrh.hena = I40E_DEFAULT_RSS_HENA_EXPANDED;
1321 else
1322 vrh.hena = I40E_DEFAULT_RSS_HENA;
1323
1324 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_GET_RSS_HENA_CAPS,
1325 I40E_SUCCESS, (uint8_t *)&vrh, sizeof(vrh));
1326 }
1327
1328 static void
i40e_pf_host_process_cmd_set_rss_hena(struct i40e_pf_vf * vf,uint8_t * msg)1329 i40e_pf_host_process_cmd_set_rss_hena(struct i40e_pf_vf *vf, uint8_t *msg)
1330 {
1331 struct virtchnl_rss_hena *vrh =
1332 (struct virtchnl_rss_hena *)msg;
1333 struct i40e_hw *hw = &vf->pf->adapter->hw;
1334
1335 i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(0, vf->vf_idx),
1336 (uint32_t)vrh->hena);
1337 i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(1, vf->vf_idx),
1338 (uint32_t)(vrh->hena >> 32));
1339
1340 i40e_pf_host_send_msg_to_vf(vf, VIRTCHNL_OP_SET_RSS_HENA,
1341 I40E_SUCCESS, NULL, 0);
1342 }
1343
1344 void
i40e_pf_host_handle_vf_msg(struct rte_eth_dev * dev,uint16_t abs_vf_id,uint32_t opcode,__rte_unused uint32_t retval,uint8_t * msg,uint16_t msglen)1345 i40e_pf_host_handle_vf_msg(struct rte_eth_dev *dev,
1346 uint16_t abs_vf_id, uint32_t opcode,
1347 __rte_unused uint32_t retval,
1348 uint8_t *msg,
1349 uint16_t msglen)
1350 {
1351 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1352 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1353 struct i40e_pf_vf *vf;
1354 /* AdminQ will pass absolute VF id, transfer to internal vf id */
1355 uint16_t vf_id = abs_vf_id - hw->func_caps.vf_base_id;
1356 struct rte_pmd_i40e_mb_event_param ret_param;
1357 uint64_t first_cycle, cur_cycle;
1358 bool b_op = TRUE;
1359 int ret;
1360
1361 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1362 PMD_DRV_LOG(ERR, "invalid argument");
1363 return;
1364 }
1365
1366 vf = &pf->vfs[vf_id];
1367
1368 cur_cycle = rte_get_timer_cycles();
1369
1370 /* if the VF being blocked, ignore the message and return */
1371 if (cur_cycle < vf->ignore_end_cycle)
1372 return;
1373
1374 if (!vf->vsi) {
1375 PMD_DRV_LOG(ERR, "NO VSI associated with VF found");
1376 i40e_pf_host_send_msg_to_vf(vf, opcode,
1377 I40E_ERR_NO_AVAILABLE_VSI, NULL, 0);
1378 goto check;
1379 }
1380
1381 /* perform basic checks on the msg */
1382 ret = virtchnl_vc_validate_vf_msg(&vf->version, opcode, msg, msglen);
1383
1384 /* perform additional checks specific to this driver */
1385 if (opcode == VIRTCHNL_OP_CONFIG_RSS_KEY) {
1386 struct virtchnl_rss_key *vrk = (struct virtchnl_rss_key *)msg;
1387
1388 if (vrk->key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4))
1389 ret = VIRTCHNL_ERR_PARAM;
1390 } else if (opcode == VIRTCHNL_OP_CONFIG_RSS_LUT) {
1391 struct virtchnl_rss_lut *vrl = (struct virtchnl_rss_lut *)msg;
1392
1393 if (vrl->lut_entries != ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4))
1394 ret = VIRTCHNL_ERR_PARAM;
1395 }
1396
1397 if (ret) {
1398 PMD_DRV_LOG(ERR, "Invalid message from VF %u, opcode %u, len %u",
1399 vf_id, opcode, msglen);
1400 i40e_pf_host_send_msg_to_vf(vf, opcode,
1401 I40E_ERR_PARAM, NULL, 0);
1402 goto check;
1403 }
1404
1405 /**
1406 * initialise structure to send to user application
1407 * will return response from user in retval field
1408 */
1409 ret_param.retval = RTE_PMD_I40E_MB_EVENT_PROCEED;
1410 ret_param.vfid = vf_id;
1411 ret_param.msg_type = opcode;
1412 ret_param.msg = (void *)msg;
1413 ret_param.msglen = msglen;
1414
1415 /**
1416 * Ask user application if we're allowed to perform those functions.
1417 * If we get ret_param.retval == RTE_PMD_I40E_MB_EVENT_PROCEED,
1418 * then business as usual.
1419 * If RTE_PMD_I40E_MB_EVENT_NOOP_ACK or RTE_PMD_I40E_MB_EVENT_NOOP_NACK,
1420 * do nothing and send not_supported to VF. As PF must send a response
1421 * to VF and ACK/NACK is not defined.
1422 */
1423 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, &ret_param);
1424 if (ret_param.retval != RTE_PMD_I40E_MB_EVENT_PROCEED) {
1425 PMD_DRV_LOG(WARNING, "VF to PF message(%d) is not permitted!",
1426 opcode);
1427 b_op = FALSE;
1428 }
1429
1430 switch (opcode) {
1431 case VIRTCHNL_OP_VERSION:
1432 PMD_DRV_LOG(INFO, "OP_VERSION received");
1433 i40e_pf_host_process_cmd_version(vf, msg, b_op);
1434 break;
1435 case VIRTCHNL_OP_RESET_VF:
1436 PMD_DRV_LOG(INFO, "OP_RESET_VF received");
1437 i40e_pf_host_process_cmd_reset_vf(vf);
1438 break;
1439 case VIRTCHNL_OP_GET_VF_RESOURCES:
1440 PMD_DRV_LOG(INFO, "OP_GET_VF_RESOURCES received");
1441 i40e_pf_host_process_cmd_get_vf_resource(vf, msg, b_op);
1442 break;
1443 case VIRTCHNL_OP_CONFIG_VSI_QUEUES:
1444 PMD_DRV_LOG(INFO, "OP_CONFIG_VSI_QUEUES received");
1445 i40e_pf_host_process_cmd_config_vsi_queues(vf, msg,
1446 msglen, b_op);
1447 break;
1448 case VIRTCHNL_OP_CONFIG_IRQ_MAP:
1449 PMD_DRV_LOG(INFO, "OP_CONFIG_IRQ_MAP received");
1450 i40e_pf_host_process_cmd_config_irq_map(vf, msg, msglen, b_op);
1451 break;
1452 case VIRTCHNL_OP_ENABLE_QUEUES:
1453 PMD_DRV_LOG(INFO, "OP_ENABLE_QUEUES received");
1454 if (b_op) {
1455 i40e_pf_host_process_cmd_enable_queues(vf, msg, msglen);
1456 i40e_notify_vf_link_status(dev, vf);
1457 } else {
1458 i40e_pf_host_send_msg_to_vf(
1459 vf, VIRTCHNL_OP_ENABLE_QUEUES,
1460 I40E_NOT_SUPPORTED, NULL, 0);
1461 }
1462 break;
1463 case VIRTCHNL_OP_DISABLE_QUEUES:
1464 PMD_DRV_LOG(INFO, "OP_DISABLE_QUEUE received");
1465 i40e_pf_host_process_cmd_disable_queues(vf, msg, msglen, b_op);
1466 break;
1467 case VIRTCHNL_OP_ADD_ETH_ADDR:
1468 PMD_DRV_LOG(INFO, "OP_ADD_ETHER_ADDRESS received");
1469 i40e_pf_host_process_cmd_add_ether_address(vf, msg,
1470 msglen, b_op);
1471 break;
1472 case VIRTCHNL_OP_DEL_ETH_ADDR:
1473 PMD_DRV_LOG(INFO, "OP_DEL_ETHER_ADDRESS received");
1474 i40e_pf_host_process_cmd_del_ether_address(vf, msg,
1475 msglen, b_op);
1476 break;
1477 case VIRTCHNL_OP_ADD_VLAN:
1478 PMD_DRV_LOG(INFO, "OP_ADD_VLAN received");
1479 i40e_pf_host_process_cmd_add_vlan(vf, msg, msglen, b_op);
1480 break;
1481 case VIRTCHNL_OP_DEL_VLAN:
1482 PMD_DRV_LOG(INFO, "OP_DEL_VLAN received");
1483 i40e_pf_host_process_cmd_del_vlan(vf, msg, msglen, b_op);
1484 break;
1485 case VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:
1486 PMD_DRV_LOG(INFO, "OP_CONFIG_PROMISCUOUS_MODE received");
1487 i40e_pf_host_process_cmd_config_promisc_mode(vf, msg,
1488 msglen, b_op);
1489 break;
1490 case VIRTCHNL_OP_GET_STATS:
1491 PMD_DRV_LOG(INFO, "OP_GET_STATS received");
1492 i40e_pf_host_process_cmd_get_stats(vf, b_op);
1493 break;
1494 case VIRTCHNL_OP_ENABLE_VLAN_STRIPPING:
1495 PMD_DRV_LOG(INFO, "OP_ENABLE_VLAN_STRIPPING received");
1496 i40e_pf_host_process_cmd_enable_vlan_strip(vf, b_op);
1497 break;
1498 case VIRTCHNL_OP_DISABLE_VLAN_STRIPPING:
1499 PMD_DRV_LOG(INFO, "OP_DISABLE_VLAN_STRIPPING received");
1500 i40e_pf_host_process_cmd_disable_vlan_strip(vf, b_op);
1501 break;
1502 case VIRTCHNL_OP_CONFIG_RSS_LUT:
1503 PMD_DRV_LOG(INFO, "OP_CONFIG_RSS_LUT received");
1504 i40e_pf_host_process_cmd_set_rss_lut(vf, msg, msglen, b_op);
1505 break;
1506 case VIRTCHNL_OP_CONFIG_RSS_KEY:
1507 PMD_DRV_LOG(INFO, "OP_CONFIG_RSS_KEY received");
1508 i40e_pf_host_process_cmd_set_rss_key(vf, msg, msglen, b_op);
1509 break;
1510 case VIRTCHNL_OP_REQUEST_QUEUES:
1511 PMD_DRV_LOG(INFO, "OP_REQUEST_QUEUES received");
1512 i40e_pf_host_process_cmd_request_queues(vf, msg);
1513 break;
1514 case VIRTCHNL_OP_GET_RSS_HENA_CAPS:
1515 PMD_DRV_LOG(INFO, "OP_GET_RSS_HENA_CAPS received");
1516 i40e_pf_host_process_cmd_get_rss_hena(vf);
1517 break;
1518 case VIRTCHNL_OP_SET_RSS_HENA:
1519 PMD_DRV_LOG(INFO, "OP_SET_RSS_HENA received");
1520 i40e_pf_host_process_cmd_set_rss_hena(vf, msg);
1521 break;
1522
1523 /* Don't add command supported below, which will
1524 * return an error code.
1525 */
1526 default:
1527 PMD_DRV_LOG(ERR, "%u received, not supported", opcode);
1528 i40e_pf_host_send_msg_to_vf(vf, opcode, I40E_ERR_PARAM,
1529 NULL, 0);
1530 break;
1531 }
1532
1533 check:
1534 /* if message validation not enabled */
1535 if (!pf->vf_msg_cfg.max_msg)
1536 return;
1537
1538 /* store current cycle */
1539 vf->msg_timestamps[vf->msg_index++] = cur_cycle;
1540 vf->msg_index %= pf->vf_msg_cfg.max_msg;
1541
1542 /* read the timestamp of earliest message */
1543 first_cycle = vf->msg_timestamps[vf->msg_index];
1544
1545 /*
1546 * If the time span from the arrival time of first message to
1547 * the arrival time of current message smaller than `period`,
1548 * that mean too much message in this statistic period.
1549 */
1550 if (first_cycle && cur_cycle < first_cycle +
1551 (uint64_t)pf->vf_msg_cfg.period * rte_get_timer_hz()) {
1552 PMD_DRV_LOG(WARNING, "VF %u too much messages(%u in %u"
1553 " seconds),\n\tany new message from which"
1554 " will be ignored during next %u seconds!",
1555 vf_id, pf->vf_msg_cfg.max_msg,
1556 (uint32_t)((cur_cycle - first_cycle +
1557 rte_get_timer_hz() - 1) / rte_get_timer_hz()),
1558 pf->vf_msg_cfg.ignore_second);
1559 vf->ignore_end_cycle = rte_get_timer_cycles() +
1560 pf->vf_msg_cfg.ignore_second *
1561 rte_get_timer_hz();
1562 }
1563 }
1564
1565 int
i40e_pf_host_init(struct rte_eth_dev * dev)1566 i40e_pf_host_init(struct rte_eth_dev *dev)
1567 {
1568 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1569 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1570 size_t size;
1571 int ret, i;
1572 uint32_t val;
1573
1574 PMD_INIT_FUNC_TRACE();
1575
1576 /**
1577 * return if SRIOV not enabled, VF number not configured or
1578 * no queue assigned.
1579 */
1580 if(!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 || pf->vf_nb_qps == 0)
1581 return I40E_SUCCESS;
1582
1583 /* Allocate memory to store VF structure */
1584 pf->vfs = rte_zmalloc("i40e_pf_vf",sizeof(*pf->vfs) * pf->vf_num, 0);
1585 if(pf->vfs == NULL)
1586 return -ENOMEM;
1587
1588 /* Disable irq0 for VFR event */
1589 i40e_pf_disable_irq0(hw);
1590
1591 /* Disable VF link status interrupt */
1592 val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1593 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1594 I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1595 I40E_WRITE_FLUSH(hw);
1596
1597 /* calculate the memory size for storing timestamp of messages */
1598 size = pf->vf_msg_cfg.max_msg * sizeof(uint64_t);
1599
1600 for (i = 0; i < pf->vf_num; i++) {
1601 pf->vfs[i].pf = pf;
1602 pf->vfs[i].state = I40E_VF_INACTIVE;
1603 pf->vfs[i].vf_idx = i;
1604
1605 if (size) {
1606 /* allocate memory for store timestamp of messages */
1607 pf->vfs[i].msg_timestamps =
1608 rte_zmalloc("i40e_pf_vf", size, 0);
1609 if (pf->vfs[i].msg_timestamps == NULL) {
1610 ret = -ENOMEM;
1611 goto fail;
1612 }
1613 }
1614
1615 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
1616 if (ret != I40E_SUCCESS)
1617 goto fail;
1618 }
1619
1620 RTE_ETH_DEV_SRIOV(dev).active = pf->vf_num;
1621 /* restore irq0 */
1622 i40e_pf_enable_irq0(hw);
1623
1624 return I40E_SUCCESS;
1625
1626 fail:
1627 for (; i >= 0; i--)
1628 rte_free(pf->vfs[i].msg_timestamps);
1629 rte_free(pf->vfs);
1630 i40e_pf_enable_irq0(hw);
1631
1632 return ret;
1633 }
1634
1635 int
i40e_pf_host_uninit(struct rte_eth_dev * dev)1636 i40e_pf_host_uninit(struct rte_eth_dev *dev)
1637 {
1638 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1639 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1640 uint32_t val;
1641 int i;
1642
1643 PMD_INIT_FUNC_TRACE();
1644
1645 /**
1646 * return if SRIOV not enabled, VF number not configured or
1647 * no queue assigned.
1648 */
1649 if ((!hw->func_caps.sr_iov_1_1) ||
1650 (pf->vf_num == 0) ||
1651 (pf->vf_nb_qps == 0))
1652 return I40E_SUCCESS;
1653
1654 /* free memory for store timestamp of messages */
1655 for (i = 0; i < pf->vf_num; i++)
1656 rte_free(pf->vfs[i].msg_timestamps);
1657
1658 /* free memory to store VF structure */
1659 rte_free(pf->vfs);
1660 pf->vfs = NULL;
1661
1662 /* Disable irq0 for VFR event */
1663 i40e_pf_disable_irq0(hw);
1664
1665 /* Disable VF link status interrupt */
1666 val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1667 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1668 I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1669 I40E_WRITE_FLUSH(hw);
1670
1671 return I40E_SUCCESS;
1672 }
1673