1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #ifndef __BXE_H__
30 #define __BXE_H__
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sx.h>
41 #include <sys/module.h>
42 #include <sys/endian.h>
43 #include <sys/types.h>
44 #include <sys/malloc.h>
45 #include <sys/kobj.h>
46 #include <sys/bus.h>
47 #include <sys/rman.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
51 #include <sys/smp.h>
52 #include <sys/bitstring.h>
53 #include <sys/limits.h>
54 #include <sys/queue.h>
55 #include <sys/taskqueue.h>
56 #include <sys/zlib.h>
57
58 #include <net/if.h>
59 #include <net/if_types.h>
60 #include <net/if_arp.h>
61 #include <net/ethernet.h>
62 #include <net/if_dl.h>
63 #include <net/if_var.h>
64 #include <net/if_media.h>
65 #include <net/if_vlan_var.h>
66 #include <net/bpf.h>
67
68 #include <netinet/in.h>
69 #include <netinet/ip.h>
70 #include <netinet/ip6.h>
71 #include <netinet/tcp.h>
72 #include <netinet/udp.h>
73 #include <netinet/netdump/netdump.h>
74
75 #include <dev/pci/pcireg.h>
76 #include <dev/pci/pcivar.h>
77
78 #include <machine/atomic.h>
79 #include <machine/resource.h>
80 #include <machine/endian.h>
81 #include <machine/bus.h>
82 #include <machine/in_cksum.h>
83
84 #include "device_if.h"
85 #include "bus_if.h"
86 #include "pci_if.h"
87
88 #if _BYTE_ORDER == _LITTLE_ENDIAN
89 #ifndef LITTLE_ENDIAN
90 #define LITTLE_ENDIAN
91 #endif
92 #ifndef __LITTLE_ENDIAN
93 #define __LITTLE_ENDIAN
94 #endif
95 #undef BIG_ENDIAN
96 #undef __BIG_ENDIAN
97 #else /* _BIG_ENDIAN */
98 #ifndef BIG_ENDIAN
99 #define BIG_ENDIAN
100 #endif
101 #ifndef __BIG_ENDIAN
102 #define __BIG_ENDIAN
103 #endif
104 #undef LITTLE_ENDIAN
105 #undef __LITTLE_ENDIAN
106 #endif
107
108 #include "ecore_mfw_req.h"
109 #include "ecore_fw_defs.h"
110 #include "ecore_hsi.h"
111 #include "ecore_reg.h"
112 #include "bxe_dcb.h"
113 #include "bxe_stats.h"
114
115 #include "bxe_elink.h"
116
117 #define VF_MAC_CREDIT_CNT 0
118 #define VF_VLAN_CREDIT_CNT (0)
119
120 #if __FreeBSD_version < 800054
121 #if defined(__i386__) || defined(__amd64__)
122 #define mb() __asm volatile("mfence;" : : : "memory")
123 #define wmb() __asm volatile("sfence;" : : : "memory")
124 #define rmb() __asm volatile("lfence;" : : : "memory")
prefetch(void * x)125 static __inline void prefetch(void *x)
126 {
127 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
128 }
129 #else
130 #define mb()
131 #define rmb()
132 #define wmb()
133 #define prefetch(x)
134 #endif
135 #endif
136
137 #if __FreeBSD_version >= 1000000
138 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA
139 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND
140 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA
141 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH
142 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED
143 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL
144 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
145 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST
146 #endif
147
148 #ifndef ARRAY_SIZE
149 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
150 #endif
151 #ifndef ARRSIZE
152 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
153 #endif
154 #ifndef DIV_ROUND_UP
155 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
156 #endif
157 #ifndef roundup
158 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
159 #endif
160 #ifndef ilog2
161 static inline
bxe_ilog2(int x)162 int bxe_ilog2(int x)
163 {
164 int log = 0;
165 while (x >>= 1) log++;
166 return (log);
167 }
168 #define ilog2(x) bxe_ilog2(x)
169 #endif
170
171 #include "ecore_sp.h"
172
173 #define BRCM_VENDORID 0x14e4
174 #define QLOGIC_VENDORID 0x1077
175 #define PCI_ANY_ID (uint16_t)(~0U)
176
177 struct bxe_device_type
178 {
179 uint16_t bxe_vid;
180 uint16_t bxe_did;
181 uint16_t bxe_svid;
182 uint16_t bxe_sdid;
183 char *bxe_name;
184 };
185
186 #define BCM_PAGE_SHIFT 12
187 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
188 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
189 #define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
190
191 #if BCM_PAGE_SIZE != 4096
192 #error Page sizes other than 4KB are unsupported!
193 #endif
194
195 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
196 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
197 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
198 #else
199 #define U64_LO(addr) ((uint32_t)(addr))
200 #define U64_HI(addr) (0)
201 #endif
202 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
203
204 #define SET_FLAG(value, mask, flag) \
205 do { \
206 (value) &= ~(mask); \
207 (value) |= ((flag) << (mask##_SHIFT)); \
208 } while (0)
209
210 #define GET_FLAG(value, mask) \
211 (((value) & (mask)) >> (mask##_SHIFT))
212
213 #define GET_FIELD(value, fname) \
214 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
215
216 #define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */
217 #define BXE_TSO_MAX_SEGMENTS 32
218 #define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header))
219 #define BXE_TSO_MAX_SEG_SIZE 4096
220
221 /* dropless fc FW/HW related params */
222 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
223 #define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \
224 ETH_MAX_AGGREGATION_QUEUES_E1 : \
225 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
226 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
227 #define FW_PREFETCH_CNT 16
228 #define DROPLESS_FC_HEADROOM 100
229
230 /******************/
231 /* RX SGE defines */
232 /******************/
233
234 #define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */
235 #define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
236 #define RX_SGE_NEXT_PAGE_DESC_CNT 2
237 #define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT)
238 #define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1)
239 #define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES)
240 #define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)
241 #define RX_SGE_MAX (RX_SGE_TOTAL - 1)
242 #define RX_SGE(x) ((x) & RX_SGE_MAX)
243
244 #define RX_SGE_NEXT(x) \
245 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \
246 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1)
247
248 #define RX_SGE_MASK_ELEM_SZ 64
249 #define RX_SGE_MASK_ELEM_SHIFT 6
250 #define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1)
251
252 /*
253 * Creates a bitmask of all ones in less significant bits.
254 * idx - index of the most significant bit in the created mask.
255 */
256 #define RX_SGE_ONES_MASK(idx) \
257 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
258 #define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0))
259
260 /* Number of uint64_t elements in SGE mask array. */
261 #define RX_SGE_MASK_LEN \
262 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ)
263 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
264 #define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
265
266 /*
267 * dropless fc calculations for SGEs
268 * Number of required SGEs is the sum of two:
269 * 1. Number of possible opened aggregations (next packet for
270 * these aggregations will probably consume SGE immidiatelly)
271 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
272 * after placement on BD for new TPA aggregation)
273 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page
274 */
275 #define NUM_SGE_REQ(sc) \
276 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2)
277 #define NUM_SGE_PG_REQ(sc) \
278 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE)
279 #define SGE_TH_LO(sc) \
280 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT)
281 #define SGE_TH_HI(sc) \
282 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM)
283
284 #define PAGES_PER_SGE_SHIFT 0
285 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
286 #define SGE_PAGE_SIZE BCM_PAGE_SIZE
287 #define SGE_PAGE_SHIFT BCM_PAGE_SHIFT
288 #define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr)
289 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
290 #define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff)
291
292 /*****************/
293 /* TX BD defines */
294 /*****************/
295
296 #define TX_BD_NUM_PAGES 16 /* must be a power of 2 */
297 #define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
298 #define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1)
299 #define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES)
300 #define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES)
301 #define TX_BD_MAX (TX_BD_TOTAL - 1)
302
303 #define TX_BD_NEXT(x) \
304 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \
305 ((x) + 2) : ((x) + 1))
306 #define TX_BD(x) ((x) & TX_BD_MAX)
307 #define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8)
308 #define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE)
309
310 /*
311 * Trigger pending transmits when the number of available BDs is greater
312 * than 1/8 of the total number of usable BDs.
313 */
314 #define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8)
315 #define BXE_TX_TIMEOUT 5
316
317 /*****************/
318 /* RX BD defines */
319 /*****************/
320
321 #define RX_BD_NUM_PAGES 8 /* power of 2 */
322 #define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
323 #define RX_BD_NEXT_PAGE_DESC_CNT 2
324 #define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT)
325 #define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1)
326 #define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES)
327 #define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES)
328 #define RX_BD_MAX (RX_BD_TOTAL - 1)
329
330 #define RX_BD_NEXT(x) \
331 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \
332 ((x) + 3) : ((x) + 1))
333 #define RX_BD(x) ((x) & RX_BD_MAX)
334 #define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
335 #define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
336
337 /*
338 * dropless fc calculations for BDs
339 * Number of BDs should be as number of buffers in BRB:
340 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
341 * "next" elements on each page
342 */
343 #define NUM_BD_REQ(sc) \
344 BRB_SIZE(sc)
345 #define NUM_BD_PG_REQ(sc) \
346 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE)
347 #define BD_TH_LO(sc) \
348 (NUM_BD_REQ(sc) + \
349 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
350 FW_DROP_LEVEL(sc))
351 #define BD_TH_HI(sc) \
352 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
353 #define MIN_RX_AVAIL(sc) \
354 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
355 #define MIN_RX_SIZE_TPA_HW(sc) \
356 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \
357 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
358 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
359 #define MIN_RX_SIZE_TPA(sc) \
360 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc)))
361 #define MIN_RX_SIZE_NONTPA(sc) \
362 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc)))
363
364 /***************/
365 /* RCQ defines */
366 /***************/
367
368 /*
369 * As long as CQE is X times bigger than BD entry we have to allocate X times
370 * more pages for CQ ring in order to keep it balanced with BD ring
371 */
372 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / \
373 sizeof(struct eth_rx_bd))
374 #define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */
375 #define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
376 #define RCQ_NEXT_PAGE_DESC_CNT 1
377 #define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT)
378 #define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES)
379 #define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES)
380 #define RCQ_MAX (RCQ_TOTAL - 1)
381
382 #define RCQ_NEXT(x) \
383 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \
384 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1))
385 #define RCQ(x) ((x) & RCQ_MAX)
386 #define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7)
387 #define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE)
388
389 /*
390 * dropless fc calculations for RCQs
391 * Number of RCQs should be as number of buffers in BRB:
392 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
393 * "next" elements on each page
394 */
395 #define NUM_RCQ_REQ(sc) \
396 BRB_SIZE(sc)
397 #define NUM_RCQ_PG_REQ(sc) \
398 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE)
399 #define RCQ_TH_LO(sc) \
400 (NUM_RCQ_REQ(sc) + \
401 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
402 FW_DROP_LEVEL(sc))
403 #define RCQ_TH_HI(sc) \
404 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
405
406 /* This is needed for determening of last_max */
407 #define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b))
408
409 #define __SGE_MASK_SET_BIT(el, bit) \
410 do { \
411 (el) = ((el) | ((uint64_t)0x1 << (bit))); \
412 } while (0)
413
414 #define __SGE_MASK_CLEAR_BIT(el, bit) \
415 do { \
416 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \
417 } while (0)
418
419 #define SGE_MASK_SET_BIT(fp, idx) \
420 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
421 ((idx) & RX_SGE_MASK_ELEM_MASK))
422
423 #define SGE_MASK_CLEAR_BIT(fp, idx) \
424 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
425 ((idx) & RX_SGE_MASK_ELEM_MASK))
426
427 /* Load / Unload modes */
428 #define LOAD_NORMAL 0
429 #define LOAD_OPEN 1
430 #define LOAD_DIAG 2
431 #define LOAD_LOOPBACK_EXT 3
432 #define UNLOAD_NORMAL 0
433 #define UNLOAD_CLOSE 1
434 #define UNLOAD_RECOVERY 2
435
436 /* Some constants... */
437 //#define MAX_PATH_NUM 2
438 //#define E2_MAX_NUM_OF_VFS 64
439 //#define E1H_FUNC_MAX 8
440 //#define E2_FUNC_MAX 4 /* per path */
441 #define MAX_VNIC_NUM 4
442 #define MAX_FUNC_NUM 8 /* common to all chips */
443 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
444 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
445 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
446
447 #define ILT_NUM_PAGE_ENTRIES 3072
448 /*
449 * 57710/11 we use whole table since we have 8 functions.
450 * 57712 we have only 4 functions, but use same size per func, so only half
451 * of the table is used.
452 */
453 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
454 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
455 /*
456 * the phys address is shifted right 12 bits and has an added
457 * 1=valid bit added to the 53rd bit
458 * then since this is a wide register(TM)
459 * we split it into two 32 bit writes
460 */
461 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
462 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
463
464 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
465 #define ETH_HLEN 14
466 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
467 #define ETH_MIN_PACKET_SIZE 60
468 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
469 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
470 /* TCP with Timestamp Option (32) + IPv6 (40) */
471 #define ETH_MAX_TPA_HEADER_SIZE 72
472
473 /* max supported alignment is 256 (8 shift) */
474 //#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8)
475 #define BXE_RX_ALIGN_SHIFT 8
476 /* FW uses 2 cache lines alignment for start packet and size */
477 #define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT)
478 #define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT)
479
480 #define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */
481 #define BXE_SET_ERROR_BIT(sc, error) \
482 { \
483 (sc)->error_status |= (error); \
484 }
485
486 struct bxe_bar {
487 struct resource *resource;
488 int rid;
489 bus_space_tag_t tag;
490 bus_space_handle_t handle;
491 vm_offset_t kva;
492 };
493
494 struct bxe_intr {
495 struct resource *resource;
496 int rid;
497 void *tag;
498 };
499
500 /* Used to manage DMA allocations. */
501 struct bxe_dma {
502 struct bxe_softc *sc;
503 bus_addr_t paddr;
504 void *vaddr;
505 bus_dma_tag_t tag;
506 bus_dmamap_t map;
507 bus_dma_segment_t seg;
508 bus_size_t size;
509 int nseg;
510 char msg[32];
511 };
512
513 /* attn group wiring */
514 #define MAX_DYNAMIC_ATTN_GRPS 8
515
516 struct attn_route {
517 uint32_t sig[5];
518 };
519
520 struct iro {
521 uint32_t base;
522 uint16_t m1;
523 uint16_t m2;
524 uint16_t m3;
525 uint16_t size;
526 };
527
528 union bxe_host_hc_status_block {
529 /* pointer to fp status block e2 */
530 struct host_hc_status_block_e2 *e2_sb;
531 /* pointer to fp status block e1x */
532 struct host_hc_status_block_e1x *e1x_sb;
533 };
534
535 union bxe_db_prod {
536 struct doorbell_set_prod data;
537 uint32_t raw;
538 };
539
540 struct bxe_sw_tx_bd {
541 struct mbuf *m;
542 bus_dmamap_t m_map;
543 uint16_t first_bd;
544 uint8_t flags;
545 /* set on the first BD descriptor when there is a split BD */
546 #define BXE_TSO_SPLIT_BD (1 << 0)
547 };
548
549 struct bxe_sw_rx_bd {
550 struct mbuf *m;
551 bus_dmamap_t m_map;
552 };
553
554 struct bxe_sw_tpa_info {
555 struct bxe_sw_rx_bd bd;
556 bus_dma_segment_t seg;
557 uint8_t state;
558 #define BXE_TPA_STATE_START 1
559 #define BXE_TPA_STATE_STOP 2
560 uint8_t placement_offset;
561 uint16_t parsing_flags;
562 uint16_t vlan_tag;
563 uint16_t len_on_bd;
564 };
565
566 /*
567 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
568 * instances of the fastpath structure when using multiple queues.
569 */
570 struct bxe_fastpath {
571 /* pointer back to parent structure */
572 struct bxe_softc *sc;
573
574 struct mtx tx_mtx;
575 char tx_mtx_name[32];
576 struct mtx rx_mtx;
577 char rx_mtx_name[32];
578
579 #define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx)
580 #define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx)
581 #define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED)
582 #define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx)
583
584 #define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx)
585 #define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx)
586 #define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED)
587
588 /* status block */
589 struct bxe_dma sb_dma;
590 union bxe_host_hc_status_block status_block;
591
592 /* transmit chain (tx bds) */
593 struct bxe_dma tx_dma;
594 union eth_tx_bd_types *tx_chain;
595
596 /* receive chain (rx bds) */
597 struct bxe_dma rx_dma;
598 struct eth_rx_bd *rx_chain;
599
600 /* receive completion queue chain (rcq bds) */
601 struct bxe_dma rcq_dma;
602 union eth_rx_cqe *rcq_chain;
603
604 /* receive scatter/gather entry chain (for TPA) */
605 struct bxe_dma rx_sge_dma;
606 struct eth_rx_sge *rx_sge_chain;
607
608 /* tx mbufs */
609 bus_dma_tag_t tx_mbuf_tag;
610 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL];
611
612 /* rx mbufs */
613 bus_dma_tag_t rx_mbuf_tag;
614 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL];
615 bus_dmamap_t rx_mbuf_spare_map;
616
617 /* rx sge mbufs */
618 bus_dma_tag_t rx_sge_mbuf_tag;
619 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL];
620 bus_dmamap_t rx_sge_mbuf_spare_map;
621
622 /* rx tpa mbufs (use the larger size for TPA queue length) */
623 int tpa_enable; /* disabled per fastpath upon error */
624 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
625 bus_dmamap_t rx_tpa_info_mbuf_spare_map;
626 uint64_t rx_tpa_queue_used;
627
628 uint16_t *sb_index_values;
629 uint16_t *sb_running_index;
630 uint32_t ustorm_rx_prods_offset;
631
632 uint8_t igu_sb_id; /* status block number in HW */
633 uint8_t fw_sb_id; /* status block number in FW */
634
635 uint32_t rx_buf_size;
636 int mbuf_alloc_size;
637
638 int state;
639 #define BXE_FP_STATE_CLOSED 0x01
640 #define BXE_FP_STATE_IRQ 0x02
641 #define BXE_FP_STATE_OPENING 0x04
642 #define BXE_FP_STATE_OPEN 0x08
643 #define BXE_FP_STATE_HALTING 0x10
644 #define BXE_FP_STATE_HALTED 0x20
645
646 /* reference back to this fastpath queue number */
647 uint8_t index; /* this is also the 'cid' */
648 #define FP_IDX(fp) (fp->index)
649
650 /* interrupt taskqueue (fast) */
651 struct task tq_task;
652 struct taskqueue *tq;
653 char tq_name[32];
654
655 struct task tx_task;
656 struct timeout_task tx_timeout_task;
657
658 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
659 uint8_t cl_id;
660 #define FP_CL_ID(fp) (fp->cl_id)
661 uint8_t cl_qzone_id;
662
663 uint16_t fp_hc_idx;
664
665 /* driver copy of the receive buffer descriptor prod/cons indices */
666 uint16_t rx_bd_prod;
667 uint16_t rx_bd_cons;
668
669 /* driver copy of the receive completion queue prod/cons indices */
670 uint16_t rx_cq_prod;
671 uint16_t rx_cq_cons;
672
673 union bxe_db_prod tx_db;
674
675 /* Transmit packet producer index (used in eth_tx_bd). */
676 uint16_t tx_pkt_prod;
677 uint16_t tx_pkt_cons;
678
679 /* Transmit buffer descriptor producer index. */
680 uint16_t tx_bd_prod;
681 uint16_t tx_bd_cons;
682
683 uint64_t sge_mask[RX_SGE_MASK_LEN];
684 uint16_t rx_sge_prod;
685
686 struct tstorm_per_queue_stats old_tclient;
687 struct ustorm_per_queue_stats old_uclient;
688 struct xstorm_per_queue_stats old_xclient;
689 struct bxe_eth_q_stats eth_q_stats;
690 struct bxe_eth_q_stats_old eth_q_stats_old;
691
692 /* Pointer to the receive consumer in the status block */
693 uint16_t *rx_cq_cons_sb;
694
695 /* Pointer to the transmit consumer in the status block */
696 uint16_t *tx_cons_sb;
697
698 /* transmit timeout until chip reset */
699 int watchdog_timer;
700
701 /* Free/used buffer descriptor counters. */
702 //uint16_t used_tx_bd;
703
704 /* Last maximal completed SGE */
705 uint16_t last_max_sge;
706
707 //uint16_t rx_sge_free_idx;
708
709 //uint8_t segs;
710
711 #if __FreeBSD_version >= 800000
712 #define BXE_BR_SIZE 4096
713 struct buf_ring *tx_br;
714 #endif
715 }; /* struct bxe_fastpath */
716
717 /* sriov XXX */
718 #define BXE_MAX_NUM_OF_VFS 64
719 #define BXE_VF_CID_WND 0
720 #define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND)
721 #define BXE_CLIENTS_PER_VF 1
722 #define BXE_FIRST_VF_CID 256
723 #define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF)
724 #define BXE_VF_ID_INVALID 0xFF
725 #define IS_SRIOV(sc) 0
726
727 #define GET_NUM_VFS_PER_PATH(sc) 0
728 #define GET_NUM_VFS_PER_PF(sc) 0
729
730 /* maximum number of fast-path interrupt contexts */
731 #define FP_SB_MAX_E1x 16
732 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
733
734 union cdu_context {
735 struct eth_context eth;
736 char pad[1024];
737 };
738
739 /* CDU host DB constants */
740 #define CDU_ILT_PAGE_SZ_HW 2
741 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
742 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
743
744 #define CNIC_ISCSI_CID_MAX 256
745 #define CNIC_FCOE_CID_MAX 2048
746 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
747 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
748
749 #define QM_ILT_PAGE_SZ_HW 0
750 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
751 #define QM_CID_ROUND 1024
752
753 /* TM (timers) host DB constants */
754 #define TM_ILT_PAGE_SZ_HW 0
755 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
756 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
757 #define TM_CONN_NUM 1024
758 #define TM_ILT_SZ (8 * TM_CONN_NUM)
759 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
760
761 /* SRC (Searcher) host DB constants */
762 #define SRC_ILT_PAGE_SZ_HW 0
763 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
764 #define SRC_HASH_BITS 10
765 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
766 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
767 #define SRC_T2_SZ SRC_ILT_SZ
768 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
769
770 struct hw_context {
771 struct bxe_dma vcxt_dma;
772 union cdu_context *vcxt;
773 //bus_addr_t cxt_mapping;
774 size_t size;
775 };
776
777 #define SM_RX_ID 0
778 #define SM_TX_ID 1
779
780 /* defines for multiple tx priority indices */
781 #define FIRST_TX_ONLY_COS_INDEX 1
782 #define FIRST_TX_COS_INDEX 0
783
784 #define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc))
785
786 #define HC_INDEX_ETH_RX_CQ_CONS 1
787 #define HC_INDEX_OOO_TX_CQ_CONS 4
788 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
789 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
790 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
791 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
792
793 /* congestion management fairness mode */
794 #define CMNG_FNS_NONE 0
795 #define CMNG_FNS_MINMAX 1
796
797 /* CMNG constants, as derived from system spec calculations */
798 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
799 #define DEF_MIN_RATE 100
800 /* resolution of the rate shaping timer - 400 usec */
801 #define RS_PERIODIC_TIMEOUT_USEC 400
802 /* number of bytes in single QM arbitration cycle -
803 * coefficient for calculating the fairness timer */
804 #define QM_ARB_BYTES 160000
805 /* resolution of Min algorithm 1:100 */
806 #define MIN_RES 100
807 /* how many bytes above threshold for the minimal credit of Min algorithm*/
808 #define MIN_ABOVE_THRESH 32768
809 /* fairness algorithm integration time coefficient -
810 * for calculating the actual Tfair */
811 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
812 /* memory of fairness algorithm - 2 cycles */
813 #define FAIR_MEM 2
814
815 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
816 #define HC_SEG_ACCESS_ATTN 4
817 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
818
819 /*
820 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
821 * control by the number of fast-path status blocks supported by the
822 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
823 * status block represents an independent interrupts context that can
824 * serve a regular L2 networking queue. However special L2 queues such
825 * as the FCoE queue do not require a FP-SB and other components like
826 * the CNIC may consume FP-SB reducing the number of possible L2 queues
827 *
828 * If the maximum number of FP-SB available is X then:
829 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
830 * regular L2 queues is Y=X-1
831 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
832 * c. If the FCoE L2 queue is supported the actual number of L2 queues
833 * is Y+1
834 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
835 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
836 * FP interrupt context for the CNIC).
837 * e. The number of HW context (CID count) is always X or X+1 if FCoE
838 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
839 *
840 * So this is quite simple for now as no ULPs are supported yet. :-)
841 */
842 #define BXE_NUM_QUEUES(sc) ((sc)->num_queues)
843 #define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc)
844 #define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc)
845 #define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc)
846
847 #define FOR_EACH_QUEUE(sc, var) \
848 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++)
849
850 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
851 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++)
852
853 #define FOR_EACH_ETH_QUEUE(sc, var) \
854 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
855
856 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
857 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
858
859 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
860 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
861
862 #define FOR_EACH_CNIC_QUEUE(sc, var) \
863 for ((var) = BXE_NUM_ETH_QUEUES(sc); \
864 (var) < BXE_NUM_QUEUES(sc); \
865 (var)++)
866
867 enum {
868 OOO_IDX_OFFSET,
869 FCOE_IDX_OFFSET,
870 FWD_IDX_OFFSET,
871 };
872
873 #define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
874 #define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
875 #define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var)
876 #define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
877 #define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var)
878 #define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
879
880 #define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
881 #define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
882 #define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var)
883 #define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
884 #define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var)
885
886 #define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
887 #define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
888 #define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var)
889 #define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
890 #define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var)
891 #define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
892
893 #define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc))
894 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
895 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
896 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
897 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
898 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
899 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
900
901 enum {
902 BXE_PORT_QUERY_IDX,
903 BXE_PF_QUERY_IDX,
904 BXE_FCOE_QUERY_IDX,
905 BXE_FIRST_QUEUE_QUERY_IDX,
906 };
907
908 struct bxe_fw_stats_req {
909 struct stats_query_header hdr;
910 struct stats_query_entry query[FP_SB_MAX_E1x +
911 BXE_FIRST_QUEUE_QUERY_IDX];
912 };
913
914 struct bxe_fw_stats_data {
915 struct stats_counter storm_counters;
916 struct per_port_stats port;
917 struct per_pf_stats pf;
918 //struct fcoe_statistics_params fcoe;
919 struct per_queue_stats queue_stats[1];
920 };
921
922 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
923 #define BXE_IGU_STAS_MSG_VF_CNT 64
924 #define BXE_IGU_STAS_MSG_PF_CNT 4
925
926 #define MAX_DMAE_C 8
927
928 /*
929 * For the main interface up/down code paths, a not-so-fine-grained CORE
930 * mutex lock is used. Inside this code are various calls to kernel routines
931 * that can cause a sleep to occur. Namely memory allocations and taskqueue
932 * handling. If using an MTX lock we are *not* allowed to sleep but we can
933 * with an SX lock. This define forces the CORE lock to use and SX lock.
934 * Undefine this and an MTX lock will be used instead. Note that the IOCTL
935 * path can cause problems since it's called by a non-sleepable thread. To
936 * alleviate a potential sleep, any IOCTL processing that results in the
937 * chip/interface being started/stopped/reinitialized, the actual work is
938 * offloaded to a taskqueue.
939 */
940 #define BXE_CORE_LOCK_SX
941
942 /*
943 * This is the slowpath data structure. It is mapped into non-paged memory
944 * so that the hardware can access it's contents directly and must be page
945 * aligned.
946 */
947 struct bxe_slowpath {
948
949 /* used by the DMAE command executer */
950 struct dmae_cmd dmae[MAX_DMAE_C];
951
952 /* statistics completion */
953 uint32_t stats_comp;
954
955 /* firmware defined statistics blocks */
956 union mac_stats mac_stats;
957 struct nig_stats nig_stats;
958 struct host_port_stats port_stats;
959 struct host_func_stats func_stats;
960 //struct host_func_stats func_stats_base;
961
962 /* DMAE completion value and data source/sink */
963 uint32_t wb_comp;
964 uint32_t wb_data[4];
965
966 union {
967 struct mac_configuration_cmd e1x;
968 struct eth_classify_rules_ramrod_data e2;
969 } mac_rdata;
970
971 union {
972 struct tstorm_eth_mac_filter_config e1x;
973 struct eth_filter_rules_ramrod_data e2;
974 } rx_mode_rdata;
975
976 struct eth_rss_update_ramrod_data rss_rdata;
977
978 union {
979 struct mac_configuration_cmd e1;
980 struct eth_multicast_rules_ramrod_data e2;
981 } mcast_rdata;
982
983 union {
984 struct function_start_data func_start;
985 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
986 } func_rdata;
987
988 /* Queue State related ramrods */
989 union {
990 struct client_init_ramrod_data init_data;
991 struct client_update_ramrod_data update_data;
992 } q_rdata;
993
994 /*
995 * AFEX ramrod can not be a part of func_rdata union because these
996 * events might arrive in parallel to other events from func_rdata.
997 * If they were defined in the same union the data can get corrupted.
998 */
999 struct afex_vif_list_ramrod_data func_afex_rdata;
1000
1001 union drv_info_to_mcp drv_info_to_mcp;
1002 }; /* struct bxe_slowpath */
1003
1004 /*
1005 * Port specifc data structure.
1006 */
1007 struct bxe_port {
1008 /*
1009 * Port Management Function (for 57711E only).
1010 * When this field is set the driver instance is
1011 * responsible for managing port specifc
1012 * configurations such as handling link attentions.
1013 */
1014 uint32_t pmf;
1015
1016 /* Ethernet maximum transmission unit. */
1017 uint16_t ether_mtu;
1018
1019 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
1020
1021 uint32_t ext_phy_config;
1022
1023 /* Port feature config.*/
1024 uint32_t config;
1025
1026 /* Defines the features supported by the PHY. */
1027 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
1028
1029 /* Defines the features advertised by the PHY. */
1030 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
1031 #define ADVERTISED_10baseT_Half (1 << 1)
1032 #define ADVERTISED_10baseT_Full (1 << 2)
1033 #define ADVERTISED_100baseT_Half (1 << 3)
1034 #define ADVERTISED_100baseT_Full (1 << 4)
1035 #define ADVERTISED_1000baseT_Half (1 << 5)
1036 #define ADVERTISED_1000baseT_Full (1 << 6)
1037 #define ADVERTISED_TP (1 << 7)
1038 #define ADVERTISED_FIBRE (1 << 8)
1039 #define ADVERTISED_Autoneg (1 << 9)
1040 #define ADVERTISED_Asym_Pause (1 << 10)
1041 #define ADVERTISED_Pause (1 << 11)
1042 #define ADVERTISED_2500baseX_Full (1 << 15)
1043 #define ADVERTISED_10000baseT_Full (1 << 16)
1044
1045 uint32_t phy_addr;
1046
1047 /* Used to synchronize phy accesses. */
1048 struct mtx phy_mtx;
1049 char phy_mtx_name[32];
1050
1051 #define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx)
1052 #define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx)
1053 #define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED)
1054
1055 /*
1056 * MCP scratchpad address for port specific statistics.
1057 * The device is responsible for writing statistcss
1058 * back to the MCP for use with management firmware such
1059 * as UMP/NC-SI.
1060 */
1061 uint32_t port_stx;
1062
1063 struct nig_stats old_nig_stats;
1064 }; /* struct bxe_port */
1065
1066 struct bxe_mf_info {
1067 uint32_t mf_config[E1HVN_MAX];
1068
1069 uint32_t vnics_per_port; /* 1, 2 or 4 */
1070 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
1071 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
1072
1073 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
1074 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
1075 #define VNICS_PER_PATH(sc) \
1076 ((sc)->devinfo.mf_info.vnics_per_port * \
1077 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
1078
1079 uint8_t min_bw[MAX_VNIC_NUM];
1080 uint8_t max_bw[MAX_VNIC_NUM];
1081
1082 uint16_t ext_id; /* vnic outer vlan or VIF ID */
1083 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
1084 #define INVALID_VIF_ID 0xFFFF
1085 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
1086 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
1087
1088 uint16_t default_vlan;
1089 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
1090
1091 uint8_t niv_allowed_priorities;
1092 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
1093
1094 uint8_t niv_default_cos;
1095 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
1096
1097 uint8_t niv_mba_enabled;
1098
1099 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1100 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
1101 int afex_def_vlan_tag;
1102 uint32_t pending_max;
1103
1104 uint16_t flags;
1105 #define MF_INFO_VALID_MAC 0x0001
1106
1107 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
1108 #define IS_MF(sc) \
1109 (IS_MULTI_VNIC(sc) && \
1110 ((sc)->devinfo.mf_info.mf_mode != 0))
1111 #define IS_MF_SD(sc) \
1112 (IS_MULTI_VNIC(sc) && \
1113 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
1114 #define IS_MF_SI(sc) \
1115 (IS_MULTI_VNIC(sc) && \
1116 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
1117 #define IS_MF_AFEX(sc) \
1118 (IS_MULTI_VNIC(sc) && \
1119 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
1120 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
1121 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
1122 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
1123
1124 uint32_t mf_protos_supported;
1125 #define MF_PROTO_SUPPORT_ETHERNET 0x1
1126 #define MF_PROTO_SUPPORT_ISCSI 0x2
1127 #define MF_PROTO_SUPPORT_FCOE 0x4
1128 }; /* struct bxe_mf_info */
1129
1130 /* Device information data structure. */
1131 struct bxe_devinfo {
1132 /* PCIe info */
1133 uint16_t vendor_id;
1134 uint16_t device_id;
1135 uint16_t subvendor_id;
1136 uint16_t subdevice_id;
1137
1138 /*
1139 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
1140 * C = Chip Number (bits 16-31)
1141 * R = Chip Revision (bits 12-15)
1142 * M = Chip Metal (bits 4-11)
1143 * B = Chip Bond ID (bits 0-3)
1144 */
1145 uint32_t chip_id;
1146 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
1147 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
1148 /* device ids */
1149 #define CHIP_NUM_57710 0x164e
1150 #define CHIP_NUM_57711 0x164f
1151 #define CHIP_NUM_57711E 0x1650
1152 #define CHIP_NUM_57712 0x1662
1153 #define CHIP_NUM_57712_MF 0x1663
1154 #define CHIP_NUM_57712_VF 0x166f
1155 #define CHIP_NUM_57800 0x168a
1156 #define CHIP_NUM_57800_MF 0x16a5
1157 #define CHIP_NUM_57800_VF 0x16a9
1158 #define CHIP_NUM_57810 0x168e
1159 #define CHIP_NUM_57810_MF 0x16ae
1160 #define CHIP_NUM_57810_VF 0x16af
1161 #define CHIP_NUM_57811 0x163d
1162 #define CHIP_NUM_57811_MF 0x163e
1163 #define CHIP_NUM_57811_VF 0x163f
1164 #define CHIP_NUM_57840_OBS 0x168d
1165 #define CHIP_NUM_57840_OBS_MF 0x16ab
1166 #define CHIP_NUM_57840_4_10 0x16a1
1167 #define CHIP_NUM_57840_2_20 0x16a2
1168 #define CHIP_NUM_57840_MF 0x16a4
1169 #define CHIP_NUM_57840_VF 0x16ad
1170
1171 #define CHIP_REV_SHIFT 12
1172 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
1173 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
1174
1175 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
1176 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
1177 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
1178
1179 #define CHIP_REV_IS_SLOW(sc) \
1180 (CHIP_REV(sc) > 0x00005000)
1181 #define CHIP_REV_IS_FPGA(sc) \
1182 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
1183 #define CHIP_REV_IS_EMUL(sc) \
1184 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
1185 #define CHIP_REV_IS_ASIC(sc) \
1186 (!CHIP_REV_IS_SLOW(sc))
1187
1188 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
1189 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
1190
1191 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1192 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1193 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
1194 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
1195 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
1196 (CHIP_IS_57711E(sc)))
1197 #define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \
1198 CHIP_IS_E1H((sc)))
1199
1200 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
1201 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
1202 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
1203 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
1204 CHIP_IS_57712_MF(sc))
1205
1206 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
1207 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
1208 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
1209 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
1210 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
1211 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
1212 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
1213 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
1214 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
1215 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
1216 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
1217 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
1218 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
1219 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
1220 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
1221
1222 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
1223 CHIP_IS_57800_MF(sc) || \
1224 CHIP_IS_57800_VF(sc) || \
1225 CHIP_IS_57810(sc) || \
1226 CHIP_IS_57810_MF(sc) || \
1227 CHIP_IS_57810_VF(sc) || \
1228 CHIP_IS_57811(sc) || \
1229 CHIP_IS_57811_MF(sc) || \
1230 CHIP_IS_57811_VF(sc) || \
1231 CHIP_IS_57840(sc) || \
1232 CHIP_IS_57840_MF(sc) || \
1233 CHIP_IS_57840_VF(sc))
1234 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
1235 (CHIP_REV(sc) == CHIP_REV_Ax))
1236 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
1237 (CHIP_REV(sc) == CHIP_REV_Bx))
1238
1239 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
1240 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
1241 CHIP_IS_E3(sc))
1242
1243 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
1244 CHIP_IS_57712_MF(sc) || \
1245 CHIP_IS_E3(sc))
1246
1247 #define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \
1248 CHIP_IS_57800_VF(sc) || \
1249 CHIP_IS_57810_VF(sc) || \
1250 CHIP_IS_57840_VF(sc))
1251 #define IS_PF(sc) (!IS_VF(sc))
1252
1253 /*
1254 * This define is used in two main places:
1255 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
1256 * to nic-only mode or to offload mode. Offload mode is configured if either
1257 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
1258 * already registered for this port (which means that the user wants storage
1259 * services).
1260 * 2. During cnic-related load, to know if offload mode is already configured
1261 * in the HW or needs to be configrued. Since the transition from nic-mode to
1262 * offload-mode in HW causes traffic coruption, nic-mode is configured only
1263 * in ports on which storage services where never requested.
1264 */
1265 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
1266
1267 uint8_t chip_port_mode;
1268 #define CHIP_4_PORT_MODE 0x0
1269 #define CHIP_2_PORT_MODE 0x1
1270 #define CHIP_PORT_MODE_NONE 0x2
1271 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
1272 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
1273
1274 uint8_t int_block;
1275 #define INT_BLOCK_HC 0
1276 #define INT_BLOCK_IGU 1
1277 #define INT_BLOCK_MODE_NORMAL 0
1278 #define INT_BLOCK_MODE_BW_COMP 2
1279 #define CHIP_INT_MODE_IS_NBC(sc) \
1280 (!CHIP_IS_E1x(sc) && \
1281 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
1282 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
1283
1284 uint32_t shmem_base;
1285 uint32_t shmem2_base;
1286 uint32_t bc_ver;
1287 char bc_ver_str[32];
1288 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
1289 struct bxe_mf_info mf_info;
1290
1291 int flash_size;
1292 #define NVRAM_1MB_SIZE 0x20000
1293 #define NVRAM_TIMEOUT_COUNT 30000
1294 #define NVRAM_PAGE_SIZE 256
1295
1296 /* PCIe capability information */
1297 uint32_t pcie_cap_flags;
1298 #define BXE_PM_CAPABLE_FLAG 0x00000001
1299 #define BXE_PCIE_CAPABLE_FLAG 0x00000002
1300 #define BXE_MSI_CAPABLE_FLAG 0x00000004
1301 #define BXE_MSIX_CAPABLE_FLAG 0x00000008
1302 uint16_t pcie_pm_cap_reg;
1303 uint16_t pcie_pcie_cap_reg;
1304 //uint16_t pcie_devctl;
1305 uint16_t pcie_link_width;
1306 uint16_t pcie_link_speed;
1307 uint16_t pcie_msi_cap_reg;
1308 uint16_t pcie_msix_cap_reg;
1309
1310 /* device configuration read from bootcode shared memory */
1311 uint32_t hw_config;
1312 uint32_t hw_config2;
1313 }; /* struct bxe_devinfo */
1314
1315 struct bxe_sp_objs {
1316 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
1317 struct ecore_queue_sp_obj q_obj; /* Queue State object */
1318 }; /* struct bxe_sp_objs */
1319
1320 /*
1321 * Data that will be used to create a link report message. We will keep the
1322 * data used for the last link report in order to prevent reporting the same
1323 * link parameters twice.
1324 */
1325 struct bxe_link_report_data {
1326 uint16_t line_speed; /* Effective line speed */
1327 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */
1328 };
1329 enum {
1330 BXE_LINK_REPORT_FULL_DUPLEX,
1331 BXE_LINK_REPORT_LINK_DOWN,
1332 BXE_LINK_REPORT_RX_FC_ON,
1333 BXE_LINK_REPORT_TX_FC_ON
1334 };
1335
1336 /* Top level device private data structure. */
1337 struct bxe_softc {
1338 /*
1339 * First entry must be a pointer to the BSD ifnet struct which
1340 * has a first element of 'void *if_softc' (which is us). XXX
1341 */
1342 if_t ifp;
1343 struct ifmedia ifmedia; /* network interface media structure */
1344 int media;
1345
1346 volatile int state; /* device state */
1347 #define BXE_STATE_CLOSED 0x0000
1348 #define BXE_STATE_OPENING_WAITING_LOAD 0x1000
1349 #define BXE_STATE_OPENING_WAITING_PORT 0x2000
1350 #define BXE_STATE_OPEN 0x3000
1351 #define BXE_STATE_CLOSING_WAITING_HALT 0x4000
1352 #define BXE_STATE_CLOSING_WAITING_DELETE 0x5000
1353 #define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000
1354 #define BXE_STATE_DISABLED 0xD000
1355 #define BXE_STATE_DIAG 0xE000
1356 #define BXE_STATE_ERROR 0xF000
1357
1358 int flags;
1359 #define BXE_ONE_PORT_FLAG 0x00000001
1360 #define BXE_NO_ISCSI 0x00000002
1361 #define BXE_NO_FCOE 0x00000004
1362 #define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG)
1363 //#define BXE_NO_WOL_FLAG 0x00000008
1364 //#define BXE_USING_DAC_FLAG 0x00000010
1365 //#define BXE_USING_MSIX_FLAG 0x00000020
1366 //#define BXE_USING_MSI_FLAG 0x00000040
1367 //#define BXE_DISABLE_MSI_FLAG 0x00000080
1368 #define BXE_NO_MCP_FLAG 0x00000200
1369 #define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG)
1370 //#define BXE_SAFC_TX_FLAG 0x00000400
1371 #define BXE_MF_FUNC_DIS 0x00000800
1372 #define BXE_TX_SWITCHING 0x00001000
1373 #define BXE_NO_PULSE 0x00002000
1374
1375 unsigned long debug; /* per-instance debug logging config */
1376
1377 #define MAX_BARS 5
1378 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1379
1380 uint16_t doorbell_size;
1381
1382 /* periodic timer callout */
1383 #define PERIODIC_STOP 0
1384 #define PERIODIC_GO 1
1385 volatile unsigned long periodic_flags;
1386 struct callout periodic_callout;
1387
1388 /* chip start/stop/reset taskqueue */
1389 #define CHIP_TQ_NONE 0
1390 #define CHIP_TQ_START 1
1391 #define CHIP_TQ_STOP 2
1392 #define CHIP_TQ_REINIT 3
1393 volatile unsigned long chip_tq_flags;
1394 struct task chip_tq_task;
1395 struct taskqueue *chip_tq;
1396 char chip_tq_name[32];
1397
1398 struct timeout_task sp_err_timeout_task;
1399
1400 /* slowpath interrupt taskqueue */
1401 struct task sp_tq_task;
1402 struct taskqueue *sp_tq;
1403 char sp_tq_name[32];
1404
1405 struct bxe_fastpath fp[MAX_RSS_CHAINS];
1406 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS];
1407
1408 device_t dev; /* parent device handle */
1409 uint8_t unit; /* driver instance number */
1410
1411 int pcie_bus; /* PCIe bus number */
1412 int pcie_device; /* PCIe device/slot number */
1413 int pcie_func; /* PCIe function number */
1414
1415 uint8_t pfunc_rel; /* function relative */
1416 uint8_t pfunc_abs; /* function absolute */
1417 uint8_t path_id; /* function absolute */
1418 #define SC_PATH(sc) (sc->path_id)
1419 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1420 #define SC_FUNC(sc) (sc->pfunc_rel)
1421 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1422 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1423 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1424 #define PORT_ID(sc) SC_PORT(sc)
1425 #define PATH_ID(sc) SC_PATH(sc)
1426 #define VNIC_ID(sc) SC_VN(sc)
1427 #define FUNC_ID(sc) SC_FUNC(sc)
1428 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1429 #define SC_FW_MB_IDX_VN(sc, vn) \
1430 (SC_PORT(sc) + (vn) * \
1431 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1432 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1433
1434 int if_capen; /* enabled interface capabilities */
1435
1436 struct bxe_devinfo devinfo;
1437 char fw_ver_str[32];
1438 char mf_mode_str[32];
1439 char pci_link_str[32];
1440
1441 const struct iro *iro_array;
1442
1443 #ifdef BXE_CORE_LOCK_SX
1444 struct sx core_sx;
1445 char core_sx_name[32];
1446 #else
1447 struct mtx core_mtx;
1448 char core_mtx_name[32];
1449 #endif
1450 struct mtx sp_mtx;
1451 char sp_mtx_name[32];
1452 struct mtx dmae_mtx;
1453 char dmae_mtx_name[32];
1454 struct mtx fwmb_mtx;
1455 char fwmb_mtx_name[32];
1456 struct mtx print_mtx;
1457 char print_mtx_name[32];
1458 struct mtx stats_mtx;
1459 char stats_mtx_name[32];
1460 struct mtx mcast_mtx;
1461 char mcast_mtx_name[32];
1462
1463 #ifdef BXE_CORE_LOCK_SX
1464 #define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx)
1465 #define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx)
1466 #define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx)
1467 #define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED)
1468 #else
1469 #define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx)
1470 #define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx)
1471 #define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx)
1472 #define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED)
1473 #endif
1474
1475 #define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx)
1476 #define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx)
1477 #define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED)
1478
1479 #define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx)
1480 #define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx)
1481 #define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED)
1482
1483 #define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx)
1484 #define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx)
1485 #define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED)
1486
1487 #define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx)
1488 #define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx)
1489 #define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED)
1490
1491 #define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx)
1492 #define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx)
1493 #define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED)
1494
1495 #if __FreeBSD_version < 800000
1496 #define BXE_MCAST_LOCK(sc) \
1497 do { \
1498 mtx_lock(&sc->mcast_mtx); \
1499 IF_ADDR_LOCK(sc->ifp); \
1500 } while (0)
1501 #define BXE_MCAST_UNLOCK(sc) \
1502 do { \
1503 IF_ADDR_UNLOCK(sc->ifp); \
1504 mtx_unlock(&sc->mcast_mtx); \
1505 } while (0)
1506 #else
1507 #define BXE_MCAST_LOCK(sc) \
1508 do { \
1509 mtx_lock(&sc->mcast_mtx); \
1510 if_maddr_rlock(sc->ifp); \
1511 } while (0)
1512 #define BXE_MCAST_UNLOCK(sc) \
1513 do { \
1514 if_maddr_runlock(sc->ifp); \
1515 mtx_unlock(&sc->mcast_mtx); \
1516 } while (0)
1517 #endif
1518 #define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED)
1519
1520 int dmae_ready;
1521 #define DMAE_READY(sc) (sc->dmae_ready)
1522
1523 struct ecore_credit_pool_obj vlans_pool;
1524 struct ecore_credit_pool_obj macs_pool;
1525 struct ecore_rx_mode_obj rx_mode_obj;
1526 struct ecore_mcast_obj mcast_obj;
1527 struct ecore_rss_config_obj rss_conf_obj;
1528 struct ecore_func_sp_obj func_obj;
1529
1530 uint16_t fw_seq;
1531 uint16_t fw_drv_pulse_wr_seq;
1532 uint32_t func_stx;
1533
1534 struct elink_params link_params;
1535 struct elink_vars link_vars;
1536 uint32_t link_cnt;
1537 struct bxe_link_report_data last_reported_link;
1538 char mac_addr_str[32];
1539
1540 int last_reported_link_state;
1541
1542 int tx_ring_size;
1543 int rx_ring_size;
1544 int wol;
1545
1546 int is_leader;
1547 int recovery_state;
1548 #define BXE_RECOVERY_DONE 1
1549 #define BXE_RECOVERY_INIT 2
1550 #define BXE_RECOVERY_WAIT 3
1551 #define BXE_RECOVERY_FAILED 4
1552 #define BXE_RECOVERY_NIC_LOADING 5
1553
1554 #define BXE_ERR_TXQ_STUCK 0x1 /* Tx queue stuck detected by driver. */
1555 #define BXE_ERR_MISC 0x2 /* MISC ERR */
1556 #define BXE_ERR_PARITY 0x4 /* Parity error detected. */
1557 #define BXE_ERR_STATS_TO 0x8 /* Statistics timeout detected. */
1558 #define BXE_ERR_MC_ASSERT 0x10 /* MC assert attention received. */
1559 #define BXE_ERR_PANIC 0x20 /* Driver asserted. */
1560 #define BXE_ERR_MCP_ASSERT 0x40 /* MCP assert attention received. No Recovery*/
1561 #define BXE_ERR_GLOBAL 0x80 /* PCIe/PXP/IGU/MISC/NIG device blocks error- needs PCIe/Fundamental reset */
1562 uint32_t error_status;
1563
1564 uint32_t rx_mode;
1565 #define BXE_RX_MODE_NONE 0
1566 #define BXE_RX_MODE_NORMAL 1
1567 #define BXE_RX_MODE_ALLMULTI 2
1568 #define BXE_RX_MODE_PROMISC 3
1569 #define BXE_MAX_MULTICAST 64
1570
1571 struct bxe_port port;
1572
1573 struct cmng_init cmng;
1574
1575 /* user configs */
1576 int num_queues;
1577 int max_rx_bufs;
1578 int hc_rx_ticks;
1579 int hc_tx_ticks;
1580 int rx_budget;
1581 int max_aggregation_size;
1582 int mrrs;
1583 int autogreeen;
1584 #define AUTO_GREEN_HW_DEFAULT 0
1585 #define AUTO_GREEN_FORCE_ON 1
1586 #define AUTO_GREEN_FORCE_OFF 2
1587 int interrupt_mode;
1588 #define INTR_MODE_INTX 0
1589 #define INTR_MODE_MSI 1
1590 #define INTR_MODE_MSIX 2
1591 int udp_rss;
1592
1593 /* interrupt allocations */
1594 struct bxe_intr intr[MAX_RSS_CHAINS+1];
1595 int intr_count;
1596 uint8_t igu_dsb_id;
1597 uint8_t igu_base_sb;
1598 uint8_t igu_sb_cnt;
1599 //uint8_t min_msix_vec_cnt;
1600 uint32_t igu_base_addr;
1601 //bus_addr_t def_status_blk_mapping;
1602 uint8_t base_fw_ndsb;
1603 #define DEF_SB_IGU_ID 16
1604 #define DEF_SB_ID HC_SP_SB_ID
1605
1606 /* parent bus DMA tag */
1607 bus_dma_tag_t parent_dma_tag;
1608
1609 /* default status block */
1610 struct bxe_dma def_sb_dma;
1611 struct host_sp_status_block *def_sb;
1612 uint16_t def_idx;
1613 uint16_t def_att_idx;
1614 uint32_t attn_state;
1615 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1616
1617 /* general SP events - stats query, cfc delete, etc */
1618 #define HC_SP_INDEX_ETH_DEF_CONS 3
1619 /* EQ completions */
1620 #define HC_SP_INDEX_EQ_CONS 7
1621 /* FCoE L2 connection completions */
1622 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1623 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1624 /* iSCSI L2 */
1625 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1626 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1627
1628 /* event queue */
1629 struct bxe_dma eq_dma;
1630 union event_ring_elem *eq;
1631 uint16_t eq_prod;
1632 uint16_t eq_cons;
1633 uint16_t *eq_cons_sb;
1634 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1635 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1636 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1637 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1638 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1639 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1640 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1641 #define NEXT_EQ_IDX(x) \
1642 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1643 ((x) + 2) : ((x) + 1))
1644 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1645 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1646
1647 /* slow path */
1648 struct bxe_dma sp_dma;
1649 struct bxe_slowpath *sp;
1650 unsigned long sp_state;
1651
1652 /* slow path queue */
1653 struct bxe_dma spq_dma;
1654 struct eth_spe *spq;
1655 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1656 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1657 #define MAX_SPQ_PENDING 8
1658
1659 uint16_t spq_prod_idx;
1660 struct eth_spe *spq_prod_bd;
1661 struct eth_spe *spq_last_bd;
1662 uint16_t *dsb_sp_prod;
1663 //uint16_t *spq_hw_con;
1664 //uint16_t spq_left;
1665
1666 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1667 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1668
1669 /* fw decompression buffer */
1670 struct bxe_dma gz_buf_dma;
1671 void *gz_buf;
1672 z_streamp gz_strm;
1673 uint32_t gz_outlen;
1674 #define GUNZIP_BUF(sc) (sc->gz_buf)
1675 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1676 #define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr)
1677 #define FW_BUF_SIZE 0x40000
1678
1679 const struct raw_op *init_ops;
1680 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1681 const uint32_t *init_data; /* data blob, 32 bit granularity */
1682 uint32_t init_mode_flags;
1683 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1684 /* PRAM blobs - raw data */
1685 const uint8_t *tsem_int_table_data;
1686 const uint8_t *tsem_pram_data;
1687 const uint8_t *usem_int_table_data;
1688 const uint8_t *usem_pram_data;
1689 const uint8_t *xsem_int_table_data;
1690 const uint8_t *xsem_pram_data;
1691 const uint8_t *csem_int_table_data;
1692 const uint8_t *csem_pram_data;
1693 #define INIT_OPS(sc) (sc->init_ops)
1694 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1695 #define INIT_DATA(sc) (sc->init_data)
1696 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1697 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1698 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1699 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1700 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1701 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1702 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1703 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1704
1705 /* ILT
1706 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1707 * context size we need 8 ILT entries.
1708 */
1709 #define ILT_MAX_L2_LINES 8
1710 struct hw_context context[ILT_MAX_L2_LINES];
1711 struct ecore_ilt *ilt;
1712 #define ILT_MAX_LINES 256
1713
1714 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1715 #define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1716 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1717 #if 1
1718 #define BXE_L2_MAX_CID(sc) \
1719 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1720 #else
1721 #define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \
1722 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1723 #endif
1724 #if 1
1725 #define BXE_L2_CID_COUNT(sc) \
1726 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1727 #else
1728 #define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \
1729 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1730 #endif
1731 #define L2_ILT_LINES(sc) \
1732 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1733
1734 int qm_cid_count;
1735
1736 uint8_t dropless_fc;
1737
1738 /* total number of FW statistics requests */
1739 uint8_t fw_stats_num;
1740 /*
1741 * This is a memory buffer that will contain both statistics ramrod
1742 * request and data.
1743 */
1744 struct bxe_dma fw_stats_dma;
1745 /*
1746 * FW statistics request shortcut (points at the beginning of fw_stats
1747 * buffer).
1748 */
1749 int fw_stats_req_size;
1750 struct bxe_fw_stats_req *fw_stats_req;
1751 bus_addr_t fw_stats_req_mapping;
1752 /*
1753 * FW statistics data shortcut (points at the beginning of fw_stats
1754 * buffer + fw_stats_req_size).
1755 */
1756 int fw_stats_data_size;
1757 struct bxe_fw_stats_data *fw_stats_data;
1758 bus_addr_t fw_stats_data_mapping;
1759
1760 /* tracking a pending STAT_QUERY ramrod */
1761 uint16_t stats_pending;
1762 /* number of completed statistics ramrods */
1763 uint16_t stats_comp;
1764 uint16_t stats_counter;
1765 uint8_t stats_init;
1766 int stats_state;
1767
1768 struct bxe_eth_stats eth_stats;
1769 struct host_func_stats func_stats;
1770 struct bxe_eth_stats_old eth_stats_old;
1771 struct bxe_net_stats_old net_stats_old;
1772 struct bxe_fw_port_stats_old fw_stats_old;
1773
1774 struct dmae_cmd stats_dmae; /* used by dmae command loader */
1775 int executer_idx;
1776
1777 int mtu;
1778
1779 /* LLDP params */
1780 struct bxe_config_lldp_params lldp_config_params;
1781 /* DCB support on/off */
1782 int dcb_state;
1783 #define BXE_DCB_STATE_OFF 0
1784 #define BXE_DCB_STATE_ON 1
1785 /* DCBX engine mode */
1786 int dcbx_enabled;
1787 #define BXE_DCBX_ENABLED_OFF 0
1788 #define BXE_DCBX_ENABLED_ON_NEG_OFF 1
1789 #define BXE_DCBX_ENABLED_ON_NEG_ON 2
1790 #define BXE_DCBX_ENABLED_INVALID -1
1791 uint8_t dcbx_mode_uset;
1792 struct bxe_config_dcbx_params dcbx_config_params;
1793 struct bxe_dcbx_port_params dcbx_port_params;
1794 int dcb_version;
1795
1796 uint8_t cnic_support;
1797 uint8_t cnic_enabled;
1798 uint8_t cnic_loaded;
1799 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1800 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1801 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1802
1803 /* multiple tx classes of service */
1804 uint8_t max_cos;
1805 #define BXE_MAX_PRIORITY 8
1806 /* priority to cos mapping */
1807 uint8_t prio_to_cos[BXE_MAX_PRIORITY];
1808
1809 int panic;
1810
1811 struct cdev *ioctl_dev;
1812
1813 void *grc_dump;
1814 unsigned int trigger_grcdump;
1815 unsigned int grcdump_done;
1816 unsigned int grcdump_started;
1817 int bxe_pause_param;
1818 void *eeprom;
1819 }; /* struct bxe_softc */
1820
1821 /* IOCTL sub-commands for edebug and firmware upgrade */
1822 #define BXE_IOC_RD_NVRAM 1
1823 #define BXE_IOC_WR_NVRAM 2
1824 #define BXE_IOC_STATS_SHOW_NUM 3
1825 #define BXE_IOC_STATS_SHOW_STR 4
1826 #define BXE_IOC_STATS_SHOW_CNT 5
1827
1828 struct bxe_nvram_data {
1829 uint32_t op; /* ioctl sub-command */
1830 uint32_t offset;
1831 uint32_t len;
1832 uint32_t value[1]; /* variable */
1833 };
1834
1835 union bxe_stats_show_data {
1836 uint32_t op; /* ioctl sub-command */
1837
1838 struct {
1839 uint32_t num; /* return number of stats */
1840 uint32_t len; /* length of each string item */
1841 } desc;
1842
1843 /* variable length... */
1844 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1845
1846 /* variable length... */
1847 uint64_t stats[1]; /* holds all stats */
1848 };
1849
1850 /* function init flags */
1851 #define FUNC_FLG_RSS 0x0001
1852 #define FUNC_FLG_STATS 0x0002
1853 /* FUNC_FLG_UNMATCHED 0x0004 */
1854 #define FUNC_FLG_TPA 0x0008
1855 #define FUNC_FLG_SPQ 0x0010
1856 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1857
1858 struct bxe_func_init_params {
1859 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1860 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1861 uint16_t func_flgs;
1862 uint16_t func_id; /* abs function id */
1863 uint16_t pf_id;
1864 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1865 };
1866
1867 /* memory resources reside at BARs 0, 2, 4 */
1868 /* Run `pciconf -lb` to see mappings */
1869 #define BAR0 0
1870 #define BAR1 2
1871 #define BAR2 4
1872
1873 #ifdef BXE_REG_NO_INLINE
1874
1875 uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset);
1876 uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset);
1877 uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset);
1878
1879 void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val);
1880 void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val);
1881 void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val);
1882
1883 #define REG_RD8(sc, offset) bxe_reg_read8(sc, offset)
1884 #define REG_RD16(sc, offset) bxe_reg_read16(sc, offset)
1885 #define REG_RD32(sc, offset) bxe_reg_read32(sc, offset)
1886
1887 #define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val)
1888 #define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val)
1889 #define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val)
1890
1891 #else /* not BXE_REG_NO_INLINE */
1892
1893 #define REG_WR8(sc, offset, val) \
1894 bus_space_write_1(sc->bar[BAR0].tag, \
1895 sc->bar[BAR0].handle, \
1896 offset, val)
1897
1898 #define REG_WR16(sc, offset, val) \
1899 bus_space_write_2(sc->bar[BAR0].tag, \
1900 sc->bar[BAR0].handle, \
1901 offset, val)
1902
1903 #define REG_WR32(sc, offset, val) \
1904 bus_space_write_4(sc->bar[BAR0].tag, \
1905 sc->bar[BAR0].handle, \
1906 offset, val)
1907
1908 #define REG_RD8(sc, offset) \
1909 bus_space_read_1(sc->bar[BAR0].tag, \
1910 sc->bar[BAR0].handle, \
1911 offset)
1912
1913 #define REG_RD16(sc, offset) \
1914 bus_space_read_2(sc->bar[BAR0].tag, \
1915 sc->bar[BAR0].handle, \
1916 offset)
1917
1918 #define REG_RD32(sc, offset) \
1919 bus_space_read_4(sc->bar[BAR0].tag, \
1920 sc->bar[BAR0].handle, \
1921 offset)
1922
1923 #endif /* BXE_REG_NO_INLINE */
1924
1925 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1926 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1927
1928 #define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset)
1929 #define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val)
1930
1931 #define BXE_SP(sc, var) (&(sc)->sp->var)
1932 #define BXE_SP_MAPPING(sc, var) \
1933 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var))
1934
1935 #define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1936 #define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1937
1938 #define REG_RD_DMAE(sc, offset, valp, len32) \
1939 do { \
1940 bxe_read_dmae(sc, offset, len32); \
1941 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \
1942 } while (0)
1943
1944 #define REG_WR_DMAE(sc, offset, valp, len32) \
1945 do { \
1946 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \
1947 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \
1948 } while (0)
1949
1950 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1951 REG_WR_DMAE(sc, offset, valp, len32)
1952
1953 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1954 REG_RD_DMAE(sc, offset, valp, len32)
1955
1956 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1957 do { \
1958 /* if (le32_swap) { */ \
1959 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \
1960 /* } */ \
1961 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1962 ecore_write_big_buf_wb(sc, addr, len32); \
1963 } while (0)
1964
1965 #define BXE_DB_MIN_SHIFT 3 /* 8 bytes */
1966 #define BXE_DB_SHIFT 7 /* 128 bytes */
1967 #if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT)
1968 #error "Minimum DB doorbell stride is 8"
1969 #endif
1970 #define DPM_TRIGGER_TYPE 0x40
1971 #define DOORBELL(sc, cid, val) \
1972 do { \
1973 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \
1974 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \
1975 (uint32_t)val); \
1976 } while(0)
1977
1978 #define SHMEM_ADDR(sc, field) \
1979 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
1980 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1981 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
1982 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1983
1984 #define SHMEM2_ADDR(sc, field) \
1985 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
1986 #define SHMEM2_HAS(sc, field) \
1987 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1988 offsetof(struct shmem2_region, field)))
1989 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1990 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1991
1992 #define MFCFG_ADDR(sc, field) \
1993 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
1994 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1995 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
1996 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
1997
1998 /* DMAE command defines */
1999
2000 #define DMAE_TIMEOUT -1
2001 #define DMAE_PCI_ERROR -2 /* E2 and onward */
2002 #define DMAE_NOT_RDY -3
2003 #define DMAE_PCI_ERR_FLAG 0x80000000
2004
2005 #define DMAE_SRC_PCI 0
2006 #define DMAE_SRC_GRC 1
2007
2008 #define DMAE_DST_NONE 0
2009 #define DMAE_DST_PCI 1
2010 #define DMAE_DST_GRC 2
2011
2012 #define DMAE_COMP_PCI 0
2013 #define DMAE_COMP_GRC 1
2014
2015 #define DMAE_COMP_REGULAR 0
2016 #define DMAE_COM_SET_ERR 1
2017
2018 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT)
2019 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT)
2020 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT)
2021 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT)
2022
2023 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT)
2024 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT)
2025
2026 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT)
2027 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT)
2028 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT)
2029 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT)
2030
2031 #define DMAE_CMD_PORT_0 0
2032 #define DMAE_CMD_PORT_1 DMAE_CMD_PORT
2033
2034 #define DMAE_SRC_PF 0
2035 #define DMAE_SRC_VF 1
2036
2037 #define DMAE_DST_PF 0
2038 #define DMAE_DST_VF 1
2039
2040 #define DMAE_C_SRC 0
2041 #define DMAE_C_DST 1
2042
2043 #define DMAE_LEN32_RD_MAX 0x80
2044 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000)
2045
2046 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
2047
2048 #define MAX_DMAE_C_PER_PORT 8
2049 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
2050 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
2051
2052 static const uint32_t dmae_reg_go_c[] = {
2053 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2054 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2055 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2056 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2057 };
2058
2059 #define ATTN_NIG_FOR_FUNC (1L << 8)
2060 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2061 #define GPIO_2_FUNC (1L << 10)
2062 #define GPIO_3_FUNC (1L << 11)
2063 #define GPIO_4_FUNC (1L << 12)
2064 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2065 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2066 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2067 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2068 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2069 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2070 #define ATTN_HARD_WIRED_MASK 0xff00
2071 #define ATTENTION_ID 4
2072
2073 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
2074 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
2075
2076 #define MAX_IGU_ATTN_ACK_TO 100
2077
2078 #define STORM_ASSERT_ARRAY_SIZE 50
2079
2080 #define BXE_PMF_LINK_ASSERT(sc) \
2081 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
2082
2083 #define BXE_MC_ASSERT_BITS \
2084 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2085 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2086 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2087 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2088
2089 #define BXE_MCP_ASSERT \
2090 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2091
2092 #define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2093 #define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2094 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2095 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2096 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2097 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2098 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2099
2100 #define MULTI_MASK 0x7f
2101
2102 #define PFS_PER_PORT(sc) \
2103 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
2104 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
2105
2106 #define FIRST_ABS_FUNC_IN_PORT(sc) \
2107 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
2108 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
2109
2110 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
2111 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
2112 (i) < MAX_FUNC_NUM; \
2113 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
2114
2115 #define BXE_SWCID_SHIFT 17
2116 #define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1)
2117
2118 #define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK)
2119 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
2120
2121 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
2122 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
2123 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
2124 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
2125 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
2126
2127 /* must be used on a CID before placing it on a HW ring */
2128 #define HW_CID(sc, x) \
2129 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x))
2130
2131 #define SPEED_10 10
2132 #define SPEED_100 100
2133 #define SPEED_1000 1000
2134 #define SPEED_2500 2500
2135 #define SPEED_10000 10000
2136
2137 #define PCI_PM_D0 1
2138 #define PCI_PM_D3hot 2
2139
2140 #ifndef DUPLEX_UNKNOWN
2141 #define DUPLEX_UNKNOWN (0xff)
2142 #endif
2143
2144 #ifndef SPEED_UNKNOWN
2145 #define SPEED_UNKNOWN (-1)
2146 #endif
2147
2148 /* Enable or disable autonegotiation. */
2149 #define AUTONEG_DISABLE 0x00
2150 #define AUTONEG_ENABLE 0x01
2151
2152 /* Which connector port. */
2153 #define PORT_TP 0x00
2154 #define PORT_AUI 0x01
2155 #define PORT_MII 0x02
2156 #define PORT_FIBRE 0x03
2157 #define PORT_BNC 0x04
2158 #define PORT_DA 0x05
2159 #define PORT_NONE 0xef
2160 #define PORT_OTHER 0xff
2161
2162 int bxe_test_bit(int nr, volatile unsigned long * addr);
2163 void bxe_set_bit(unsigned int nr, volatile unsigned long * addr);
2164 void bxe_clear_bit(int nr, volatile unsigned long * addr);
2165 int bxe_test_and_set_bit(int nr, volatile unsigned long * addr);
2166 int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr);
2167 int bxe_cmpxchg(volatile int *addr, int old, int new);
2168
2169 void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr,
2170 uint32_t val);
2171 uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr);
2172
2173
2174 int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size,
2175 struct bxe_dma *dma, const char *msg);
2176 void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma);
2177
2178 uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
2179 uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode);
2180 uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type,
2181 uint8_t dst_type, uint8_t with_comp,
2182 uint8_t comp_type);
2183 void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx);
2184 void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32);
2185 void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr,
2186 uint32_t dst_addr, uint32_t len32);
2187 void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr,
2188 uint32_t addr, uint32_t len);
2189
2190 void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt,
2191 uint32_t cid);
2192 void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id,
2193 uint8_t sb_index, uint8_t disable,
2194 uint16_t usec);
2195
2196 int bxe_sp_post(struct bxe_softc *sc, int command, int cid,
2197 uint32_t data_hi, uint32_t data_lo, int cmd_type);
2198
2199 void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id,
2200 uint8_t segment, uint16_t index, uint8_t op,
2201 uint8_t update);
2202
2203 void ecore_init_e1_firmware(struct bxe_softc *sc);
2204 void ecore_init_e1h_firmware(struct bxe_softc *sc);
2205 void ecore_init_e2_firmware(struct bxe_softc *sc);
2206
2207 void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr,
2208 size_t size, uint32_t *data);
2209
2210 /*********************/
2211 /* LOGGING AND DEBUG */
2212 /*********************/
2213
2214 /* debug logging codepaths */
2215 #define DBG_LOAD 0x00000001 /* load and unload */
2216 #define DBG_INTR 0x00000002 /* interrupt handling */
2217 #define DBG_SP 0x00000004 /* slowpath handling */
2218 #define DBG_STATS 0x00000008 /* stats updates */
2219 #define DBG_TX 0x00000010 /* packet transmit */
2220 #define DBG_RX 0x00000020 /* packet receive */
2221 #define DBG_PHY 0x00000040 /* phy/link handling */
2222 #define DBG_IOCTL 0x00000080 /* ioctl handling */
2223 #define DBG_MBUF 0x00000100 /* dumping mbuf info */
2224 #define DBG_REGS 0x00000200 /* register access */
2225 #define DBG_LRO 0x00000400 /* lro processing */
2226 #define DBG_ASSERT 0x80000000 /* debug assert */
2227 #define DBG_ALL 0xFFFFFFFF /* flying monkeys */
2228
2229 #define DBASSERT(sc, exp, msg) \
2230 do { \
2231 if (__predict_false(sc->debug & DBG_ASSERT)) { \
2232 if (__predict_false(!(exp))) { \
2233 panic msg; \
2234 } \
2235 } \
2236 } while (0)
2237
2238 /* log a debug message */
2239 #define BLOGD(sc, codepath, format, args...) \
2240 do { \
2241 if (__predict_false(sc->debug & (codepath))) { \
2242 device_printf((sc)->dev, \
2243 "%s(%s:%d) " format, \
2244 __FUNCTION__, \
2245 __FILE__, \
2246 __LINE__, \
2247 ## args); \
2248 } \
2249 } while(0)
2250
2251 /* log a info message */
2252 #define BLOGI(sc, format, args...) \
2253 do { \
2254 if (__predict_false(sc->debug)) { \
2255 device_printf((sc)->dev, \
2256 "%s(%s:%d) " format, \
2257 __FUNCTION__, \
2258 __FILE__, \
2259 __LINE__, \
2260 ## args); \
2261 } else { \
2262 device_printf((sc)->dev, \
2263 format, \
2264 ## args); \
2265 } \
2266 } while(0)
2267
2268 /* log a warning message */
2269 #define BLOGW(sc, format, args...) \
2270 do { \
2271 if (__predict_false(sc->debug)) { \
2272 device_printf((sc)->dev, \
2273 "%s(%s:%d) WARNING: " format, \
2274 __FUNCTION__, \
2275 __FILE__, \
2276 __LINE__, \
2277 ## args); \
2278 } else { \
2279 device_printf((sc)->dev, \
2280 "WARNING: " format, \
2281 ## args); \
2282 } \
2283 } while(0)
2284
2285 /* log a error message */
2286 #define BLOGE(sc, format, args...) \
2287 do { \
2288 if (__predict_false(sc->debug)) { \
2289 device_printf((sc)->dev, \
2290 "%s(%s:%d) ERROR: " format, \
2291 __FUNCTION__, \
2292 __FILE__, \
2293 __LINE__, \
2294 ## args); \
2295 } else { \
2296 device_printf((sc)->dev, \
2297 "ERROR: " format, \
2298 ## args); \
2299 } \
2300 } while(0)
2301
2302 #ifdef ECORE_STOP_ON_ERROR
2303
2304 #define bxe_panic(sc, msg) \
2305 do { \
2306 panic msg; \
2307 } while (0)
2308
2309 #else
2310
2311 #define bxe_panic(sc, msg) \
2312 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__);
2313
2314 #endif
2315
2316 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
2317 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
2318
2319 void bxe_dump_mem(struct bxe_softc *sc, char *tag,
2320 uint8_t *mem, uint32_t len);
2321 void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag,
2322 struct mbuf *m, uint8_t contents);
2323
2324 #if __FreeBSD_version >= 800000
2325 #if (__FreeBSD_version >= 1001513 && __FreeBSD_version < 1100000) ||\
2326 __FreeBSD_version >= 1100048
2327 #define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE)
2328 #define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2329 #else
2330 #define BXE_VALID_FLOWID(m) ((m->m_flags & M_FLOWID) != 0)
2331 #define BXE_SET_FLOWID(m) m->m_flags |= M_FLOWID
2332 #endif
2333 #endif /* #if __FreeBSD_version >= 800000 */
2334
2335 /***********/
2336 /* INLINES */
2337 /***********/
2338
2339 static inline uint32_t
reg_poll(struct bxe_softc * sc,uint32_t reg,uint32_t expected,int ms,int wait)2340 reg_poll(struct bxe_softc *sc,
2341 uint32_t reg,
2342 uint32_t expected,
2343 int ms,
2344 int wait)
2345 {
2346 uint32_t val;
2347
2348 do {
2349 val = REG_RD(sc, reg);
2350 if (val == expected) {
2351 break;
2352 }
2353 ms -= wait;
2354 DELAY(wait * 1000);
2355 } while (ms > 0);
2356
2357 return (val);
2358 }
2359
2360 static inline void
bxe_update_fp_sb_idx(struct bxe_fastpath * fp)2361 bxe_update_fp_sb_idx(struct bxe_fastpath *fp)
2362 {
2363 mb(); /* status block is written to by the chip */
2364 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
2365 }
2366
2367 static inline void
bxe_igu_ack_sb_gen(struct bxe_softc * sc,uint8_t igu_sb_id,uint8_t segment,uint16_t index,uint8_t op,uint8_t update,uint32_t igu_addr)2368 bxe_igu_ack_sb_gen(struct bxe_softc *sc,
2369 uint8_t igu_sb_id,
2370 uint8_t segment,
2371 uint16_t index,
2372 uint8_t op,
2373 uint8_t update,
2374 uint32_t igu_addr)
2375 {
2376 struct igu_regular cmd_data = {0};
2377
2378 cmd_data.sb_id_and_flags =
2379 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
2380 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
2381 (update << IGU_REGULAR_BUPDATE_SHIFT) |
2382 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
2383
2384 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n",
2385 cmd_data.sb_id_and_flags, igu_addr);
2386 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
2387
2388 /* Make sure that ACK is written */
2389 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0,
2390 BUS_SPACE_BARRIER_WRITE);
2391 mb();
2392 }
2393
2394 static inline void
bxe_hc_ack_sb(struct bxe_softc * sc,uint8_t sb_id,uint8_t storm,uint16_t index,uint8_t op,uint8_t update)2395 bxe_hc_ack_sb(struct bxe_softc *sc,
2396 uint8_t sb_id,
2397 uint8_t storm,
2398 uint16_t index,
2399 uint8_t op,
2400 uint8_t update)
2401 {
2402 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
2403 COMMAND_REG_INT_ACK);
2404 struct igu_ack_register igu_ack;
2405
2406 igu_ack.status_block_index = index;
2407 igu_ack.sb_id_and_flags =
2408 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2409 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2410 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2411 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2412
2413 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack));
2414
2415 /* Make sure that ACK is written */
2416 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0,
2417 BUS_SPACE_BARRIER_WRITE);
2418 mb();
2419 }
2420
2421 static inline void
bxe_ack_sb(struct bxe_softc * sc,uint8_t igu_sb_id,uint8_t storm,uint16_t index,uint8_t op,uint8_t update)2422 bxe_ack_sb(struct bxe_softc *sc,
2423 uint8_t igu_sb_id,
2424 uint8_t storm,
2425 uint16_t index,
2426 uint8_t op,
2427 uint8_t update)
2428 {
2429 if (sc->devinfo.int_block == INT_BLOCK_HC)
2430 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
2431 else {
2432 uint8_t segment;
2433 if (CHIP_INT_MODE_IS_BC(sc)) {
2434 segment = storm;
2435 } else if (igu_sb_id != sc->igu_dsb_id) {
2436 segment = IGU_SEG_ACCESS_DEF;
2437 } else if (storm == ATTENTION_ID) {
2438 segment = IGU_SEG_ACCESS_ATTN;
2439 } else {
2440 segment = IGU_SEG_ACCESS_DEF;
2441 }
2442 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
2443 }
2444 }
2445
2446 static inline uint16_t
bxe_hc_ack_int(struct bxe_softc * sc)2447 bxe_hc_ack_int(struct bxe_softc *sc)
2448 {
2449 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
2450 COMMAND_REG_SIMD_MASK);
2451 uint32_t result = REG_RD(sc, hc_addr);
2452
2453 mb();
2454 return (result);
2455 }
2456
2457 static inline uint16_t
bxe_igu_ack_int(struct bxe_softc * sc)2458 bxe_igu_ack_int(struct bxe_softc *sc)
2459 {
2460 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
2461 uint32_t result = REG_RD(sc, igu_addr);
2462
2463 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n",
2464 result, igu_addr);
2465
2466 mb();
2467 return (result);
2468 }
2469
2470 static inline uint16_t
bxe_ack_int(struct bxe_softc * sc)2471 bxe_ack_int(struct bxe_softc *sc)
2472 {
2473 mb();
2474 if (sc->devinfo.int_block == INT_BLOCK_HC) {
2475 return (bxe_hc_ack_int(sc));
2476 } else {
2477 return (bxe_igu_ack_int(sc));
2478 }
2479 }
2480
2481 static inline int
func_by_vn(struct bxe_softc * sc,int vn)2482 func_by_vn(struct bxe_softc *sc,
2483 int vn)
2484 {
2485 return (2 * vn + SC_PORT(sc));
2486 }
2487
2488 /*
2489 * Statistics ID are global per chip/path, while Client IDs for E1x
2490 * are per port.
2491 */
2492 static inline uint8_t
bxe_stats_id(struct bxe_fastpath * fp)2493 bxe_stats_id(struct bxe_fastpath *fp)
2494 {
2495 struct bxe_softc *sc = fp->sc;
2496
2497 if (!CHIP_IS_E1x(sc)) {
2498 return (fp->cl_id);
2499 }
2500
2501 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x);
2502 }
2503
2504 #endif /* __BXE_H__ */
2505
2506