1 /*-
2 * Copyright 2014 Luiz Otavio O Souza <[email protected]>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include "opt_evdev.h"
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35
36 #include <sys/conf.h>
37 #include <sys/kernel.h>
38 #include <sys/limits.h>
39 #include <sys/lock.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/condvar.h>
43 #include <sys/resource.h>
44 #include <sys/rman.h>
45 #include <sys/sysctl.h>
46 #include <sys/selinfo.h>
47 #include <sys/poll.h>
48 #include <sys/uio.h>
49
50 #include <machine/bus.h>
51
52 #include <dev/ofw/openfirm.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
55
56 #ifdef EVDEV_SUPPORT
57 #include <dev/evdev/input.h>
58 #include <dev/evdev/evdev.h>
59 #endif
60
61 #include <arm/ti/ti_sysc.h>
62 #include <arm/ti/ti_adcreg.h>
63 #include <arm/ti/ti_adcvar.h>
64
65 #undef DEBUG_TSC
66
67 #define DEFAULT_CHARGE_DELAY 0x400
68 #define STEPDLY_OPEN 0x98
69
70 #define ORDER_XP 0
71 #define ORDER_XN 1
72 #define ORDER_YP 2
73 #define ORDER_YN 3
74
75 /* Define our 8 steps, one for each input channel. */
76 static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = {
77 { .stepconfig = ADC_STEPCFG(1), .stepdelay = ADC_STEPDLY(1) },
78 { .stepconfig = ADC_STEPCFG(2), .stepdelay = ADC_STEPDLY(2) },
79 { .stepconfig = ADC_STEPCFG(3), .stepdelay = ADC_STEPDLY(3) },
80 { .stepconfig = ADC_STEPCFG(4), .stepdelay = ADC_STEPDLY(4) },
81 { .stepconfig = ADC_STEPCFG(5), .stepdelay = ADC_STEPDLY(5) },
82 { .stepconfig = ADC_STEPCFG(6), .stepdelay = ADC_STEPDLY(6) },
83 { .stepconfig = ADC_STEPCFG(7), .stepdelay = ADC_STEPDLY(7) },
84 { .stepconfig = ADC_STEPCFG(8), .stepdelay = ADC_STEPDLY(8) },
85 };
86
87 static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 };
88
89 static int ti_adc_detach(device_t dev);
90
91 #ifdef EVDEV_SUPPORT
92 static void
ti_adc_ev_report(struct ti_adc_softc * sc)93 ti_adc_ev_report(struct ti_adc_softc *sc)
94 {
95
96 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_X, sc->sc_x);
97 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_Y, sc->sc_y);
98 evdev_push_event(sc->sc_evdev, EV_KEY, BTN_TOUCH, sc->sc_pen_down);
99 evdev_sync(sc->sc_evdev);
100 }
101 #endif /* EVDEV */
102
103 static void
ti_adc_enable(struct ti_adc_softc * sc)104 ti_adc_enable(struct ti_adc_softc *sc)
105 {
106 uint32_t reg;
107
108 TI_ADC_LOCK_ASSERT(sc);
109
110 if (sc->sc_last_state == 1)
111 return;
112
113 /* Enable the FIFO0 threshold and the end of sequence interrupt. */
114 ADC_WRITE4(sc, ADC_IRQENABLE_SET,
115 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ);
116
117 reg = ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID;
118 if (sc->sc_tsc_wires > 0) {
119 reg |= ADC_CTRL_TSC_ENABLE;
120 switch (sc->sc_tsc_wires) {
121 case 4:
122 reg |= ADC_CTRL_TSC_4WIRE;
123 break;
124 case 5:
125 reg |= ADC_CTRL_TSC_5WIRE;
126 break;
127 case 8:
128 reg |= ADC_CTRL_TSC_8WIRE;
129 break;
130 default:
131 break;
132 }
133 }
134 reg |= ADC_CTRL_ENABLE;
135 /* Enable the ADC. Run thru enabled steps, start the conversions. */
136 ADC_WRITE4(sc, ADC_CTRL, reg);
137
138 sc->sc_last_state = 1;
139 }
140
141 static void
ti_adc_disable(struct ti_adc_softc * sc)142 ti_adc_disable(struct ti_adc_softc *sc)
143 {
144 int count;
145 uint32_t data;
146
147 TI_ADC_LOCK_ASSERT(sc);
148
149 if (sc->sc_last_state == 0)
150 return;
151
152 /* Disable all the enabled steps. */
153 ADC_WRITE4(sc, ADC_STEPENABLE, 0);
154
155 /* Disable the ADC. */
156 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE);
157
158 /* Disable the FIFO0 threshold and the end of sequence interrupt. */
159 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
160 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ);
161
162 /* ACK any pending interrupt. */
163 ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));
164
165 /* Drain the FIFO data. */
166 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
167 while (count > 0) {
168 data = ADC_READ4(sc, ADC_FIFO0DATA);
169 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
170 }
171
172 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
173 while (count > 0) {
174 data = ADC_READ4(sc, ADC_FIFO1DATA);
175 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
176 }
177
178 sc->sc_last_state = 0;
179 }
180
181 static int
ti_adc_setup(struct ti_adc_softc * sc)182 ti_adc_setup(struct ti_adc_softc *sc)
183 {
184 int ain, i;
185 uint32_t enabled;
186
187 TI_ADC_LOCK_ASSERT(sc);
188
189 /* Check for enabled inputs. */
190 enabled = sc->sc_tsc_enabled;
191 for (i = 0; i < sc->sc_adc_nchannels; i++) {
192 ain = sc->sc_adc_channels[i];
193 if (ti_adc_inputs[ain].enable)
194 enabled |= (1U << (ain + 1));
195 }
196
197 /* Set the ADC global status. */
198 if (enabled != 0) {
199 ti_adc_enable(sc);
200 /* Update the enabled steps. */
201 if (enabled != ADC_READ4(sc, ADC_STEPENABLE))
202 ADC_WRITE4(sc, ADC_STEPENABLE, enabled);
203 } else
204 ti_adc_disable(sc);
205
206 return (0);
207 }
208
209 static void
ti_adc_input_setup(struct ti_adc_softc * sc,int32_t ain)210 ti_adc_input_setup(struct ti_adc_softc *sc, int32_t ain)
211 {
212 struct ti_adc_input *input;
213 uint32_t reg, val;
214
215 TI_ADC_LOCK_ASSERT(sc);
216
217 input = &ti_adc_inputs[ain];
218 reg = input->stepconfig;
219 val = ADC_READ4(sc, reg);
220
221 /* Set single ended operation. */
222 val &= ~ADC_STEP_DIFF_CNTRL;
223
224 /* Set the negative voltage reference. */
225 val &= ~ADC_STEP_RFM_MSK;
226
227 /* Set the positive voltage reference. */
228 val &= ~ADC_STEP_RFP_MSK;
229
230 /* Set the samples average. */
231 val &= ~ADC_STEP_AVG_MSK;
232 val |= input->samples << ADC_STEP_AVG_SHIFT;
233
234 /* Select the desired input. */
235 val &= ~ADC_STEP_INP_MSK;
236 val |= ain << ADC_STEP_INP_SHIFT;
237
238 /* Set the ADC to one-shot mode. */
239 val &= ~ADC_STEP_MODE_MSK;
240
241 ADC_WRITE4(sc, reg, val);
242 }
243
244 static void
ti_adc_reset(struct ti_adc_softc * sc)245 ti_adc_reset(struct ti_adc_softc *sc)
246 {
247 int ain, i;
248
249 TI_ADC_LOCK_ASSERT(sc);
250
251 /* Disable all the inputs. */
252 for (i = 0; i < sc->sc_adc_nchannels; i++) {
253 ain = sc->sc_adc_channels[i];
254 ti_adc_inputs[ain].enable = 0;
255 }
256 }
257
258 static int
ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS)259 ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS)
260 {
261 int error, reg;
262 struct ti_adc_softc *sc;
263
264 sc = (struct ti_adc_softc *)arg1;
265
266 TI_ADC_LOCK(sc);
267 reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1;
268 TI_ADC_UNLOCK(sc);
269
270 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
271 if (error != 0 || req->newptr == NULL)
272 return (error);
273
274 /*
275 * The actual written value is the prescaler setting - 1.
276 * Enforce a minimum value of 10 (i.e. 9) which limits the maximum
277 * ADC clock to ~2.4Mhz (CLK_M_OSC / 10).
278 */
279 reg--;
280 if (reg < 9)
281 reg = 9;
282 if (reg > USHRT_MAX)
283 reg = USHRT_MAX;
284
285 TI_ADC_LOCK(sc);
286 /* Disable the ADC. */
287 ti_adc_disable(sc);
288 /* Update the ADC prescaler setting. */
289 ADC_WRITE4(sc, ADC_CLKDIV, reg);
290 /* Enable the ADC again. */
291 ti_adc_setup(sc);
292 TI_ADC_UNLOCK(sc);
293
294 return (0);
295 }
296
297 static int
ti_adc_enable_proc(SYSCTL_HANDLER_ARGS)298 ti_adc_enable_proc(SYSCTL_HANDLER_ARGS)
299 {
300 int error;
301 int32_t enable;
302 struct ti_adc_softc *sc;
303 struct ti_adc_input *input;
304
305 input = (struct ti_adc_input *)arg1;
306 sc = input->sc;
307
308 enable = input->enable;
309 error = sysctl_handle_int(oidp, &enable, sizeof(enable),
310 req);
311 if (error != 0 || req->newptr == NULL)
312 return (error);
313
314 if (enable)
315 enable = 1;
316
317 TI_ADC_LOCK(sc);
318 /* Setup the ADC as needed. */
319 if (input->enable != enable) {
320 input->enable = enable;
321 ti_adc_setup(sc);
322 if (input->enable == 0)
323 input->value = 0;
324 }
325 TI_ADC_UNLOCK(sc);
326
327 return (0);
328 }
329
330 static int
ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS)331 ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS)
332 {
333 int error, reg;
334 struct ti_adc_softc *sc;
335 struct ti_adc_input *input;
336
337 input = (struct ti_adc_input *)arg1;
338 sc = input->sc;
339
340 TI_ADC_LOCK(sc);
341 reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY;
342 TI_ADC_UNLOCK(sc);
343
344 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
345 if (error != 0 || req->newptr == NULL)
346 return (error);
347
348 if (reg < 0)
349 reg = 0;
350
351 TI_ADC_LOCK(sc);
352 ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY);
353 TI_ADC_UNLOCK(sc);
354
355 return (0);
356 }
357
358 static int
ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS)359 ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS)
360 {
361 int error, samples, i;
362 struct ti_adc_softc *sc;
363 struct ti_adc_input *input;
364
365 input = (struct ti_adc_input *)arg1;
366 sc = input->sc;
367
368 if (input->samples > nitems(ti_adc_samples))
369 input->samples = nitems(ti_adc_samples);
370 samples = ti_adc_samples[input->samples];
371
372 error = sysctl_handle_int(oidp, &samples, 0, req);
373 if (error != 0 || req->newptr == NULL)
374 return (error);
375
376 TI_ADC_LOCK(sc);
377 if (samples != ti_adc_samples[input->samples]) {
378 input->samples = 0;
379 for (i = 0; i < nitems(ti_adc_samples); i++)
380 if (samples >= ti_adc_samples[i])
381 input->samples = i;
382 ti_adc_input_setup(sc, input->input);
383 }
384 TI_ADC_UNLOCK(sc);
385
386 return (error);
387 }
388
389 static void
ti_adc_read_data(struct ti_adc_softc * sc)390 ti_adc_read_data(struct ti_adc_softc *sc)
391 {
392 int count, ain;
393 struct ti_adc_input *input;
394 uint32_t data;
395
396 TI_ADC_LOCK_ASSERT(sc);
397
398 /* Read the available data. */
399 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
400 while (count > 0) {
401 data = ADC_READ4(sc, ADC_FIFO0DATA);
402 ain = (data & ADC_FIFO_STEP_ID_MSK) >> ADC_FIFO_STEP_ID_SHIFT;
403 input = &ti_adc_inputs[ain];
404 if (input->enable == 0)
405 input->value = 0;
406 else
407 input->value = (int32_t)(data & ADC_FIFO_DATA_MSK);
408 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;
409 }
410 }
411
412 static int
cmp_values(const void * a,const void * b)413 cmp_values(const void *a, const void *b)
414 {
415 const uint32_t *v1, *v2;
416 v1 = a;
417 v2 = b;
418 if (*v1 < *v2)
419 return -1;
420 if (*v1 > *v2)
421 return 1;
422
423 return (0);
424 }
425
426 static void
ti_adc_tsc_read_data(struct ti_adc_softc * sc)427 ti_adc_tsc_read_data(struct ti_adc_softc *sc)
428 {
429 int count;
430 uint32_t data[16];
431 uint32_t x, y;
432 int i, start, end;
433
434 TI_ADC_LOCK_ASSERT(sc);
435
436 /* Read the available data. */
437 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
438 if (count == 0)
439 return;
440
441 i = 0;
442 while (count > 0) {
443 data[i++] = ADC_READ4(sc, ADC_FIFO1DATA) & ADC_FIFO_DATA_MSK;
444 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;
445 }
446
447 if (sc->sc_coord_readouts > 3) {
448 start = 1;
449 end = sc->sc_coord_readouts - 1;
450 qsort(data, sc->sc_coord_readouts,
451 sizeof(data[0]), &cmp_values);
452 qsort(&data[sc->sc_coord_readouts + 2],
453 sc->sc_coord_readouts,
454 sizeof(data[0]), &cmp_values);
455 }
456 else {
457 start = 0;
458 end = sc->sc_coord_readouts;
459 }
460
461 x = y = 0;
462 for (i = start; i < end; i++)
463 y += data[i];
464 y /= (end - start);
465
466 for (i = sc->sc_coord_readouts + 2 + start; i < sc->sc_coord_readouts + 2 + end; i++)
467 x += data[i];
468 x /= (end - start);
469
470 #ifdef DEBUG_TSC
471 device_printf(sc->sc_dev, "touchscreen x: %d, y: %d\n", x, y);
472 #endif
473
474 #ifdef EVDEV_SUPPORT
475 if ((sc->sc_x != x) || (sc->sc_y != y)) {
476 sc->sc_x = x;
477 sc->sc_y = y;
478 ti_adc_ev_report(sc);
479 }
480 #endif
481 }
482
483 static void
ti_adc_intr_locked(struct ti_adc_softc * sc,uint32_t status)484 ti_adc_intr_locked(struct ti_adc_softc *sc, uint32_t status)
485 {
486 /* Read the available data. */
487 if (status & ADC_IRQ_FIFO0_THRES)
488 ti_adc_read_data(sc);
489 }
490
491 static void
ti_adc_tsc_intr_locked(struct ti_adc_softc * sc,uint32_t status)492 ti_adc_tsc_intr_locked(struct ti_adc_softc *sc, uint32_t status)
493 {
494 /* Read the available data. */
495 if (status & ADC_IRQ_FIFO1_THRES)
496 ti_adc_tsc_read_data(sc);
497
498 }
499
500 static void
ti_adc_intr(void * arg)501 ti_adc_intr(void *arg)
502 {
503 struct ti_adc_softc *sc;
504 uint32_t status, rawstatus;
505
506 sc = (struct ti_adc_softc *)arg;
507
508 TI_ADC_LOCK(sc);
509
510 rawstatus = ADC_READ4(sc, ADC_IRQSTATUS_RAW);
511 status = ADC_READ4(sc, ADC_IRQSTATUS);
512
513 if (rawstatus & ADC_IRQ_HW_PEN_ASYNC) {
514 sc->sc_pen_down = 1;
515 status |= ADC_IRQ_HW_PEN_ASYNC;
516 ADC_WRITE4(sc, ADC_IRQENABLE_CLR,
517 ADC_IRQ_HW_PEN_ASYNC);
518 #ifdef EVDEV_SUPPORT
519 ti_adc_ev_report(sc);
520 #endif
521 }
522
523 if (rawstatus & ADC_IRQ_PEN_UP) {
524 sc->sc_pen_down = 0;
525 status |= ADC_IRQ_PEN_UP;
526 #ifdef EVDEV_SUPPORT
527 ti_adc_ev_report(sc);
528 #endif
529 }
530
531 if (status & ADC_IRQ_FIFO0_THRES)
532 ti_adc_intr_locked(sc, status);
533
534 if (status & ADC_IRQ_FIFO1_THRES)
535 ti_adc_tsc_intr_locked(sc, status);
536
537 if (status) {
538 /* ACK the interrupt. */
539 ADC_WRITE4(sc, ADC_IRQSTATUS, status);
540 }
541
542 /* Start the next conversion ? */
543 if (status & ADC_IRQ_END_OF_SEQ)
544 ti_adc_setup(sc);
545
546 TI_ADC_UNLOCK(sc);
547 }
548
549 static void
ti_adc_sysctl_init(struct ti_adc_softc * sc)550 ti_adc_sysctl_init(struct ti_adc_softc *sc)
551 {
552 char pinbuf[3];
553 struct sysctl_ctx_list *ctx;
554 struct sysctl_oid *tree_node, *inp_node, *inpN_node;
555 struct sysctl_oid_list *tree, *inp_tree, *inpN_tree;
556 int ain, i;
557
558 /*
559 * Add per-pin sysctl tree/handlers.
560 */
561 ctx = device_get_sysctl_ctx(sc->sc_dev);
562 tree_node = device_get_sysctl_tree(sc->sc_dev);
563 tree = SYSCTL_CHILDREN(tree_node);
564 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clockdiv",
565 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, sc, 0,
566 ti_adc_clockdiv_proc, "IU", "ADC clock prescaler");
567 inp_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "ain",
568 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ADC inputs");
569 inp_tree = SYSCTL_CHILDREN(inp_node);
570
571 for (i = 0; i < sc->sc_adc_nchannels; i++) {
572 ain = sc->sc_adc_channels[i];
573
574 snprintf(pinbuf, sizeof(pinbuf), "%d", ain);
575 inpN_node = SYSCTL_ADD_NODE(ctx, inp_tree, OID_AUTO, pinbuf,
576 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ADC input");
577 inpN_tree = SYSCTL_CHILDREN(inpN_node);
578
579 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "enable",
580 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
581 &ti_adc_inputs[ain], 0,
582 ti_adc_enable_proc, "IU", "Enable ADC input");
583 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "open_delay",
584 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
585 &ti_adc_inputs[ain], 0,
586 ti_adc_open_delay_proc, "IU", "ADC open delay");
587 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "samples_avg",
588 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT,
589 &ti_adc_inputs[ain], 0,
590 ti_adc_samples_avg_proc, "IU", "ADC samples average");
591 SYSCTL_ADD_INT(ctx, inpN_tree, OID_AUTO, "input",
592 CTLFLAG_RD, &ti_adc_inputs[ain].value, 0,
593 "Converted raw value for the ADC input");
594 }
595 }
596
597 static void
ti_adc_inputs_init(struct ti_adc_softc * sc)598 ti_adc_inputs_init(struct ti_adc_softc *sc)
599 {
600 int ain, i;
601 struct ti_adc_input *input;
602
603 TI_ADC_LOCK(sc);
604 for (i = 0; i < sc->sc_adc_nchannels; i++) {
605 ain = sc->sc_adc_channels[i];
606 input = &ti_adc_inputs[ain];
607 input->sc = sc;
608 input->input = ain;
609 input->value = 0;
610 input->enable = 0;
611 input->samples = 0;
612 ti_adc_input_setup(sc, ain);
613 }
614 TI_ADC_UNLOCK(sc);
615 }
616
617 static void
ti_adc_tsc_init(struct ti_adc_softc * sc)618 ti_adc_tsc_init(struct ti_adc_softc *sc)
619 {
620 int i, start_step, end_step;
621 uint32_t stepconfig, val;
622
623 TI_ADC_LOCK(sc);
624
625 /* X coordinates */
626 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
627 ADC_STEP_MODE_HW_ONESHOT | sc->sc_xp_bit;
628 if (sc->sc_tsc_wires == 4)
629 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit;
630 else if (sc->sc_tsc_wires == 5)
631 stepconfig |= ADC_STEP_INP(4) |
632 sc->sc_xn_bit | sc->sc_yn_bit | sc->sc_yp_bit;
633 else if (sc->sc_tsc_wires == 8)
634 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit;
635
636 start_step = ADC_STEPS - sc->sc_coord_readouts + 1;
637 end_step = start_step + sc->sc_coord_readouts - 1;
638 for (i = start_step; i <= end_step; i++) {
639 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
640 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
641 }
642
643 /* Y coordinates */
644 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
645 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yn_bit |
646 ADC_STEP_INM(8);
647 if (sc->sc_tsc_wires == 4)
648 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit;
649 else if (sc->sc_tsc_wires == 5)
650 stepconfig |= ADC_STEP_INP(4) |
651 sc->sc_xp_bit | sc->sc_xn_bit | sc->sc_yp_bit;
652 else if (sc->sc_tsc_wires == 8)
653 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit;
654
655 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1;
656 end_step = start_step + sc->sc_coord_readouts - 1;
657 for (i = start_step; i <= end_step; i++) {
658 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig);
659 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN);
660 }
661
662 /* Charge config */
663 val = ADC_READ4(sc, ADC_IDLECONFIG);
664 ADC_WRITE4(sc, ADC_TC_CHARGE_STEPCONFIG, val);
665 ADC_WRITE4(sc, ADC_TC_CHARGE_DELAY, sc->sc_charge_delay);
666
667 /* 2 steps for Z */
668 start_step = ADC_STEPS - (sc->sc_coord_readouts + 2) + 1;
669 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) |
670 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yp_bit |
671 sc->sc_xn_bit | ADC_STEP_INP(sc->sc_xp_inp) |
672 ADC_STEP_INM(8);
673 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
674 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
675 start_step++;
676 stepconfig |= ADC_STEP_INP(sc->sc_yn_inp);
677 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig);
678 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN);
679
680 ADC_WRITE4(sc, ADC_FIFO1THRESHOLD, (sc->sc_coord_readouts*2 + 2) - 1);
681
682 sc->sc_tsc_enabled = 1;
683 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1;
684 end_step = ADC_STEPS;
685 for (i = start_step; i <= end_step; i++) {
686 sc->sc_tsc_enabled |= (1 << i);
687 }
688
689 TI_ADC_UNLOCK(sc);
690 }
691
692 static void
ti_adc_idlestep_init(struct ti_adc_softc * sc)693 ti_adc_idlestep_init(struct ti_adc_softc *sc)
694 {
695 uint32_t val;
696
697 val = ADC_STEP_YNN_SW | ADC_STEP_INM(8) | ADC_STEP_INP(8) | ADC_STEP_YPN_SW;
698
699 ADC_WRITE4(sc, ADC_IDLECONFIG, val);
700 }
701
702 static int
ti_adc_config_wires(struct ti_adc_softc * sc,int * wire_configs,int nwire_configs)703 ti_adc_config_wires(struct ti_adc_softc *sc, int *wire_configs, int nwire_configs)
704 {
705 int i;
706 int wire, ai;
707
708 for (i = 0; i < nwire_configs; i++) {
709 wire = wire_configs[i] & 0xf;
710 ai = (wire_configs[i] >> 4) & 0xf;
711 switch (wire) {
712 case ORDER_XP:
713 sc->sc_xp_bit = ADC_STEP_XPP_SW;
714 sc->sc_xp_inp = ai;
715 break;
716 case ORDER_XN:
717 sc->sc_xn_bit = ADC_STEP_XNN_SW;
718 sc->sc_xn_inp = ai;
719 break;
720 case ORDER_YP:
721 sc->sc_yp_bit = ADC_STEP_YPP_SW;
722 sc->sc_yp_inp = ai;
723 break;
724 case ORDER_YN:
725 sc->sc_yn_bit = ADC_STEP_YNN_SW;
726 sc->sc_yn_inp = ai;
727 break;
728 default:
729 device_printf(sc->sc_dev, "Invalid wire config\n");
730 return (-1);
731 }
732 }
733 return (0);
734 }
735
736 static int
ti_adc_probe(device_t dev)737 ti_adc_probe(device_t dev)
738 {
739
740 if (!ofw_bus_is_compatible(dev, "ti,am3359-tscadc"))
741 return (ENXIO);
742 device_set_desc(dev, "TI ADC controller");
743
744 return (BUS_PROBE_DEFAULT);
745 }
746
747 static int
ti_adc_attach(device_t dev)748 ti_adc_attach(device_t dev)
749 {
750 int err, rid, i;
751 struct ti_adc_softc *sc;
752 uint32_t rev, reg;
753 phandle_t node, child;
754 pcell_t cell;
755 int *channels;
756 int nwire_configs;
757 int *wire_configs;
758
759 sc = device_get_softc(dev);
760 sc->sc_dev = dev;
761
762 node = ofw_bus_get_node(dev);
763
764 sc->sc_tsc_wires = 0;
765 sc->sc_coord_readouts = 1;
766 sc->sc_x_plate_resistance = 0;
767 sc->sc_charge_delay = DEFAULT_CHARGE_DELAY;
768 /* Read "tsc" node properties */
769 child = ofw_bus_find_child(node, "tsc");
770 if (child != 0 && OF_hasprop(child, "ti,wires")) {
771 if ((OF_getencprop(child, "ti,wires", &cell, sizeof(cell))) > 0)
772 sc->sc_tsc_wires = cell;
773 if ((OF_getencprop(child, "ti,coordinate-readouts", &cell,
774 sizeof(cell))) > 0)
775 sc->sc_coord_readouts = cell;
776 if ((OF_getencprop(child, "ti,x-plate-resistance", &cell,
777 sizeof(cell))) > 0)
778 sc->sc_x_plate_resistance = cell;
779 if ((OF_getencprop(child, "ti,charge-delay", &cell,
780 sizeof(cell))) > 0)
781 sc->sc_charge_delay = cell;
782 nwire_configs = OF_getencprop_alloc_multi(child,
783 "ti,wire-config", sizeof(*wire_configs),
784 (void **)&wire_configs);
785 if (nwire_configs != sc->sc_tsc_wires) {
786 device_printf(sc->sc_dev,
787 "invalid number of ti,wire-config: %d (should be %d)\n",
788 nwire_configs, sc->sc_tsc_wires);
789 OF_prop_free(wire_configs);
790 return (EINVAL);
791 }
792 err = ti_adc_config_wires(sc, wire_configs, nwire_configs);
793 OF_prop_free(wire_configs);
794 if (err)
795 return (EINVAL);
796 }
797
798 /* Read "adc" node properties */
799 child = ofw_bus_find_child(node, "adc");
800 if (child != 0) {
801 sc->sc_adc_nchannels = OF_getencprop_alloc_multi(child,
802 "ti,adc-channels", sizeof(*channels), (void **)&channels);
803 if (sc->sc_adc_nchannels > 0) {
804 for (i = 0; i < sc->sc_adc_nchannels; i++)
805 sc->sc_adc_channels[i] = channels[i];
806 OF_prop_free(channels);
807 }
808 }
809
810 /* Sanity check FDT data */
811 if (sc->sc_tsc_wires + sc->sc_adc_nchannels > TI_ADC_NPINS) {
812 device_printf(dev, "total number of channels (%d) is larger than %d\n",
813 sc->sc_tsc_wires + sc->sc_adc_nchannels, TI_ADC_NPINS);
814 return (ENXIO);
815 }
816
817 rid = 0;
818 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
819 RF_ACTIVE);
820 if (!sc->sc_mem_res) {
821 device_printf(dev, "cannot allocate memory window\n");
822 return (ENXIO);
823 }
824
825 /* Activate the ADC_TSC module. */
826 err = ti_sysc_clock_enable(device_get_parent(dev));
827 if (err)
828 return (err);
829
830 rid = 0;
831 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
832 RF_ACTIVE);
833 if (!sc->sc_irq_res) {
834 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
835 device_printf(dev, "cannot allocate interrupt\n");
836 return (ENXIO);
837 }
838
839 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
840 NULL, ti_adc_intr, sc, &sc->sc_intrhand) != 0) {
841 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
842 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
843 device_printf(dev, "Unable to setup the irq handler.\n");
844 return (ENXIO);
845 }
846
847 /* Check the ADC revision. */
848 rev = ADC_READ4(sc, ti_sysc_get_rev_address_offset_host(device_get_parent(dev)));
849 device_printf(dev,
850 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n",
851 (rev & ADC_REV_SCHEME_MSK) >> ADC_REV_SCHEME_SHIFT,
852 (rev & ADC_REV_FUNC_MSK) >> ADC_REV_FUNC_SHIFT,
853 (rev & ADC_REV_RTL_MSK) >> ADC_REV_RTL_SHIFT,
854 (rev & ADC_REV_MAJOR_MSK) >> ADC_REV_MAJOR_SHIFT,
855 rev & ADC_REV_MINOR_MSK,
856 (rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT);
857
858 reg = ADC_READ4(sc, ADC_CTRL);
859 ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID);
860
861 /*
862 * Set the ADC prescaler to 2400 if touchscreen is not enabled
863 * and to 24 if it is. This sets the ADC clock to ~10Khz and
864 * ~1Mhz respectively (CLK_M_OSC / prescaler).
865 */
866 if (sc->sc_tsc_wires)
867 ADC_WRITE4(sc, ADC_CLKDIV, 24 - 1);
868 else
869 ADC_WRITE4(sc, ADC_CLKDIV, 2400 - 1);
870
871 TI_ADC_LOCK_INIT(sc);
872
873 ti_adc_idlestep_init(sc);
874 ti_adc_inputs_init(sc);
875 ti_adc_sysctl_init(sc);
876 ti_adc_tsc_init(sc);
877
878 TI_ADC_LOCK(sc);
879 ti_adc_setup(sc);
880 TI_ADC_UNLOCK(sc);
881
882 #ifdef EVDEV_SUPPORT
883 if (sc->sc_tsc_wires > 0) {
884 sc->sc_evdev = evdev_alloc();
885 evdev_set_name(sc->sc_evdev, device_get_desc(dev));
886 evdev_set_phys(sc->sc_evdev, device_get_nameunit(dev));
887 evdev_set_id(sc->sc_evdev, BUS_VIRTUAL, 0, 0, 0);
888 evdev_support_prop(sc->sc_evdev, INPUT_PROP_DIRECT);
889 evdev_support_event(sc->sc_evdev, EV_SYN);
890 evdev_support_event(sc->sc_evdev, EV_ABS);
891 evdev_support_event(sc->sc_evdev, EV_KEY);
892
893 evdev_support_abs(sc->sc_evdev, ABS_X, 0,
894 ADC_MAX_VALUE, 0, 0, 0);
895 evdev_support_abs(sc->sc_evdev, ABS_Y, 0,
896 ADC_MAX_VALUE, 0, 0, 0);
897
898 evdev_support_key(sc->sc_evdev, BTN_TOUCH);
899
900 err = evdev_register(sc->sc_evdev);
901 if (err) {
902 device_printf(dev,
903 "failed to register evdev: error=%d\n", err);
904 ti_adc_detach(dev);
905 return (err);
906 }
907
908 sc->sc_pen_down = 0;
909 sc->sc_x = -1;
910 sc->sc_y = -1;
911 }
912 #endif /* EVDEV */
913
914 return (0);
915 }
916
917 static int
ti_adc_detach(device_t dev)918 ti_adc_detach(device_t dev)
919 {
920 struct ti_adc_softc *sc;
921
922 sc = device_get_softc(dev);
923
924 /* Turn off the ADC. */
925 TI_ADC_LOCK(sc);
926 ti_adc_reset(sc);
927 ti_adc_setup(sc);
928
929 #ifdef EVDEV_SUPPORT
930 evdev_free(sc->sc_evdev);
931 #endif
932
933 TI_ADC_UNLOCK(sc);
934
935 TI_ADC_LOCK_DESTROY(sc);
936
937 if (sc->sc_intrhand)
938 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
939 if (sc->sc_irq_res)
940 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
941 if (sc->sc_mem_res)
942 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
943
944 return (bus_generic_detach(dev));
945 }
946
947 static device_method_t ti_adc_methods[] = {
948 DEVMETHOD(device_probe, ti_adc_probe),
949 DEVMETHOD(device_attach, ti_adc_attach),
950 DEVMETHOD(device_detach, ti_adc_detach),
951
952 DEVMETHOD_END
953 };
954
955 static driver_t ti_adc_driver = {
956 "ti_adc",
957 ti_adc_methods,
958 sizeof(struct ti_adc_softc),
959 };
960
961 static devclass_t ti_adc_devclass;
962
963 DRIVER_MODULE(ti_adc, simplebus, ti_adc_driver, ti_adc_devclass, 0, 0);
964 MODULE_VERSION(ti_adc, 1);
965 MODULE_DEPEND(ti_adc, simplebus, 1, 1, 1);
966 MODULE_DEPEND(ti_adc, ti_sysc, 1, 1, 1);
967 #ifdef EVDEV_SUPPORT
968 MODULE_DEPEND(ti_adc, evdev, 1, 1, 1);
969 #endif
970