1 /*-
2 * Copyright (C) 2012 Intel Corporation
3 * All rights reserved.
4 * Copyright (C) 2018 Alexander Motin <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30
31 #include "opt_ddb.h"
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/conf.h>
37 #include <sys/fail.h>
38 #include <sys/ioccom.h>
39 #include <sys/kernel.h>
40 #include <sys/lock.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/rman.h>
45 #include <sys/sbuf.h>
46 #include <sys/sysctl.h>
47 #include <sys/taskqueue.h>
48 #include <sys/time.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcivar.h>
51 #include <machine/bus.h>
52 #include <machine/resource.h>
53 #include <machine/stdarg.h>
54
55 #ifdef DDB
56 #include <ddb/ddb.h>
57 #endif
58
59 #include "ioat.h"
60 #include "ioat_hw.h"
61 #include "ioat_internal.h"
62
63 #ifndef BUS_SPACE_MAXADDR_40BIT
64 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL
65 #endif
66
67 static int ioat_probe(device_t device);
68 static int ioat_attach(device_t device);
69 static int ioat_detach(device_t device);
70 static int ioat_setup_intr(struct ioat_softc *ioat);
71 static int ioat_teardown_intr(struct ioat_softc *ioat);
72 static int ioat3_attach(device_t device);
73 static int ioat_start_channel(struct ioat_softc *ioat);
74 static int ioat_map_pci_bar(struct ioat_softc *ioat);
75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg,
76 int error);
77 static void ioat_interrupt_handler(void *arg);
78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat);
79 static int chanerr_to_errno(uint32_t);
80 static void ioat_process_events(struct ioat_softc *ioat, boolean_t intr);
81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat);
82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat);
83 static void ioat_free_ring(struct ioat_softc *, uint32_t size,
84 struct ioat_descriptor *);
85 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags);
86 static union ioat_hw_descriptor *ioat_get_descriptor(struct ioat_softc *,
87 uint32_t index);
88 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *,
89 uint32_t index);
90 static void ioat_halted_debug(struct ioat_softc *, uint32_t);
91 static void ioat_poll_timer_callback(void *arg);
92 static void dump_descriptor(void *hw_desc);
93 static void ioat_submit_single(struct ioat_softc *ioat);
94 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg,
95 int error);
96 static int ioat_reset_hw(struct ioat_softc *ioat);
97 static void ioat_reset_hw_task(void *, int);
98 static void ioat_setup_sysctl(device_t device);
99 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS);
100 static void ioat_get(struct ioat_softc *);
101 static void ioat_put(struct ioat_softc *);
102 static void ioat_drain_locked(struct ioat_softc *);
103
104 #define ioat_log_message(v, ...) do { \
105 if ((v) <= g_ioat_debug_level) { \
106 device_printf(ioat->device, __VA_ARGS__); \
107 } \
108 } while (0)
109
110 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations");
111 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node");
112
113 static int g_force_legacy_interrupts;
114 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN,
115 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled");
116
117 int g_ioat_debug_level = 0;
118 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level,
119 0, "Set log level (0-3) for ioat(4). Higher is more verbose.");
120
121 unsigned g_ioat_ring_order = 13;
122 SYSCTL_UINT(_hw_ioat, OID_AUTO, ring_order, CTLFLAG_RDTUN, &g_ioat_ring_order,
123 0, "Set IOAT ring order. (1 << this) == ring size.");
124
125 /*
126 * OS <-> Driver interface structures
127 */
128 static device_method_t ioat_pci_methods[] = {
129 /* Device interface */
130 DEVMETHOD(device_probe, ioat_probe),
131 DEVMETHOD(device_attach, ioat_attach),
132 DEVMETHOD(device_detach, ioat_detach),
133 DEVMETHOD_END
134 };
135
136 static driver_t ioat_pci_driver = {
137 "ioat",
138 ioat_pci_methods,
139 sizeof(struct ioat_softc),
140 };
141
142 static devclass_t ioat_devclass;
143 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0);
144 MODULE_VERSION(ioat, 1);
145
146 /*
147 * Private data structures
148 */
149 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS];
150 static unsigned ioat_channel_index = 0;
151 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0,
152 "Number of IOAT channels attached");
153 static struct mtx ioat_list_mtx;
154 MTX_SYSINIT(ioat_list_mtx, &ioat_list_mtx, "ioat list mtx", MTX_DEF);
155
156 static struct _pcsid
157 {
158 u_int32_t type;
159 const char *desc;
160 } pci_ids[] = {
161 { 0x34308086, "TBG IOAT Ch0" },
162 { 0x34318086, "TBG IOAT Ch1" },
163 { 0x34328086, "TBG IOAT Ch2" },
164 { 0x34338086, "TBG IOAT Ch3" },
165 { 0x34298086, "TBG IOAT Ch4" },
166 { 0x342a8086, "TBG IOAT Ch5" },
167 { 0x342b8086, "TBG IOAT Ch6" },
168 { 0x342c8086, "TBG IOAT Ch7" },
169
170 { 0x37108086, "JSF IOAT Ch0" },
171 { 0x37118086, "JSF IOAT Ch1" },
172 { 0x37128086, "JSF IOAT Ch2" },
173 { 0x37138086, "JSF IOAT Ch3" },
174 { 0x37148086, "JSF IOAT Ch4" },
175 { 0x37158086, "JSF IOAT Ch5" },
176 { 0x37168086, "JSF IOAT Ch6" },
177 { 0x37178086, "JSF IOAT Ch7" },
178 { 0x37188086, "JSF IOAT Ch0 (RAID)" },
179 { 0x37198086, "JSF IOAT Ch1 (RAID)" },
180
181 { 0x3c208086, "SNB IOAT Ch0" },
182 { 0x3c218086, "SNB IOAT Ch1" },
183 { 0x3c228086, "SNB IOAT Ch2" },
184 { 0x3c238086, "SNB IOAT Ch3" },
185 { 0x3c248086, "SNB IOAT Ch4" },
186 { 0x3c258086, "SNB IOAT Ch5" },
187 { 0x3c268086, "SNB IOAT Ch6" },
188 { 0x3c278086, "SNB IOAT Ch7" },
189 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" },
190 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" },
191
192 { 0x0e208086, "IVB IOAT Ch0" },
193 { 0x0e218086, "IVB IOAT Ch1" },
194 { 0x0e228086, "IVB IOAT Ch2" },
195 { 0x0e238086, "IVB IOAT Ch3" },
196 { 0x0e248086, "IVB IOAT Ch4" },
197 { 0x0e258086, "IVB IOAT Ch5" },
198 { 0x0e268086, "IVB IOAT Ch6" },
199 { 0x0e278086, "IVB IOAT Ch7" },
200 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" },
201 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" },
202
203 { 0x2f208086, "HSW IOAT Ch0" },
204 { 0x2f218086, "HSW IOAT Ch1" },
205 { 0x2f228086, "HSW IOAT Ch2" },
206 { 0x2f238086, "HSW IOAT Ch3" },
207 { 0x2f248086, "HSW IOAT Ch4" },
208 { 0x2f258086, "HSW IOAT Ch5" },
209 { 0x2f268086, "HSW IOAT Ch6" },
210 { 0x2f278086, "HSW IOAT Ch7" },
211 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" },
212 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" },
213
214 { 0x0c508086, "BWD IOAT Ch0" },
215 { 0x0c518086, "BWD IOAT Ch1" },
216 { 0x0c528086, "BWD IOAT Ch2" },
217 { 0x0c538086, "BWD IOAT Ch3" },
218
219 { 0x6f508086, "BDXDE IOAT Ch0" },
220 { 0x6f518086, "BDXDE IOAT Ch1" },
221 { 0x6f528086, "BDXDE IOAT Ch2" },
222 { 0x6f538086, "BDXDE IOAT Ch3" },
223
224 { 0x6f208086, "BDX IOAT Ch0" },
225 { 0x6f218086, "BDX IOAT Ch1" },
226 { 0x6f228086, "BDX IOAT Ch2" },
227 { 0x6f238086, "BDX IOAT Ch3" },
228 { 0x6f248086, "BDX IOAT Ch4" },
229 { 0x6f258086, "BDX IOAT Ch5" },
230 { 0x6f268086, "BDX IOAT Ch6" },
231 { 0x6f278086, "BDX IOAT Ch7" },
232 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" },
233 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" },
234
235 { 0x20218086, "SKX IOAT" },
236 };
237
238 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, ioat, pci_ids,
239 nitems(pci_ids));
240
241 /*
242 * OS <-> Driver linkage functions
243 */
244 static int
ioat_probe(device_t device)245 ioat_probe(device_t device)
246 {
247 struct _pcsid *ep;
248 u_int32_t type;
249
250 type = pci_get_devid(device);
251 for (ep = pci_ids; ep < &pci_ids[nitems(pci_ids)]; ep++) {
252 if (ep->type == type) {
253 device_set_desc(device, ep->desc);
254 return (0);
255 }
256 }
257 return (ENXIO);
258 }
259
260 static int
ioat_attach(device_t device)261 ioat_attach(device_t device)
262 {
263 struct ioat_softc *ioat;
264 int error, i;
265
266 ioat = DEVICE2SOFTC(device);
267 ioat->device = device;
268
269 error = ioat_map_pci_bar(ioat);
270 if (error != 0)
271 goto err;
272
273 ioat->version = ioat_read_cbver(ioat);
274 if (ioat->version < IOAT_VER_3_0) {
275 error = ENODEV;
276 goto err;
277 }
278
279 error = ioat3_attach(device);
280 if (error != 0)
281 goto err;
282
283 error = pci_enable_busmaster(device);
284 if (error != 0)
285 goto err;
286
287 error = ioat_setup_intr(ioat);
288 if (error != 0)
289 goto err;
290
291 error = ioat_reset_hw(ioat);
292 if (error != 0)
293 goto err;
294
295 ioat_process_events(ioat, FALSE);
296 ioat_setup_sysctl(device);
297
298 mtx_lock(&ioat_list_mtx);
299 for (i = 0; i < IOAT_MAX_CHANNELS; i++) {
300 if (ioat_channel[i] == NULL)
301 break;
302 }
303 if (i >= IOAT_MAX_CHANNELS) {
304 mtx_unlock(&ioat_list_mtx);
305 device_printf(device, "Too many I/OAT devices in system\n");
306 error = ENXIO;
307 goto err;
308 }
309 ioat->chan_idx = i;
310 ioat_channel[i] = ioat;
311 if (i >= ioat_channel_index)
312 ioat_channel_index = i + 1;
313 mtx_unlock(&ioat_list_mtx);
314
315 ioat_test_attach();
316
317 err:
318 if (error != 0)
319 ioat_detach(device);
320 return (error);
321 }
322
323 static int
ioat_detach(device_t device)324 ioat_detach(device_t device)
325 {
326 struct ioat_softc *ioat;
327
328 ioat = DEVICE2SOFTC(device);
329
330 mtx_lock(&ioat_list_mtx);
331 ioat_channel[ioat->chan_idx] = NULL;
332 while (ioat_channel_index > 0 &&
333 ioat_channel[ioat_channel_index - 1] == NULL)
334 ioat_channel_index--;
335 mtx_unlock(&ioat_list_mtx);
336
337 ioat_test_detach();
338 taskqueue_drain(taskqueue_thread, &ioat->reset_task);
339
340 mtx_lock(&ioat->submit_lock);
341 ioat->quiescing = TRUE;
342 ioat->destroying = TRUE;
343 wakeup(&ioat->quiescing);
344 wakeup(&ioat->resetting);
345
346 ioat_drain_locked(ioat);
347 mtx_unlock(&ioat->submit_lock);
348 mtx_lock(&ioat->cleanup_lock);
349 while (ioat_get_active(ioat) > 0)
350 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1);
351 mtx_unlock(&ioat->cleanup_lock);
352
353 ioat_teardown_intr(ioat);
354 callout_drain(&ioat->poll_timer);
355
356 pci_disable_busmaster(device);
357
358 if (ioat->pci_resource != NULL)
359 bus_release_resource(device, SYS_RES_MEMORY,
360 ioat->pci_resource_id, ioat->pci_resource);
361
362 if (ioat->ring != NULL)
363 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring);
364
365 if (ioat->comp_update != NULL) {
366 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map);
367 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update,
368 ioat->comp_update_map);
369 bus_dma_tag_destroy(ioat->comp_update_tag);
370 }
371
372 if (ioat->hw_desc_ring != NULL) {
373 bus_dmamap_unload(ioat->hw_desc_tag, ioat->hw_desc_map);
374 bus_dmamem_free(ioat->hw_desc_tag, ioat->hw_desc_ring,
375 ioat->hw_desc_map);
376 bus_dma_tag_destroy(ioat->hw_desc_tag);
377 }
378
379 return (0);
380 }
381
382 static int
ioat_teardown_intr(struct ioat_softc * ioat)383 ioat_teardown_intr(struct ioat_softc *ioat)
384 {
385
386 if (ioat->tag != NULL)
387 bus_teardown_intr(ioat->device, ioat->res, ioat->tag);
388
389 if (ioat->res != NULL)
390 bus_release_resource(ioat->device, SYS_RES_IRQ,
391 rman_get_rid(ioat->res), ioat->res);
392
393 pci_release_msi(ioat->device);
394 return (0);
395 }
396
397 static int
ioat_start_channel(struct ioat_softc * ioat)398 ioat_start_channel(struct ioat_softc *ioat)
399 {
400 struct ioat_dma_hw_descriptor *hw_desc;
401 struct ioat_descriptor *desc;
402 struct bus_dmadesc *dmadesc;
403 uint64_t status;
404 uint32_t chanerr;
405 int i;
406
407 ioat_acquire(&ioat->dmaengine);
408
409 /* Submit 'NULL' operation manually to avoid quiescing flag */
410 desc = ioat_get_ring_entry(ioat, ioat->head);
411 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->dma;
412 dmadesc = &desc->bus_dmadesc;
413
414 dmadesc->callback_fn = NULL;
415 dmadesc->callback_arg = NULL;
416
417 hw_desc->u.control_raw = 0;
418 hw_desc->u.control_generic.op = IOAT_OP_COPY;
419 hw_desc->u.control_generic.completion_update = 1;
420 hw_desc->size = 8;
421 hw_desc->src_addr = 0;
422 hw_desc->dest_addr = 0;
423 hw_desc->u.control.null = 1;
424
425 ioat_submit_single(ioat);
426 ioat_release(&ioat->dmaengine);
427
428 for (i = 0; i < 100; i++) {
429 DELAY(1);
430 status = ioat_get_chansts(ioat);
431 if (is_ioat_idle(status))
432 return (0);
433 }
434
435 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
436 ioat_log_message(0, "could not start channel: "
437 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr,
438 IOAT_CHANERR_STR);
439 return (ENXIO);
440 }
441
442 /*
443 * Initialize Hardware
444 */
445 static int
ioat3_attach(device_t device)446 ioat3_attach(device_t device)
447 {
448 struct ioat_softc *ioat;
449 struct ioat_descriptor *ring;
450 struct ioat_dma_hw_descriptor *dma_hw_desc;
451 void *hw_desc;
452 size_t ringsz;
453 int i, num_descriptors;
454 int error;
455 uint8_t xfercap;
456
457 error = 0;
458 ioat = DEVICE2SOFTC(device);
459 ioat->capabilities = ioat_read_dmacapability(ioat);
460
461 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities,
462 IOAT_DMACAP_STR);
463
464 xfercap = ioat_read_xfercap(ioat);
465 ioat->max_xfer_size = 1 << xfercap;
466
467 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) &
468 IOAT_INTRDELAY_SUPPORTED) != 0;
469 if (ioat->intrdelay_supported)
470 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK;
471
472 /* TODO: need to check DCA here if we ever do XOR/PQ */
473
474 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF);
475 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF);
476 callout_init(&ioat->poll_timer, 1);
477 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat);
478
479 /* Establish lock order for Witness */
480 mtx_lock(&ioat->cleanup_lock);
481 mtx_lock(&ioat->submit_lock);
482 mtx_unlock(&ioat->submit_lock);
483 mtx_unlock(&ioat->cleanup_lock);
484
485 ioat->is_submitter_processing = FALSE;
486
487 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0,
488 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
489 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL,
490 &ioat->comp_update_tag);
491
492 error = bus_dmamem_alloc(ioat->comp_update_tag,
493 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map);
494 if (ioat->comp_update == NULL)
495 return (ENOMEM);
496
497 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map,
498 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat,
499 0);
500 if (error != 0)
501 return (error);
502
503 ioat->ring_size_order = g_ioat_ring_order;
504 num_descriptors = 1 << ioat->ring_size_order;
505 ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors;
506
507 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
508 2 * 1024 * 1024, 0x0, (bus_addr_t)BUS_SPACE_MAXADDR_40BIT,
509 BUS_SPACE_MAXADDR, NULL, NULL, ringsz, 1, ringsz, 0, NULL, NULL,
510 &ioat->hw_desc_tag);
511 if (error != 0)
512 return (error);
513
514 error = bus_dmamem_alloc(ioat->hw_desc_tag, &hw_desc,
515 BUS_DMA_ZERO | BUS_DMA_WAITOK, &ioat->hw_desc_map);
516 if (error != 0)
517 return (error);
518
519 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc,
520 ringsz, ioat_dmamap_cb, &ioat->hw_desc_bus_addr, BUS_DMA_WAITOK);
521 if (error)
522 return (error);
523
524 ioat->hw_desc_ring = hw_desc;
525
526 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT,
527 M_ZERO | M_WAITOK);
528
529 ring = ioat->ring;
530 for (i = 0; i < num_descriptors; i++) {
531 memset(&ring[i].bus_dmadesc, 0, sizeof(ring[i].bus_dmadesc));
532 ring[i].id = i;
533 }
534
535 for (i = 0; i < num_descriptors; i++) {
536 dma_hw_desc = &ioat->hw_desc_ring[i].dma;
537 dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1);
538 }
539
540 ioat->head = 0;
541 ioat->tail = 0;
542 ioat->last_seen = 0;
543 *ioat->comp_update = 0;
544 return (0);
545 }
546
547 static int
ioat_map_pci_bar(struct ioat_softc * ioat)548 ioat_map_pci_bar(struct ioat_softc *ioat)
549 {
550
551 ioat->pci_resource_id = PCIR_BAR(0);
552 ioat->pci_resource = bus_alloc_resource_any(ioat->device,
553 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE);
554
555 if (ioat->pci_resource == NULL) {
556 ioat_log_message(0, "unable to allocate pci resource\n");
557 return (ENODEV);
558 }
559
560 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource);
561 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource);
562 return (0);
563 }
564
565 static void
ioat_comp_update_map(void * arg,bus_dma_segment_t * seg,int nseg,int error)566 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
567 {
568 struct ioat_softc *ioat = arg;
569
570 KASSERT(error == 0, ("%s: error:%d", __func__, error));
571 ioat->comp_update_bus_addr = seg[0].ds_addr;
572 }
573
574 static void
ioat_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)575 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
576 {
577 bus_addr_t *baddr;
578
579 KASSERT(error == 0, ("%s: error:%d", __func__, error));
580 baddr = arg;
581 *baddr = segs->ds_addr;
582 }
583
584 /*
585 * Interrupt setup and handlers
586 */
587 static int
ioat_setup_intr(struct ioat_softc * ioat)588 ioat_setup_intr(struct ioat_softc *ioat)
589 {
590 uint32_t num_vectors;
591 int error;
592 boolean_t use_msix;
593 boolean_t force_legacy_interrupts;
594
595 use_msix = FALSE;
596 force_legacy_interrupts = FALSE;
597
598 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) {
599 num_vectors = 1;
600 pci_alloc_msix(ioat->device, &num_vectors);
601 if (num_vectors == 1)
602 use_msix = TRUE;
603 }
604
605 if (use_msix) {
606 ioat->rid = 1;
607 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
608 &ioat->rid, RF_ACTIVE);
609 } else {
610 ioat->rid = 0;
611 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
612 &ioat->rid, RF_SHAREABLE | RF_ACTIVE);
613 }
614 if (ioat->res == NULL) {
615 ioat_log_message(0, "bus_alloc_resource failed\n");
616 return (ENOMEM);
617 }
618
619 ioat->tag = NULL;
620 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE |
621 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag);
622 if (error != 0) {
623 ioat_log_message(0, "bus_setup_intr failed\n");
624 return (error);
625 }
626
627 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN);
628 return (0);
629 }
630
631 static boolean_t
ioat_model_resets_msix(struct ioat_softc * ioat)632 ioat_model_resets_msix(struct ioat_softc *ioat)
633 {
634 u_int32_t pciid;
635
636 pciid = pci_get_devid(ioat->device);
637 switch (pciid) {
638 /* BWD: */
639 case 0x0c508086:
640 case 0x0c518086:
641 case 0x0c528086:
642 case 0x0c538086:
643 /* BDXDE: */
644 case 0x6f508086:
645 case 0x6f518086:
646 case 0x6f528086:
647 case 0x6f538086:
648 return (TRUE);
649 }
650
651 return (FALSE);
652 }
653
654 static void
ioat_interrupt_handler(void * arg)655 ioat_interrupt_handler(void *arg)
656 {
657 struct ioat_softc *ioat = arg;
658
659 ioat->stats.interrupts++;
660 ioat_process_events(ioat, TRUE);
661 }
662
663 static int
chanerr_to_errno(uint32_t chanerr)664 chanerr_to_errno(uint32_t chanerr)
665 {
666
667 if (chanerr == 0)
668 return (0);
669 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0)
670 return (EFAULT);
671 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0)
672 return (EIO);
673 /* This one is probably our fault: */
674 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0)
675 return (EIO);
676 return (EIO);
677 }
678
679 static void
ioat_process_events(struct ioat_softc * ioat,boolean_t intr)680 ioat_process_events(struct ioat_softc *ioat, boolean_t intr)
681 {
682 struct ioat_descriptor *desc;
683 struct bus_dmadesc *dmadesc;
684 uint64_t comp_update, status;
685 uint32_t completed, chanerr;
686 int error;
687
688 mtx_lock(&ioat->cleanup_lock);
689
690 /*
691 * Don't run while the hardware is being reset. Reset is responsible
692 * for blocking new work and draining & completing existing work, so
693 * there is nothing to do until new work is queued after reset anyway.
694 */
695 if (ioat->resetting_cleanup) {
696 mtx_unlock(&ioat->cleanup_lock);
697 return;
698 }
699
700 completed = 0;
701 comp_update = *ioat->comp_update;
702 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK;
703
704 if (status < ioat->hw_desc_bus_addr ||
705 status >= ioat->hw_desc_bus_addr + (1 << ioat->ring_size_order) *
706 sizeof(struct ioat_generic_hw_descriptor))
707 panic("Bogus completion address %jx (channel %u)",
708 (uintmax_t)status, ioat->chan_idx);
709
710 if (status == ioat->last_seen) {
711 /*
712 * If we landed in process_events and nothing has been
713 * completed, check for a timeout due to channel halt.
714 */
715 goto out;
716 }
717 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx",
718 __func__, ioat->chan_idx, comp_update, ioat->last_seen);
719
720 while (RING_PHYS_ADDR(ioat, ioat->tail - 1) != status) {
721 desc = ioat_get_ring_entry(ioat, ioat->tail);
722 dmadesc = &desc->bus_dmadesc;
723 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)",
724 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn,
725 dmadesc->callback_arg);
726
727 if (dmadesc->callback_fn != NULL)
728 dmadesc->callback_fn(dmadesc->callback_arg, 0);
729
730 completed++;
731 ioat->tail++;
732 }
733 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__,
734 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat));
735
736 if (completed != 0) {
737 ioat->last_seen = RING_PHYS_ADDR(ioat, ioat->tail - 1);
738 ioat->stats.descriptors_processed += completed;
739 wakeup(&ioat->tail);
740 }
741
742 out:
743 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
744 mtx_unlock(&ioat->cleanup_lock);
745
746 /*
747 * The device doesn't seem to reliably push suspend/halt statuses to
748 * the channel completion memory address, so poll the device register
749 * here. For performance reasons skip it on interrupts, do it only
750 * on much more rare polling events.
751 */
752 if (!intr)
753 comp_update = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS;
754 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update))
755 return;
756
757 ioat->stats.channel_halts++;
758
759 /*
760 * Fatal programming error on this DMA channel. Flush any outstanding
761 * work with error status and restart the engine.
762 */
763 mtx_lock(&ioat->submit_lock);
764 ioat->quiescing = TRUE;
765 mtx_unlock(&ioat->submit_lock);
766
767 /*
768 * This is safe to do here because the submit queue is quiesced. We
769 * know that we will drain all outstanding events, so ioat_reset_hw
770 * can't deadlock. It is necessary to protect other ioat_process_event
771 * threads from racing ioat_reset_hw, reading an indeterminate hw
772 * state, and attempting to continue issuing completions.
773 */
774 mtx_lock(&ioat->cleanup_lock);
775 ioat->resetting_cleanup = TRUE;
776
777 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
778 if (1 <= g_ioat_debug_level)
779 ioat_halted_debug(ioat, chanerr);
780 ioat->stats.last_halt_chanerr = chanerr;
781
782 while (ioat_get_active(ioat) > 0) {
783 desc = ioat_get_ring_entry(ioat, ioat->tail);
784 dmadesc = &desc->bus_dmadesc;
785 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)",
786 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn,
787 dmadesc->callback_arg);
788
789 if (dmadesc->callback_fn != NULL)
790 dmadesc->callback_fn(dmadesc->callback_arg,
791 chanerr_to_errno(chanerr));
792
793 ioat->tail++;
794 ioat->stats.descriptors_processed++;
795 ioat->stats.descriptors_error++;
796 }
797 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__,
798 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat));
799
800 /* Clear error status */
801 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr);
802
803 mtx_unlock(&ioat->cleanup_lock);
804
805 ioat_log_message(0, "Resetting channel to recover from error\n");
806 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task);
807 KASSERT(error == 0,
808 ("%s: taskqueue_enqueue failed: %d", __func__, error));
809 }
810
811 static void
ioat_reset_hw_task(void * ctx,int pending __unused)812 ioat_reset_hw_task(void *ctx, int pending __unused)
813 {
814 struct ioat_softc *ioat;
815 int error;
816
817 ioat = ctx;
818 ioat_log_message(1, "%s: Resetting channel\n", __func__);
819
820 error = ioat_reset_hw(ioat);
821 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error));
822 (void)error;
823 }
824
825 /*
826 * User API functions
827 */
828 unsigned
ioat_get_nchannels(void)829 ioat_get_nchannels(void)
830 {
831
832 return (ioat_channel_index);
833 }
834
835 bus_dmaengine_t
ioat_get_dmaengine(uint32_t index,int flags)836 ioat_get_dmaengine(uint32_t index, int flags)
837 {
838 struct ioat_softc *ioat;
839
840 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0,
841 ("invalid flags: 0x%08x", flags));
842 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK),
843 ("invalid wait | nowait"));
844
845 mtx_lock(&ioat_list_mtx);
846 if (index >= ioat_channel_index ||
847 (ioat = ioat_channel[index]) == NULL) {
848 mtx_unlock(&ioat_list_mtx);
849 return (NULL);
850 }
851 mtx_lock(&ioat->submit_lock);
852 mtx_unlock(&ioat_list_mtx);
853
854 if (ioat->destroying) {
855 mtx_unlock(&ioat->submit_lock);
856 return (NULL);
857 }
858
859 ioat_get(ioat);
860 if (ioat->quiescing) {
861 if ((flags & M_NOWAIT) != 0) {
862 ioat_put(ioat);
863 mtx_unlock(&ioat->submit_lock);
864 return (NULL);
865 }
866
867 while (ioat->quiescing && !ioat->destroying)
868 msleep(&ioat->quiescing, &ioat->submit_lock, 0, "getdma", 0);
869
870 if (ioat->destroying) {
871 ioat_put(ioat);
872 mtx_unlock(&ioat->submit_lock);
873 return (NULL);
874 }
875 }
876 mtx_unlock(&ioat->submit_lock);
877 return (&ioat->dmaengine);
878 }
879
880 void
ioat_put_dmaengine(bus_dmaengine_t dmaengine)881 ioat_put_dmaengine(bus_dmaengine_t dmaengine)
882 {
883 struct ioat_softc *ioat;
884
885 ioat = to_ioat_softc(dmaengine);
886 mtx_lock(&ioat->submit_lock);
887 ioat_put(ioat);
888 mtx_unlock(&ioat->submit_lock);
889 }
890
891 int
ioat_get_hwversion(bus_dmaengine_t dmaengine)892 ioat_get_hwversion(bus_dmaengine_t dmaengine)
893 {
894 struct ioat_softc *ioat;
895
896 ioat = to_ioat_softc(dmaengine);
897 return (ioat->version);
898 }
899
900 size_t
ioat_get_max_io_size(bus_dmaengine_t dmaengine)901 ioat_get_max_io_size(bus_dmaengine_t dmaengine)
902 {
903 struct ioat_softc *ioat;
904
905 ioat = to_ioat_softc(dmaengine);
906 return (ioat->max_xfer_size);
907 }
908
909 uint32_t
ioat_get_capabilities(bus_dmaengine_t dmaengine)910 ioat_get_capabilities(bus_dmaengine_t dmaengine)
911 {
912 struct ioat_softc *ioat;
913
914 ioat = to_ioat_softc(dmaengine);
915 return (ioat->capabilities);
916 }
917
918 int
ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine,uint16_t delay)919 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay)
920 {
921 struct ioat_softc *ioat;
922
923 ioat = to_ioat_softc(dmaengine);
924 if (!ioat->intrdelay_supported)
925 return (ENODEV);
926 if (delay > ioat->intrdelay_max)
927 return (ERANGE);
928
929 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay);
930 ioat->cached_intrdelay =
931 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK;
932 return (0);
933 }
934
935 uint16_t
ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine)936 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine)
937 {
938 struct ioat_softc *ioat;
939
940 ioat = to_ioat_softc(dmaengine);
941 return (ioat->intrdelay_max);
942 }
943
944 void
ioat_acquire(bus_dmaengine_t dmaengine)945 ioat_acquire(bus_dmaengine_t dmaengine)
946 {
947 struct ioat_softc *ioat;
948
949 ioat = to_ioat_softc(dmaengine);
950 mtx_lock(&ioat->submit_lock);
951 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
952 ioat->acq_head = ioat->head;
953 }
954
955 int
ioat_acquire_reserve(bus_dmaengine_t dmaengine,unsigned n,int mflags)956 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags)
957 {
958 struct ioat_softc *ioat;
959 int error;
960
961 ioat = to_ioat_softc(dmaengine);
962 ioat_acquire(dmaengine);
963
964 error = ioat_reserve_space(ioat, n, mflags);
965 if (error != 0)
966 ioat_release(dmaengine);
967 return (error);
968 }
969
970 void
ioat_release(bus_dmaengine_t dmaengine)971 ioat_release(bus_dmaengine_t dmaengine)
972 {
973 struct ioat_softc *ioat;
974
975 ioat = to_ioat_softc(dmaengine);
976 CTR3(KTR_IOAT, "%s channel=%u dispatch1 head=%u", __func__,
977 ioat->chan_idx, ioat->head);
978 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */);
979 CTR3(KTR_IOAT, "%s channel=%u dispatch2 head=%u", __func__,
980 ioat->chan_idx, ioat->head);
981
982 if (ioat->acq_head != ioat->head) {
983 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET,
984 (uint16_t)ioat->head);
985
986 if (!callout_pending(&ioat->poll_timer)) {
987 callout_reset(&ioat->poll_timer, 1,
988 ioat_poll_timer_callback, ioat);
989 }
990 }
991 mtx_unlock(&ioat->submit_lock);
992 }
993
994 static struct ioat_descriptor *
ioat_op_generic(struct ioat_softc * ioat,uint8_t op,uint32_t size,uint64_t src,uint64_t dst,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)995 ioat_op_generic(struct ioat_softc *ioat, uint8_t op,
996 uint32_t size, uint64_t src, uint64_t dst,
997 bus_dmaengine_callback_t callback_fn, void *callback_arg,
998 uint32_t flags)
999 {
1000 struct ioat_generic_hw_descriptor *hw_desc;
1001 struct ioat_descriptor *desc;
1002 int mflags;
1003
1004 mtx_assert(&ioat->submit_lock, MA_OWNED);
1005
1006 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0,
1007 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS));
1008 if ((flags & DMA_NO_WAIT) != 0)
1009 mflags = M_NOWAIT;
1010 else
1011 mflags = M_WAITOK;
1012
1013 if (size > ioat->max_xfer_size) {
1014 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n",
1015 __func__, ioat->max_xfer_size, (unsigned)size);
1016 return (NULL);
1017 }
1018
1019 if (ioat_reserve_space(ioat, 1, mflags) != 0)
1020 return (NULL);
1021
1022 desc = ioat_get_ring_entry(ioat, ioat->head);
1023 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->generic;
1024
1025 hw_desc->u.control_raw = 0;
1026 hw_desc->u.control_generic.op = op;
1027 hw_desc->u.control_generic.completion_update = 1;
1028
1029 if ((flags & DMA_INT_EN) != 0)
1030 hw_desc->u.control_generic.int_enable = 1;
1031 if ((flags & DMA_FENCE) != 0)
1032 hw_desc->u.control_generic.fence = 1;
1033
1034 hw_desc->size = size;
1035 hw_desc->src_addr = src;
1036 hw_desc->dest_addr = dst;
1037
1038 desc->bus_dmadesc.callback_fn = callback_fn;
1039 desc->bus_dmadesc.callback_arg = callback_arg;
1040 return (desc);
1041 }
1042
1043 struct bus_dmadesc *
ioat_null(bus_dmaengine_t dmaengine,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1044 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn,
1045 void *callback_arg, uint32_t flags)
1046 {
1047 struct ioat_dma_hw_descriptor *hw_desc;
1048 struct ioat_descriptor *desc;
1049 struct ioat_softc *ioat;
1050
1051 ioat = to_ioat_softc(dmaengine);
1052 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1053
1054 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn,
1055 callback_arg, flags);
1056 if (desc == NULL)
1057 return (NULL);
1058
1059 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1060 hw_desc->u.control.null = 1;
1061 ioat_submit_single(ioat);
1062 return (&desc->bus_dmadesc);
1063 }
1064
1065 struct bus_dmadesc *
ioat_copy(bus_dmaengine_t dmaengine,bus_addr_t dst,bus_addr_t src,bus_size_t len,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1066 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst,
1067 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn,
1068 void *callback_arg, uint32_t flags)
1069 {
1070 struct ioat_dma_hw_descriptor *hw_desc;
1071 struct ioat_descriptor *desc;
1072 struct ioat_softc *ioat;
1073
1074 ioat = to_ioat_softc(dmaengine);
1075
1076 if (((src | dst) & (0xffffull << 48)) != 0) {
1077 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n",
1078 __func__);
1079 return (NULL);
1080 }
1081
1082 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn,
1083 callback_arg, flags);
1084 if (desc == NULL)
1085 return (NULL);
1086
1087 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1088 if (g_ioat_debug_level >= 3)
1089 dump_descriptor(hw_desc);
1090
1091 ioat_submit_single(ioat);
1092 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx",
1093 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len);
1094 return (&desc->bus_dmadesc);
1095 }
1096
1097 struct bus_dmadesc *
ioat_copy_8k_aligned(bus_dmaengine_t dmaengine,bus_addr_t dst1,bus_addr_t dst2,bus_addr_t src1,bus_addr_t src2,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1098 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1,
1099 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2,
1100 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1101 {
1102 struct ioat_dma_hw_descriptor *hw_desc;
1103 struct ioat_descriptor *desc;
1104 struct ioat_softc *ioat;
1105
1106 ioat = to_ioat_softc(dmaengine);
1107 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1108
1109 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) {
1110 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n",
1111 __func__);
1112 return (NULL);
1113 }
1114 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) {
1115 ioat_log_message(0, "%s: Addresses must be page-aligned\n",
1116 __func__);
1117 return (NULL);
1118 }
1119
1120 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1,
1121 callback_fn, callback_arg, flags);
1122 if (desc == NULL)
1123 return (NULL);
1124
1125 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1126 if (src2 != src1 + PAGE_SIZE) {
1127 hw_desc->u.control.src_page_break = 1;
1128 hw_desc->next_src_addr = src2;
1129 }
1130 if (dst2 != dst1 + PAGE_SIZE) {
1131 hw_desc->u.control.dest_page_break = 1;
1132 hw_desc->next_dest_addr = dst2;
1133 }
1134
1135 if (g_ioat_debug_level >= 3)
1136 dump_descriptor(hw_desc);
1137
1138 ioat_submit_single(ioat);
1139 return (&desc->bus_dmadesc);
1140 }
1141
1142 struct bus_dmadesc *
ioat_copy_crc(bus_dmaengine_t dmaengine,bus_addr_t dst,bus_addr_t src,bus_size_t len,uint32_t * initialseed,bus_addr_t crcptr,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1143 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
1144 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr,
1145 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1146 {
1147 struct ioat_crc32_hw_descriptor *hw_desc;
1148 struct ioat_descriptor *desc;
1149 struct ioat_softc *ioat;
1150 uint32_t teststore;
1151 uint8_t op;
1152
1153 ioat = to_ioat_softc(dmaengine);
1154 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1155
1156 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) {
1157 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n",
1158 __func__);
1159 return (NULL);
1160 }
1161 if (((src | dst) & (0xffffffull << 40)) != 0) {
1162 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n",
1163 __func__);
1164 return (NULL);
1165 }
1166 teststore = (flags & _DMA_CRC_TESTSTORE);
1167 if (teststore == _DMA_CRC_TESTSTORE) {
1168 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__);
1169 return (NULL);
1170 }
1171 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) {
1172 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n",
1173 __func__);
1174 return (NULL);
1175 }
1176
1177 switch (teststore) {
1178 case DMA_CRC_STORE:
1179 op = IOAT_OP_MOVECRC_STORE;
1180 break;
1181 case DMA_CRC_TEST:
1182 op = IOAT_OP_MOVECRC_TEST;
1183 break;
1184 default:
1185 KASSERT(teststore == 0, ("bogus"));
1186 op = IOAT_OP_MOVECRC;
1187 break;
1188 }
1189
1190 if ((flags & DMA_CRC_INLINE) == 0 &&
1191 (crcptr & (0xffffffull << 40)) != 0) {
1192 ioat_log_message(0,
1193 "%s: High 24 bits of crcptr invalid\n", __func__);
1194 return (NULL);
1195 }
1196
1197 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn,
1198 callback_arg, flags & ~_DMA_CRC_FLAGS);
1199 if (desc == NULL)
1200 return (NULL);
1201
1202 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32;
1203
1204 if ((flags & DMA_CRC_INLINE) == 0)
1205 hw_desc->crc_address = crcptr;
1206 else
1207 hw_desc->u.control.crc_location = 1;
1208
1209 if (initialseed != NULL) {
1210 hw_desc->u.control.use_seed = 1;
1211 hw_desc->seed = *initialseed;
1212 }
1213
1214 if (g_ioat_debug_level >= 3)
1215 dump_descriptor(hw_desc);
1216
1217 ioat_submit_single(ioat);
1218 return (&desc->bus_dmadesc);
1219 }
1220
1221 struct bus_dmadesc *
ioat_crc(bus_dmaengine_t dmaengine,bus_addr_t src,bus_size_t len,uint32_t * initialseed,bus_addr_t crcptr,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1222 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
1223 uint32_t *initialseed, bus_addr_t crcptr,
1224 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1225 {
1226 struct ioat_crc32_hw_descriptor *hw_desc;
1227 struct ioat_descriptor *desc;
1228 struct ioat_softc *ioat;
1229 uint32_t teststore;
1230 uint8_t op;
1231
1232 ioat = to_ioat_softc(dmaengine);
1233 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1234
1235 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) {
1236 ioat_log_message(0, "%s: Device lacks CRC capability\n",
1237 __func__);
1238 return (NULL);
1239 }
1240 if ((src & (0xffffffull << 40)) != 0) {
1241 ioat_log_message(0, "%s: High 24 bits of src invalid\n",
1242 __func__);
1243 return (NULL);
1244 }
1245 teststore = (flags & _DMA_CRC_TESTSTORE);
1246 if (teststore == _DMA_CRC_TESTSTORE) {
1247 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__);
1248 return (NULL);
1249 }
1250 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) {
1251 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n",
1252 __func__);
1253 return (NULL);
1254 }
1255
1256 switch (teststore) {
1257 case DMA_CRC_STORE:
1258 op = IOAT_OP_CRC_STORE;
1259 break;
1260 case DMA_CRC_TEST:
1261 op = IOAT_OP_CRC_TEST;
1262 break;
1263 default:
1264 KASSERT(teststore == 0, ("bogus"));
1265 op = IOAT_OP_CRC;
1266 break;
1267 }
1268
1269 if ((flags & DMA_CRC_INLINE) == 0 &&
1270 (crcptr & (0xffffffull << 40)) != 0) {
1271 ioat_log_message(0,
1272 "%s: High 24 bits of crcptr invalid\n", __func__);
1273 return (NULL);
1274 }
1275
1276 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn,
1277 callback_arg, flags & ~_DMA_CRC_FLAGS);
1278 if (desc == NULL)
1279 return (NULL);
1280
1281 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32;
1282
1283 if ((flags & DMA_CRC_INLINE) == 0)
1284 hw_desc->crc_address = crcptr;
1285 else
1286 hw_desc->u.control.crc_location = 1;
1287
1288 if (initialseed != NULL) {
1289 hw_desc->u.control.use_seed = 1;
1290 hw_desc->seed = *initialseed;
1291 }
1292
1293 if (g_ioat_debug_level >= 3)
1294 dump_descriptor(hw_desc);
1295
1296 ioat_submit_single(ioat);
1297 return (&desc->bus_dmadesc);
1298 }
1299
1300 struct bus_dmadesc *
ioat_blockfill(bus_dmaengine_t dmaengine,bus_addr_t dst,uint64_t fillpattern,bus_size_t len,bus_dmaengine_callback_t callback_fn,void * callback_arg,uint32_t flags)1301 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern,
1302 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg,
1303 uint32_t flags)
1304 {
1305 struct ioat_fill_hw_descriptor *hw_desc;
1306 struct ioat_descriptor *desc;
1307 struct ioat_softc *ioat;
1308
1309 ioat = to_ioat_softc(dmaengine);
1310 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1311
1312 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) {
1313 ioat_log_message(0, "%s: Device lacks BFILL capability\n",
1314 __func__);
1315 return (NULL);
1316 }
1317
1318 if ((dst & (0xffffull << 48)) != 0) {
1319 ioat_log_message(0, "%s: High 16 bits of dst invalid\n",
1320 __func__);
1321 return (NULL);
1322 }
1323
1324 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst,
1325 callback_fn, callback_arg, flags);
1326 if (desc == NULL)
1327 return (NULL);
1328
1329 hw_desc = &ioat_get_descriptor(ioat, desc->id)->fill;
1330 if (g_ioat_debug_level >= 3)
1331 dump_descriptor(hw_desc);
1332
1333 ioat_submit_single(ioat);
1334 return (&desc->bus_dmadesc);
1335 }
1336
1337 /*
1338 * Ring Management
1339 */
1340 static inline uint32_t
ioat_get_active(struct ioat_softc * ioat)1341 ioat_get_active(struct ioat_softc *ioat)
1342 {
1343
1344 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1));
1345 }
1346
1347 static inline uint32_t
ioat_get_ring_space(struct ioat_softc * ioat)1348 ioat_get_ring_space(struct ioat_softc *ioat)
1349 {
1350
1351 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1);
1352 }
1353
1354 /*
1355 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain
1356 * for 'num_descs'.
1357 *
1358 * If mflags contains M_WAITOK, blocks until enough space is available.
1359 *
1360 * Returns zero on success, or an errno on error. If num_descs is beyond the
1361 * maximum ring size, returns EINVAl; if allocation would block and mflags
1362 * contains M_NOWAIT, returns EAGAIN.
1363 *
1364 * Must be called with the submit_lock held; returns with the lock held. The
1365 * lock may be dropped to allocate the ring.
1366 *
1367 * (The submit_lock is needed to add any entries to the ring, so callers are
1368 * assured enough room is available.)
1369 */
1370 static int
ioat_reserve_space(struct ioat_softc * ioat,uint32_t num_descs,int mflags)1371 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags)
1372 {
1373 boolean_t dug;
1374 int error;
1375
1376 mtx_assert(&ioat->submit_lock, MA_OWNED);
1377 error = 0;
1378 dug = FALSE;
1379
1380 if (num_descs < 1 || num_descs >= (1 << ioat->ring_size_order)) {
1381 error = EINVAL;
1382 goto out;
1383 }
1384
1385 for (;;) {
1386 if (ioat->quiescing) {
1387 error = ENXIO;
1388 goto out;
1389 }
1390
1391 if (ioat_get_ring_space(ioat) >= num_descs)
1392 goto out;
1393
1394 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__,
1395 ioat->chan_idx, num_descs);
1396
1397 if (!dug && !ioat->is_submitter_processing) {
1398 ioat->is_submitter_processing = TRUE;
1399 mtx_unlock(&ioat->submit_lock);
1400
1401 CTR2(KTR_IOAT, "%s channel=%u attempting to process events",
1402 __func__, ioat->chan_idx);
1403 ioat_process_events(ioat, FALSE);
1404
1405 mtx_lock(&ioat->submit_lock);
1406 dug = TRUE;
1407 KASSERT(ioat->is_submitter_processing == TRUE,
1408 ("is_submitter_processing"));
1409 ioat->is_submitter_processing = FALSE;
1410 wakeup(&ioat->tail);
1411 continue;
1412 }
1413
1414 if ((mflags & M_WAITOK) == 0) {
1415 error = EAGAIN;
1416 break;
1417 }
1418 CTR2(KTR_IOAT, "%s channel=%u blocking on completions",
1419 __func__, ioat->chan_idx);
1420 msleep(&ioat->tail, &ioat->submit_lock, 0,
1421 "ioat_full", 0);
1422 continue;
1423 }
1424
1425 out:
1426 mtx_assert(&ioat->submit_lock, MA_OWNED);
1427 KASSERT(!ioat->quiescing || error == ENXIO,
1428 ("reserved during quiesce"));
1429 return (error);
1430 }
1431
1432 static void
ioat_free_ring(struct ioat_softc * ioat,uint32_t size,struct ioat_descriptor * ring)1433 ioat_free_ring(struct ioat_softc *ioat, uint32_t size,
1434 struct ioat_descriptor *ring)
1435 {
1436
1437 free(ring, M_IOAT);
1438 }
1439
1440 static struct ioat_descriptor *
ioat_get_ring_entry(struct ioat_softc * ioat,uint32_t index)1441 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index)
1442 {
1443
1444 return (&ioat->ring[index % (1 << ioat->ring_size_order)]);
1445 }
1446
1447 static union ioat_hw_descriptor *
ioat_get_descriptor(struct ioat_softc * ioat,uint32_t index)1448 ioat_get_descriptor(struct ioat_softc *ioat, uint32_t index)
1449 {
1450
1451 return (&ioat->hw_desc_ring[index % (1 << ioat->ring_size_order)]);
1452 }
1453
1454 static void
ioat_halted_debug(struct ioat_softc * ioat,uint32_t chanerr)1455 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr)
1456 {
1457 union ioat_hw_descriptor *desc;
1458
1459 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr,
1460 IOAT_CHANERR_STR);
1461 if (chanerr == 0)
1462 return;
1463
1464 mtx_assert(&ioat->cleanup_lock, MA_OWNED);
1465
1466 desc = ioat_get_descriptor(ioat, ioat->tail + 0);
1467 dump_descriptor(desc);
1468
1469 desc = ioat_get_descriptor(ioat, ioat->tail + 1);
1470 dump_descriptor(desc);
1471 }
1472
1473 static void
ioat_poll_timer_callback(void * arg)1474 ioat_poll_timer_callback(void *arg)
1475 {
1476 struct ioat_softc *ioat;
1477
1478 ioat = arg;
1479 ioat_log_message(3, "%s\n", __func__);
1480
1481 ioat_process_events(ioat, FALSE);
1482
1483 mtx_lock(&ioat->submit_lock);
1484 if (ioat_get_active(ioat) > 0)
1485 callout_schedule(&ioat->poll_timer, 1);
1486 mtx_unlock(&ioat->submit_lock);
1487 }
1488
1489 /*
1490 * Support Functions
1491 */
1492 static void
ioat_submit_single(struct ioat_softc * ioat)1493 ioat_submit_single(struct ioat_softc *ioat)
1494 {
1495
1496 mtx_assert(&ioat->submit_lock, MA_OWNED);
1497
1498 ioat->head++;
1499 CTR4(KTR_IOAT, "%s channel=%u head=%u tail=%u", __func__,
1500 ioat->chan_idx, ioat->head, ioat->tail);
1501
1502 ioat->stats.descriptors_submitted++;
1503 }
1504
1505 static int
ioat_reset_hw(struct ioat_softc * ioat)1506 ioat_reset_hw(struct ioat_softc *ioat)
1507 {
1508 uint64_t status;
1509 uint32_t chanerr;
1510 unsigned timeout;
1511 int error;
1512
1513 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1514
1515 mtx_lock(&ioat->submit_lock);
1516 while (ioat->resetting && !ioat->destroying)
1517 msleep(&ioat->resetting, &ioat->submit_lock, 0, "IRH_drain", 0);
1518 if (ioat->destroying) {
1519 mtx_unlock(&ioat->submit_lock);
1520 return (ENXIO);
1521 }
1522 ioat->resetting = TRUE;
1523 ioat->quiescing = TRUE;
1524 mtx_unlock(&ioat->submit_lock);
1525 mtx_lock(&ioat->cleanup_lock);
1526 while (ioat_get_active(ioat) > 0)
1527 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1);
1528
1529 /*
1530 * Suspend ioat_process_events while the hardware and softc are in an
1531 * indeterminate state.
1532 */
1533 ioat->resetting_cleanup = TRUE;
1534 mtx_unlock(&ioat->cleanup_lock);
1535
1536 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__,
1537 ioat->chan_idx);
1538
1539 status = ioat_get_chansts(ioat);
1540 if (is_ioat_active(status) || is_ioat_idle(status))
1541 ioat_suspend(ioat);
1542
1543 /* Wait at most 20 ms */
1544 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) &&
1545 timeout < 20; timeout++) {
1546 DELAY(1000);
1547 status = ioat_get_chansts(ioat);
1548 }
1549 if (timeout == 20) {
1550 error = ETIMEDOUT;
1551 goto out;
1552 }
1553
1554 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce"));
1555
1556 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
1557 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr);
1558
1559 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__,
1560 ioat->chan_idx);
1561
1562 /*
1563 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors
1564 * that can cause stability issues for IOAT v3.
1565 */
1566 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07,
1567 4);
1568 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4);
1569 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4);
1570
1571 /*
1572 * BDXDE and BWD models reset MSI-X registers on device reset.
1573 * Save/restore their contents manually.
1574 */
1575 if (ioat_model_resets_msix(ioat)) {
1576 ioat_log_message(1, "device resets MSI-X registers; saving\n");
1577 pci_save_state(ioat->device);
1578 }
1579
1580 ioat_reset(ioat);
1581 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__,
1582 ioat->chan_idx);
1583
1584 /* Wait at most 20 ms */
1585 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++)
1586 DELAY(1000);
1587 if (timeout == 20) {
1588 error = ETIMEDOUT;
1589 goto out;
1590 }
1591
1592 if (ioat_model_resets_msix(ioat)) {
1593 ioat_log_message(1, "device resets registers; restored\n");
1594 pci_restore_state(ioat->device);
1595 }
1596
1597 /* Reset attempts to return the hardware to "halted." */
1598 status = ioat_get_chansts(ioat);
1599 if (is_ioat_active(status) || is_ioat_idle(status)) {
1600 /* So this really shouldn't happen... */
1601 ioat_log_message(0, "Device is active after a reset?\n");
1602 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
1603 error = 0;
1604 goto out;
1605 }
1606
1607 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
1608 if (chanerr != 0) {
1609 mtx_lock(&ioat->cleanup_lock);
1610 ioat_halted_debug(ioat, chanerr);
1611 mtx_unlock(&ioat->cleanup_lock);
1612 error = EIO;
1613 goto out;
1614 }
1615
1616 /*
1617 * Bring device back online after reset. Writing CHAINADDR brings the
1618 * device back to active.
1619 *
1620 * The internal ring counter resets to zero, so we have to start over
1621 * at zero as well.
1622 */
1623 ioat->tail = ioat->head = 0;
1624 ioat->last_seen = 0;
1625 *ioat->comp_update = 0;
1626
1627 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
1628 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr);
1629 ioat_write_chainaddr(ioat, RING_PHYS_ADDR(ioat, 0));
1630 error = 0;
1631 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__,
1632 ioat->chan_idx);
1633
1634 out:
1635 /* Enqueues a null operation and ensures it completes. */
1636 if (error == 0) {
1637 error = ioat_start_channel(ioat);
1638 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__,
1639 ioat->chan_idx);
1640 }
1641
1642 /*
1643 * Resume completions now that ring state is consistent.
1644 */
1645 mtx_lock(&ioat->cleanup_lock);
1646 ioat->resetting_cleanup = FALSE;
1647 mtx_unlock(&ioat->cleanup_lock);
1648
1649 /* Unblock submission of new work */
1650 mtx_lock(&ioat->submit_lock);
1651 ioat->quiescing = FALSE;
1652 wakeup(&ioat->quiescing);
1653
1654 ioat->resetting = FALSE;
1655 wakeup(&ioat->resetting);
1656
1657 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx);
1658 mtx_unlock(&ioat->submit_lock);
1659
1660 return (error);
1661 }
1662
1663 static int
sysctl_handle_chansts(SYSCTL_HANDLER_ARGS)1664 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS)
1665 {
1666 struct ioat_softc *ioat;
1667 struct sbuf sb;
1668 uint64_t status;
1669 int error;
1670
1671 ioat = arg1;
1672
1673 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS;
1674
1675 sbuf_new_for_sysctl(&sb, NULL, 256, req);
1676 switch (status) {
1677 case IOAT_CHANSTS_ACTIVE:
1678 sbuf_printf(&sb, "ACTIVE");
1679 break;
1680 case IOAT_CHANSTS_IDLE:
1681 sbuf_printf(&sb, "IDLE");
1682 break;
1683 case IOAT_CHANSTS_SUSPENDED:
1684 sbuf_printf(&sb, "SUSPENDED");
1685 break;
1686 case IOAT_CHANSTS_HALTED:
1687 sbuf_printf(&sb, "HALTED");
1688 break;
1689 case IOAT_CHANSTS_ARMED:
1690 sbuf_printf(&sb, "ARMED");
1691 break;
1692 default:
1693 sbuf_printf(&sb, "UNKNOWN");
1694 break;
1695 }
1696 error = sbuf_finish(&sb);
1697 sbuf_delete(&sb);
1698
1699 if (error != 0 || req->newptr == NULL)
1700 return (error);
1701 return (EINVAL);
1702 }
1703
1704 static int
sysctl_handle_dpi(SYSCTL_HANDLER_ARGS)1705 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS)
1706 {
1707 struct ioat_softc *ioat;
1708 struct sbuf sb;
1709 #define PRECISION "1"
1710 const uintmax_t factor = 10;
1711 uintmax_t rate;
1712 int error;
1713
1714 ioat = arg1;
1715 sbuf_new_for_sysctl(&sb, NULL, 16, req);
1716
1717 if (ioat->stats.interrupts == 0) {
1718 sbuf_printf(&sb, "NaN");
1719 goto out;
1720 }
1721 rate = ioat->stats.descriptors_processed * factor /
1722 ioat->stats.interrupts;
1723 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor,
1724 rate % factor);
1725 #undef PRECISION
1726 out:
1727 error = sbuf_finish(&sb);
1728 sbuf_delete(&sb);
1729 if (error != 0 || req->newptr == NULL)
1730 return (error);
1731 return (EINVAL);
1732 }
1733
1734 static int
sysctl_handle_reset(SYSCTL_HANDLER_ARGS)1735 sysctl_handle_reset(SYSCTL_HANDLER_ARGS)
1736 {
1737 struct ioat_softc *ioat;
1738 int error, arg;
1739
1740 ioat = arg1;
1741
1742 arg = 0;
1743 error = SYSCTL_OUT(req, &arg, sizeof(arg));
1744 if (error != 0 || req->newptr == NULL)
1745 return (error);
1746
1747 error = SYSCTL_IN(req, &arg, sizeof(arg));
1748 if (error != 0)
1749 return (error);
1750
1751 if (arg != 0)
1752 error = ioat_reset_hw(ioat);
1753
1754 return (error);
1755 }
1756
1757 static void
dump_descriptor(void * hw_desc)1758 dump_descriptor(void *hw_desc)
1759 {
1760 int i, j;
1761
1762 for (i = 0; i < 2; i++) {
1763 for (j = 0; j < 8; j++)
1764 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]);
1765 printf("\n");
1766 }
1767 }
1768
1769 static void
ioat_setup_sysctl(device_t device)1770 ioat_setup_sysctl(device_t device)
1771 {
1772 struct sysctl_oid_list *par, *statpar, *state, *hammer;
1773 struct sysctl_ctx_list *ctx;
1774 struct sysctl_oid *tree, *tmp;
1775 struct ioat_softc *ioat;
1776
1777 ioat = DEVICE2SOFTC(device);
1778 ctx = device_get_sysctl_ctx(device);
1779 tree = device_get_sysctl_tree(device);
1780 par = SYSCTL_CHILDREN(tree);
1781
1782 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD,
1783 &ioat->version, 0, "HW version (0xMM form)");
1784 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD,
1785 &ioat->max_xfer_size, 0, "HW maximum transfer size");
1786 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD,
1787 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported");
1788 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD,
1789 &ioat->intrdelay_max, 0,
1790 "Maximum configurable INTRDELAY on this channel (microseconds)");
1791
1792 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL,
1793 "IOAT channel internal state");
1794 state = SYSCTL_CHILDREN(tmp);
1795
1796 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD,
1797 &ioat->ring_size_order, 0, "SW descriptor ring size order");
1798 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head,
1799 0, "SW descriptor head pointer index");
1800 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail,
1801 0, "SW descriptor tail pointer index");
1802
1803 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD,
1804 ioat->comp_update, "HW addr of last completion");
1805
1806 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing",
1807 CTLFLAG_RD, &ioat->is_submitter_processing, 0,
1808 "submitter processing");
1809
1810 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts",
1811 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A",
1812 "String of the channel status");
1813
1814 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD,
1815 &ioat->cached_intrdelay, 0,
1816 "Current INTRDELAY on this channel (cached, microseconds)");
1817
1818 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL,
1819 "Big hammers (mostly for testing)");
1820 hammer = SYSCTL_CHILDREN(tmp);
1821
1822 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset",
1823 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I",
1824 "Set to non-zero to reset the hardware");
1825
1826 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL,
1827 "IOAT channel statistics");
1828 statpar = SYSCTL_CHILDREN(tmp);
1829
1830 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW,
1831 &ioat->stats.interrupts,
1832 "Number of interrupts processed on this channel");
1833 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW,
1834 &ioat->stats.descriptors_processed,
1835 "Number of descriptors processed on this channel");
1836 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW,
1837 &ioat->stats.descriptors_submitted,
1838 "Number of descriptors submitted to this channel");
1839 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW,
1840 &ioat->stats.descriptors_error,
1841 "Number of descriptors failed by channel errors");
1842 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW,
1843 &ioat->stats.channel_halts, 0,
1844 "Number of times the channel has halted");
1845 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW,
1846 &ioat->stats.last_halt_chanerr, 0,
1847 "The raw CHANERR when the channel was last halted");
1848
1849 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt",
1850 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A",
1851 "Descriptors per interrupt");
1852 }
1853
1854 static void
ioat_get(struct ioat_softc * ioat)1855 ioat_get(struct ioat_softc *ioat)
1856 {
1857
1858 mtx_assert(&ioat->submit_lock, MA_OWNED);
1859 KASSERT(ioat->refcnt < UINT32_MAX, ("refcnt overflow"));
1860
1861 ioat->refcnt++;
1862 }
1863
1864 static void
ioat_put(struct ioat_softc * ioat)1865 ioat_put(struct ioat_softc *ioat)
1866 {
1867
1868 mtx_assert(&ioat->submit_lock, MA_OWNED);
1869 KASSERT(ioat->refcnt >= 1, ("refcnt error"));
1870
1871 if (--ioat->refcnt == 0)
1872 wakeup(&ioat->refcnt);
1873 }
1874
1875 static void
ioat_drain_locked(struct ioat_softc * ioat)1876 ioat_drain_locked(struct ioat_softc *ioat)
1877 {
1878
1879 mtx_assert(&ioat->submit_lock, MA_OWNED);
1880
1881 while (ioat->refcnt > 0)
1882 msleep(&ioat->refcnt, &ioat->submit_lock, 0, "ioat_drain", 0);
1883 }
1884
1885 #ifdef DDB
1886 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo)
1887 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object)
DB_SHOW_COMMAND(ioat,db_show_ioat)1888 DB_SHOW_COMMAND(ioat, db_show_ioat)
1889 {
1890 struct ioat_softc *sc;
1891 unsigned idx;
1892
1893 if (!have_addr)
1894 goto usage;
1895 idx = (unsigned)addr;
1896 if (idx >= ioat_channel_index)
1897 goto usage;
1898
1899 sc = ioat_channel[idx];
1900 db_printf("ioat softc at %p\n", sc);
1901 if (sc == NULL)
1902 return;
1903
1904 db_printf(" version: %d\n", sc->version);
1905 db_printf(" chan_idx: %u\n", sc->chan_idx);
1906 db_printf(" submit_lock: ");
1907 db_show_lock(&sc->submit_lock);
1908
1909 db_printf(" capabilities: %b\n", (int)sc->capabilities,
1910 IOAT_DMACAP_STR);
1911 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay);
1912 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update);
1913
1914 db_printf(" poll_timer:\n");
1915 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time);
1916 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg);
1917 db_printf(" c_func: %p\n", sc->poll_timer.c_func);
1918 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock);
1919 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags);
1920
1921 db_printf(" quiescing: %d\n", (int)sc->quiescing);
1922 db_printf(" destroying: %d\n", (int)sc->destroying);
1923 db_printf(" is_submitter_processing: %d\n",
1924 (int)sc->is_submitter_processing);
1925 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported);
1926 db_printf(" resetting: %d\n", (int)sc->resetting);
1927
1928 db_printf(" head: %u\n", sc->head);
1929 db_printf(" tail: %u\n", sc->tail);
1930 db_printf(" ring_size_order: %u\n", sc->ring_size_order);
1931 db_printf(" last_seen: 0x%lx\n", sc->last_seen);
1932 db_printf(" ring: %p\n", sc->ring);
1933 db_printf(" descriptors: %p\n", sc->hw_desc_ring);
1934 db_printf(" descriptors (phys): 0x%jx\n",
1935 (uintmax_t)sc->hw_desc_bus_addr);
1936
1937 db_printf(" ring[%u] (tail):\n", sc->tail %
1938 (1 << sc->ring_size_order));
1939 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id);
1940 db_printf(" addr: 0x%lx\n",
1941 RING_PHYS_ADDR(sc, sc->tail));
1942 db_printf(" next: 0x%lx\n",
1943 ioat_get_descriptor(sc, sc->tail)->generic.next);
1944
1945 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) %
1946 (1 << sc->ring_size_order));
1947 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id);
1948 db_printf(" addr: 0x%lx\n",
1949 RING_PHYS_ADDR(sc, sc->head - 1));
1950 db_printf(" next: 0x%lx\n",
1951 ioat_get_descriptor(sc, sc->head - 1)->generic.next);
1952
1953 db_printf(" ring[%u] (head):\n", (sc->head) %
1954 (1 << sc->ring_size_order));
1955 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id);
1956 db_printf(" addr: 0x%lx\n",
1957 RING_PHYS_ADDR(sc, sc->head));
1958 db_printf(" next: 0x%lx\n",
1959 ioat_get_descriptor(sc, sc->head)->generic.next);
1960
1961 for (idx = 0; idx < (1 << sc->ring_size_order); idx++)
1962 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK)
1963 == RING_PHYS_ADDR(sc, idx))
1964 db_printf(" ring[%u] == hardware tail\n", idx);
1965
1966 db_printf(" cleanup_lock: ");
1967 db_show_lock(&sc->cleanup_lock);
1968
1969 db_printf(" refcnt: %u\n", sc->refcnt);
1970 db_printf(" stats:\n");
1971 db_printf(" interrupts: %lu\n", sc->stats.interrupts);
1972 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed);
1973 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error);
1974 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted);
1975
1976 db_printf(" channel_halts: %u\n", sc->stats.channel_halts);
1977 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr);
1978
1979 if (db_pager_quit)
1980 return;
1981
1982 db_printf(" hw status:\n");
1983 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc));
1984 db_printf(" chanctrl: 0x%x\n",
1985 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET));
1986 db_printf(" chancmd: 0x%x\n",
1987 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET));
1988 db_printf(" dmacount: 0x%x\n",
1989 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET));
1990 db_printf(" chainaddr: 0x%lx\n",
1991 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW));
1992 db_printf(" chancmp: 0x%lx\n",
1993 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW));
1994 db_printf(" chanerr: %b\n",
1995 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR);
1996 return;
1997 usage:
1998 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index);
1999 return;
2000 }
2001 #endif /* DDB */
2002