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39
40
41 /**
42 * cvmx-uctlx-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon uctlx.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_UCTLX_DEFS_H__
53 #define __CVMX_UCTLX_DEFS_H__
54
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_BIST_STATUS(unsigned long block_id)56 static inline uint64_t CVMX_UCTLX_BIST_STATUS(unsigned long block_id)
57 {
58 if (!(
59 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
63 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
64 cvmx_warn("CVMX_UCTLX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
65 return CVMX_ADD_IO_SEG(0x000118006F0000A0ull);
66 }
67 #else
68 #define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
69 #endif
70 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_CLK_RST_CTL(unsigned long block_id)71 static inline uint64_t CVMX_UCTLX_CLK_RST_CTL(unsigned long block_id)
72 {
73 if (!(
74 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
75 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
76 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
77 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
78 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
79 cvmx_warn("CVMX_UCTLX_CLK_RST_CTL(%lu) is invalid on this chip\n", block_id);
80 return CVMX_ADD_IO_SEG(0x000118006F000000ull);
81 }
82 #else
83 #define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
84 #endif
85 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_EHCI_CTL(unsigned long block_id)86 static inline uint64_t CVMX_UCTLX_EHCI_CTL(unsigned long block_id)
87 {
88 if (!(
89 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
90 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
91 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
92 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
93 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
94 cvmx_warn("CVMX_UCTLX_EHCI_CTL(%lu) is invalid on this chip\n", block_id);
95 return CVMX_ADD_IO_SEG(0x000118006F000080ull);
96 }
97 #else
98 #define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
99 #endif
100 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_EHCI_FLA(unsigned long block_id)101 static inline uint64_t CVMX_UCTLX_EHCI_FLA(unsigned long block_id)
102 {
103 if (!(
104 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
105 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
106 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
107 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
108 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
109 cvmx_warn("CVMX_UCTLX_EHCI_FLA(%lu) is invalid on this chip\n", block_id);
110 return CVMX_ADD_IO_SEG(0x000118006F0000A8ull);
111 }
112 #else
113 #define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
114 #endif
115 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_ERTO_CTL(unsigned long block_id)116 static inline uint64_t CVMX_UCTLX_ERTO_CTL(unsigned long block_id)
117 {
118 if (!(
119 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
121 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
122 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
123 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
124 cvmx_warn("CVMX_UCTLX_ERTO_CTL(%lu) is invalid on this chip\n", block_id);
125 return CVMX_ADD_IO_SEG(0x000118006F000090ull);
126 }
127 #else
128 #define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
129 #endif
130 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_IF_ENA(unsigned long block_id)131 static inline uint64_t CVMX_UCTLX_IF_ENA(unsigned long block_id)
132 {
133 if (!(
134 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
135 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
136 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
137 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
138 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
139 cvmx_warn("CVMX_UCTLX_IF_ENA(%lu) is invalid on this chip\n", block_id);
140 return CVMX_ADD_IO_SEG(0x000118006F000030ull);
141 }
142 #else
143 #define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
144 #endif
145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_INT_ENA(unsigned long block_id)146 static inline uint64_t CVMX_UCTLX_INT_ENA(unsigned long block_id)
147 {
148 if (!(
149 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
150 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
151 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
152 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
153 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
154 cvmx_warn("CVMX_UCTLX_INT_ENA(%lu) is invalid on this chip\n", block_id);
155 return CVMX_ADD_IO_SEG(0x000118006F000028ull);
156 }
157 #else
158 #define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
159 #endif
160 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_INT_REG(unsigned long block_id)161 static inline uint64_t CVMX_UCTLX_INT_REG(unsigned long block_id)
162 {
163 if (!(
164 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
166 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
167 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
168 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
169 cvmx_warn("CVMX_UCTLX_INT_REG(%lu) is invalid on this chip\n", block_id);
170 return CVMX_ADD_IO_SEG(0x000118006F000020ull);
171 }
172 #else
173 #define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
174 #endif
175 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_OHCI_CTL(unsigned long block_id)176 static inline uint64_t CVMX_UCTLX_OHCI_CTL(unsigned long block_id)
177 {
178 if (!(
179 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
181 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
182 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
183 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
184 cvmx_warn("CVMX_UCTLX_OHCI_CTL(%lu) is invalid on this chip\n", block_id);
185 return CVMX_ADD_IO_SEG(0x000118006F000088ull);
186 }
187 #else
188 #define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
189 #endif
190 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_ORTO_CTL(unsigned long block_id)191 static inline uint64_t CVMX_UCTLX_ORTO_CTL(unsigned long block_id)
192 {
193 if (!(
194 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
195 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
196 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
197 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
198 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
199 cvmx_warn("CVMX_UCTLX_ORTO_CTL(%lu) is invalid on this chip\n", block_id);
200 return CVMX_ADD_IO_SEG(0x000118006F000098ull);
201 }
202 #else
203 #define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
204 #endif
205 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_PPAF_WM(unsigned long block_id)206 static inline uint64_t CVMX_UCTLX_PPAF_WM(unsigned long block_id)
207 {
208 if (!(
209 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
210 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
211 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
212 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
213 cvmx_warn("CVMX_UCTLX_PPAF_WM(%lu) is invalid on this chip\n", block_id);
214 return CVMX_ADD_IO_SEG(0x000118006F000038ull);
215 }
216 #else
217 #define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
218 #endif
219 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_UPHY_CTL_STATUS(unsigned long block_id)220 static inline uint64_t CVMX_UCTLX_UPHY_CTL_STATUS(unsigned long block_id)
221 {
222 if (!(
223 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
224 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) ||
225 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
227 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
228 cvmx_warn("CVMX_UCTLX_UPHY_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
229 return CVMX_ADD_IO_SEG(0x000118006F000008ull);
230 }
231 #else
232 #define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
233 #endif
234 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(unsigned long offset,unsigned long block_id)235 static inline uint64_t CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(unsigned long offset, unsigned long block_id)
236 {
237 if (!(
238 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 1)) && ((block_id == 0)))) ||
239 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id == 0)))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0)))) ||
241 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 1)) && ((block_id == 0)))) ||
242 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 1)) && ((block_id == 0))))))
243 cvmx_warn("CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(%lu,%lu) is invalid on this chip\n", offset, block_id);
244 return CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8;
245 }
246 #else
247 #define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
248 #endif
249
250 /**
251 * cvmx_uctl#_bist_status
252 *
253 * UCTL_BIST_STATUS = UCTL Bist Status
254 *
255 * Results from BIST runs of UCTL's memories.
256 */
257 union cvmx_uctlx_bist_status {
258 uint64_t u64;
259 struct cvmx_uctlx_bist_status_s {
260 #ifdef __BIG_ENDIAN_BITFIELD
261 uint64_t reserved_6_63 : 58;
262 uint64_t data_bis : 1; /**< UAHC EHCI Data Ram Bist Status */
263 uint64_t desc_bis : 1; /**< UAHC EHCI Descriptor Ram Bist Status */
264 uint64_t erbm_bis : 1; /**< UCTL EHCI Read Buffer Memory Bist Status */
265 uint64_t orbm_bis : 1; /**< UCTL OHCI Read Buffer Memory Bist Status */
266 uint64_t wrbm_bis : 1; /**< UCTL Write Buffer Memory Bist Sta */
267 uint64_t ppaf_bis : 1; /**< PP Access FIFO Memory Bist Status */
268 #else
269 uint64_t ppaf_bis : 1;
270 uint64_t wrbm_bis : 1;
271 uint64_t orbm_bis : 1;
272 uint64_t erbm_bis : 1;
273 uint64_t desc_bis : 1;
274 uint64_t data_bis : 1;
275 uint64_t reserved_6_63 : 58;
276 #endif
277 } s;
278 struct cvmx_uctlx_bist_status_s cn61xx;
279 struct cvmx_uctlx_bist_status_s cn63xx;
280 struct cvmx_uctlx_bist_status_s cn63xxp1;
281 struct cvmx_uctlx_bist_status_s cn66xx;
282 struct cvmx_uctlx_bist_status_s cn68xx;
283 struct cvmx_uctlx_bist_status_s cn68xxp1;
284 struct cvmx_uctlx_bist_status_s cnf71xx;
285 };
286 typedef union cvmx_uctlx_bist_status cvmx_uctlx_bist_status_t;
287
288 /**
289 * cvmx_uctl#_clk_rst_ctl
290 *
291 * CLK_RST_CTL = Clock and Reset Control Reigster
292 * This register controls the frequceny of hclk and resets for hclk and phy clocks. It also controls Simulation modes and Bists.
293 */
294 union cvmx_uctlx_clk_rst_ctl {
295 uint64_t u64;
296 struct cvmx_uctlx_clk_rst_ctl_s {
297 #ifdef __BIG_ENDIAN_BITFIELD
298 uint64_t reserved_25_63 : 39;
299 uint64_t clear_bist : 1; /**< Clear BIST on the HCLK memories */
300 uint64_t start_bist : 1; /**< Starts BIST on the HCLK memories during 0-to-1
301 transition. */
302 uint64_t ehci_sm : 1; /**< Only set it during simulation time. When set to 1,
303 this bit sets the PHY in a non-driving mode so the
304 EHCI can detect device connection.
305 Note: it must not be set to 1, during normal
306 operation. */
307 uint64_t ohci_clkcktrst : 1; /**< Clear clock reset. Active low. OHCI initial reset
308 signal for the DPLL block. This is only needed by
309 simulation. The duration of the reset in simulation
310 must be the same as HRST.
311 Note: it must be set to 1 during normal operation. */
312 uint64_t ohci_sm : 1; /**< OHCI Simulation Mode. It selects the counter value
313 for simulation or real time for 1 ms.
314 - 0: counter full 1ms; 1: simulation time. */
315 uint64_t ohci_susp_lgcy : 1; /**< OHCI Clock Control Signal. Note: This bit must be
316 set to 0 if the OHCI 48/12Mhz clocks must be
317 suspended when the EHCI and OHCI controllers are
318 not active. */
319 uint64_t app_start_clk : 1; /**< OHCI Clock Control Signal. When the OHCI clocks are
320 suspended, the system has to assert this signal to
321 start the clocks (12 and 48 Mhz). */
322 uint64_t o_clkdiv_rst : 1; /**< OHCI 12Mhz clock divider reset. Active low. When
323 set to 0, divider is held in reset.
324 The reset to the divider is also asserted when core
325 reset is asserted. */
326 uint64_t h_clkdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV */
327 uint64_t h_clkdiv_rst : 1; /**< Host clock divider reset. Active low. When set to 0,
328 divider is held in reset. This must be set to 0
329 before change H_DIV0 and H_DIV1.
330 The reset to the divider is also asserted when core
331 reset is asserted. */
332 uint64_t h_clkdiv_en : 1; /**< Hclk enable. When set to 1, the hclk is gernerated. */
333 uint64_t o_clkdiv_en : 1; /**< OHCI 48Mhz/12MHz clock enable. When set to 1, the
334 clocks are gernerated. */
335 uint64_t h_div : 4; /**< The hclk frequency is sclk frequency divided by
336 H_DIV. The maximum frequency of hclk is 200Mhz.
337 The minimum frequency of hclk is no less than the
338 UTMI clock frequency which is 60Mhz. After writing a
339 value to this field, the software should read the
340 field for the value written. The [H_ENABLE] field of
341 this register should not be set until after this
342 field is set and then read.
343 Only the following values are valid:
344 1, 2, 3, 4, 6, 8, 12.
345 All other values are reserved and will be coded as
346 following:
347 0 -> 1
348 5 -> 4
349 7 -> 6
350 9,10,11 -> 8
351 13,14,15 -> 12 */
352 uint64_t p_refclk_sel : 2; /**< PHY PLL Reference Clock Select.
353 - 00: uses 12Mhz crystal at USB_XO and USB_XI;
354 - 01: uses 12/24/48Mhz 2.5V clock source at USB_XO.
355 USB_XI should be tied to GND(Not Supported).
356 1x: Reserved. */
357 uint64_t p_refclk_div : 2; /**< PHY Reference Clock Frequency Select.
358 - 00: 12MHz,
359 - 01: 24Mhz (Not Supported),
360 - 10: 48Mhz (Not Supported),
361 - 11: Reserved.
362 Note: This value must be set during POR is active.
363 If a crystal is used as a reference clock,this field
364 must be set to 12 MHz. Values 01 and 10 are reserved
365 when a crystal is used. */
366 uint64_t reserved_4_4 : 1;
367 uint64_t p_com_on : 1; /**< PHY Common Block Power-Down Control.
368 - 1: The XO, Bias, and PLL blocks are powered down in
369 Suspend mode.
370 - 0: The XO, Bias, and PLL blocks remain powered in
371 suspend mode.
372 Note: This bit must be set to 0 during POR is active
373 in current design. */
374 uint64_t p_por : 1; /**< Power on reset for PHY. Resets all the PHY's
375 registers and state machines. */
376 uint64_t p_prst : 1; /**< PHY Clock Reset. The is the value for phy_rst_n,
377 utmi_rst_n[1] and utmi_rst_n[0]. It is synchronized
378 to each clock domain to generate the corresponding
379 reset signal. This should not be set to 1 until the
380 time it takes for six clock cycles (HCLK and
381 PHY CLK, which ever is slower) has passed. */
382 uint64_t hrst : 1; /**< Host Clock Reset. This is the value for hreset_n.
383 This should not be set to 1 until 12ms after PHY CLK
384 is stable. */
385 #else
386 uint64_t hrst : 1;
387 uint64_t p_prst : 1;
388 uint64_t p_por : 1;
389 uint64_t p_com_on : 1;
390 uint64_t reserved_4_4 : 1;
391 uint64_t p_refclk_div : 2;
392 uint64_t p_refclk_sel : 2;
393 uint64_t h_div : 4;
394 uint64_t o_clkdiv_en : 1;
395 uint64_t h_clkdiv_en : 1;
396 uint64_t h_clkdiv_rst : 1;
397 uint64_t h_clkdiv_byp : 1;
398 uint64_t o_clkdiv_rst : 1;
399 uint64_t app_start_clk : 1;
400 uint64_t ohci_susp_lgcy : 1;
401 uint64_t ohci_sm : 1;
402 uint64_t ohci_clkcktrst : 1;
403 uint64_t ehci_sm : 1;
404 uint64_t start_bist : 1;
405 uint64_t clear_bist : 1;
406 uint64_t reserved_25_63 : 39;
407 #endif
408 } s;
409 struct cvmx_uctlx_clk_rst_ctl_s cn61xx;
410 struct cvmx_uctlx_clk_rst_ctl_s cn63xx;
411 struct cvmx_uctlx_clk_rst_ctl_s cn63xxp1;
412 struct cvmx_uctlx_clk_rst_ctl_s cn66xx;
413 struct cvmx_uctlx_clk_rst_ctl_s cn68xx;
414 struct cvmx_uctlx_clk_rst_ctl_s cn68xxp1;
415 struct cvmx_uctlx_clk_rst_ctl_s cnf71xx;
416 };
417 typedef union cvmx_uctlx_clk_rst_ctl cvmx_uctlx_clk_rst_ctl_t;
418
419 /**
420 * cvmx_uctl#_ehci_ctl
421 *
422 * UCTL_EHCI_CTL = UCTL EHCI Control Register
423 * This register controls the general behavior of UCTL EHCI datapath.
424 */
425 union cvmx_uctlx_ehci_ctl {
426 uint64_t u64;
427 struct cvmx_uctlx_ehci_ctl_s {
428 #ifdef __BIG_ENDIAN_BITFIELD
429 uint64_t reserved_20_63 : 44;
430 uint64_t desc_rbm : 1; /**< Descriptor Read Burst Mode on AHB bus
431 - 1: A read burst can be interruprted after 16 AHB
432 clock cycle
433 - 0: A read burst will not be interrupted until it
434 finishes or no more data available */
435 uint64_t reg_nb : 1; /**< 1: EHCI register access will not be blocked by EHCI
436 buffer/descriptor access on AHB
437 - 0: Buffer/descriptor and register access will be
438 mutually exclusive */
439 uint64_t l2c_dc : 1; /**< When set to 1, set the commit bit in the descriptor
440 store commands to L2C. */
441 uint64_t l2c_bc : 1; /**< When set to 1, set the commit bit in the buffer
442 store commands to L2C. */
443 uint64_t l2c_0pag : 1; /**< When set to 1, sets the zero-page bit in store
444 command to L2C. */
445 uint64_t l2c_stt : 1; /**< When set to 1, use STT when store to L2C. */
446 uint64_t l2c_buff_emod : 2; /**< Endian format for buffer from/to the L2C.
447 IN: A-B-C-D-E-F-G-H
448 OUT0: A-B-C-D-E-F-G-H
449 OUT1: H-G-F-E-D-C-B-A
450 OUT2: D-C-B-A-H-G-F-E
451 OUT3: E-F-G-H-A-B-C-D */
452 uint64_t l2c_desc_emod : 2; /**< Endian format for descriptor from/to the L2C.
453 IN: A-B-C-D-E-F-G-H
454 OUT0: A-B-C-D-E-F-G-H
455 OUT1: H-G-F-E-D-C-B-A
456 OUT2: D-C-B-A-H-G-F-E
457 OUT3: E-F-G-H-A-B-C-D */
458 uint64_t inv_reg_a2 : 1; /**< UAHC register address bit<2> invert. When set to 1,
459 for a 32-bit NCB I/O register access, the address
460 offset will be flipped between 0x4 and 0x0. */
461 uint64_t ehci_64b_addr_en : 1; /**< EHCI AHB Master 64-bit Addressing Enable.
462 - 1: enable ehci 64-bit addressing mode;
463 - 0: disable ehci 64-bit addressing mode.
464 When ehci 64-bit addressing mode is disabled,
465 UCTL_EHCI_CTL[L2C_ADDR_MSB] is used as the address
466 bit[39:32]. */
467 uint64_t l2c_addr_msb : 8; /**< This is the bit [39:32] of an address sent to L2C
468 for ehci whenUCTL_EHCI_CFG[EHCI_64B_ADDR_EN=0]). */
469 #else
470 uint64_t l2c_addr_msb : 8;
471 uint64_t ehci_64b_addr_en : 1;
472 uint64_t inv_reg_a2 : 1;
473 uint64_t l2c_desc_emod : 2;
474 uint64_t l2c_buff_emod : 2;
475 uint64_t l2c_stt : 1;
476 uint64_t l2c_0pag : 1;
477 uint64_t l2c_bc : 1;
478 uint64_t l2c_dc : 1;
479 uint64_t reg_nb : 1;
480 uint64_t desc_rbm : 1;
481 uint64_t reserved_20_63 : 44;
482 #endif
483 } s;
484 struct cvmx_uctlx_ehci_ctl_s cn61xx;
485 struct cvmx_uctlx_ehci_ctl_s cn63xx;
486 struct cvmx_uctlx_ehci_ctl_s cn63xxp1;
487 struct cvmx_uctlx_ehci_ctl_s cn66xx;
488 struct cvmx_uctlx_ehci_ctl_s cn68xx;
489 struct cvmx_uctlx_ehci_ctl_s cn68xxp1;
490 struct cvmx_uctlx_ehci_ctl_s cnf71xx;
491 };
492 typedef union cvmx_uctlx_ehci_ctl cvmx_uctlx_ehci_ctl_t;
493
494 /**
495 * cvmx_uctl#_ehci_fla
496 *
497 * UCTL_EHCI_FLA = UCTL EHCI Frame Length Adjument Register
498 * This register configures the EHCI Frame Length Adjustment.
499 */
500 union cvmx_uctlx_ehci_fla {
501 uint64_t u64;
502 struct cvmx_uctlx_ehci_fla_s {
503 #ifdef __BIG_ENDIAN_BITFIELD
504 uint64_t reserved_6_63 : 58;
505 uint64_t fla : 6; /**< EHCI Frame Length Adjustment. This feature
506 adjusts any offset from the clock source that drives
507 the uSOF counter. The uSOF cycle time (number of
508 uSOF counter clock periods to generate a uSOF
509 microframe length) is equal to 59,488 plus this value.
510 The default value is 32(0x20), which gives an SOF cycle
511 time of 60,000 (each microframe has 60,000 bit times).
512 -------------------------------------------------
513 Frame Length (decimal) FLA Value
514 -------------------------------------------------
515 59488 0x00
516 59504 0x01
517 59520 0x02
518 ... ...
519 59984 0x1F
520 60000 0x20
521 60016 0x21
522 ... ...
523 60496 0x3F
524 --------------------------------------------------
525 Note: keep this value to 0x20 (decimal 32) for no
526 offset. */
527 #else
528 uint64_t fla : 6;
529 uint64_t reserved_6_63 : 58;
530 #endif
531 } s;
532 struct cvmx_uctlx_ehci_fla_s cn61xx;
533 struct cvmx_uctlx_ehci_fla_s cn63xx;
534 struct cvmx_uctlx_ehci_fla_s cn63xxp1;
535 struct cvmx_uctlx_ehci_fla_s cn66xx;
536 struct cvmx_uctlx_ehci_fla_s cn68xx;
537 struct cvmx_uctlx_ehci_fla_s cn68xxp1;
538 struct cvmx_uctlx_ehci_fla_s cnf71xx;
539 };
540 typedef union cvmx_uctlx_ehci_fla cvmx_uctlx_ehci_fla_t;
541
542 /**
543 * cvmx_uctl#_erto_ctl
544 *
545 * UCTL_ERTO_CTL = UCTL EHCI Readbuffer TimeOut Control Register
546 * This register controls timeout for EHCI Readbuffer.
547 */
548 union cvmx_uctlx_erto_ctl {
549 uint64_t u64;
550 struct cvmx_uctlx_erto_ctl_s {
551 #ifdef __BIG_ENDIAN_BITFIELD
552 uint64_t reserved_32_63 : 32;
553 uint64_t to_val : 27; /**< Read buffer timeout value
554 (value 0 means timeout disabled) */
555 uint64_t reserved_0_4 : 5;
556 #else
557 uint64_t reserved_0_4 : 5;
558 uint64_t to_val : 27;
559 uint64_t reserved_32_63 : 32;
560 #endif
561 } s;
562 struct cvmx_uctlx_erto_ctl_s cn61xx;
563 struct cvmx_uctlx_erto_ctl_s cn63xx;
564 struct cvmx_uctlx_erto_ctl_s cn63xxp1;
565 struct cvmx_uctlx_erto_ctl_s cn66xx;
566 struct cvmx_uctlx_erto_ctl_s cn68xx;
567 struct cvmx_uctlx_erto_ctl_s cn68xxp1;
568 struct cvmx_uctlx_erto_ctl_s cnf71xx;
569 };
570 typedef union cvmx_uctlx_erto_ctl cvmx_uctlx_erto_ctl_t;
571
572 /**
573 * cvmx_uctl#_if_ena
574 *
575 * UCTL_IF_ENA = UCTL Interface Enable Register
576 *
577 * Register to enable the uctl interface clock.
578 */
579 union cvmx_uctlx_if_ena {
580 uint64_t u64;
581 struct cvmx_uctlx_if_ena_s {
582 #ifdef __BIG_ENDIAN_BITFIELD
583 uint64_t reserved_1_63 : 63;
584 uint64_t en : 1; /**< Turns on the USB UCTL interface clock */
585 #else
586 uint64_t en : 1;
587 uint64_t reserved_1_63 : 63;
588 #endif
589 } s;
590 struct cvmx_uctlx_if_ena_s cn61xx;
591 struct cvmx_uctlx_if_ena_s cn63xx;
592 struct cvmx_uctlx_if_ena_s cn63xxp1;
593 struct cvmx_uctlx_if_ena_s cn66xx;
594 struct cvmx_uctlx_if_ena_s cn68xx;
595 struct cvmx_uctlx_if_ena_s cn68xxp1;
596 struct cvmx_uctlx_if_ena_s cnf71xx;
597 };
598 typedef union cvmx_uctlx_if_ena cvmx_uctlx_if_ena_t;
599
600 /**
601 * cvmx_uctl#_int_ena
602 *
603 * UCTL_INT_ENA = UCTL Interrupt Enable Register
604 *
605 * Register to enable individual interrupt source in corresponding to UCTL_INT_REG
606 */
607 union cvmx_uctlx_int_ena {
608 uint64_t u64;
609 struct cvmx_uctlx_int_ena_s {
610 #ifdef __BIG_ENDIAN_BITFIELD
611 uint64_t reserved_8_63 : 56;
612 uint64_t ec_ovf_e : 1; /**< Ehci Commit OVerFlow Error */
613 uint64_t oc_ovf_e : 1; /**< Ohci Commit OVerFlow Error */
614 uint64_t wb_pop_e : 1; /**< Write Buffer FIFO Poped When Empty */
615 uint64_t wb_psh_f : 1; /**< Write Buffer FIFO Pushed When Full */
616 uint64_t cf_psh_f : 1; /**< Command FIFO Pushed When Full */
617 uint64_t or_psh_f : 1; /**< OHCI Read Buffer FIFO Pushed When Full */
618 uint64_t er_psh_f : 1; /**< EHCI Read Buffer FIFO Pushed When Full */
619 uint64_t pp_psh_f : 1; /**< PP Access FIFO Pushed When Full */
620 #else
621 uint64_t pp_psh_f : 1;
622 uint64_t er_psh_f : 1;
623 uint64_t or_psh_f : 1;
624 uint64_t cf_psh_f : 1;
625 uint64_t wb_psh_f : 1;
626 uint64_t wb_pop_e : 1;
627 uint64_t oc_ovf_e : 1;
628 uint64_t ec_ovf_e : 1;
629 uint64_t reserved_8_63 : 56;
630 #endif
631 } s;
632 struct cvmx_uctlx_int_ena_s cn61xx;
633 struct cvmx_uctlx_int_ena_s cn63xx;
634 struct cvmx_uctlx_int_ena_s cn63xxp1;
635 struct cvmx_uctlx_int_ena_s cn66xx;
636 struct cvmx_uctlx_int_ena_s cn68xx;
637 struct cvmx_uctlx_int_ena_s cn68xxp1;
638 struct cvmx_uctlx_int_ena_s cnf71xx;
639 };
640 typedef union cvmx_uctlx_int_ena cvmx_uctlx_int_ena_t;
641
642 /**
643 * cvmx_uctl#_int_reg
644 *
645 * UCTL_INT_REG = UCTL Interrupt Register
646 *
647 * Summary of different bits of RSL interrupt status.
648 */
649 union cvmx_uctlx_int_reg {
650 uint64_t u64;
651 struct cvmx_uctlx_int_reg_s {
652 #ifdef __BIG_ENDIAN_BITFIELD
653 uint64_t reserved_8_63 : 56;
654 uint64_t ec_ovf_e : 1; /**< Ehci Commit OVerFlow Error
655 When the error happenes, the whole NCB system needs
656 to be reset. */
657 uint64_t oc_ovf_e : 1; /**< Ohci Commit OVerFlow Error
658 When the error happenes, the whole NCB system needs
659 to be reset. */
660 uint64_t wb_pop_e : 1; /**< Write Buffer FIFO Poped When Empty */
661 uint64_t wb_psh_f : 1; /**< Write Buffer FIFO Pushed When Full */
662 uint64_t cf_psh_f : 1; /**< Command FIFO Pushed When Full */
663 uint64_t or_psh_f : 1; /**< OHCI Read Buffer FIFO Pushed When Full */
664 uint64_t er_psh_f : 1; /**< EHCI Read Buffer FIFO Pushed When Full */
665 uint64_t pp_psh_f : 1; /**< PP Access FIFO Pushed When Full */
666 #else
667 uint64_t pp_psh_f : 1;
668 uint64_t er_psh_f : 1;
669 uint64_t or_psh_f : 1;
670 uint64_t cf_psh_f : 1;
671 uint64_t wb_psh_f : 1;
672 uint64_t wb_pop_e : 1;
673 uint64_t oc_ovf_e : 1;
674 uint64_t ec_ovf_e : 1;
675 uint64_t reserved_8_63 : 56;
676 #endif
677 } s;
678 struct cvmx_uctlx_int_reg_s cn61xx;
679 struct cvmx_uctlx_int_reg_s cn63xx;
680 struct cvmx_uctlx_int_reg_s cn63xxp1;
681 struct cvmx_uctlx_int_reg_s cn66xx;
682 struct cvmx_uctlx_int_reg_s cn68xx;
683 struct cvmx_uctlx_int_reg_s cn68xxp1;
684 struct cvmx_uctlx_int_reg_s cnf71xx;
685 };
686 typedef union cvmx_uctlx_int_reg cvmx_uctlx_int_reg_t;
687
688 /**
689 * cvmx_uctl#_ohci_ctl
690 *
691 * RSL registers starting from 0x10 can be accessed only after hclk is active and hreset is deasserted.
692 *
693 * UCTL_OHCI_CTL = UCTL OHCI Control Register
694 * This register controls the general behavior of UCTL OHCI datapath.
695 */
696 union cvmx_uctlx_ohci_ctl {
697 uint64_t u64;
698 struct cvmx_uctlx_ohci_ctl_s {
699 #ifdef __BIG_ENDIAN_BITFIELD
700 uint64_t reserved_19_63 : 45;
701 uint64_t reg_nb : 1; /**< 1: OHCI register access will not be blocked by EHCI
702 buffer/descriptor access on AHB
703 - 0: Buffer/descriptor and register access will be
704 mutually exclusive */
705 uint64_t l2c_dc : 1; /**< When set to 1, set the commit bit in the descriptor
706 store commands to L2C. */
707 uint64_t l2c_bc : 1; /**< When set to 1, set the commit bit in the buffer
708 store commands to L2C. */
709 uint64_t l2c_0pag : 1; /**< When set to 1, sets the zero-page bit in store
710 command to L2C. */
711 uint64_t l2c_stt : 1; /**< When set to 1, use STT when store to L2C. */
712 uint64_t l2c_buff_emod : 2; /**< Endian format for buffer from/to the L2C.
713 IN: A-B-C-D-E-F-G-H
714 OUT0: A-B-C-D-E-F-G-H
715 OUT1: H-G-F-E-D-C-B-A
716 OUT2: D-C-B-A-H-G-F-E
717 OUT3: E-F-G-H-A-B-C-D */
718 uint64_t l2c_desc_emod : 2; /**< Endian format for descriptor from/to the L2C.
719 IN: A-B-C-D-E-F-G-H
720 OUT0: A-B-C-D-E-F-G-H
721 OUT1: H-G-F-E-D-C-B-A
722 OUT2: D-C-B-A-H-G-F-E
723 OUT3: E-F-G-H-A-B-C-D */
724 uint64_t inv_reg_a2 : 1; /**< UAHC register address bit<2> invert. When set to 1,
725 for a 32-bit NCB I/O register access, the address
726 offset will be flipped between 0x4 and 0x0. */
727 uint64_t reserved_8_8 : 1;
728 uint64_t l2c_addr_msb : 8; /**< This is the bit [39:32] of an address sent to L2C
729 for ohci. */
730 #else
731 uint64_t l2c_addr_msb : 8;
732 uint64_t reserved_8_8 : 1;
733 uint64_t inv_reg_a2 : 1;
734 uint64_t l2c_desc_emod : 2;
735 uint64_t l2c_buff_emod : 2;
736 uint64_t l2c_stt : 1;
737 uint64_t l2c_0pag : 1;
738 uint64_t l2c_bc : 1;
739 uint64_t l2c_dc : 1;
740 uint64_t reg_nb : 1;
741 uint64_t reserved_19_63 : 45;
742 #endif
743 } s;
744 struct cvmx_uctlx_ohci_ctl_s cn61xx;
745 struct cvmx_uctlx_ohci_ctl_s cn63xx;
746 struct cvmx_uctlx_ohci_ctl_s cn63xxp1;
747 struct cvmx_uctlx_ohci_ctl_s cn66xx;
748 struct cvmx_uctlx_ohci_ctl_s cn68xx;
749 struct cvmx_uctlx_ohci_ctl_s cn68xxp1;
750 struct cvmx_uctlx_ohci_ctl_s cnf71xx;
751 };
752 typedef union cvmx_uctlx_ohci_ctl cvmx_uctlx_ohci_ctl_t;
753
754 /**
755 * cvmx_uctl#_orto_ctl
756 *
757 * UCTL_ORTO_CTL = UCTL OHCI Readbuffer TimeOut Control Register
758 * This register controls timeout for OHCI Readbuffer.
759 */
760 union cvmx_uctlx_orto_ctl {
761 uint64_t u64;
762 struct cvmx_uctlx_orto_ctl_s {
763 #ifdef __BIG_ENDIAN_BITFIELD
764 uint64_t reserved_32_63 : 32;
765 uint64_t to_val : 24; /**< Read buffer timeout value
766 (value 0 means timeout disabled) */
767 uint64_t reserved_0_7 : 8;
768 #else
769 uint64_t reserved_0_7 : 8;
770 uint64_t to_val : 24;
771 uint64_t reserved_32_63 : 32;
772 #endif
773 } s;
774 struct cvmx_uctlx_orto_ctl_s cn61xx;
775 struct cvmx_uctlx_orto_ctl_s cn63xx;
776 struct cvmx_uctlx_orto_ctl_s cn63xxp1;
777 struct cvmx_uctlx_orto_ctl_s cn66xx;
778 struct cvmx_uctlx_orto_ctl_s cn68xx;
779 struct cvmx_uctlx_orto_ctl_s cn68xxp1;
780 struct cvmx_uctlx_orto_ctl_s cnf71xx;
781 };
782 typedef union cvmx_uctlx_orto_ctl cvmx_uctlx_orto_ctl_t;
783
784 /**
785 * cvmx_uctl#_ppaf_wm
786 *
787 * UCTL_PPAF_WM = UCTL PP Access FIFO WaterMark Register
788 *
789 * Register to set PP access FIFO full watermark.
790 */
791 union cvmx_uctlx_ppaf_wm {
792 uint64_t u64;
793 struct cvmx_uctlx_ppaf_wm_s {
794 #ifdef __BIG_ENDIAN_BITFIELD
795 uint64_t reserved_5_63 : 59;
796 uint64_t wm : 5; /**< Number of entries when PP Access FIFO will assert
797 full (back pressure) */
798 #else
799 uint64_t wm : 5;
800 uint64_t reserved_5_63 : 59;
801 #endif
802 } s;
803 struct cvmx_uctlx_ppaf_wm_s cn61xx;
804 struct cvmx_uctlx_ppaf_wm_s cn63xx;
805 struct cvmx_uctlx_ppaf_wm_s cn63xxp1;
806 struct cvmx_uctlx_ppaf_wm_s cn66xx;
807 struct cvmx_uctlx_ppaf_wm_s cnf71xx;
808 };
809 typedef union cvmx_uctlx_ppaf_wm cvmx_uctlx_ppaf_wm_t;
810
811 /**
812 * cvmx_uctl#_uphy_ctl_status
813 *
814 * UPHY_CTL_STATUS = USB PHY Control and Status Reigster
815 * This register controls the USB PHY test and Bist.
816 */
817 union cvmx_uctlx_uphy_ctl_status {
818 uint64_t u64;
819 struct cvmx_uctlx_uphy_ctl_status_s {
820 #ifdef __BIG_ENDIAN_BITFIELD
821 uint64_t reserved_10_63 : 54;
822 uint64_t bist_done : 1; /**< PHY BIST DONE. Asserted at the end of the PHY BIST
823 sequence. */
824 uint64_t bist_err : 1; /**< PHY BIST Error. Valid when BIST_ENB is high.
825 Indicates an internal error was detected during the
826 BIST sequence. */
827 uint64_t hsbist : 1; /**< High-Speed BIST Enable */
828 uint64_t fsbist : 1; /**< Full-Speed BIST Enable */
829 uint64_t lsbist : 1; /**< Low-Speed BIST Enable */
830 uint64_t siddq : 1; /**< Drives the PHY SIDDQ input. Normally should be set
831 to zero. Customers not using USB PHY interface
832 should do the following:
833 Provide 3.3V to USB_VDD33 Tie USB_REXT to 3.3V
834 supply and Set SIDDQ to 1. */
835 uint64_t vtest_en : 1; /**< Analog Test Pin Enable.
836 1 = The PHY's ANALOG_TEST pin is enabled for the
837 input and output of applicable analog test
838 signals.
839 0 = The ANALOG_TEST pin is disabled. */
840 uint64_t uphy_bist : 1; /**< When set to 1, it makes sure that during PHY BIST,
841 utmi_txvld == 0. */
842 uint64_t bist_en : 1; /**< PHY BIST ENABLE */
843 uint64_t ate_reset : 1; /**< Reset Input from ATE. This is a test signal. When
844 the USB core is powered up (not in suspend mode), an
845 automatic tester can use this to disable PHYCLOCK
846 and FREECLK, then re-enable them with an aligned
847 phase.
848 - 1: PHYCLOCKs and FREECLK outputs are disable.
849 - 0: PHYCLOCKs and FREECLK are available within a
850 specific period after ATERESET is de-asserted. */
851 #else
852 uint64_t ate_reset : 1;
853 uint64_t bist_en : 1;
854 uint64_t uphy_bist : 1;
855 uint64_t vtest_en : 1;
856 uint64_t siddq : 1;
857 uint64_t lsbist : 1;
858 uint64_t fsbist : 1;
859 uint64_t hsbist : 1;
860 uint64_t bist_err : 1;
861 uint64_t bist_done : 1;
862 uint64_t reserved_10_63 : 54;
863 #endif
864 } s;
865 struct cvmx_uctlx_uphy_ctl_status_s cn61xx;
866 struct cvmx_uctlx_uphy_ctl_status_s cn63xx;
867 struct cvmx_uctlx_uphy_ctl_status_s cn63xxp1;
868 struct cvmx_uctlx_uphy_ctl_status_s cn66xx;
869 struct cvmx_uctlx_uphy_ctl_status_s cn68xx;
870 struct cvmx_uctlx_uphy_ctl_status_s cn68xxp1;
871 struct cvmx_uctlx_uphy_ctl_status_s cnf71xx;
872 };
873 typedef union cvmx_uctlx_uphy_ctl_status cvmx_uctlx_uphy_ctl_status_t;
874
875 /**
876 * cvmx_uctl#_uphy_port#_ctl_status
877 *
878 * UPHY_PORTX_CTL_STATUS = USB PHY Port X Control and Status Reigsters
879 * This register controls the each port of the USB PHY.
880 */
881 union cvmx_uctlx_uphy_portx_ctl_status {
882 uint64_t u64;
883 struct cvmx_uctlx_uphy_portx_ctl_status_s {
884 #ifdef __BIG_ENDIAN_BITFIELD
885 uint64_t reserved_43_63 : 21;
886 uint64_t tdata_out : 4; /**< PHY test data out. Presents either interlly
887 generated signals or test register contenets, based
888 upon the value of TDATA_SEL */
889 uint64_t txbiststuffenh : 1; /**< High-Byte Transmit Bit-Stuffing Enable. It must be
890 set to 1'b1 in normal operation. */
891 uint64_t txbiststuffen : 1; /**< Low-Byte Transmit Bit-Stuffing Enable. It must be
892 set to 1'b1 in normal operation. */
893 uint64_t dmpulldown : 1; /**< D- Pull-Down Resistor Enable. It must be set to 1'b1
894 in normal operation. */
895 uint64_t dppulldown : 1; /**< D+ Pull-Down Resistor Enable. It must be set to 1'b1
896 in normal operation. */
897 uint64_t vbusvldext : 1; /**< In host mode, this input is not used and can be tied
898 to 1'b0. */
899 uint64_t portreset : 1; /**< Per-port reset */
900 uint64_t txhsvxtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
901 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment
902 When the recommended 37.4 Ohm resistor is present
903 on USB_REXT, the recommended TXVREFTUNE value is 15 */
904 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment
905 When the recommended 37.4 Ohm resistor is present
906 on USB_REXT, the recommended TXRISETUNE value is 1 */
907 uint64_t txpreemphasistune : 1; /**< HS transmitter pre-emphasis enable.
908 When the recommended 37.4 Ohm resistor is present
909 on USB_REXT, the recommended TXPREEMPHASISTUNE
910 value is 1 */
911 uint64_t txfslstune : 4; /**< FS/LS Source Impedance Adjustment */
912 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
913 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
914 uint64_t loop_en : 1; /**< Port Loop back Test Enable
915 - 1: During data transmission, the receive logic is
916 enabled
917 - 0: During data transmission, the receive logic is
918 disabled */
919 uint64_t tclk : 1; /**< PHY port test clock, used to load TDATA_IN to the
920 UPHY. */
921 uint64_t tdata_sel : 1; /**< Test Data out select
922 - 1: Mode-defined test register contents are output
923 - 0: internally generated signals are output */
924 uint64_t taddr_in : 4; /**< Mode address for test interface. Specifies the
925 register address for writing to or reading from the
926 PHY test interface register. */
927 uint64_t tdata_in : 8; /**< Internal testing Register input data and select.
928 This is a test bus. Data presents on [3:0] and the
929 corresponding select (enable) presents on bits[7:4]. */
930 #else
931 uint64_t tdata_in : 8;
932 uint64_t taddr_in : 4;
933 uint64_t tdata_sel : 1;
934 uint64_t tclk : 1;
935 uint64_t loop_en : 1;
936 uint64_t compdistune : 3;
937 uint64_t sqrxtune : 3;
938 uint64_t txfslstune : 4;
939 uint64_t txpreemphasistune : 1;
940 uint64_t txrisetune : 1;
941 uint64_t txvreftune : 4;
942 uint64_t txhsvxtune : 2;
943 uint64_t portreset : 1;
944 uint64_t vbusvldext : 1;
945 uint64_t dppulldown : 1;
946 uint64_t dmpulldown : 1;
947 uint64_t txbiststuffen : 1;
948 uint64_t txbiststuffenh : 1;
949 uint64_t tdata_out : 4;
950 uint64_t reserved_43_63 : 21;
951 #endif
952 } s;
953 struct cvmx_uctlx_uphy_portx_ctl_status_s cn61xx;
954 struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
955 struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
956 struct cvmx_uctlx_uphy_portx_ctl_status_s cn66xx;
957 struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xx;
958 struct cvmx_uctlx_uphy_portx_ctl_status_s cn68xxp1;
959 struct cvmx_uctlx_uphy_portx_ctl_status_s cnf71xx;
960 };
961 typedef union cvmx_uctlx_uphy_portx_ctl_status cvmx_uctlx_uphy_portx_ctl_status_t;
962
963 #endif
964