1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2018 The FreeBSD Foundation
5 * Copyright (c) 1992 Terrence R. Lambert.
6 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Portions of this software were developed by A. Joseph Koshy under
13 * sponsorship from the FreeBSD Foundation and Google, Inc.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * SUCH DAMAGE.
42 *
43 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
44 */
45
46 #include <sys/cdefs.h>
47 #include "opt_apic.h"
48 #include "opt_atpic.h"
49 #include "opt_cpu.h"
50 #include "opt_ddb.h"
51 #include "opt_inet.h"
52 #include "opt_isa.h"
53 #include "opt_kstack_pages.h"
54 #include "opt_maxmem.h"
55 #include "opt_perfmon.h"
56 #include "opt_platform.h"
57
58 #include <sys/param.h>
59 #include <sys/proc.h>
60 #include <sys/systm.h>
61 #include <sys/bio.h>
62 #include <sys/buf.h>
63 #include <sys/bus.h>
64 #include <sys/callout.h>
65 #include <sys/cons.h>
66 #include <sys/cpu.h>
67 #include <sys/eventhandler.h>
68 #include <sys/exec.h>
69 #include <sys/imgact.h>
70 #include <sys/kdb.h>
71 #include <sys/kernel.h>
72 #include <sys/ktr.h>
73 #include <sys/linker.h>
74 #include <sys/lock.h>
75 #include <sys/malloc.h>
76 #include <sys/memrange.h>
77 #include <sys/msgbuf.h>
78 #include <sys/mutex.h>
79 #include <sys/pcpu.h>
80 #include <sys/ptrace.h>
81 #include <sys/reboot.h>
82 #include <sys/reg.h>
83 #include <sys/rwlock.h>
84 #include <sys/sched.h>
85 #include <sys/signalvar.h>
86 #include <sys/smp.h>
87 #include <sys/syscallsubr.h>
88 #include <sys/sysctl.h>
89 #include <sys/sysent.h>
90 #include <sys/sysproto.h>
91 #include <sys/ucontext.h>
92 #include <sys/vmmeter.h>
93
94 #include <vm/vm.h>
95 #include <vm/vm_param.h>
96 #include <vm/vm_extern.h>
97 #include <vm/vm_kern.h>
98 #include <vm/vm_page.h>
99 #include <vm/vm_map.h>
100 #include <vm/vm_object.h>
101 #include <vm/vm_pager.h>
102 #include <vm/vm_phys.h>
103 #include <vm/vm_dumpset.h>
104
105 #ifdef DDB
106 #ifndef KDB
107 #error KDB must be enabled in order for DDB to work!
108 #endif
109 #include <ddb/ddb.h>
110 #include <ddb/db_sym.h>
111 #endif
112
113 #include <isa/rtc.h>
114
115 #include <net/netisr.h>
116
117 #include <dev/smbios/smbios.h>
118
119 #include <machine/bootinfo.h>
120 #include <machine/clock.h>
121 #include <machine/cpu.h>
122 #include <machine/cputypes.h>
123 #include <machine/intr_machdep.h>
124 #include <x86/mca.h>
125 #include <machine/md_var.h>
126 #include <machine/metadata.h>
127 #include <machine/pc/bios.h>
128 #include <machine/pcb.h>
129 #include <machine/pcb_ext.h>
130 #include <machine/proc.h>
131 #include <machine/sigframe.h>
132 #include <machine/specialreg.h>
133 #include <machine/sysarch.h>
134 #include <machine/trap.h>
135 #include <x86/ucode.h>
136 #include <machine/vm86.h>
137 #include <x86/init.h>
138 #ifdef PERFMON
139 #include <machine/perfmon.h>
140 #endif
141 #ifdef SMP
142 #include <machine/smp.h>
143 #endif
144 #ifdef FDT
145 #include <x86/fdt.h>
146 #endif
147
148 #ifdef DEV_APIC
149 #include <x86/apicvar.h>
150 #endif
151
152 #ifdef DEV_ISA
153 #include <x86/isa/icu.h>
154 #endif
155
156 /* Sanity check for __curthread() */
157 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0);
158
159 register_t init386(int first);
160 void dblfault_handler(void);
161 void identify_cpu(void);
162
163 static void cpu_startup(void *);
164 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
165
166 /* Intel ICH registers */
167 #define ICH_PMBASE 0x400
168 #define ICH_SMI_EN ICH_PMBASE + 0x30
169
170 int _udatasel, _ucodesel;
171 u_int basemem;
172 static int above4g_allow = 1;
173 static int above24g_allow = 0;
174
175 int cold = 1;
176
177 long Maxmem = 0;
178 long realmem = 0;
179 int late_console = 1;
180
181 #ifdef PAE
182 FEATURE(pae, "Physical Address Extensions");
183 #endif
184
185 struct kva_md_info kmi;
186
187 static struct trapframe proc0_tf;
188 struct pcpu __pcpu[MAXCPU];
189
190 static void i386_clock_source_init(void);
191
192 struct mtx icu_lock;
193
194 struct mem_range_softc mem_range_softc;
195
196 extern char start_exceptions[], end_exceptions[];
197
198 extern struct sysentvec elf32_freebsd_sysvec;
199
200 /* Default init_ops implementation. */
201 struct init_ops init_ops = {
202 .early_clock_source_init = i386_clock_source_init,
203 .early_delay = i8254_delay,
204 };
205
206 static void
i386_clock_source_init(void)207 i386_clock_source_init(void)
208 {
209 i8254_init();
210 }
211
212 static void
cpu_startup(void * dummy)213 cpu_startup(void *dummy)
214 {
215 uintmax_t memsize;
216 char *sysenv;
217
218 /*
219 * On MacBooks, we need to disallow the legacy USB circuit to
220 * generate an SMI# because this can cause several problems,
221 * namely: incorrect CPU frequency detection and failure to
222 * start the APs.
223 * We do this by disabling a bit in the SMI_EN (SMI Control and
224 * Enable register) of the Intel ICH LPC Interface Bridge.
225 */
226 sysenv = kern_getenv("smbios.system.product");
227 if (sysenv != NULL) {
228 if (strncmp(sysenv, "MacBook1,1", 10) == 0 ||
229 strncmp(sysenv, "MacBook3,1", 10) == 0 ||
230 strncmp(sysenv, "MacBook4,1", 10) == 0 ||
231 strncmp(sysenv, "MacBookPro1,1", 13) == 0 ||
232 strncmp(sysenv, "MacBookPro1,2", 13) == 0 ||
233 strncmp(sysenv, "MacBookPro3,1", 13) == 0 ||
234 strncmp(sysenv, "MacBookPro4,1", 13) == 0 ||
235 strncmp(sysenv, "Macmini1,1", 10) == 0) {
236 if (bootverbose)
237 printf("Disabling LEGACY_USB_EN bit on "
238 "Intel ICH.\n");
239 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8);
240 }
241 freeenv(sysenv);
242 }
243
244 /*
245 * Good {morning,afternoon,evening,night}.
246 */
247 startrtclock();
248 printcpuinfo();
249 panicifcpuunsupported();
250 #ifdef PERFMON
251 perfmon_init();
252 #endif
253
254 /*
255 * Display physical memory if SMBIOS reports reasonable amount.
256 */
257 memsize = 0;
258 sysenv = kern_getenv("smbios.memory.enabled");
259 if (sysenv != NULL) {
260 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10;
261 freeenv(sysenv);
262 }
263 if (memsize < ptoa((uintmax_t)vm_free_count()))
264 memsize = ptoa((uintmax_t)Maxmem);
265 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20);
266 realmem = atop(memsize);
267
268 /*
269 * Display any holes after the first chunk of extended memory.
270 */
271 if (bootverbose) {
272 int indx;
273
274 printf("Physical memory chunk(s):\n");
275 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
276 vm_paddr_t size;
277
278 size = phys_avail[indx + 1] - phys_avail[indx];
279 printf(
280 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n",
281 (uintmax_t)phys_avail[indx],
282 (uintmax_t)phys_avail[indx + 1] - 1,
283 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE);
284 }
285 }
286
287 vm_ksubmap_init(&kmi);
288
289 printf("avail memory = %ju (%ju MB)\n",
290 ptoa((uintmax_t)vm_free_count()),
291 ptoa((uintmax_t)vm_free_count()) / 1048576);
292
293 /*
294 * Set up buffers, so they can be used to read disk labels.
295 */
296 bufinit();
297 vm_pager_bufferinit();
298 cpu_setregs();
299 }
300
301 void
cpu_setregs(void)302 cpu_setregs(void)
303 {
304 unsigned int cr0;
305
306 cr0 = rcr0();
307
308 /*
309 * CR0_MP, CR0_NE and CR0_TS are set for NPX (FPU) support:
310 *
311 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
312 * instructions. We must set the CR0_MP bit and use the CR0_TS
313 * bit to control the trap, because setting the CR0_EM bit does
314 * not cause WAIT instructions to trap. It's important to trap
315 * WAIT instructions - otherwise the "wait" variants of no-wait
316 * control instructions would degenerate to the "no-wait" variants
317 * after FP context switches but work correctly otherwise. It's
318 * particularly important to trap WAITs when there is no NPX -
319 * otherwise the "wait" variants would always degenerate.
320 *
321 * Try setting CR0_NE to get correct error reporting on 486DX's.
322 * Setting it should fail or do nothing on lesser processors.
323 */
324 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM;
325 load_cr0(cr0);
326 load_gs(_udatasel);
327 }
328
329 u_long bootdev; /* not a struct cdev *- encoding is different */
330 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
331 CTLFLAG_RD, &bootdev, 0, "Maybe the Boot device (not in struct cdev *format)");
332
333 /*
334 * Initialize 386 and configure to run kernel
335 */
336
337 /*
338 * Initialize segments & interrupt table
339 */
340
341 int _default_ldt;
342
343 struct mtx dt_lock; /* lock for GDT and LDT */
344
345 union descriptor gdt0[NGDT]; /* initial global descriptor table */
346 union descriptor *gdt = gdt0; /* global descriptor table */
347
348 union descriptor *ldt; /* local descriptor table */
349
350 static struct gate_descriptor idt0[NIDT];
351 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
352
353 static struct i386tss *dblfault_tss;
354 static char *dblfault_stack;
355
356 static struct i386tss common_tss0;
357
358 vm_offset_t proc0kstack;
359
360 /*
361 * software prototypes -- in more palatable form.
362 *
363 * GCODE_SEL through GUDATA_SEL must be in this order for syscall/sysret
364 * GUFS_SEL and GUGS_SEL must be in this order (swtch.s knows it)
365 */
366 struct soft_segment_descriptor gdt_segs[] = {
367 /* GNULL_SEL 0 Null Descriptor */
368 { .ssd_base = 0x0,
369 .ssd_limit = 0x0,
370 .ssd_type = 0,
371 .ssd_dpl = SEL_KPL,
372 .ssd_p = 0,
373 .ssd_xx = 0, .ssd_xx1 = 0,
374 .ssd_def32 = 0,
375 .ssd_gran = 0 },
376 /* GPRIV_SEL 1 SMP Per-Processor Private Data Descriptor */
377 { .ssd_base = 0x0,
378 .ssd_limit = 0xfffff,
379 .ssd_type = SDT_MEMRWA,
380 .ssd_dpl = SEL_KPL,
381 .ssd_p = 1,
382 .ssd_xx = 0, .ssd_xx1 = 0,
383 .ssd_def32 = 1,
384 .ssd_gran = 1 },
385 /* GUFS_SEL 2 %fs Descriptor for user */
386 { .ssd_base = 0x0,
387 .ssd_limit = 0xfffff,
388 .ssd_type = SDT_MEMRWA,
389 .ssd_dpl = SEL_UPL,
390 .ssd_p = 1,
391 .ssd_xx = 0, .ssd_xx1 = 0,
392 .ssd_def32 = 1,
393 .ssd_gran = 1 },
394 /* GUGS_SEL 3 %gs Descriptor for user */
395 { .ssd_base = 0x0,
396 .ssd_limit = 0xfffff,
397 .ssd_type = SDT_MEMRWA,
398 .ssd_dpl = SEL_UPL,
399 .ssd_p = 1,
400 .ssd_xx = 0, .ssd_xx1 = 0,
401 .ssd_def32 = 1,
402 .ssd_gran = 1 },
403 /* GCODE_SEL 4 Code Descriptor for kernel */
404 { .ssd_base = 0x0,
405 .ssd_limit = 0xfffff,
406 .ssd_type = SDT_MEMERA,
407 .ssd_dpl = SEL_KPL,
408 .ssd_p = 1,
409 .ssd_xx = 0, .ssd_xx1 = 0,
410 .ssd_def32 = 1,
411 .ssd_gran = 1 },
412 /* GDATA_SEL 5 Data Descriptor for kernel */
413 { .ssd_base = 0x0,
414 .ssd_limit = 0xfffff,
415 .ssd_type = SDT_MEMRWA,
416 .ssd_dpl = SEL_KPL,
417 .ssd_p = 1,
418 .ssd_xx = 0, .ssd_xx1 = 0,
419 .ssd_def32 = 1,
420 .ssd_gran = 1 },
421 /* GUCODE_SEL 6 Code Descriptor for user */
422 { .ssd_base = 0x0,
423 .ssd_limit = 0xfffff,
424 .ssd_type = SDT_MEMERA,
425 .ssd_dpl = SEL_UPL,
426 .ssd_p = 1,
427 .ssd_xx = 0, .ssd_xx1 = 0,
428 .ssd_def32 = 1,
429 .ssd_gran = 1 },
430 /* GUDATA_SEL 7 Data Descriptor for user */
431 { .ssd_base = 0x0,
432 .ssd_limit = 0xfffff,
433 .ssd_type = SDT_MEMRWA,
434 .ssd_dpl = SEL_UPL,
435 .ssd_p = 1,
436 .ssd_xx = 0, .ssd_xx1 = 0,
437 .ssd_def32 = 1,
438 .ssd_gran = 1 },
439 /* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
440 { .ssd_base = 0x400,
441 .ssd_limit = 0xfffff,
442 .ssd_type = SDT_MEMRWA,
443 .ssd_dpl = SEL_KPL,
444 .ssd_p = 1,
445 .ssd_xx = 0, .ssd_xx1 = 0,
446 .ssd_def32 = 1,
447 .ssd_gran = 1 },
448 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */
449 {
450 .ssd_base = 0x0,
451 .ssd_limit = sizeof(struct i386tss)-1,
452 .ssd_type = SDT_SYS386TSS,
453 .ssd_dpl = 0,
454 .ssd_p = 1,
455 .ssd_xx = 0, .ssd_xx1 = 0,
456 .ssd_def32 = 0,
457 .ssd_gran = 0 },
458 /* GLDT_SEL 10 LDT Descriptor */
459 { .ssd_base = 0,
460 .ssd_limit = sizeof(union descriptor) * NLDT - 1,
461 .ssd_type = SDT_SYSLDT,
462 .ssd_dpl = SEL_UPL,
463 .ssd_p = 1,
464 .ssd_xx = 0, .ssd_xx1 = 0,
465 .ssd_def32 = 0,
466 .ssd_gran = 0 },
467 /* GUSERLDT_SEL 11 User LDT Descriptor per process */
468 { .ssd_base = 0,
469 .ssd_limit = (512 * sizeof(union descriptor)-1),
470 .ssd_type = SDT_SYSLDT,
471 .ssd_dpl = 0,
472 .ssd_p = 1,
473 .ssd_xx = 0, .ssd_xx1 = 0,
474 .ssd_def32 = 0,
475 .ssd_gran = 0 },
476 /* GPANIC_SEL 12 Panic Tss Descriptor */
477 { .ssd_base = 0,
478 .ssd_limit = sizeof(struct i386tss)-1,
479 .ssd_type = SDT_SYS386TSS,
480 .ssd_dpl = 0,
481 .ssd_p = 1,
482 .ssd_xx = 0, .ssd_xx1 = 0,
483 .ssd_def32 = 0,
484 .ssd_gran = 0 },
485 /* GBIOSCODE32_SEL 13 BIOS 32-bit interface (32bit Code) */
486 { .ssd_base = 0,
487 .ssd_limit = 0xfffff,
488 .ssd_type = SDT_MEMERA,
489 .ssd_dpl = 0,
490 .ssd_p = 1,
491 .ssd_xx = 0, .ssd_xx1 = 0,
492 .ssd_def32 = 0,
493 .ssd_gran = 1 },
494 /* GBIOSCODE16_SEL 14 BIOS 32-bit interface (16bit Code) */
495 { .ssd_base = 0,
496 .ssd_limit = 0xfffff,
497 .ssd_type = SDT_MEMERA,
498 .ssd_dpl = 0,
499 .ssd_p = 1,
500 .ssd_xx = 0, .ssd_xx1 = 0,
501 .ssd_def32 = 0,
502 .ssd_gran = 1 },
503 /* GBIOSDATA_SEL 15 BIOS 32-bit interface (Data) */
504 { .ssd_base = 0,
505 .ssd_limit = 0xfffff,
506 .ssd_type = SDT_MEMRWA,
507 .ssd_dpl = 0,
508 .ssd_p = 1,
509 .ssd_xx = 0, .ssd_xx1 = 0,
510 .ssd_def32 = 1,
511 .ssd_gran = 1 },
512 /* GBIOSUTIL_SEL 16 BIOS 16-bit interface (Utility) */
513 { .ssd_base = 0,
514 .ssd_limit = 0xfffff,
515 .ssd_type = SDT_MEMRWA,
516 .ssd_dpl = 0,
517 .ssd_p = 1,
518 .ssd_xx = 0, .ssd_xx1 = 0,
519 .ssd_def32 = 0,
520 .ssd_gran = 1 },
521 /* GBIOSARGS_SEL 17 BIOS 16-bit interface (Arguments) */
522 { .ssd_base = 0,
523 .ssd_limit = 0xfffff,
524 .ssd_type = SDT_MEMRWA,
525 .ssd_dpl = 0,
526 .ssd_p = 1,
527 .ssd_xx = 0, .ssd_xx1 = 0,
528 .ssd_def32 = 0,
529 .ssd_gran = 1 },
530 /* GNDIS_SEL 18 NDIS Descriptor */
531 { .ssd_base = 0x0,
532 .ssd_limit = 0x0,
533 .ssd_type = 0,
534 .ssd_dpl = 0,
535 .ssd_p = 0,
536 .ssd_xx = 0, .ssd_xx1 = 0,
537 .ssd_def32 = 0,
538 .ssd_gran = 0 },
539 };
540
541 static struct soft_segment_descriptor ldt_segs[] = {
542 /* Null Descriptor - overwritten by call gate */
543 { .ssd_base = 0x0,
544 .ssd_limit = 0x0,
545 .ssd_type = 0,
546 .ssd_dpl = 0,
547 .ssd_p = 0,
548 .ssd_xx = 0, .ssd_xx1 = 0,
549 .ssd_def32 = 0,
550 .ssd_gran = 0 },
551 /* Null Descriptor - overwritten by call gate */
552 { .ssd_base = 0x0,
553 .ssd_limit = 0x0,
554 .ssd_type = 0,
555 .ssd_dpl = 0,
556 .ssd_p = 0,
557 .ssd_xx = 0, .ssd_xx1 = 0,
558 .ssd_def32 = 0,
559 .ssd_gran = 0 },
560 /* Null Descriptor - overwritten by call gate */
561 { .ssd_base = 0x0,
562 .ssd_limit = 0x0,
563 .ssd_type = 0,
564 .ssd_dpl = 0,
565 .ssd_p = 0,
566 .ssd_xx = 0, .ssd_xx1 = 0,
567 .ssd_def32 = 0,
568 .ssd_gran = 0 },
569 /* Code Descriptor for user */
570 { .ssd_base = 0x0,
571 .ssd_limit = 0xfffff,
572 .ssd_type = SDT_MEMERA,
573 .ssd_dpl = SEL_UPL,
574 .ssd_p = 1,
575 .ssd_xx = 0, .ssd_xx1 = 0,
576 .ssd_def32 = 1,
577 .ssd_gran = 1 },
578 /* Null Descriptor - overwritten by call gate */
579 { .ssd_base = 0x0,
580 .ssd_limit = 0x0,
581 .ssd_type = 0,
582 .ssd_dpl = 0,
583 .ssd_p = 0,
584 .ssd_xx = 0, .ssd_xx1 = 0,
585 .ssd_def32 = 0,
586 .ssd_gran = 0 },
587 /* Data Descriptor for user */
588 { .ssd_base = 0x0,
589 .ssd_limit = 0xfffff,
590 .ssd_type = SDT_MEMRWA,
591 .ssd_dpl = SEL_UPL,
592 .ssd_p = 1,
593 .ssd_xx = 0, .ssd_xx1 = 0,
594 .ssd_def32 = 1,
595 .ssd_gran = 1 },
596 };
597
598 size_t setidt_disp;
599
600 void
setidt(int idx,inthand_t * func,int typ,int dpl,int selec)601 setidt(int idx, inthand_t *func, int typ, int dpl, int selec)
602 {
603 uintptr_t off;
604
605 off = func != NULL ? (uintptr_t)func + setidt_disp : 0;
606 setidt_nodisp(idx, off, typ, dpl, selec);
607 }
608
609 void
setidt_nodisp(int idx,uintptr_t off,int typ,int dpl,int selec)610 setidt_nodisp(int idx, uintptr_t off, int typ, int dpl, int selec)
611 {
612 struct gate_descriptor *ip;
613
614 ip = idt + idx;
615 ip->gd_looffset = off;
616 ip->gd_selector = selec;
617 ip->gd_stkcpy = 0;
618 ip->gd_xx = 0;
619 ip->gd_type = typ;
620 ip->gd_dpl = dpl;
621 ip->gd_p = 1;
622 ip->gd_hioffset = ((u_int)off) >> 16 ;
623 }
624
625 extern inthand_t
626 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
627 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
628 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
629 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
630 IDTVEC(xmm),
631 #ifdef KDTRACE_HOOKS
632 IDTVEC(dtrace_ret),
633 #endif
634 #ifdef XENHVM
635 IDTVEC(xen_intr_upcall),
636 #endif
637 IDTVEC(int0x80_syscall);
638
639 #ifdef DDB
640 /*
641 * Display the index and function name of any IDT entries that don't use
642 * the default 'rsvd' entry point.
643 */
DB_SHOW_COMMAND_FLAGS(idt,db_show_idt,DB_CMD_MEMSAFE)644 DB_SHOW_COMMAND_FLAGS(idt, db_show_idt, DB_CMD_MEMSAFE)
645 {
646 struct gate_descriptor *ip;
647 int idx;
648 uintptr_t func, func_trm;
649 bool trm;
650
651 ip = idt;
652 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) {
653 if (ip->gd_type == SDT_SYSTASKGT) {
654 db_printf("%3d\t<TASK>\n", idx);
655 } else {
656 func = (ip->gd_hioffset << 16 | ip->gd_looffset);
657 if (func >= PMAP_TRM_MIN_ADDRESS) {
658 func_trm = func;
659 func -= setidt_disp;
660 trm = true;
661 } else
662 trm = false;
663 if (func != (uintptr_t)&IDTVEC(rsvd)) {
664 db_printf("%3d\t", idx);
665 db_printsym(func, DB_STGY_PROC);
666 if (trm)
667 db_printf(" (trampoline %#x)",
668 func_trm);
669 db_printf("\n");
670 }
671 }
672 ip++;
673 }
674 }
675
676 /* Show privileged registers. */
DB_SHOW_COMMAND_FLAGS(sysregs,db_show_sysregs,DB_CMD_MEMSAFE)677 DB_SHOW_COMMAND_FLAGS(sysregs, db_show_sysregs, DB_CMD_MEMSAFE)
678 {
679 uint64_t idtr, gdtr;
680
681 idtr = ridt();
682 db_printf("idtr\t0x%08x/%04x\n",
683 (u_int)(idtr >> 16), (u_int)idtr & 0xffff);
684 gdtr = rgdt();
685 db_printf("gdtr\t0x%08x/%04x\n",
686 (u_int)(gdtr >> 16), (u_int)gdtr & 0xffff);
687 db_printf("ldtr\t0x%04x\n", rldt());
688 db_printf("tr\t0x%04x\n", rtr());
689 db_printf("cr0\t0x%08x\n", rcr0());
690 db_printf("cr2\t0x%08x\n", rcr2());
691 db_printf("cr3\t0x%08x\n", rcr3());
692 db_printf("cr4\t0x%08x\n", rcr4());
693 if (rcr4() & CR4_XSAVE)
694 db_printf("xcr0\t0x%016llx\n", rxcr(0));
695 if (amd_feature & (AMDID_NX | AMDID_LM))
696 db_printf("EFER\t0x%016llx\n", rdmsr(MSR_EFER));
697 if (cpu_feature2 & (CPUID2_VMX | CPUID2_SMX))
698 db_printf("FEATURES_CTL\t0x%016llx\n",
699 rdmsr(MSR_IA32_FEATURE_CONTROL));
700 if (((cpu_vendor_id == CPU_VENDOR_INTEL ||
701 cpu_vendor_id == CPU_VENDOR_AMD) && CPUID_TO_FAMILY(cpu_id) >= 6) ||
702 cpu_vendor_id == CPU_VENDOR_HYGON)
703 db_printf("DEBUG_CTL\t0x%016llx\n", rdmsr(MSR_DEBUGCTLMSR));
704 if (cpu_feature & CPUID_PAT)
705 db_printf("PAT\t0x%016llx\n", rdmsr(MSR_PAT));
706 }
707
DB_SHOW_COMMAND_FLAGS(dbregs,db_show_dbregs,DB_CMD_MEMSAFE)708 DB_SHOW_COMMAND_FLAGS(dbregs, db_show_dbregs, DB_CMD_MEMSAFE)
709 {
710
711 db_printf("dr0\t0x%08x\n", rdr0());
712 db_printf("dr1\t0x%08x\n", rdr1());
713 db_printf("dr2\t0x%08x\n", rdr2());
714 db_printf("dr3\t0x%08x\n", rdr3());
715 db_printf("dr6\t0x%08x\n", rdr6());
716 db_printf("dr7\t0x%08x\n", rdr7());
717 }
718
DB_SHOW_COMMAND(frame,db_show_frame)719 DB_SHOW_COMMAND(frame, db_show_frame)
720 {
721 struct trapframe *frame;
722
723 frame = have_addr ? (struct trapframe *)addr : curthread->td_frame;
724 printf("ss %#x esp %#x efl %#x cs %#x eip %#x\n",
725 frame->tf_ss, frame->tf_esp, frame->tf_eflags, frame->tf_cs,
726 frame->tf_eip);
727 printf("err %#x trapno %d\n", frame->tf_err, frame->tf_trapno);
728 printf("ds %#x es %#x fs %#x\n",
729 frame->tf_ds, frame->tf_es, frame->tf_fs);
730 printf("eax %#x ecx %#x edx %#x ebx %#x\n",
731 frame->tf_eax, frame->tf_ecx, frame->tf_edx, frame->tf_ebx);
732 printf("ebp %#x esi %#x edi %#x\n",
733 frame->tf_ebp, frame->tf_esi, frame->tf_edi);
734
735 }
736 #endif
737
738 void
sdtossd(struct segment_descriptor * sd,struct soft_segment_descriptor * ssd)739 sdtossd(struct segment_descriptor *sd, struct soft_segment_descriptor *ssd)
740 {
741 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
742 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
743 ssd->ssd_type = sd->sd_type;
744 ssd->ssd_dpl = sd->sd_dpl;
745 ssd->ssd_p = sd->sd_p;
746 ssd->ssd_def32 = sd->sd_def32;
747 ssd->ssd_gran = sd->sd_gran;
748 }
749
750 static int
add_physmap_entry(uint64_t base,uint64_t length,vm_paddr_t * physmap,int * physmap_idxp)751 add_physmap_entry(uint64_t base, uint64_t length, vm_paddr_t *physmap,
752 int *physmap_idxp)
753 {
754 uint64_t lim, ign;
755 int i, insert_idx, physmap_idx;
756
757 physmap_idx = *physmap_idxp;
758
759 if (length == 0)
760 return (1);
761
762 lim = 0x100000000; /* 4G */
763 if (pae_mode && above4g_allow)
764 lim = above24g_allow ? -1ULL : 0x600000000; /* 24G */
765 if (base >= lim) {
766 printf("%uK of memory above %uGB ignored, pae %d "
767 "above4g_allow %d above24g_allow %d\n",
768 (u_int)(length / 1024), (u_int)(lim >> 30), pae_mode,
769 above4g_allow, above24g_allow);
770 return (1);
771 }
772 if (base + length >= lim) {
773 ign = base + length - lim;
774 length -= ign;
775 printf("%uK of memory above %uGB ignored, pae %d "
776 "above4g_allow %d above24g_allow %d\n",
777 (u_int)(ign / 1024), (u_int)(lim >> 30), pae_mode,
778 above4g_allow, above24g_allow);
779 }
780
781 /*
782 * Find insertion point while checking for overlap. Start off by
783 * assuming the new entry will be added to the end.
784 */
785 insert_idx = physmap_idx + 2;
786 for (i = 0; i <= physmap_idx; i += 2) {
787 if (base < physmap[i + 1]) {
788 if (base + length <= physmap[i]) {
789 insert_idx = i;
790 break;
791 }
792 if (boothowto & RB_VERBOSE)
793 printf(
794 "Overlapping memory regions, ignoring second region\n");
795 return (1);
796 }
797 }
798
799 /* See if we can prepend to the next entry. */
800 if (insert_idx <= physmap_idx && base + length == physmap[insert_idx]) {
801 physmap[insert_idx] = base;
802 return (1);
803 }
804
805 /* See if we can append to the previous entry. */
806 if (insert_idx > 0 && base == physmap[insert_idx - 1]) {
807 physmap[insert_idx - 1] += length;
808 return (1);
809 }
810
811 physmap_idx += 2;
812 *physmap_idxp = physmap_idx;
813 if (physmap_idx == PHYS_AVAIL_ENTRIES) {
814 printf(
815 "Too many segments in the physical address map, giving up\n");
816 return (0);
817 }
818
819 /*
820 * Move the last 'N' entries down to make room for the new
821 * entry if needed.
822 */
823 for (i = physmap_idx; i > insert_idx; i -= 2) {
824 physmap[i] = physmap[i - 2];
825 physmap[i + 1] = physmap[i - 1];
826 }
827
828 /* Insert the new entry. */
829 physmap[insert_idx] = base;
830 physmap[insert_idx + 1] = base + length;
831 return (1);
832 }
833
834 static int
add_smap_entry(struct bios_smap * smap,vm_paddr_t * physmap,int * physmap_idxp)835 add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp)
836 {
837 if (boothowto & RB_VERBOSE)
838 printf("SMAP type=%02x base=%016llx len=%016llx\n",
839 smap->type, smap->base, smap->length);
840
841 if (smap->type != SMAP_TYPE_MEMORY)
842 return (1);
843
844 return (add_physmap_entry(smap->base, smap->length, physmap,
845 physmap_idxp));
846 }
847
848 static void
add_smap_entries(struct bios_smap * smapbase,vm_paddr_t * physmap,int * physmap_idxp)849 add_smap_entries(struct bios_smap *smapbase, vm_paddr_t *physmap,
850 int *physmap_idxp)
851 {
852 struct bios_smap *smap, *smapend;
853 u_int32_t smapsize;
854 /*
855 * Memory map from INT 15:E820.
856 *
857 * subr_module.c says:
858 * "Consumer may safely assume that size value precedes data."
859 * ie: an int32_t immediately precedes SMAP.
860 */
861 smapsize = *((u_int32_t *)smapbase - 1);
862 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
863
864 for (smap = smapbase; smap < smapend; smap++)
865 if (!add_smap_entry(smap, physmap, physmap_idxp))
866 break;
867 }
868
869 static void
basemem_setup(void)870 basemem_setup(void)
871 {
872
873 if (basemem > 640) {
874 printf("Preposterous BIOS basemem of %uK, truncating to 640K\n",
875 basemem);
876 basemem = 640;
877 }
878
879 pmap_basemem_setup(basemem);
880 }
881
882 /*
883 * Populate the (physmap) array with base/bound pairs describing the
884 * available physical memory in the system, then test this memory and
885 * build the phys_avail array describing the actually-available memory.
886 *
887 * If we cannot accurately determine the physical memory map, then use
888 * value from the 0xE801 call, and failing that, the RTC.
889 *
890 * Total memory size may be set by the kernel environment variable
891 * hw.physmem or the compile-time define MAXMEM.
892 *
893 * XXX first should be vm_paddr_t.
894 */
895 static void
getmemsize(int first)896 getmemsize(int first)
897 {
898 int has_smap, off, physmap_idx, pa_indx, da_indx;
899 u_long memtest;
900 vm_paddr_t physmap[PHYS_AVAIL_ENTRIES];
901 quad_t dcons_addr, dcons_size, physmem_tunable;
902 int hasbrokenint12, i, res __diagused;
903 u_int extmem;
904 struct vm86frame vmf;
905 struct vm86context vmc;
906 vm_paddr_t pa;
907 struct bios_smap *smap, *smapbase;
908 caddr_t kmdp;
909
910 has_smap = 0;
911 bzero(&vmf, sizeof(vmf));
912 bzero(physmap, sizeof(physmap));
913 basemem = 0;
914
915 /*
916 * Tell the physical memory allocator about pages used to store
917 * the kernel and preloaded data. See kmem_bootstrap_free().
918 */
919 vm_phys_early_add_seg((vm_paddr_t)KERNLOAD, trunc_page(first));
920
921 TUNABLE_INT_FETCH("hw.above4g_allow", &above4g_allow);
922 TUNABLE_INT_FETCH("hw.above24g_allow", &above24g_allow);
923
924 /*
925 * Check if the loader supplied an SMAP memory map. If so,
926 * use that and do not make any VM86 calls.
927 */
928 physmap_idx = 0;
929 kmdp = preload_search_by_type("elf kernel");
930 if (kmdp == NULL)
931 kmdp = preload_search_by_type("elf32 kernel");
932 smapbase = (struct bios_smap *)preload_search_info(kmdp,
933 MODINFO_METADATA | MODINFOMD_SMAP);
934 if (smapbase != NULL) {
935 add_smap_entries(smapbase, physmap, &physmap_idx);
936 has_smap = 1;
937 goto have_smap;
938 }
939
940 /*
941 * Some newer BIOSes have a broken INT 12H implementation
942 * which causes a kernel panic immediately. In this case, we
943 * need use the SMAP to determine the base memory size.
944 */
945 hasbrokenint12 = 0;
946 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
947 if (hasbrokenint12 == 0) {
948 /* Use INT12 to determine base memory size. */
949 vm86_intcall(0x12, &vmf);
950 basemem = vmf.vmf_ax;
951 basemem_setup();
952 }
953
954 /*
955 * Fetch the memory map with INT 15:E820. Map page 1 R/W into
956 * the kernel page table so we can use it as a buffer. The
957 * kernel will unmap this page later.
958 */
959 vmc.npages = 0;
960 smap = (void *)vm86_addpage(&vmc, 1, PMAP_MAP_LOW + ptoa(1));
961 res = vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
962 KASSERT(res != 0, ("vm86_getptr() failed: address not found"));
963
964 vmf.vmf_ebx = 0;
965 do {
966 vmf.vmf_eax = 0xE820;
967 vmf.vmf_edx = SMAP_SIG;
968 vmf.vmf_ecx = sizeof(struct bios_smap);
969 i = vm86_datacall(0x15, &vmf, &vmc);
970 if (i || vmf.vmf_eax != SMAP_SIG)
971 break;
972 has_smap = 1;
973 if (!add_smap_entry(smap, physmap, &physmap_idx))
974 break;
975 } while (vmf.vmf_ebx != 0);
976
977 have_smap:
978 /*
979 * If we didn't fetch the "base memory" size from INT12,
980 * figure it out from the SMAP (or just guess).
981 */
982 if (basemem == 0) {
983 for (i = 0; i <= physmap_idx; i += 2) {
984 if (physmap[i] == 0x00000000) {
985 basemem = physmap[i + 1] / 1024;
986 break;
987 }
988 }
989
990 /* XXX: If we couldn't find basemem from SMAP, just guess. */
991 if (basemem == 0)
992 basemem = 640;
993 basemem_setup();
994 }
995
996 if (physmap[1] != 0)
997 goto physmap_done;
998
999 /*
1000 * If we failed to find an SMAP, figure out the extended
1001 * memory size. We will then build a simple memory map with
1002 * two segments, one for "base memory" and the second for
1003 * "extended memory". Note that "extended memory" starts at a
1004 * physical address of 1MB and that both basemem and extmem
1005 * are in units of 1KB.
1006 *
1007 * First, try to fetch the extended memory size via INT 15:E801.
1008 */
1009 vmf.vmf_ax = 0xE801;
1010 if (vm86_intcall(0x15, &vmf) == 0) {
1011 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1012 } else {
1013 /*
1014 * If INT15:E801 fails, this is our last ditch effort
1015 * to determine the extended memory size. Currently
1016 * we prefer the RTC value over INT15:88.
1017 */
1018 #if 0
1019 vmf.vmf_ah = 0x88;
1020 vm86_intcall(0x15, &vmf);
1021 extmem = vmf.vmf_ax;
1022 #else
1023 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1024 #endif
1025 }
1026
1027 /*
1028 * Special hack for chipsets that still remap the 384k hole when
1029 * there's 16MB of memory - this really confuses people that
1030 * are trying to use bus mastering ISA controllers with the
1031 * "16MB limit"; they only have 16MB, but the remapping puts
1032 * them beyond the limit.
1033 *
1034 * If extended memory is between 15-16MB (16-17MB phys address range),
1035 * chop it to 15MB.
1036 */
1037 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1038 extmem = 15 * 1024;
1039
1040 physmap[0] = 0;
1041 physmap[1] = basemem * 1024;
1042 physmap_idx = 2;
1043 physmap[physmap_idx] = 0x100000;
1044 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1045
1046 physmap_done:
1047 /*
1048 * Now, physmap contains a map of physical memory.
1049 */
1050
1051 #ifdef SMP
1052 /* make hole for AP bootstrap code */
1053 alloc_ap_trampoline(physmap, &physmap_idx);
1054 #endif
1055
1056 /*
1057 * Maxmem isn't the "maximum memory", it's one larger than the
1058 * highest page of the physical address space. It should be
1059 * called something like "Maxphyspage". We may adjust this
1060 * based on ``hw.physmem'' and the results of the memory test.
1061 *
1062 * This is especially confusing when it is much larger than the
1063 * memory size and is displayed as "realmem".
1064 */
1065 Maxmem = atop(physmap[physmap_idx + 1]);
1066
1067 #ifdef MAXMEM
1068 Maxmem = MAXMEM / 4;
1069 #endif
1070
1071 if (TUNABLE_QUAD_FETCH("hw.physmem", &physmem_tunable))
1072 Maxmem = atop(physmem_tunable);
1073
1074 /*
1075 * If we have an SMAP, don't allow MAXMEM or hw.physmem to extend
1076 * the amount of memory in the system.
1077 */
1078 if (has_smap && Maxmem > atop(physmap[physmap_idx + 1]))
1079 Maxmem = atop(physmap[physmap_idx + 1]);
1080
1081 /*
1082 * The boot memory test is disabled by default, as it takes a
1083 * significant amount of time on large-memory systems, and is
1084 * unfriendly to virtual machines as it unnecessarily touches all
1085 * pages.
1086 *
1087 * A general name is used as the code may be extended to support
1088 * additional tests beyond the current "page present" test.
1089 */
1090 memtest = 0;
1091 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest);
1092
1093 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1094 (boothowto & RB_VERBOSE))
1095 printf("Physical memory use set to %ldK\n", Maxmem * 4);
1096
1097 /*
1098 * If Maxmem has been increased beyond what the system has detected,
1099 * extend the last memory segment to the new limit.
1100 */
1101 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1102 physmap[physmap_idx + 1] = ptoa((vm_paddr_t)Maxmem);
1103
1104 /* call pmap initialization to make new kernel address space */
1105 pmap_bootstrap(first);
1106
1107 /*
1108 * Size up each available chunk of physical memory.
1109 */
1110 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1111 pa_indx = 0;
1112 da_indx = 1;
1113 phys_avail[pa_indx++] = physmap[0];
1114 phys_avail[pa_indx] = physmap[0];
1115 dump_avail[da_indx] = physmap[0];
1116
1117 /*
1118 * Get dcons buffer address
1119 */
1120 if (getenv_quad("dcons.addr", &dcons_addr) == 0 ||
1121 getenv_quad("dcons.size", &dcons_size) == 0)
1122 dcons_addr = 0;
1123
1124 /*
1125 * physmap is in bytes, so when converting to page boundaries,
1126 * round up the start address and round down the end address.
1127 */
1128 for (i = 0; i <= physmap_idx; i += 2) {
1129 vm_paddr_t end;
1130
1131 end = ptoa((vm_paddr_t)Maxmem);
1132 if (physmap[i + 1] < end)
1133 end = trunc_page(physmap[i + 1]);
1134 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
1135 int tmp, page_bad, full;
1136 int *ptr;
1137
1138 full = FALSE;
1139 /*
1140 * block out kernel memory as not available.
1141 */
1142 if (pa >= KERNLOAD && pa < first)
1143 goto do_dump_avail;
1144
1145 /*
1146 * block out dcons buffer
1147 */
1148 if (dcons_addr > 0
1149 && pa >= trunc_page(dcons_addr)
1150 && pa < dcons_addr + dcons_size)
1151 goto do_dump_avail;
1152
1153 page_bad = FALSE;
1154 if (memtest == 0)
1155 goto skip_memtest;
1156
1157 /*
1158 * map page into kernel: valid, read/write,non-cacheable
1159 */
1160 ptr = (int *)pmap_cmap3(pa, PG_V | PG_RW | PG_N);
1161
1162 tmp = *(int *)ptr;
1163 /*
1164 * Test for alternating 1's and 0's
1165 */
1166 *(volatile int *)ptr = 0xaaaaaaaa;
1167 if (*(volatile int *)ptr != 0xaaaaaaaa)
1168 page_bad = TRUE;
1169 /*
1170 * Test for alternating 0's and 1's
1171 */
1172 *(volatile int *)ptr = 0x55555555;
1173 if (*(volatile int *)ptr != 0x55555555)
1174 page_bad = TRUE;
1175 /*
1176 * Test for all 1's
1177 */
1178 *(volatile int *)ptr = 0xffffffff;
1179 if (*(volatile int *)ptr != 0xffffffff)
1180 page_bad = TRUE;
1181 /*
1182 * Test for all 0's
1183 */
1184 *(volatile int *)ptr = 0x0;
1185 if (*(volatile int *)ptr != 0x0)
1186 page_bad = TRUE;
1187 /*
1188 * Restore original value.
1189 */
1190 *(int *)ptr = tmp;
1191
1192 skip_memtest:
1193 /*
1194 * Adjust array of valid/good pages.
1195 */
1196 if (page_bad == TRUE)
1197 continue;
1198 /*
1199 * If this good page is a continuation of the
1200 * previous set of good pages, then just increase
1201 * the end pointer. Otherwise start a new chunk.
1202 * Note that "end" points one higher than end,
1203 * making the range >= start and < end.
1204 * If we're also doing a speculative memory
1205 * test and we at or past the end, bump up Maxmem
1206 * so that we keep going. The first bad page
1207 * will terminate the loop.
1208 */
1209 if (phys_avail[pa_indx] == pa) {
1210 phys_avail[pa_indx] += PAGE_SIZE;
1211 } else {
1212 pa_indx++;
1213 if (pa_indx == PHYS_AVAIL_ENTRIES) {
1214 printf(
1215 "Too many holes in the physical address space, giving up\n");
1216 pa_indx--;
1217 full = TRUE;
1218 goto do_dump_avail;
1219 }
1220 phys_avail[pa_indx++] = pa; /* start */
1221 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1222 }
1223 physmem++;
1224 do_dump_avail:
1225 if (dump_avail[da_indx] == pa) {
1226 dump_avail[da_indx] += PAGE_SIZE;
1227 } else {
1228 da_indx++;
1229 if (da_indx == PHYS_AVAIL_ENTRIES) {
1230 da_indx--;
1231 goto do_next;
1232 }
1233 dump_avail[da_indx++] = pa; /* start */
1234 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1235 }
1236 do_next:
1237 if (full)
1238 break;
1239 }
1240 }
1241 pmap_cmap3(0, 0);
1242
1243 /*
1244 * XXX
1245 * The last chunk must contain at least one page plus the message
1246 * buffer to avoid complicating other code (message buffer address
1247 * calculation, etc.).
1248 */
1249 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1250 round_page(msgbufsize) >= phys_avail[pa_indx]) {
1251 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1252 phys_avail[pa_indx--] = 0;
1253 phys_avail[pa_indx--] = 0;
1254 }
1255
1256 Maxmem = atop(phys_avail[pa_indx]);
1257
1258 /* Trim off space for the message buffer. */
1259 phys_avail[pa_indx] -= round_page(msgbufsize);
1260
1261 /* Map the message buffer. */
1262 for (off = 0; off < round_page(msgbufsize); off += PAGE_SIZE)
1263 pmap_kenter((vm_offset_t)msgbufp + off, phys_avail[pa_indx] +
1264 off);
1265 }
1266
1267 static void
i386_kdb_init(void)1268 i386_kdb_init(void)
1269 {
1270 #ifdef DDB
1271 db_fetch_ksymtab(bootinfo.bi_symtab, bootinfo.bi_esymtab, 0);
1272 #endif
1273 kdb_init();
1274 #ifdef KDB
1275 if (boothowto & RB_KDB)
1276 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
1277 #endif
1278 }
1279
1280 static void
fixup_idt(void)1281 fixup_idt(void)
1282 {
1283 struct gate_descriptor *ip;
1284 uintptr_t off;
1285 int x;
1286
1287 for (x = 0; x < NIDT; x++) {
1288 ip = &idt[x];
1289 if (ip->gd_type != SDT_SYS386IGT &&
1290 ip->gd_type != SDT_SYS386TGT)
1291 continue;
1292 off = ip->gd_looffset + (((u_int)ip->gd_hioffset) << 16);
1293 KASSERT(off >= (uintptr_t)start_exceptions &&
1294 off < (uintptr_t)end_exceptions,
1295 ("IDT[%d] type %d off %#x", x, ip->gd_type, off));
1296 off += setidt_disp;
1297 MPASS(off >= PMAP_TRM_MIN_ADDRESS &&
1298 off < PMAP_TRM_MAX_ADDRESS);
1299 ip->gd_looffset = off;
1300 ip->gd_hioffset = off >> 16;
1301 }
1302 }
1303
1304 static void
i386_setidt1(void)1305 i386_setidt1(void)
1306 {
1307 int x;
1308
1309 /* exceptions */
1310 for (x = 0; x < NIDT; x++)
1311 setidt(x, &IDTVEC(rsvd), SDT_SYS386IGT, SEL_KPL,
1312 GSEL(GCODE_SEL, SEL_KPL));
1313 setidt(IDT_DE, &IDTVEC(div), SDT_SYS386IGT, SEL_KPL,
1314 GSEL(GCODE_SEL, SEL_KPL));
1315 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYS386IGT, SEL_KPL,
1316 GSEL(GCODE_SEL, SEL_KPL));
1317 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYS386IGT, SEL_KPL,
1318 GSEL(GCODE_SEL, SEL_KPL));
1319 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYS386IGT, SEL_UPL,
1320 GSEL(GCODE_SEL, SEL_KPL));
1321 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYS386IGT, SEL_UPL,
1322 GSEL(GCODE_SEL, SEL_KPL));
1323 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYS386IGT, SEL_KPL,
1324 GSEL(GCODE_SEL, SEL_KPL));
1325 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL,
1326 GSEL(GCODE_SEL, SEL_KPL));
1327 setidt(IDT_NM, &IDTVEC(dna), SDT_SYS386IGT, SEL_KPL,
1328 GSEL(GCODE_SEL, SEL_KPL));
1329 setidt(IDT_DF, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL,
1330 SEL_KPL));
1331 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYS386IGT,
1332 SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1333 setidt(IDT_TS, &IDTVEC(tss), SDT_SYS386IGT, SEL_KPL,
1334 GSEL(GCODE_SEL, SEL_KPL));
1335 setidt(IDT_NP, &IDTVEC(missing), SDT_SYS386IGT, SEL_KPL,
1336 GSEL(GCODE_SEL, SEL_KPL));
1337 setidt(IDT_SS, &IDTVEC(stk), SDT_SYS386IGT, SEL_KPL,
1338 GSEL(GCODE_SEL, SEL_KPL));
1339 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL,
1340 GSEL(GCODE_SEL, SEL_KPL));
1341 setidt(IDT_PF, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL,
1342 GSEL(GCODE_SEL, SEL_KPL));
1343 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYS386IGT, SEL_KPL,
1344 GSEL(GCODE_SEL, SEL_KPL));
1345 setidt(IDT_AC, &IDTVEC(align), SDT_SYS386IGT, SEL_KPL,
1346 GSEL(GCODE_SEL, SEL_KPL));
1347 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYS386IGT, SEL_KPL,
1348 GSEL(GCODE_SEL, SEL_KPL));
1349 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYS386IGT, SEL_KPL,
1350 GSEL(GCODE_SEL, SEL_KPL));
1351 setidt(IDT_SYSCALL, &IDTVEC(int0x80_syscall),
1352 SDT_SYS386IGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1353 #ifdef KDTRACE_HOOKS
1354 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret),
1355 SDT_SYS386IGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1356 #endif
1357 #ifdef XENHVM
1358 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall),
1359 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1360 #endif
1361 }
1362
1363 static void
i386_setidt2(void)1364 i386_setidt2(void)
1365 {
1366
1367 setidt(IDT_UD, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL,
1368 GSEL(GCODE_SEL, SEL_KPL));
1369 setidt(IDT_GP, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL,
1370 GSEL(GCODE_SEL, SEL_KPL));
1371 }
1372
1373 #if defined(DEV_ISA) && !defined(DEV_ATPIC)
1374 static void
i386_setidt3(void)1375 i386_setidt3(void)
1376 {
1377
1378 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint),
1379 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1380 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint),
1381 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1382 }
1383 #endif
1384
1385 register_t
init386(int first)1386 init386(int first)
1387 {
1388 struct region_descriptor r_gdt, r_idt; /* table descriptors */
1389 int gsel_tss, metadata_missing, x, pa;
1390 struct pcpu *pc;
1391 struct xstate_hdr *xhdr;
1392 caddr_t kmdp;
1393 vm_offset_t addend;
1394 size_t ucode_len;
1395
1396 thread0.td_kstack = proc0kstack;
1397 thread0.td_kstack_pages = TD0_KSTACK_PAGES;
1398
1399 /*
1400 * This may be done better later if it gets more high level
1401 * components in it. If so just link td->td_proc here.
1402 */
1403 proc_linkup0(&proc0, &thread0);
1404
1405 if (bootinfo.bi_modulep) {
1406 metadata_missing = 0;
1407 addend = (vm_paddr_t)bootinfo.bi_modulep < KERNBASE ?
1408 PMAP_MAP_LOW : 0;
1409 preload_metadata = (caddr_t)bootinfo.bi_modulep + addend;
1410 preload_bootstrap_relocate(addend);
1411 } else {
1412 metadata_missing = 1;
1413 }
1414
1415 if (bootinfo.bi_envp != 0) {
1416 addend = (vm_paddr_t)bootinfo.bi_envp < KERNBASE ?
1417 PMAP_MAP_LOW : 0;
1418 init_static_kenv((char *)bootinfo.bi_envp + addend, 0);
1419 } else {
1420 init_static_kenv(NULL, 0);
1421 }
1422
1423 /*
1424 * Re-evaluate CPU features if we loaded a microcode update.
1425 */
1426 ucode_len = ucode_load_bsp(first);
1427 if (ucode_len != 0) {
1428 identify_cpu();
1429 first = roundup2(first + ucode_len, PAGE_SIZE);
1430 }
1431
1432 identify_hypervisor();
1433 identify_hypervisor_smbios();
1434
1435 /* Init basic tunables, hz etc */
1436 init_param1();
1437
1438 /* Set bootmethod to BIOS: it's the only supported on i386. */
1439 strlcpy(bootmethod, "BIOS", sizeof(bootmethod));
1440
1441 /*
1442 * Make gdt memory segments. All segments cover the full 4GB
1443 * of address space and permissions are enforced at page level.
1444 */
1445 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1446 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
1447 gdt_segs[GUCODE_SEL].ssd_limit = atop(0 - 1);
1448 gdt_segs[GUDATA_SEL].ssd_limit = atop(0 - 1);
1449 gdt_segs[GUFS_SEL].ssd_limit = atop(0 - 1);
1450 gdt_segs[GUGS_SEL].ssd_limit = atop(0 - 1);
1451
1452 pc = &__pcpu[0];
1453 gdt_segs[GPRIV_SEL].ssd_limit = atop(0 - 1);
1454 gdt_segs[GPRIV_SEL].ssd_base = (int)pc;
1455 gdt_segs[GPROC0_SEL].ssd_base = (int)&common_tss0;
1456
1457 for (x = 0; x < NGDT; x++)
1458 ssdtosd(&gdt_segs[x], &gdt0[x].sd);
1459
1460 r_gdt.rd_limit = NGDT * sizeof(gdt0[0]) - 1;
1461 r_gdt.rd_base = (int)gdt0;
1462 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_SPIN);
1463 lgdt(&r_gdt);
1464
1465 pcpu_init(pc, 0, sizeof(struct pcpu));
1466 for (pa = first; pa < first + DPCPU_SIZE; pa += PAGE_SIZE)
1467 pmap_kenter(pa, pa);
1468 dpcpu_init((void *)first, 0);
1469 first += DPCPU_SIZE;
1470 PCPU_SET(prvspace, pc);
1471 PCPU_SET(curthread, &thread0);
1472 /* Non-late cninit() and printf() can be moved up to here. */
1473
1474 /*
1475 * Initialize mutexes.
1476 *
1477 * icu_lock: in order to allow an interrupt to occur in a critical
1478 * section, to set pcpu->ipending (etc...) properly, we
1479 * must be able to get the icu lock, so it can't be
1480 * under witness.
1481 */
1482 mutex_init();
1483 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS | MTX_NOPROFILE);
1484
1485 i386_setidt1();
1486
1487 r_idt.rd_limit = sizeof(idt0) - 1;
1488 r_idt.rd_base = (int) idt;
1489 lidt(&r_idt);
1490
1491 finishidentcpu(); /* Final stage of CPU initialization */
1492
1493 /*
1494 * Initialize the clock before the console so that console
1495 * initialization can use DELAY().
1496 */
1497 clock_init();
1498
1499 i386_setidt2();
1500 pmap_set_nx();
1501 initializecpu(); /* Initialize CPU registers */
1502 initializecpucache();
1503
1504 /* pointer to selector slot for %fs/%gs */
1505 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
1506
1507 /* Initialize the tss (except for the final esp0) early for vm86. */
1508 common_tss0.tss_esp0 = thread0.td_kstack + thread0.td_kstack_pages *
1509 PAGE_SIZE - VM86_STACK_SPACE;
1510 common_tss0.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
1511 common_tss0.tss_ioopt = sizeof(struct i386tss) << 16;
1512 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1513 PCPU_SET(tss_gdt, &gdt[GPROC0_SEL].sd);
1514 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
1515 ltr(gsel_tss);
1516
1517 /* Initialize the PIC early for vm86 calls. */
1518 #ifdef DEV_ISA
1519 #ifdef DEV_ATPIC
1520 elcr_probe();
1521 atpic_startup();
1522 #else
1523 /* Reset and mask the atpics and leave them shut down. */
1524 atpic_reset();
1525
1526 /*
1527 * Point the ICU spurious interrupt vectors at the APIC spurious
1528 * interrupt handler.
1529 */
1530 i386_setidt3();
1531 #endif
1532 #endif
1533
1534 /*
1535 * The console and kdb should be initialized even earlier than here,
1536 * but some console drivers don't work until after getmemsize().
1537 * Default to late console initialization to support these drivers.
1538 * This loses mainly printf()s in getmemsize() and early debugging.
1539 */
1540 TUNABLE_INT_FETCH("debug.late_console", &late_console);
1541 if (!late_console) {
1542 cninit();
1543 i386_kdb_init();
1544 }
1545
1546 if (cpu_fxsr && (cpu_feature2 & CPUID2_XSAVE) != 0) {
1547 use_xsave = 1;
1548 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
1549 }
1550
1551 kmdp = preload_search_by_type("elf kernel");
1552 link_elf_ireloc(kmdp);
1553
1554 vm86_initialize();
1555 getmemsize(first);
1556 init_param2(physmem);
1557
1558 /* now running on new page tables, configured,and u/iom is accessible */
1559
1560 if (late_console)
1561 cninit();
1562
1563 if (metadata_missing)
1564 printf("WARNING: loader(8) metadata is missing!\n");
1565
1566 if (late_console)
1567 i386_kdb_init();
1568
1569 msgbufinit(msgbufp, msgbufsize);
1570 npxinit(true);
1571
1572 /*
1573 * Set up thread0 pcb after npxinit calculated pcb + fpu save
1574 * area size. Zero out the extended state header in fpu save
1575 * area.
1576 */
1577 thread0.td_pcb = get_pcb_td(&thread0);
1578 thread0.td_pcb->pcb_save = get_pcb_user_save_td(&thread0);
1579 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size);
1580 if (use_xsave) {
1581 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) +
1582 1);
1583 xhdr->xstate_bv = xsave_mask;
1584 }
1585 PCPU_SET(curpcb, thread0.td_pcb);
1586 /* Move esp0 in the tss to its final place. */
1587 /* Note: -16 is so we can grow the trapframe if we came from vm86 */
1588 common_tss0.tss_esp0 = (vm_offset_t)thread0.td_pcb - VM86_STACK_SPACE;
1589 PCPU_SET(kesp0, common_tss0.tss_esp0);
1590 gdt[GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; /* clear busy bit */
1591 ltr(gsel_tss);
1592
1593 /* transfer to user mode */
1594
1595 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1596 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1597
1598 /* setup proc 0's pcb */
1599 thread0.td_pcb->pcb_flags = 0;
1600 thread0.td_pcb->pcb_cr3 = pmap_get_kcr3();
1601 thread0.td_pcb->pcb_ext = 0;
1602 thread0.td_frame = &proc0_tf;
1603
1604 #ifdef FDT
1605 x86_init_fdt();
1606 #endif
1607
1608 /* Location of kernel stack for locore */
1609 return ((register_t)thread0.td_pcb);
1610 }
1611
1612 static void
machdep_init_trampoline(void)1613 machdep_init_trampoline(void)
1614 {
1615 struct region_descriptor r_gdt, r_idt;
1616 struct i386tss *tss;
1617 char *copyout_buf, *trampoline, *tramp_stack_base;
1618 int x;
1619
1620 gdt = pmap_trm_alloc(sizeof(union descriptor) * NGDT * mp_ncpus,
1621 M_NOWAIT | M_ZERO);
1622 bcopy(gdt0, gdt, sizeof(union descriptor) * NGDT);
1623 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1624 r_gdt.rd_base = (int)gdt;
1625 lgdt(&r_gdt);
1626
1627 tss = pmap_trm_alloc(sizeof(struct i386tss) * mp_ncpus,
1628 M_NOWAIT | M_ZERO);
1629 bcopy(&common_tss0, tss, sizeof(struct i386tss));
1630 gdt[GPROC0_SEL].sd.sd_lobase = (int)tss;
1631 gdt[GPROC0_SEL].sd.sd_hibase = (u_int)tss >> 24;
1632 gdt[GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
1633
1634 PCPU_SET(fsgs_gdt, &gdt[GUFS_SEL].sd);
1635 PCPU_SET(tss_gdt, &gdt[GPROC0_SEL].sd);
1636 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
1637 PCPU_SET(common_tssp, tss);
1638 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1639
1640 trampoline = pmap_trm_alloc(end_exceptions - start_exceptions,
1641 M_NOWAIT);
1642 bcopy(start_exceptions, trampoline, end_exceptions - start_exceptions);
1643 tramp_stack_base = pmap_trm_alloc(TRAMP_STACK_SZ, M_NOWAIT);
1644 PCPU_SET(trampstk, (uintptr_t)tramp_stack_base + TRAMP_STACK_SZ -
1645 VM86_STACK_SPACE);
1646 tss[0].tss_esp0 = PCPU_GET(trampstk);
1647
1648 idt = pmap_trm_alloc(sizeof(idt0), M_NOWAIT | M_ZERO);
1649 bcopy(idt0, idt, sizeof(idt0));
1650
1651 /* Re-initialize new IDT since the handlers were relocated */
1652 setidt_disp = trampoline - start_exceptions;
1653 if (bootverbose)
1654 printf("Trampoline disposition %#zx\n", setidt_disp);
1655 fixup_idt();
1656
1657 r_idt.rd_limit = sizeof(struct gate_descriptor) * NIDT - 1;
1658 r_idt.rd_base = (int)idt;
1659 lidt(&r_idt);
1660
1661 /* dblfault TSS */
1662 dblfault_tss = pmap_trm_alloc(sizeof(struct i386tss), M_NOWAIT | M_ZERO);
1663 dblfault_stack = pmap_trm_alloc(PAGE_SIZE, M_NOWAIT);
1664 dblfault_tss->tss_esp = dblfault_tss->tss_esp0 =
1665 dblfault_tss->tss_esp1 = dblfault_tss->tss_esp2 =
1666 (int)dblfault_stack + PAGE_SIZE;
1667 dblfault_tss->tss_ss = dblfault_tss->tss_ss0 = dblfault_tss->tss_ss1 =
1668 dblfault_tss->tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
1669 dblfault_tss->tss_cr3 = pmap_get_kcr3();
1670 dblfault_tss->tss_eip = (int)dblfault_handler;
1671 dblfault_tss->tss_eflags = PSL_KERNEL;
1672 dblfault_tss->tss_ds = dblfault_tss->tss_es =
1673 dblfault_tss->tss_gs = GSEL(GDATA_SEL, SEL_KPL);
1674 dblfault_tss->tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
1675 dblfault_tss->tss_cs = GSEL(GCODE_SEL, SEL_KPL);
1676 dblfault_tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
1677 gdt[GPANIC_SEL].sd.sd_lobase = (int)dblfault_tss;
1678 gdt[GPANIC_SEL].sd.sd_hibase = (u_int)dblfault_tss >> 24;
1679
1680 /* make ldt memory segments */
1681 ldt = pmap_trm_alloc(sizeof(union descriptor) * NLDT,
1682 M_NOWAIT | M_ZERO);
1683 gdt[GLDT_SEL].sd.sd_lobase = (int)ldt;
1684 gdt[GLDT_SEL].sd.sd_hibase = (u_int)ldt >> 24;
1685 ldt_segs[LUCODE_SEL].ssd_limit = atop(0 - 1);
1686 ldt_segs[LUDATA_SEL].ssd_limit = atop(0 - 1);
1687 for (x = 0; x < nitems(ldt_segs); x++)
1688 ssdtosd(&ldt_segs[x], &ldt[x].sd);
1689
1690 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
1691 lldt(_default_ldt);
1692 PCPU_SET(currentldt, _default_ldt);
1693
1694 copyout_buf = pmap_trm_alloc(TRAMP_COPYOUT_SZ, M_NOWAIT);
1695 PCPU_SET(copyout_buf, copyout_buf);
1696 copyout_init_tramp();
1697 }
1698 SYSINIT(vm_mem, SI_SUB_VM, SI_ORDER_SECOND, machdep_init_trampoline, NULL);
1699
1700 #ifdef COMPAT_43
1701 static void
i386_setup_lcall_gate(void)1702 i386_setup_lcall_gate(void)
1703 {
1704 struct sysentvec *sv;
1705 struct user_segment_descriptor desc;
1706 u_int lcall_addr;
1707
1708 sv = &elf32_freebsd_sysvec;
1709 lcall_addr = (uintptr_t)sv->sv_psstrings - sz_lcall_tramp;
1710
1711 bzero(&desc, sizeof(desc));
1712 desc.sd_type = SDT_MEMERA;
1713 desc.sd_dpl = SEL_UPL;
1714 desc.sd_p = 1;
1715 desc.sd_def32 = 1;
1716 desc.sd_gran = 1;
1717 desc.sd_lolimit = 0xffff;
1718 desc.sd_hilimit = 0xf;
1719 desc.sd_lobase = lcall_addr;
1720 desc.sd_hibase = lcall_addr >> 24;
1721 bcopy(&desc, &ldt[LSYS5CALLS_SEL], sizeof(desc));
1722 }
1723 SYSINIT(elf32, SI_SUB_EXEC, SI_ORDER_ANY, i386_setup_lcall_gate, NULL);
1724 #endif
1725
1726 void
cpu_pcpu_init(struct pcpu * pcpu,int cpuid,size_t size)1727 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
1728 {
1729
1730 pcpu->pc_acpi_id = 0xffffffff;
1731 }
1732
1733 static int
smap_sysctl_handler(SYSCTL_HANDLER_ARGS)1734 smap_sysctl_handler(SYSCTL_HANDLER_ARGS)
1735 {
1736 struct bios_smap *smapbase;
1737 struct bios_smap_xattr smap;
1738 caddr_t kmdp;
1739 uint32_t *smapattr;
1740 int count, error, i;
1741
1742 /* Retrieve the system memory map from the loader. */
1743 kmdp = preload_search_by_type("elf kernel");
1744 if (kmdp == NULL)
1745 kmdp = preload_search_by_type("elf32 kernel");
1746 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1747 MODINFO_METADATA | MODINFOMD_SMAP);
1748 if (smapbase == NULL)
1749 return (0);
1750 smapattr = (uint32_t *)preload_search_info(kmdp,
1751 MODINFO_METADATA | MODINFOMD_SMAP_XATTR);
1752 count = *((u_int32_t *)smapbase - 1) / sizeof(*smapbase);
1753 error = 0;
1754 for (i = 0; i < count; i++) {
1755 smap.base = smapbase[i].base;
1756 smap.length = smapbase[i].length;
1757 smap.type = smapbase[i].type;
1758 if (smapattr != NULL)
1759 smap.xattr = smapattr[i];
1760 else
1761 smap.xattr = 0;
1762 error = SYSCTL_OUT(req, &smap, sizeof(smap));
1763 }
1764 return (error);
1765 }
1766 SYSCTL_PROC(_machdep, OID_AUTO, smap,
1767 CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 0,
1768 smap_sysctl_handler, "S,bios_smap_xattr",
1769 "Raw BIOS SMAP data");
1770
1771 void
spinlock_enter(void)1772 spinlock_enter(void)
1773 {
1774 struct thread *td;
1775 register_t flags;
1776
1777 td = curthread;
1778 if (td->td_md.md_spinlock_count == 0) {
1779 flags = intr_disable();
1780 td->td_md.md_spinlock_count = 1;
1781 td->td_md.md_saved_flags = flags;
1782 critical_enter();
1783 } else
1784 td->td_md.md_spinlock_count++;
1785 }
1786
1787 void
spinlock_exit(void)1788 spinlock_exit(void)
1789 {
1790 struct thread *td;
1791 register_t flags;
1792
1793 td = curthread;
1794 flags = td->td_md.md_saved_flags;
1795 td->td_md.md_spinlock_count--;
1796 if (td->td_md.md_spinlock_count == 0) {
1797 critical_exit();
1798 intr_restore(flags);
1799 }
1800 }
1801
1802 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
1803 static void f00f_hack(void *unused);
1804 SYSINIT(f00f_hack, SI_SUB_INTRINSIC, SI_ORDER_FIRST, f00f_hack, NULL);
1805
1806 static void
f00f_hack(void * unused)1807 f00f_hack(void *unused)
1808 {
1809 struct region_descriptor r_idt;
1810 struct gate_descriptor *new_idt;
1811 vm_offset_t tmp;
1812
1813 if (!has_f00f_bug)
1814 return;
1815
1816 printf("Intel Pentium detected, installing workaround for F00F bug\n");
1817
1818 tmp = (vm_offset_t)pmap_trm_alloc(PAGE_SIZE * 3, M_NOWAIT | M_ZERO);
1819 if (tmp == 0)
1820 panic("kmem_malloc returned 0");
1821 tmp = round_page(tmp);
1822
1823 /* Put the problematic entry (#6) at the end of the lower page. */
1824 new_idt = (struct gate_descriptor *)
1825 (tmp + PAGE_SIZE - 7 * sizeof(struct gate_descriptor));
1826 bcopy(idt, new_idt, sizeof(idt0));
1827 r_idt.rd_base = (u_int)new_idt;
1828 r_idt.rd_limit = sizeof(idt0) - 1;
1829 lidt(&r_idt);
1830 /* SMP machines do not need the F00F hack. */
1831 idt = new_idt;
1832 pmap_protect(kernel_pmap, tmp, tmp + PAGE_SIZE, VM_PROT_READ);
1833 }
1834 #endif /* defined(I586_CPU) && !NO_F00F_HACK */
1835
1836 /*
1837 * Construct a PCB from a trapframe. This is called from kdb_trap() where
1838 * we want to start a backtrace from the function that caused us to enter
1839 * the debugger. We have the context in the trapframe, but base the trace
1840 * on the PCB. The PCB doesn't have to be perfect, as long as it contains
1841 * enough for a backtrace.
1842 */
1843 void
makectx(struct trapframe * tf,struct pcb * pcb)1844 makectx(struct trapframe *tf, struct pcb *pcb)
1845 {
1846
1847 pcb->pcb_edi = tf->tf_edi;
1848 pcb->pcb_esi = tf->tf_esi;
1849 pcb->pcb_ebp = tf->tf_ebp;
1850 pcb->pcb_ebx = tf->tf_ebx;
1851 pcb->pcb_eip = tf->tf_eip;
1852 pcb->pcb_esp = (ISPL(tf->tf_cs)) ? tf->tf_esp : (int)(tf + 1) - 8;
1853 pcb->pcb_gs = rgs();
1854 }
1855
1856 #ifdef KDB
1857
1858 /*
1859 * Provide inb() and outb() as functions. They are normally only available as
1860 * inline functions, thus cannot be called from the debugger.
1861 */
1862
1863 /* silence compiler warnings */
1864 u_char inb_(u_short);
1865 void outb_(u_short, u_char);
1866
1867 u_char
inb_(u_short port)1868 inb_(u_short port)
1869 {
1870 return inb(port);
1871 }
1872
1873 void
outb_(u_short port,u_char data)1874 outb_(u_short port, u_char data)
1875 {
1876 outb(port, data);
1877 }
1878
1879 #endif /* KDB */
1880