1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
3 *
4 * Copyright (c) 1995, David Greenman
5 * Copyright (c) 2001 Jonathan Lemon <[email protected]>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 /*
36 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
37 */
38
39 #ifdef HAVE_KERNEL_OPTION_HEADERS
40 #include "opt_device_polling.h"
41 #endif
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/bus.h>
46 #include <sys/endian.h>
47 #include <sys/kernel.h>
48 #include <sys/mbuf.h>
49 #include <sys/lock.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
53 #include <sys/rman.h>
54 #include <sys/socket.h>
55 #include <sys/sockio.h>
56 #include <sys/sysctl.h>
57
58 #include <net/bpf.h>
59 #include <net/ethernet.h>
60 #include <net/if.h>
61 #include <net/if_var.h>
62 #include <net/if_arp.h>
63 #include <net/if_dl.h>
64 #include <net/if_media.h>
65 #include <net/if_types.h>
66 #include <net/if_vlan_var.h>
67
68 #include <netinet/in.h>
69 #include <netinet/in_systm.h>
70 #include <netinet/ip.h>
71 #include <netinet/tcp.h>
72 #include <netinet/udp.h>
73
74 #include <machine/bus.h>
75 #include <machine/in_cksum.h>
76 #include <machine/resource.h>
77
78 #include <dev/pci/pcivar.h>
79 #include <dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
80
81 #include <dev/mii/mii.h>
82 #include <dev/mii/miivar.h>
83
84 #include <dev/fxp/if_fxpreg.h>
85 #include <dev/fxp/if_fxpvar.h>
86 #include <dev/fxp/rcvbundl.h>
87
88 MODULE_DEPEND(fxp, pci, 1, 1, 1);
89 MODULE_DEPEND(fxp, ether, 1, 1, 1);
90 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
91 #include "miibus_if.h"
92
93 /*
94 * NOTE! On !x86 we typically have an alignment constraint. The
95 * card DMAs the packet immediately following the RFA. However,
96 * the first thing in the packet is a 14-byte Ethernet header.
97 * This means that the packet is misaligned. To compensate,
98 * we actually offset the RFA 2 bytes into the cluster. This
99 * alignes the packet after the Ethernet header at a 32-bit
100 * boundary. HOWEVER! This means that the RFA is misaligned!
101 */
102 #define RFA_ALIGNMENT_FUDGE 2
103
104 /*
105 * Set initial transmit threshold at 64 (512 bytes). This is
106 * increased by 64 (512 bytes) at a time, to maximum of 192
107 * (1536 bytes), if an underrun occurs.
108 */
109 static int tx_threshold = 64;
110
111 /*
112 * The configuration byte map has several undefined fields which
113 * must be one or must be zero. Set up a template for these bits.
114 * The actual configuration is performed in fxp_init_body.
115 *
116 * See struct fxp_cb_config for the bit definitions.
117 */
118 static const u_char fxp_cb_config_template[] = {
119 0x0, 0x0, /* cb_status */
120 0x0, 0x0, /* cb_command */
121 0x0, 0x0, 0x0, 0x0, /* link_addr */
122 0x0, /* 0 */
123 0x0, /* 1 */
124 0x0, /* 2 */
125 0x0, /* 3 */
126 0x0, /* 4 */
127 0x0, /* 5 */
128 0x32, /* 6 */
129 0x0, /* 7 */
130 0x0, /* 8 */
131 0x0, /* 9 */
132 0x6, /* 10 */
133 0x0, /* 11 */
134 0x0, /* 12 */
135 0x0, /* 13 */
136 0xf2, /* 14 */
137 0x48, /* 15 */
138 0x0, /* 16 */
139 0x40, /* 17 */
140 0xf0, /* 18 */
141 0x0, /* 19 */
142 0x3f, /* 20 */
143 0x5, /* 21 */
144 0x0, /* 22 */
145 0x0, /* 23 */
146 0x0, /* 24 */
147 0x0, /* 25 */
148 0x0, /* 26 */
149 0x0, /* 27 */
150 0x0, /* 28 */
151 0x0, /* 29 */
152 0x0, /* 30 */
153 0x0 /* 31 */
154 };
155
156 /*
157 * Claim various Intel PCI device identifiers for this driver. The
158 * sub-vendor and sub-device field are extensively used to identify
159 * particular variants, but we don't currently differentiate between
160 * them.
161 */
162 static const struct fxp_ident fxp_ident_table[] = {
163 { 0x8086, 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
164 { 0x8086, 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
165 { 0x8086, 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
166 { 0x8086, 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
167 { 0x8086, 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
168 { 0x8086, 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
169 { 0x8086, 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
170 { 0x8086, 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
171 { 0x8086, 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
172 { 0x8086, 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
173 { 0x8086, 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
174 { 0x8086, 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
175 { 0x8086, 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
176 { 0x8086, 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
177 { 0x8086, 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
178 { 0x8086, 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
179 { 0x8086, 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
180 { 0x8086, 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
181 { 0x8086, 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
182 { 0x8086, 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
183 { 0x8086, 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
184 { 0x8086, 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
185 { 0x8086, 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
186 { 0x8086, 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
187 { 0x8086, 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
188 { 0x8086, 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
189 { 0x8086, 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
190 { 0x8086, 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
191 { 0x8086, 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
192 { 0x8086, 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
193 { 0x8086, 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
194 { 0x8086, 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
195 { 0x8086, 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
196 { 0x8086, 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
197 { 0x8086, 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
198 { 0x8086, 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
199 { 0x8086, 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
200 { 0x8086, 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
201 { 0x8086, 0x1229, 0x0d, 0, "Intel 82550C Pro/100 Ethernet" },
202 { 0x8086, 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
203 { 0x8086, 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
204 { 0x8086, 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
205 { 0x8086, 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
206 { 0x8086, 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
207 { 0x8086, 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
208 { 0, 0, -1, 0, NULL },
209 };
210
211 #ifdef FXP_IP_CSUM_WAR
212 #define FXP_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
213 #else
214 #define FXP_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
215 #endif
216
217 static int fxp_probe(device_t dev);
218 static int fxp_attach(device_t dev);
219 static int fxp_detach(device_t dev);
220 static int fxp_shutdown(device_t dev);
221 static int fxp_suspend(device_t dev);
222 static int fxp_resume(device_t dev);
223
224 static const struct fxp_ident *fxp_find_ident(device_t dev);
225 static void fxp_intr(void *xsc);
226 static void fxp_rxcsum(struct fxp_softc *sc, if_t ifp,
227 struct mbuf *m, uint16_t status, int pos);
228 static int fxp_intr_body(struct fxp_softc *sc, if_t ifp,
229 uint8_t statack, int count);
230 static void fxp_init(void *xsc);
231 static void fxp_init_body(struct fxp_softc *sc, int);
232 static void fxp_tick(void *xsc);
233 static void fxp_start(if_t ifp);
234 static void fxp_start_body(if_t ifp);
235 static int fxp_encap(struct fxp_softc *sc, struct mbuf **m_head);
236 static void fxp_txeof(struct fxp_softc *sc);
237 static void fxp_stop(struct fxp_softc *sc);
238 static void fxp_release(struct fxp_softc *sc);
239 static int fxp_ioctl(if_t ifp, u_long command,
240 caddr_t data);
241 static void fxp_watchdog(struct fxp_softc *sc);
242 static void fxp_add_rfabuf(struct fxp_softc *sc,
243 struct fxp_rx *rxp);
244 static void fxp_discard_rfabuf(struct fxp_softc *sc,
245 struct fxp_rx *rxp);
246 static int fxp_new_rfabuf(struct fxp_softc *sc,
247 struct fxp_rx *rxp);
248 static void fxp_mc_addrs(struct fxp_softc *sc);
249 static void fxp_mc_setup(struct fxp_softc *sc);
250 static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
251 int autosize);
252 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
253 uint16_t data);
254 static void fxp_autosize_eeprom(struct fxp_softc *sc);
255 static void fxp_load_eeprom(struct fxp_softc *sc);
256 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
257 int offset, int words);
258 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
259 int offset, int words);
260 static int fxp_ifmedia_upd(if_t ifp);
261 static void fxp_ifmedia_sts(if_t ifp,
262 struct ifmediareq *ifmr);
263 static int fxp_serial_ifmedia_upd(if_t ifp);
264 static void fxp_serial_ifmedia_sts(if_t ifp,
265 struct ifmediareq *ifmr);
266 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
267 static int fxp_miibus_writereg(device_t dev, int phy, int reg,
268 int value);
269 static void fxp_miibus_statchg(device_t dev);
270 static void fxp_load_ucode(struct fxp_softc *sc);
271 static void fxp_update_stats(struct fxp_softc *sc);
272 static void fxp_sysctl_node(struct fxp_softc *sc);
273 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
274 int low, int high);
275 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
276 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
277 static void fxp_scb_wait(struct fxp_softc *sc);
278 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
279 static void fxp_dma_wait(struct fxp_softc *sc,
280 volatile uint16_t *status, bus_dma_tag_t dmat,
281 bus_dmamap_t map);
282
283 static device_method_t fxp_methods[] = {
284 /* Device interface */
285 DEVMETHOD(device_probe, fxp_probe),
286 DEVMETHOD(device_attach, fxp_attach),
287 DEVMETHOD(device_detach, fxp_detach),
288 DEVMETHOD(device_shutdown, fxp_shutdown),
289 DEVMETHOD(device_suspend, fxp_suspend),
290 DEVMETHOD(device_resume, fxp_resume),
291
292 /* MII interface */
293 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
294 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
295 DEVMETHOD(miibus_statchg, fxp_miibus_statchg),
296
297 DEVMETHOD_END
298 };
299
300 static driver_t fxp_driver = {
301 "fxp",
302 fxp_methods,
303 sizeof(struct fxp_softc),
304 };
305
306 static devclass_t fxp_devclass;
307
308 DRIVER_MODULE_ORDERED(fxp, pci, fxp_driver, fxp_devclass, NULL, NULL,
309 SI_ORDER_ANY);
310 MODULE_PNP_INFO("U16:vendor;U16:device", pci, fxp, fxp_ident_table,
311 nitems(fxp_ident_table) - 1);
312 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, NULL, NULL);
313
314 static struct resource_spec fxp_res_spec_mem[] = {
315 { SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
316 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
317 { -1, 0 }
318 };
319
320 static struct resource_spec fxp_res_spec_io[] = {
321 { SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
322 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
323 { -1, 0 }
324 };
325
326 /*
327 * Wait for the previous command to be accepted (but not necessarily
328 * completed).
329 */
330 static void
fxp_scb_wait(struct fxp_softc * sc)331 fxp_scb_wait(struct fxp_softc *sc)
332 {
333 union {
334 uint16_t w;
335 uint8_t b[2];
336 } flowctl;
337 int i = 10000;
338
339 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
340 DELAY(2);
341 if (i == 0) {
342 flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
343 flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
344 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
345 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
346 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
347 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
348 }
349 }
350
351 static void
fxp_scb_cmd(struct fxp_softc * sc,int cmd)352 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
353 {
354
355 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
356 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
357 fxp_scb_wait(sc);
358 }
359 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
360 }
361
362 static void
fxp_dma_wait(struct fxp_softc * sc,volatile uint16_t * status,bus_dma_tag_t dmat,bus_dmamap_t map)363 fxp_dma_wait(struct fxp_softc *sc, volatile uint16_t *status,
364 bus_dma_tag_t dmat, bus_dmamap_t map)
365 {
366 int i;
367
368 for (i = 10000; i > 0; i--) {
369 DELAY(2);
370 bus_dmamap_sync(dmat, map,
371 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
372 if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
373 break;
374 }
375 if (i == 0)
376 device_printf(sc->dev, "DMA timeout\n");
377 }
378
379 static const struct fxp_ident *
fxp_find_ident(device_t dev)380 fxp_find_ident(device_t dev)
381 {
382 uint16_t vendor;
383 uint16_t device;
384 uint8_t revid;
385 const struct fxp_ident *ident;
386
387 vendor = pci_get_vendor(dev);
388 device = pci_get_device(dev);
389 revid = pci_get_revid(dev);
390 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
391 if (ident->vendor == vendor && ident->device == device &&
392 (ident->revid == revid || ident->revid == -1)) {
393 return (ident);
394 }
395 }
396 return (NULL);
397 }
398
399 /*
400 * Return identification string if this device is ours.
401 */
402 static int
fxp_probe(device_t dev)403 fxp_probe(device_t dev)
404 {
405 const struct fxp_ident *ident;
406
407 ident = fxp_find_ident(dev);
408 if (ident != NULL) {
409 device_set_desc(dev, ident->name);
410 return (BUS_PROBE_DEFAULT);
411 }
412 return (ENXIO);
413 }
414
415 static void
fxp_dma_map_addr(void * arg,bus_dma_segment_t * segs,int nseg,int error)416 fxp_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
417 {
418 uint32_t *addr;
419
420 if (error)
421 return;
422
423 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
424 addr = arg;
425 *addr = segs->ds_addr;
426 }
427
428 static int
fxp_attach(device_t dev)429 fxp_attach(device_t dev)
430 {
431 struct fxp_softc *sc;
432 struct fxp_cb_tx *tcbp;
433 struct fxp_tx *txp;
434 struct fxp_rx *rxp;
435 if_t ifp;
436 uint32_t val;
437 uint16_t data;
438 u_char eaddr[ETHER_ADDR_LEN];
439 int error, flags, i, pmc, prefer_iomap;
440
441 error = 0;
442 sc = device_get_softc(dev);
443 sc->dev = dev;
444 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
445 MTX_DEF);
446 callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
447 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
448 fxp_serial_ifmedia_sts);
449
450 ifp = sc->ifp = if_gethandle(IFT_ETHER);
451 if (ifp == (void *)NULL) {
452 device_printf(dev, "can not if_alloc()\n");
453 error = ENOSPC;
454 goto fail;
455 }
456
457 /*
458 * Enable bus mastering.
459 */
460 pci_enable_busmaster(dev);
461
462 /*
463 * Figure out which we should try first - memory mapping or i/o mapping?
464 * We default to memory mapping. Then we accept an override from the
465 * command line. Then we check to see which one is enabled.
466 */
467 prefer_iomap = 0;
468 resource_int_value(device_get_name(dev), device_get_unit(dev),
469 "prefer_iomap", &prefer_iomap);
470 if (prefer_iomap)
471 sc->fxp_spec = fxp_res_spec_io;
472 else
473 sc->fxp_spec = fxp_res_spec_mem;
474
475 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
476 if (error) {
477 if (sc->fxp_spec == fxp_res_spec_mem)
478 sc->fxp_spec = fxp_res_spec_io;
479 else
480 sc->fxp_spec = fxp_res_spec_mem;
481 error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
482 }
483 if (error) {
484 device_printf(dev, "could not allocate resources\n");
485 error = ENXIO;
486 goto fail;
487 }
488
489 if (bootverbose) {
490 device_printf(dev, "using %s space register mapping\n",
491 sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
492 }
493
494 /*
495 * Put CU/RU idle state and prepare full reset.
496 */
497 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
498 DELAY(10);
499 /* Full reset and disable interrupts. */
500 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
501 DELAY(10);
502 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
503
504 /*
505 * Find out how large of an SEEPROM we have.
506 */
507 fxp_autosize_eeprom(sc);
508 fxp_load_eeprom(sc);
509
510 /*
511 * Find out the chip revision; lump all 82557 revs together.
512 */
513 sc->ident = fxp_find_ident(dev);
514 if (sc->ident->ich > 0) {
515 /* Assume ICH controllers are 82559. */
516 sc->revision = FXP_REV_82559_A0;
517 } else {
518 data = sc->eeprom[FXP_EEPROM_MAP_CNTR];
519 if ((data >> 8) == 1)
520 sc->revision = FXP_REV_82557;
521 else
522 sc->revision = pci_get_revid(dev);
523 }
524
525 /*
526 * Check availability of WOL. 82559ER does not support WOL.
527 */
528 if (sc->revision >= FXP_REV_82558_A4 &&
529 sc->revision != FXP_REV_82559S_A) {
530 data = sc->eeprom[FXP_EEPROM_MAP_ID];
531 if ((data & 0x20) != 0 &&
532 pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0)
533 sc->flags |= FXP_FLAG_WOLCAP;
534 }
535
536 if (sc->revision == FXP_REV_82550_C) {
537 /*
538 * 82550C with server extension requires microcode to
539 * receive fragmented UDP datagrams. However if the
540 * microcode is used for client-only featured 82550C
541 * it locks up controller.
542 */
543 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
544 if ((data & 0x0400) == 0)
545 sc->flags |= FXP_FLAG_NO_UCODE;
546 }
547
548 /* Receiver lock-up workaround detection. */
549 if (sc->revision < FXP_REV_82558_A4) {
550 data = sc->eeprom[FXP_EEPROM_MAP_COMPAT];
551 if ((data & 0x03) != 0x03) {
552 sc->flags |= FXP_FLAG_RXBUG;
553 device_printf(dev, "Enabling Rx lock-up workaround\n");
554 }
555 }
556
557 /*
558 * Determine whether we must use the 503 serial interface.
559 */
560 data = sc->eeprom[FXP_EEPROM_MAP_PRI_PHY];
561 if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
562 && (data & FXP_PHY_SERIAL_ONLY))
563 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
564
565 fxp_sysctl_node(sc);
566 /*
567 * Enable workarounds for certain chip revision deficiencies.
568 *
569 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
570 * some systems based a normal 82559 design, have a defect where
571 * the chip can cause a PCI protocol violation if it receives
572 * a CU_RESUME command when it is entering the IDLE state. The
573 * workaround is to disable Dynamic Standby Mode, so the chip never
574 * deasserts CLKRUN#, and always remains in an active state.
575 *
576 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
577 */
578 if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) ||
579 (sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
580 data = sc->eeprom[FXP_EEPROM_MAP_ID];
581 if (data & 0x02) { /* STB enable */
582 uint16_t cksum;
583 int i;
584
585 device_printf(dev,
586 "Disabling dynamic standby mode in EEPROM\n");
587 data &= ~0x02;
588 sc->eeprom[FXP_EEPROM_MAP_ID] = data;
589 fxp_write_eeprom(sc, &data, FXP_EEPROM_MAP_ID, 1);
590 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
591 cksum = 0;
592 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
593 cksum += sc->eeprom[i];
594 i = (1 << sc->eeprom_size) - 1;
595 cksum = 0xBABA - cksum;
596 fxp_write_eeprom(sc, &cksum, i, 1);
597 device_printf(dev,
598 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
599 i, sc->eeprom[i], cksum);
600 sc->eeprom[i] = cksum;
601 /*
602 * If the user elects to continue, try the software
603 * workaround, as it is better than nothing.
604 */
605 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
606 }
607 }
608
609 /*
610 * If we are not a 82557 chip, we can enable extended features.
611 */
612 if (sc->revision != FXP_REV_82557) {
613 /*
614 * If MWI is enabled in the PCI configuration, and there
615 * is a valid cacheline size (8 or 16 dwords), then tell
616 * the board to turn on MWI.
617 */
618 val = pci_read_config(dev, PCIR_COMMAND, 2);
619 if (val & PCIM_CMD_MWRICEN &&
620 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
621 sc->flags |= FXP_FLAG_MWI_ENABLE;
622
623 /* turn on the extended TxCB feature */
624 sc->flags |= FXP_FLAG_EXT_TXCB;
625
626 /* enable reception of long frames for VLAN */
627 sc->flags |= FXP_FLAG_LONG_PKT_EN;
628 } else {
629 /* a hack to get long VLAN frames on a 82557 */
630 sc->flags |= FXP_FLAG_SAVE_BAD;
631 }
632
633 /* For 82559 or later chips, Rx checksum offload is supported. */
634 if (sc->revision >= FXP_REV_82559_A0) {
635 /* 82559ER does not support Rx checksum offloading. */
636 if (sc->ident->device != 0x1209)
637 sc->flags |= FXP_FLAG_82559_RXCSUM;
638 }
639 /*
640 * Enable use of extended RFDs and TCBs for 82550
641 * and later chips. Note: we need extended TXCB support
642 * too, but that's already enabled by the code above.
643 * Be careful to do this only on the right devices.
644 */
645 if (sc->revision == FXP_REV_82550 || sc->revision == FXP_REV_82550_C ||
646 sc->revision == FXP_REV_82551_E || sc->revision == FXP_REV_82551_F
647 || sc->revision == FXP_REV_82551_10) {
648 sc->rfa_size = sizeof (struct fxp_rfa);
649 sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
650 sc->flags |= FXP_FLAG_EXT_RFA;
651 /* Use extended RFA instead of 82559 checksum mode. */
652 sc->flags &= ~FXP_FLAG_82559_RXCSUM;
653 } else {
654 sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
655 sc->tx_cmd = FXP_CB_COMMAND_XMIT;
656 }
657
658 /*
659 * Allocate DMA tags and DMA safe memory.
660 */
661 sc->maxtxseg = FXP_NTXSEG;
662 sc->maxsegsize = MCLBYTES;
663 if (sc->flags & FXP_FLAG_EXT_RFA) {
664 sc->maxtxseg--;
665 sc->maxsegsize = FXP_TSO_SEGSIZE;
666 }
667 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
668 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
669 sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
670 sc->maxtxseg, sc->maxsegsize, 0, NULL, NULL, &sc->fxp_txmtag);
671 if (error) {
672 device_printf(dev, "could not create TX DMA tag\n");
673 goto fail;
674 }
675
676 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
677 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
678 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->fxp_rxmtag);
679 if (error) {
680 device_printf(dev, "could not create RX DMA tag\n");
681 goto fail;
682 }
683
684 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
685 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
686 sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
687 NULL, NULL, &sc->fxp_stag);
688 if (error) {
689 device_printf(dev, "could not create stats DMA tag\n");
690 goto fail;
691 }
692
693 error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
694 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->fxp_smap);
695 if (error) {
696 device_printf(dev, "could not allocate stats DMA memory\n");
697 goto fail;
698 }
699 error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
700 sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr,
701 BUS_DMA_NOWAIT);
702 if (error) {
703 device_printf(dev, "could not load the stats DMA buffer\n");
704 goto fail;
705 }
706
707 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
708 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
709 FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0, NULL, NULL, &sc->cbl_tag);
710 if (error) {
711 device_printf(dev, "could not create TxCB DMA tag\n");
712 goto fail;
713 }
714
715 error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
716 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->cbl_map);
717 if (error) {
718 device_printf(dev, "could not allocate TxCB DMA memory\n");
719 goto fail;
720 }
721
722 error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
723 sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
724 &sc->fxp_desc.cbl_addr, BUS_DMA_NOWAIT);
725 if (error) {
726 device_printf(dev, "could not load TxCB DMA buffer\n");
727 goto fail;
728 }
729
730 error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
731 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
732 sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
733 NULL, NULL, &sc->mcs_tag);
734 if (error) {
735 device_printf(dev,
736 "could not create multicast setup DMA tag\n");
737 goto fail;
738 }
739
740 error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
741 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->mcs_map);
742 if (error) {
743 device_printf(dev,
744 "could not allocate multicast setup DMA memory\n");
745 goto fail;
746 }
747 error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
748 sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr,
749 BUS_DMA_NOWAIT);
750 if (error) {
751 device_printf(dev,
752 "can't load the multicast setup DMA buffer\n");
753 goto fail;
754 }
755
756 /*
757 * Pre-allocate the TX DMA maps and setup the pointers to
758 * the TX command blocks.
759 */
760 txp = sc->fxp_desc.tx_list;
761 tcbp = sc->fxp_desc.cbl_list;
762 for (i = 0; i < FXP_NTXCB; i++) {
763 txp[i].tx_cb = tcbp + i;
764 error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
765 if (error) {
766 device_printf(dev, "can't create DMA map for TX\n");
767 goto fail;
768 }
769 }
770 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
771 if (error) {
772 device_printf(dev, "can't create spare DMA map\n");
773 goto fail;
774 }
775
776 /*
777 * Pre-allocate our receive buffers.
778 */
779 sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
780 for (i = 0; i < FXP_NRFABUFS; i++) {
781 rxp = &sc->fxp_desc.rx_list[i];
782 error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
783 if (error) {
784 device_printf(dev, "can't create DMA map for RX\n");
785 goto fail;
786 }
787 if (fxp_new_rfabuf(sc, rxp) != 0) {
788 error = ENOMEM;
789 goto fail;
790 }
791 fxp_add_rfabuf(sc, rxp);
792 }
793
794 /*
795 * Read MAC address.
796 */
797 eaddr[0] = sc->eeprom[FXP_EEPROM_MAP_IA0] & 0xff;
798 eaddr[1] = sc->eeprom[FXP_EEPROM_MAP_IA0] >> 8;
799 eaddr[2] = sc->eeprom[FXP_EEPROM_MAP_IA1] & 0xff;
800 eaddr[3] = sc->eeprom[FXP_EEPROM_MAP_IA1] >> 8;
801 eaddr[4] = sc->eeprom[FXP_EEPROM_MAP_IA2] & 0xff;
802 eaddr[5] = sc->eeprom[FXP_EEPROM_MAP_IA2] >> 8;
803 if (bootverbose) {
804 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
805 pci_get_vendor(dev), pci_get_device(dev),
806 pci_get_subvendor(dev), pci_get_subdevice(dev),
807 pci_get_revid(dev));
808 device_printf(dev, "Dynamic Standby mode is %s\n",
809 sc->eeprom[FXP_EEPROM_MAP_ID] & 0x02 ? "enabled" :
810 "disabled");
811 }
812
813 /*
814 * If this is only a 10Mbps device, then there is no MII, and
815 * the PHY will use a serial interface instead.
816 *
817 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
818 * doesn't have a programming interface of any sort. The
819 * media is sensed automatically based on how the link partner
820 * is configured. This is, in essence, manual configuration.
821 */
822 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
823 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
824 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
825 } else {
826 /*
827 * i82557 wedge when isolating all of their PHYs.
828 */
829 flags = MIIF_NOISOLATE;
830 if (sc->revision >= FXP_REV_82558_A4)
831 flags |= MIIF_DOPAUSE;
832 error = mii_attach(dev, &sc->miibus, ifp,
833 (ifm_change_cb_t)fxp_ifmedia_upd,
834 (ifm_stat_cb_t)fxp_ifmedia_sts, BMSR_DEFCAPMASK,
835 MII_PHY_ANY, MII_OFFSET_ANY, flags);
836 if (error != 0) {
837 device_printf(dev, "attaching PHYs failed\n");
838 goto fail;
839 }
840 }
841
842 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
843 if_setdev(ifp, dev);
844 if_setinitfn(ifp, fxp_init);
845 if_setsoftc(ifp, sc);
846 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
847 if_setioctlfn(ifp, fxp_ioctl);
848 if_setstartfn(ifp, fxp_start);
849
850 if_setcapabilities(ifp, 0);
851 if_setcapenable(ifp, 0);
852
853 /* Enable checksum offload/TSO for 82550 or better chips */
854 if (sc->flags & FXP_FLAG_EXT_RFA) {
855 if_sethwassist(ifp, FXP_CSUM_FEATURES | CSUM_TSO);
856 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
857 if_setcapenablebit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0);
858 }
859
860 if (sc->flags & FXP_FLAG_82559_RXCSUM) {
861 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0);
862 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0);
863 }
864
865 if (sc->flags & FXP_FLAG_WOLCAP) {
866 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
867 if_setcapenablebit(ifp, IFCAP_WOL_MAGIC, 0);
868 }
869
870 #ifdef DEVICE_POLLING
871 /* Inform the world we support polling. */
872 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
873 #endif
874
875 /*
876 * Attach the interface.
877 */
878 ether_ifattach(ifp, eaddr);
879
880 /*
881 * Tell the upper layer(s) we support long frames.
882 * Must appear after the call to ether_ifattach() because
883 * ether_ifattach() sets ifi_hdrlen to the default value.
884 */
885 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
886 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
887 if_setcapenablebit(ifp, IFCAP_VLAN_MTU, 0);
888 if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
889 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING |
890 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
891 if_setcapenablebit(ifp, IFCAP_VLAN_HWTAGGING |
892 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
893 }
894
895 /*
896 * Let the system queue as many packets as we have available
897 * TX descriptors.
898 */
899 if_setsendqlen(ifp, FXP_NTXCB - 1);
900 if_setsendqready(ifp);
901
902 /*
903 * Hook our interrupt after all initialization is complete.
904 */
905 error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
906 NULL, fxp_intr, sc, &sc->ih);
907 if (error) {
908 device_printf(dev, "could not setup irq\n");
909 ether_ifdetach(sc->ifp);
910 goto fail;
911 }
912
913 /*
914 * Configure hardware to reject magic frames otherwise
915 * system will hang on recipt of magic frames.
916 */
917 if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
918 FXP_LOCK(sc);
919 /* Clear wakeup events. */
920 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
921 fxp_init_body(sc, 0);
922 fxp_stop(sc);
923 FXP_UNLOCK(sc);
924 }
925
926 fail:
927 if (error)
928 fxp_release(sc);
929 return (error);
930 }
931
932 /*
933 * Release all resources. The softc lock should not be held and the
934 * interrupt should already be torn down.
935 */
936 static void
fxp_release(struct fxp_softc * sc)937 fxp_release(struct fxp_softc *sc)
938 {
939 struct fxp_rx *rxp;
940 struct fxp_tx *txp;
941 int i;
942
943 FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
944 KASSERT(sc->ih == NULL,
945 ("fxp_release() called with intr handle still active"));
946 if (sc->miibus)
947 device_delete_child(sc->dev, sc->miibus);
948 bus_generic_detach(sc->dev);
949 ifmedia_removeall(&sc->sc_media);
950 if (sc->fxp_desc.cbl_list) {
951 bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
952 bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
953 sc->cbl_map);
954 }
955 if (sc->fxp_stats) {
956 bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
957 bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
958 }
959 if (sc->mcsp) {
960 bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
961 bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
962 }
963 bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
964 if (sc->fxp_rxmtag) {
965 for (i = 0; i < FXP_NRFABUFS; i++) {
966 rxp = &sc->fxp_desc.rx_list[i];
967 if (rxp->rx_mbuf != NULL) {
968 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
969 BUS_DMASYNC_POSTREAD);
970 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
971 m_freem(rxp->rx_mbuf);
972 }
973 bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
974 }
975 bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
976 bus_dma_tag_destroy(sc->fxp_rxmtag);
977 }
978 if (sc->fxp_txmtag) {
979 for (i = 0; i < FXP_NTXCB; i++) {
980 txp = &sc->fxp_desc.tx_list[i];
981 if (txp->tx_mbuf != NULL) {
982 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
983 BUS_DMASYNC_POSTWRITE);
984 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
985 m_freem(txp->tx_mbuf);
986 }
987 bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
988 }
989 bus_dma_tag_destroy(sc->fxp_txmtag);
990 }
991 if (sc->fxp_stag)
992 bus_dma_tag_destroy(sc->fxp_stag);
993 if (sc->cbl_tag)
994 bus_dma_tag_destroy(sc->cbl_tag);
995 if (sc->mcs_tag)
996 bus_dma_tag_destroy(sc->mcs_tag);
997 if (sc->ifp)
998 if_free(sc->ifp);
999
1000 mtx_destroy(&sc->sc_mtx);
1001 }
1002
1003 /*
1004 * Detach interface.
1005 */
1006 static int
fxp_detach(device_t dev)1007 fxp_detach(device_t dev)
1008 {
1009 struct fxp_softc *sc = device_get_softc(dev);
1010
1011 #ifdef DEVICE_POLLING
1012 if (if_getcapenable(sc->ifp) & IFCAP_POLLING)
1013 ether_poll_deregister(sc->ifp);
1014 #endif
1015
1016 FXP_LOCK(sc);
1017 /*
1018 * Stop DMA and drop transmit queue, but disable interrupts first.
1019 */
1020 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1021 fxp_stop(sc);
1022 FXP_UNLOCK(sc);
1023 callout_drain(&sc->stat_ch);
1024
1025 /*
1026 * Close down routes etc.
1027 */
1028 ether_ifdetach(sc->ifp);
1029
1030 /*
1031 * Unhook interrupt before dropping lock. This is to prevent
1032 * races with fxp_intr().
1033 */
1034 bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1035 sc->ih = NULL;
1036
1037 /* Release our allocated resources. */
1038 fxp_release(sc);
1039 return (0);
1040 }
1041
1042 /*
1043 * Device shutdown routine. Called at system shutdown after sync. The
1044 * main purpose of this routine is to shut off receiver DMA so that
1045 * kernel memory doesn't get clobbered during warmboot.
1046 */
1047 static int
fxp_shutdown(device_t dev)1048 fxp_shutdown(device_t dev)
1049 {
1050
1051 /*
1052 * Make sure that DMA is disabled prior to reboot. Not doing
1053 * do could allow DMA to corrupt kernel memory during the
1054 * reboot before the driver initializes.
1055 */
1056 return (fxp_suspend(dev));
1057 }
1058
1059 /*
1060 * Device suspend routine. Stop the interface and save some PCI
1061 * settings in case the BIOS doesn't restore them properly on
1062 * resume.
1063 */
1064 static int
fxp_suspend(device_t dev)1065 fxp_suspend(device_t dev)
1066 {
1067 struct fxp_softc *sc = device_get_softc(dev);
1068 if_t ifp;
1069 int pmc;
1070 uint16_t pmstat;
1071
1072 FXP_LOCK(sc);
1073
1074 ifp = sc->ifp;
1075 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1076 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1077 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1078 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) {
1079 /* Request PME. */
1080 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1081 sc->flags |= FXP_FLAG_WOL;
1082 /* Reconfigure hardware to accept magic frames. */
1083 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1084 fxp_init_body(sc, 0);
1085 }
1086 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1087 }
1088 fxp_stop(sc);
1089
1090 sc->suspended = 1;
1091
1092 FXP_UNLOCK(sc);
1093 return (0);
1094 }
1095
1096 /*
1097 * Device resume routine. re-enable busmastering, and restart the interface if
1098 * appropriate.
1099 */
1100 static int
fxp_resume(device_t dev)1101 fxp_resume(device_t dev)
1102 {
1103 struct fxp_softc *sc = device_get_softc(dev);
1104 if_t ifp = sc->ifp;
1105 int pmc;
1106 uint16_t pmstat;
1107
1108 FXP_LOCK(sc);
1109
1110 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1111 sc->flags &= ~FXP_FLAG_WOL;
1112 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1113 /* Disable PME and clear PME status. */
1114 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1115 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1116 if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1117 CSR_WRITE_1(sc, FXP_CSR_PMDR,
1118 CSR_READ_1(sc, FXP_CSR_PMDR));
1119 }
1120
1121 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1122 DELAY(10);
1123
1124 /* reinitialize interface if necessary */
1125 if (if_getflags(ifp) & IFF_UP)
1126 fxp_init_body(sc, 1);
1127
1128 sc->suspended = 0;
1129
1130 FXP_UNLOCK(sc);
1131 return (0);
1132 }
1133
1134 static void
fxp_eeprom_shiftin(struct fxp_softc * sc,int data,int length)1135 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1136 {
1137 uint16_t reg;
1138 int x;
1139
1140 /*
1141 * Shift in data.
1142 */
1143 for (x = 1 << (length - 1); x; x >>= 1) {
1144 if (data & x)
1145 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1146 else
1147 reg = FXP_EEPROM_EECS;
1148 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1149 DELAY(1);
1150 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1151 DELAY(1);
1152 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1153 DELAY(1);
1154 }
1155 }
1156
1157 /*
1158 * Read from the serial EEPROM. Basically, you manually shift in
1159 * the read opcode (one bit at a time) and then shift in the address,
1160 * and then you shift out the data (all of this one bit at a time).
1161 * The word size is 16 bits, so you have to provide the address for
1162 * every 16 bits of data.
1163 */
1164 static uint16_t
fxp_eeprom_getword(struct fxp_softc * sc,int offset,int autosize)1165 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1166 {
1167 uint16_t reg, data;
1168 int x;
1169
1170 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1171 /*
1172 * Shift in read opcode.
1173 */
1174 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1175 /*
1176 * Shift in address.
1177 */
1178 data = 0;
1179 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1180 if (offset & x)
1181 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
1182 else
1183 reg = FXP_EEPROM_EECS;
1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1185 DELAY(1);
1186 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1187 DELAY(1);
1188 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1189 DELAY(1);
1190 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1191 data++;
1192 if (autosize && reg == 0) {
1193 sc->eeprom_size = data;
1194 break;
1195 }
1196 }
1197 /*
1198 * Shift out data.
1199 */
1200 data = 0;
1201 reg = FXP_EEPROM_EECS;
1202 for (x = 1 << 15; x; x >>= 1) {
1203 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1204 DELAY(1);
1205 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1206 data |= x;
1207 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1208 DELAY(1);
1209 }
1210 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1211 DELAY(1);
1212
1213 return (data);
1214 }
1215
1216 static void
fxp_eeprom_putword(struct fxp_softc * sc,int offset,uint16_t data)1217 fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1218 {
1219 int i;
1220
1221 /*
1222 * Erase/write enable.
1223 */
1224 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1225 fxp_eeprom_shiftin(sc, 0x4, 3);
1226 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1227 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1228 DELAY(1);
1229 /*
1230 * Shift in write opcode, address, data.
1231 */
1232 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1233 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1234 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1235 fxp_eeprom_shiftin(sc, data, 16);
1236 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1237 DELAY(1);
1238 /*
1239 * Wait for EEPROM to finish up.
1240 */
1241 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1242 DELAY(1);
1243 for (i = 0; i < 1000; i++) {
1244 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1245 break;
1246 DELAY(50);
1247 }
1248 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1249 DELAY(1);
1250 /*
1251 * Erase/write disable.
1252 */
1253 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1254 fxp_eeprom_shiftin(sc, 0x4, 3);
1255 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1256 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1257 DELAY(1);
1258 }
1259
1260 /*
1261 * From NetBSD:
1262 *
1263 * Figure out EEPROM size.
1264 *
1265 * 559's can have either 64-word or 256-word EEPROMs, the 558
1266 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1267 * talks about the existence of 16 to 256 word EEPROMs.
1268 *
1269 * The only known sizes are 64 and 256, where the 256 version is used
1270 * by CardBus cards to store CIS information.
1271 *
1272 * The address is shifted in msb-to-lsb, and after the last
1273 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1274 * after which follows the actual data. We try to detect this zero, by
1275 * probing the data-out bit in the EEPROM control register just after
1276 * having shifted in a bit. If the bit is zero, we assume we've
1277 * shifted enough address bits. The data-out should be tri-state,
1278 * before this, which should translate to a logical one.
1279 */
1280 static void
fxp_autosize_eeprom(struct fxp_softc * sc)1281 fxp_autosize_eeprom(struct fxp_softc *sc)
1282 {
1283
1284 /* guess maximum size of 256 words */
1285 sc->eeprom_size = 8;
1286
1287 /* autosize */
1288 (void) fxp_eeprom_getword(sc, 0, 1);
1289 }
1290
1291 static void
fxp_read_eeprom(struct fxp_softc * sc,u_short * data,int offset,int words)1292 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1293 {
1294 int i;
1295
1296 for (i = 0; i < words; i++)
1297 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1298 }
1299
1300 static void
fxp_write_eeprom(struct fxp_softc * sc,u_short * data,int offset,int words)1301 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1302 {
1303 int i;
1304
1305 for (i = 0; i < words; i++)
1306 fxp_eeprom_putword(sc, offset + i, data[i]);
1307 }
1308
1309 static void
fxp_load_eeprom(struct fxp_softc * sc)1310 fxp_load_eeprom(struct fxp_softc *sc)
1311 {
1312 int i;
1313 uint16_t cksum;
1314
1315 fxp_read_eeprom(sc, sc->eeprom, 0, 1 << sc->eeprom_size);
1316 cksum = 0;
1317 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++)
1318 cksum += sc->eeprom[i];
1319 cksum = 0xBABA - cksum;
1320 if (cksum != sc->eeprom[(1 << sc->eeprom_size) - 1])
1321 device_printf(sc->dev,
1322 "EEPROM checksum mismatch! (0x%04x -> 0x%04x)\n",
1323 cksum, sc->eeprom[(1 << sc->eeprom_size) - 1]);
1324 }
1325
1326 /*
1327 * Grab the softc lock and call the real fxp_start_body() routine
1328 */
1329 static void
fxp_start(if_t ifp)1330 fxp_start(if_t ifp)
1331 {
1332 struct fxp_softc *sc = if_getsoftc(ifp);
1333
1334 FXP_LOCK(sc);
1335 fxp_start_body(ifp);
1336 FXP_UNLOCK(sc);
1337 }
1338
1339 /*
1340 * Start packet transmission on the interface.
1341 * This routine must be called with the softc lock held, and is an
1342 * internal entry point only.
1343 */
1344 static void
fxp_start_body(if_t ifp)1345 fxp_start_body(if_t ifp)
1346 {
1347 struct fxp_softc *sc = if_getsoftc(ifp);
1348 struct mbuf *mb_head;
1349 int txqueued;
1350
1351 FXP_LOCK_ASSERT(sc, MA_OWNED);
1352
1353 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1354 IFF_DRV_RUNNING)
1355 return;
1356
1357 if (sc->tx_queued > FXP_NTXCB_HIWAT)
1358 fxp_txeof(sc);
1359 /*
1360 * We're finished if there is nothing more to add to the list or if
1361 * we're all filled up with buffers to transmit.
1362 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1363 * a NOP command when needed.
1364 */
1365 txqueued = 0;
1366 while (!if_sendq_empty(ifp) && sc->tx_queued < FXP_NTXCB - 1) {
1367
1368 /*
1369 * Grab a packet to transmit.
1370 */
1371 mb_head = if_dequeue(ifp);
1372 if (mb_head == NULL)
1373 break;
1374
1375 if (fxp_encap(sc, &mb_head)) {
1376 if (mb_head == NULL)
1377 break;
1378 if_sendq_prepend(ifp, mb_head);
1379 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1380 }
1381 txqueued++;
1382 /*
1383 * Pass packet to bpf if there is a listener.
1384 */
1385 if_bpfmtap(ifp, mb_head);
1386 }
1387
1388 /*
1389 * We're finished. If we added to the list, issue a RESUME to get DMA
1390 * going again if suspended.
1391 */
1392 if (txqueued > 0) {
1393 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1394 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1395 fxp_scb_wait(sc);
1396 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1397 /*
1398 * Set a 5 second timer just in case we don't hear
1399 * from the card again.
1400 */
1401 sc->watchdog_timer = 5;
1402 }
1403 }
1404
1405 static int
fxp_encap(struct fxp_softc * sc,struct mbuf ** m_head)1406 fxp_encap(struct fxp_softc *sc, struct mbuf **m_head)
1407 {
1408 if_t ifp;
1409 struct mbuf *m;
1410 struct fxp_tx *txp;
1411 struct fxp_cb_tx *cbp;
1412 struct tcphdr *tcp;
1413 bus_dma_segment_t segs[FXP_NTXSEG];
1414 int error, i, nseg, tcp_payload;
1415
1416 FXP_LOCK_ASSERT(sc, MA_OWNED);
1417 ifp = sc->ifp;
1418
1419 tcp_payload = 0;
1420 tcp = NULL;
1421 /*
1422 * Get pointer to next available tx desc.
1423 */
1424 txp = sc->fxp_desc.tx_last->tx_next;
1425
1426 /*
1427 * A note in Appendix B of the Intel 8255x 10/100 Mbps
1428 * Ethernet Controller Family Open Source Software
1429 * Developer Manual says:
1430 * Using software parsing is only allowed with legal
1431 * TCP/IP or UDP/IP packets.
1432 * ...
1433 * For all other datagrams, hardware parsing must
1434 * be used.
1435 * Software parsing appears to truncate ICMP and
1436 * fragmented UDP packets that contain one to three
1437 * bytes in the second (and final) mbuf of the packet.
1438 */
1439 if (sc->flags & FXP_FLAG_EXT_RFA)
1440 txp->tx_cb->ipcb_ip_activation_high =
1441 FXP_IPCB_HARDWAREPARSING_ENABLE;
1442
1443 m = *m_head;
1444 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1445 /*
1446 * 82550/82551 requires ethernet/IP/TCP headers must be
1447 * contained in the first active transmit buffer.
1448 */
1449 struct ether_header *eh;
1450 struct ip *ip;
1451 uint32_t ip_off, poff;
1452
1453 if (M_WRITABLE(*m_head) == 0) {
1454 /* Get a writable copy. */
1455 m = m_dup(*m_head, M_NOWAIT);
1456 m_freem(*m_head);
1457 if (m == NULL) {
1458 *m_head = NULL;
1459 return (ENOBUFS);
1460 }
1461 *m_head = m;
1462 }
1463 ip_off = sizeof(struct ether_header);
1464 m = m_pullup(*m_head, ip_off);
1465 if (m == NULL) {
1466 *m_head = NULL;
1467 return (ENOBUFS);
1468 }
1469 eh = mtod(m, struct ether_header *);
1470 /* Check the existence of VLAN tag. */
1471 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1472 ip_off = sizeof(struct ether_vlan_header);
1473 m = m_pullup(m, ip_off);
1474 if (m == NULL) {
1475 *m_head = NULL;
1476 return (ENOBUFS);
1477 }
1478 }
1479 m = m_pullup(m, ip_off + sizeof(struct ip));
1480 if (m == NULL) {
1481 *m_head = NULL;
1482 return (ENOBUFS);
1483 }
1484 ip = (struct ip *)(mtod(m, char *) + ip_off);
1485 poff = ip_off + (ip->ip_hl << 2);
1486 m = m_pullup(m, poff + sizeof(struct tcphdr));
1487 if (m == NULL) {
1488 *m_head = NULL;
1489 return (ENOBUFS);
1490 }
1491 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1492 m = m_pullup(m, poff + (tcp->th_off << 2));
1493 if (m == NULL) {
1494 *m_head = NULL;
1495 return (ENOBUFS);
1496 }
1497
1498 /*
1499 * Since 82550/82551 doesn't modify IP length and pseudo
1500 * checksum in the first frame driver should compute it.
1501 */
1502 ip = (struct ip *)(mtod(m, char *) + ip_off);
1503 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1504 ip->ip_sum = 0;
1505 ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1506 (tcp->th_off << 2));
1507 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1508 htons(IPPROTO_TCP + (tcp->th_off << 2) +
1509 m->m_pkthdr.tso_segsz));
1510 /* Compute total TCP payload. */
1511 tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1512 tcp_payload -= tcp->th_off << 2;
1513 *m_head = m;
1514 } else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1515 /*
1516 * Deal with TCP/IP checksum offload. Note that
1517 * in order for TCP checksum offload to work,
1518 * the pseudo header checksum must have already
1519 * been computed and stored in the checksum field
1520 * in the TCP header. The stack should have
1521 * already done this for us.
1522 */
1523 txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1524 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1525 txp->tx_cb->ipcb_ip_schedule |= FXP_IPCB_TCP_PACKET;
1526
1527 #ifdef FXP_IP_CSUM_WAR
1528 /*
1529 * XXX The 82550 chip appears to have trouble
1530 * dealing with IP header checksums in very small
1531 * datagrams, namely fragments from 1 to 3 bytes
1532 * in size. For example, say you want to transmit
1533 * a UDP packet of 1473 bytes. The packet will be
1534 * fragmented over two IP datagrams, the latter
1535 * containing only one byte of data. The 82550 will
1536 * botch the header checksum on the 1-byte fragment.
1537 * As long as the datagram contains 4 or more bytes
1538 * of data, you're ok.
1539 *
1540 * The following code attempts to work around this
1541 * problem: if the datagram is less than 38 bytes
1542 * in size (14 bytes ether header, 20 bytes IP header,
1543 * plus 4 bytes of data), we punt and compute the IP
1544 * header checksum by hand. This workaround doesn't
1545 * work very well, however, since it can be fooled
1546 * by things like VLAN tags and IP options that make
1547 * the header sizes/offsets vary.
1548 */
1549
1550 if (m->m_pkthdr.csum_flags & CSUM_IP) {
1551 if (m->m_pkthdr.len < 38) {
1552 struct ip *ip;
1553 m->m_data += ETHER_HDR_LEN;
1554 ip = mtod(m, struct ip *);
1555 ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1556 m->m_data -= ETHER_HDR_LEN;
1557 m->m_pkthdr.csum_flags &= ~CSUM_IP;
1558 } else {
1559 txp->tx_cb->ipcb_ip_activation_high =
1560 FXP_IPCB_HARDWAREPARSING_ENABLE;
1561 txp->tx_cb->ipcb_ip_schedule |=
1562 FXP_IPCB_IP_CHECKSUM_ENABLE;
1563 }
1564 }
1565 #endif
1566 }
1567
1568 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1569 segs, &nseg, 0);
1570 if (error == EFBIG) {
1571 m = m_collapse(*m_head, M_NOWAIT, sc->maxtxseg);
1572 if (m == NULL) {
1573 m_freem(*m_head);
1574 *m_head = NULL;
1575 return (ENOMEM);
1576 }
1577 *m_head = m;
1578 error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1579 *m_head, segs, &nseg, 0);
1580 if (error != 0) {
1581 m_freem(*m_head);
1582 *m_head = NULL;
1583 return (ENOMEM);
1584 }
1585 } else if (error != 0)
1586 return (error);
1587 if (nseg == 0) {
1588 m_freem(*m_head);
1589 *m_head = NULL;
1590 return (EIO);
1591 }
1592
1593 KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1594 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1595
1596 cbp = txp->tx_cb;
1597 for (i = 0; i < nseg; i++) {
1598 /*
1599 * If this is an 82550/82551, then we're using extended
1600 * TxCBs _and_ we're using checksum offload. This means
1601 * that the TxCB is really an IPCB. One major difference
1602 * between the two is that with plain extended TxCBs,
1603 * the bottom half of the TxCB contains two entries from
1604 * the TBD array, whereas IPCBs contain just one entry:
1605 * one entry (8 bytes) has been sacrificed for the TCP/IP
1606 * checksum offload control bits. So to make things work
1607 * right, we have to start filling in the TBD array
1608 * starting from a different place depending on whether
1609 * the chip is an 82550/82551 or not.
1610 */
1611 if (sc->flags & FXP_FLAG_EXT_RFA) {
1612 cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1613 cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1614 } else {
1615 cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1616 cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1617 }
1618 }
1619 if (sc->flags & FXP_FLAG_EXT_RFA) {
1620 /* Configure dynamic TBD for 82550/82551. */
1621 cbp->tbd_number = 0xFF;
1622 cbp->tbd[nseg].tb_size |= htole32(0x8000);
1623 } else
1624 cbp->tbd_number = nseg;
1625 /* Configure TSO. */
1626 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1627 cbp->tbdtso.tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1628 cbp->tbd[1].tb_size |= htole32(tcp_payload << 16);
1629 cbp->ipcb_ip_schedule |= FXP_IPCB_LARGESEND_ENABLE |
1630 FXP_IPCB_IP_CHECKSUM_ENABLE |
1631 FXP_IPCB_TCP_PACKET |
1632 FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1633 }
1634 /* Configure VLAN hardware tag insertion. */
1635 if ((m->m_flags & M_VLANTAG) != 0) {
1636 cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1637 txp->tx_cb->ipcb_ip_activation_high |=
1638 FXP_IPCB_INSERTVLAN_ENABLE;
1639 }
1640
1641 txp->tx_mbuf = m;
1642 txp->tx_cb->cb_status = 0;
1643 txp->tx_cb->byte_count = 0;
1644 if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1645 txp->tx_cb->cb_command =
1646 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1647 FXP_CB_COMMAND_S);
1648 else
1649 txp->tx_cb->cb_command =
1650 htole16(sc->tx_cmd | FXP_CB_COMMAND_SF |
1651 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I);
1652 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1653 txp->tx_cb->tx_threshold = tx_threshold;
1654
1655 /*
1656 * Advance the end of list forward.
1657 */
1658 sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1659 sc->fxp_desc.tx_last = txp;
1660
1661 /*
1662 * Advance the beginning of the list forward if there are
1663 * no other packets queued (when nothing is queued, tx_first
1664 * sits on the last TxCB that was sent out).
1665 */
1666 if (sc->tx_queued == 0)
1667 sc->fxp_desc.tx_first = txp;
1668
1669 sc->tx_queued++;
1670
1671 return (0);
1672 }
1673
1674 #ifdef DEVICE_POLLING
1675 static poll_handler_t fxp_poll;
1676
1677 static int
fxp_poll(if_t ifp,enum poll_cmd cmd,int count)1678 fxp_poll(if_t ifp, enum poll_cmd cmd, int count)
1679 {
1680 struct fxp_softc *sc = if_getsoftc(ifp);
1681 uint8_t statack;
1682 int rx_npkts = 0;
1683
1684 FXP_LOCK(sc);
1685 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
1686 FXP_UNLOCK(sc);
1687 return (rx_npkts);
1688 }
1689
1690 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1691 FXP_SCB_STATACK_FR;
1692 if (cmd == POLL_AND_CHECK_STATUS) {
1693 uint8_t tmp;
1694
1695 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1696 if (tmp == 0xff || tmp == 0) {
1697 FXP_UNLOCK(sc);
1698 return (rx_npkts); /* nothing to do */
1699 }
1700 tmp &= ~statack;
1701 /* ack what we can */
1702 if (tmp != 0)
1703 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1704 statack |= tmp;
1705 }
1706 rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1707 FXP_UNLOCK(sc);
1708 return (rx_npkts);
1709 }
1710 #endif /* DEVICE_POLLING */
1711
1712 /*
1713 * Process interface interrupts.
1714 */
1715 static void
fxp_intr(void * xsc)1716 fxp_intr(void *xsc)
1717 {
1718 struct fxp_softc *sc = xsc;
1719 if_t ifp = sc->ifp;
1720 uint8_t statack;
1721
1722 FXP_LOCK(sc);
1723 if (sc->suspended) {
1724 FXP_UNLOCK(sc);
1725 return;
1726 }
1727
1728 #ifdef DEVICE_POLLING
1729 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1730 FXP_UNLOCK(sc);
1731 return;
1732 }
1733 #endif
1734 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1735 /*
1736 * It should not be possible to have all bits set; the
1737 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1738 * all bits are set, this may indicate that the card has
1739 * been physically ejected, so ignore it.
1740 */
1741 if (statack == 0xff) {
1742 FXP_UNLOCK(sc);
1743 return;
1744 }
1745
1746 /*
1747 * First ACK all the interrupts in this pass.
1748 */
1749 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1750 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1751 fxp_intr_body(sc, ifp, statack, -1);
1752 }
1753 FXP_UNLOCK(sc);
1754 }
1755
1756 static void
fxp_txeof(struct fxp_softc * sc)1757 fxp_txeof(struct fxp_softc *sc)
1758 {
1759 if_t ifp;
1760 struct fxp_tx *txp;
1761
1762 ifp = sc->ifp;
1763 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1764 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1765 for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1766 (le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1767 txp = txp->tx_next) {
1768 if (txp->tx_mbuf != NULL) {
1769 bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1770 BUS_DMASYNC_POSTWRITE);
1771 bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1772 m_freem(txp->tx_mbuf);
1773 txp->tx_mbuf = NULL;
1774 /* clear this to reset csum offload bits */
1775 txp->tx_cb->tbd[0].tb_addr = 0;
1776 }
1777 sc->tx_queued--;
1778 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1779 }
1780 sc->fxp_desc.tx_first = txp;
1781 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1782 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1783 if (sc->tx_queued == 0)
1784 sc->watchdog_timer = 0;
1785 }
1786
1787 static void
fxp_rxcsum(struct fxp_softc * sc,if_t ifp,struct mbuf * m,uint16_t status,int pos)1788 fxp_rxcsum(struct fxp_softc *sc, if_t ifp, struct mbuf *m,
1789 uint16_t status, int pos)
1790 {
1791 struct ether_header *eh;
1792 struct ip *ip;
1793 struct udphdr *uh;
1794 int32_t hlen, len, pktlen, temp32;
1795 uint16_t csum, *opts;
1796
1797 if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1798 if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1799 if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1800 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1801 if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1802 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1803 if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1804 (status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1805 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1806 CSUM_PSEUDO_HDR;
1807 m->m_pkthdr.csum_data = 0xffff;
1808 }
1809 }
1810 return;
1811 }
1812
1813 pktlen = m->m_pkthdr.len;
1814 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1815 return;
1816 eh = mtod(m, struct ether_header *);
1817 if (eh->ether_type != htons(ETHERTYPE_IP))
1818 return;
1819 ip = (struct ip *)(eh + 1);
1820 if (ip->ip_v != IPVERSION)
1821 return;
1822
1823 hlen = ip->ip_hl << 2;
1824 pktlen -= sizeof(struct ether_header);
1825 if (hlen < sizeof(struct ip))
1826 return;
1827 if (ntohs(ip->ip_len) < hlen)
1828 return;
1829 if (ntohs(ip->ip_len) != pktlen)
1830 return;
1831 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1832 return; /* can't handle fragmented packet */
1833
1834 switch (ip->ip_p) {
1835 case IPPROTO_TCP:
1836 if (pktlen < (hlen + sizeof(struct tcphdr)))
1837 return;
1838 break;
1839 case IPPROTO_UDP:
1840 if (pktlen < (hlen + sizeof(struct udphdr)))
1841 return;
1842 uh = (struct udphdr *)((caddr_t)ip + hlen);
1843 if (uh->uh_sum == 0)
1844 return; /* no checksum */
1845 break;
1846 default:
1847 return;
1848 }
1849 /* Extract computed checksum. */
1850 csum = be16dec(mtod(m, char *) + pos);
1851 /* checksum fixup for IP options */
1852 len = hlen - sizeof(struct ip);
1853 if (len > 0) {
1854 opts = (uint16_t *)(ip + 1);
1855 for (; len > 0; len -= sizeof(uint16_t), opts++) {
1856 temp32 = csum - *opts;
1857 temp32 = (temp32 >> 16) + (temp32 & 65535);
1858 csum = temp32 & 65535;
1859 }
1860 }
1861 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
1862 m->m_pkthdr.csum_data = csum;
1863 }
1864
1865 static int
fxp_intr_body(struct fxp_softc * sc,if_t ifp,uint8_t statack,int count)1866 fxp_intr_body(struct fxp_softc *sc, if_t ifp, uint8_t statack,
1867 int count)
1868 {
1869 struct mbuf *m;
1870 struct fxp_rx *rxp;
1871 struct fxp_rfa *rfa;
1872 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1873 int rx_npkts;
1874 uint16_t status;
1875
1876 rx_npkts = 0;
1877 FXP_LOCK_ASSERT(sc, MA_OWNED);
1878
1879 if (rnr)
1880 sc->rnr++;
1881 #ifdef DEVICE_POLLING
1882 /* Pick up a deferred RNR condition if `count' ran out last time. */
1883 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1884 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1885 rnr = 1;
1886 }
1887 #endif
1888
1889 /*
1890 * Free any finished transmit mbuf chains.
1891 *
1892 * Handle the CNA event likt a CXTNO event. It used to
1893 * be that this event (control unit not ready) was not
1894 * encountered, but it is now with the SMPng modifications.
1895 * The exact sequence of events that occur when the interface
1896 * is brought up are different now, and if this event
1897 * goes unhandled, the configuration/rxfilter setup sequence
1898 * can stall for several seconds. The result is that no
1899 * packets go out onto the wire for about 5 to 10 seconds
1900 * after the interface is ifconfig'ed for the first time.
1901 */
1902 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA))
1903 fxp_txeof(sc);
1904
1905 /*
1906 * Try to start more packets transmitting.
1907 */
1908 if (!if_sendq_empty(ifp))
1909 fxp_start_body(ifp);
1910
1911 /*
1912 * Just return if nothing happened on the receive side.
1913 */
1914 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1915 return (rx_npkts);
1916
1917 /*
1918 * Process receiver interrupts. If a no-resource (RNR)
1919 * condition exists, get whatever packets we can and
1920 * re-start the receiver.
1921 *
1922 * When using polling, we do not process the list to completion,
1923 * so when we get an RNR interrupt we must defer the restart
1924 * until we hit the last buffer with the C bit set.
1925 * If we run out of cycles and rfa_headm has the C bit set,
1926 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1927 * that the info will be used in the subsequent polling cycle.
1928 */
1929 for (;;) {
1930 rxp = sc->fxp_desc.rx_head;
1931 m = rxp->rx_mbuf;
1932 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1933 RFA_ALIGNMENT_FUDGE);
1934 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1935 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1936
1937 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1938 if (count >= 0 && count-- == 0) {
1939 if (rnr) {
1940 /* Defer RNR processing until the next time. */
1941 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1942 rnr = 0;
1943 }
1944 break;
1945 }
1946 #endif /* DEVICE_POLLING */
1947
1948 status = le16toh(rfa->rfa_status);
1949 if ((status & FXP_RFA_STATUS_C) == 0)
1950 break;
1951
1952 if ((status & FXP_RFA_STATUS_RNR) != 0)
1953 rnr++;
1954 /*
1955 * Advance head forward.
1956 */
1957 sc->fxp_desc.rx_head = rxp->rx_next;
1958
1959 /*
1960 * Add a new buffer to the receive chain.
1961 * If this fails, the old buffer is recycled
1962 * instead.
1963 */
1964 if (fxp_new_rfabuf(sc, rxp) == 0) {
1965 int total_len;
1966
1967 /*
1968 * Fetch packet length (the top 2 bits of
1969 * actual_size are flags set by the controller
1970 * upon completion), and drop the packet in case
1971 * of bogus length or CRC errors.
1972 */
1973 total_len = le16toh(rfa->actual_size) & 0x3fff;
1974 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1975 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
1976 /* Adjust for appended checksum bytes. */
1977 total_len -= 2;
1978 }
1979 if (total_len < (int)sizeof(struct ether_header) ||
1980 total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1981 sc->rfa_size) ||
1982 status & (FXP_RFA_STATUS_CRC |
1983 FXP_RFA_STATUS_ALIGN | FXP_RFA_STATUS_OVERRUN)) {
1984 m_freem(m);
1985 fxp_add_rfabuf(sc, rxp);
1986 continue;
1987 }
1988
1989 m->m_pkthdr.len = m->m_len = total_len;
1990 if_setrcvif(m, ifp);
1991
1992 /* Do IP checksum checking. */
1993 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1994 fxp_rxcsum(sc, ifp, m, status, total_len);
1995 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
1996 (status & FXP_RFA_STATUS_VLAN) != 0) {
1997 m->m_pkthdr.ether_vtag =
1998 ntohs(rfa->rfax_vlan_id);
1999 m->m_flags |= M_VLANTAG;
2000 }
2001 /*
2002 * Drop locks before calling if_input() since it
2003 * may re-enter fxp_start() in the netisr case.
2004 * This would result in a lock reversal. Better
2005 * performance might be obtained by chaining all
2006 * packets received, dropping the lock, and then
2007 * calling if_input() on each one.
2008 */
2009 FXP_UNLOCK(sc);
2010 if_input(ifp, m);
2011 FXP_LOCK(sc);
2012 rx_npkts++;
2013 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2014 return (rx_npkts);
2015 } else {
2016 /* Reuse RFA and loaded DMA map. */
2017 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2018 fxp_discard_rfabuf(sc, rxp);
2019 }
2020 fxp_add_rfabuf(sc, rxp);
2021 }
2022 if (rnr) {
2023 fxp_scb_wait(sc);
2024 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
2025 sc->fxp_desc.rx_head->rx_addr);
2026 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2027 }
2028 return (rx_npkts);
2029 }
2030
2031 static void
fxp_update_stats(struct fxp_softc * sc)2032 fxp_update_stats(struct fxp_softc *sc)
2033 {
2034 if_t ifp = sc->ifp;
2035 struct fxp_stats *sp = sc->fxp_stats;
2036 struct fxp_hwstats *hsp;
2037 uint32_t *status;
2038
2039 FXP_LOCK_ASSERT(sc, MA_OWNED);
2040
2041 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2042 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2043 /* Update statistical counters. */
2044 if (sc->revision >= FXP_REV_82559_A0)
2045 status = &sp->completion_status;
2046 else if (sc->revision >= FXP_REV_82558_A4)
2047 status = (uint32_t *)&sp->tx_tco;
2048 else
2049 status = &sp->tx_pause;
2050 if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2051 hsp = &sc->fxp_hwstats;
2052 hsp->tx_good += le32toh(sp->tx_good);
2053 hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2054 hsp->tx_latecols += le32toh(sp->tx_latecols);
2055 hsp->tx_underruns += le32toh(sp->tx_underruns);
2056 hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2057 hsp->tx_deffered += le32toh(sp->tx_deffered);
2058 hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2059 hsp->tx_multiple_collisions +=
2060 le32toh(sp->tx_multiple_collisions);
2061 hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2062 hsp->rx_good += le32toh(sp->rx_good);
2063 hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2064 hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2065 hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2066 hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2067 hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2068 hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2069 hsp->tx_pause += le32toh(sp->tx_pause);
2070 hsp->rx_pause += le32toh(sp->rx_pause);
2071 hsp->rx_controls += le32toh(sp->rx_controls);
2072 hsp->tx_tco += le16toh(sp->tx_tco);
2073 hsp->rx_tco += le16toh(sp->rx_tco);
2074
2075 if_inc_counter(ifp, IFCOUNTER_OPACKETS, le32toh(sp->tx_good));
2076 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2077 le32toh(sp->tx_total_collisions));
2078 if (sp->rx_good) {
2079 if_inc_counter(ifp, IFCOUNTER_IPACKETS,
2080 le32toh(sp->rx_good));
2081 sc->rx_idle_secs = 0;
2082 } else if (sc->flags & FXP_FLAG_RXBUG) {
2083 /*
2084 * Receiver's been idle for another second.
2085 */
2086 sc->rx_idle_secs++;
2087 }
2088 if_inc_counter(ifp, IFCOUNTER_IERRORS,
2089 le32toh(sp->rx_crc_errors) +
2090 le32toh(sp->rx_alignment_errors) +
2091 le32toh(sp->rx_rnr_errors) +
2092 le32toh(sp->rx_overrun_errors));
2093 /*
2094 * If any transmit underruns occurred, bump up the transmit
2095 * threshold by another 512 bytes (64 * 8).
2096 */
2097 if (sp->tx_underruns) {
2098 if_inc_counter(ifp, IFCOUNTER_OERRORS,
2099 le32toh(sp->tx_underruns));
2100 if (tx_threshold < 192)
2101 tx_threshold += 64;
2102 }
2103 *status = 0;
2104 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2105 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2106 }
2107 }
2108
2109 /*
2110 * Update packet in/out/collision statistics. The i82557 doesn't
2111 * allow you to access these counters without doing a fairly
2112 * expensive DMA to get _all_ of the statistics it maintains, so
2113 * we do this operation here only once per second. The statistics
2114 * counters in the kernel are updated from the previous dump-stats
2115 * DMA and then a new dump-stats DMA is started. The on-chip
2116 * counters are zeroed when the DMA completes. If we can't start
2117 * the DMA immediately, we don't wait - we just prepare to read
2118 * them again next time.
2119 */
2120 static void
fxp_tick(void * xsc)2121 fxp_tick(void *xsc)
2122 {
2123 struct fxp_softc *sc = xsc;
2124 if_t ifp = sc->ifp;
2125
2126 FXP_LOCK_ASSERT(sc, MA_OWNED);
2127
2128 /* Update statistical counters. */
2129 fxp_update_stats(sc);
2130
2131 /*
2132 * Release any xmit buffers that have completed DMA. This isn't
2133 * strictly necessary to do here, but it's advantagous for mbufs
2134 * with external storage to be released in a timely manner rather
2135 * than being defered for a potentially long time. This limits
2136 * the delay to a maximum of one second.
2137 */
2138 fxp_txeof(sc);
2139
2140 /*
2141 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2142 * then assume the receiver has locked up and attempt to clear
2143 * the condition by reprogramming the multicast filter. This is
2144 * a work-around for a bug in the 82557 where the receiver locks
2145 * up if it gets certain types of garbage in the synchronization
2146 * bits prior to the packet header. This bug is supposed to only
2147 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
2148 * mode as well (perhaps due to a 10/100 speed transition).
2149 */
2150 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2151 sc->rx_idle_secs = 0;
2152 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2153 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2154 fxp_init_body(sc, 1);
2155 }
2156 return;
2157 }
2158 /*
2159 * If there is no pending command, start another stats
2160 * dump. Otherwise punt for now.
2161 */
2162 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2163 /*
2164 * Start another stats dump.
2165 */
2166 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2167 }
2168 if (sc->miibus != NULL)
2169 mii_tick(device_get_softc(sc->miibus));
2170
2171 /*
2172 * Check that chip hasn't hung.
2173 */
2174 fxp_watchdog(sc);
2175
2176 /*
2177 * Schedule another timeout one second from now.
2178 */
2179 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2180 }
2181
2182 /*
2183 * Stop the interface. Cancels the statistics updater and resets
2184 * the interface.
2185 */
2186 static void
fxp_stop(struct fxp_softc * sc)2187 fxp_stop(struct fxp_softc *sc)
2188 {
2189 if_t ifp = sc->ifp;
2190 struct fxp_tx *txp;
2191 int i;
2192
2193 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2194 sc->watchdog_timer = 0;
2195
2196 /*
2197 * Cancel stats updater.
2198 */
2199 callout_stop(&sc->stat_ch);
2200
2201 /*
2202 * Preserve PCI configuration, configure, IA/multicast
2203 * setup and put RU and CU into idle state.
2204 */
2205 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2206 DELAY(50);
2207 /* Disable interrupts. */
2208 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2209
2210 fxp_update_stats(sc);
2211
2212 /*
2213 * Release any xmit buffers.
2214 */
2215 txp = sc->fxp_desc.tx_list;
2216 for (i = 0; i < FXP_NTXCB; i++) {
2217 if (txp[i].tx_mbuf != NULL) {
2218 bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2219 BUS_DMASYNC_POSTWRITE);
2220 bus_dmamap_unload(sc->fxp_txmtag, txp[i].tx_map);
2221 m_freem(txp[i].tx_mbuf);
2222 txp[i].tx_mbuf = NULL;
2223 /* clear this to reset csum offload bits */
2224 txp[i].tx_cb->tbd[0].tb_addr = 0;
2225 }
2226 }
2227 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2228 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2229 sc->tx_queued = 0;
2230 }
2231
2232 /*
2233 * Watchdog/transmission transmit timeout handler. Called when a
2234 * transmission is started on the interface, but no interrupt is
2235 * received before the timeout. This usually indicates that the
2236 * card has wedged for some reason.
2237 */
2238 static void
fxp_watchdog(struct fxp_softc * sc)2239 fxp_watchdog(struct fxp_softc *sc)
2240 {
2241 if_t ifp = sc->ifp;
2242
2243 FXP_LOCK_ASSERT(sc, MA_OWNED);
2244
2245 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
2246 return;
2247
2248 device_printf(sc->dev, "device timeout\n");
2249 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2250
2251 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2252 fxp_init_body(sc, 1);
2253 }
2254
2255 /*
2256 * Acquire locks and then call the real initialization function. This
2257 * is necessary because ether_ioctl() calls if_init() and this would
2258 * result in mutex recursion if the mutex was held.
2259 */
2260 static void
fxp_init(void * xsc)2261 fxp_init(void *xsc)
2262 {
2263 struct fxp_softc *sc = xsc;
2264
2265 FXP_LOCK(sc);
2266 fxp_init_body(sc, 1);
2267 FXP_UNLOCK(sc);
2268 }
2269
2270 /*
2271 * Perform device initialization. This routine must be called with the
2272 * softc lock held.
2273 */
2274 static void
fxp_init_body(struct fxp_softc * sc,int setmedia)2275 fxp_init_body(struct fxp_softc *sc, int setmedia)
2276 {
2277 if_t ifp = sc->ifp;
2278 struct mii_data *mii;
2279 struct fxp_cb_config *cbp;
2280 struct fxp_cb_ias *cb_ias;
2281 struct fxp_cb_tx *tcbp;
2282 struct fxp_tx *txp;
2283 int i, prm;
2284
2285 FXP_LOCK_ASSERT(sc, MA_OWNED);
2286
2287 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2288 return;
2289
2290 /*
2291 * Cancel any pending I/O
2292 */
2293 fxp_stop(sc);
2294
2295 /*
2296 * Issue software reset, which also unloads the microcode.
2297 */
2298 sc->flags &= ~FXP_FLAG_UCODE;
2299 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2300 DELAY(50);
2301
2302 prm = (if_getflags(ifp) & IFF_PROMISC) ? 1 : 0;
2303
2304 /*
2305 * Initialize base of CBL and RFA memory. Loading with zero
2306 * sets it up for regular linear addressing.
2307 */
2308 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2309 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2310
2311 fxp_scb_wait(sc);
2312 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2313
2314 /*
2315 * Initialize base of dump-stats buffer.
2316 */
2317 fxp_scb_wait(sc);
2318 bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2319 bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2320 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2321 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2322 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2323
2324 /*
2325 * Attempt to load microcode if requested.
2326 * For ICH based controllers do not load microcode.
2327 */
2328 if (sc->ident->ich == 0) {
2329 if (if_getflags(ifp) & IFF_LINK0 &&
2330 (sc->flags & FXP_FLAG_UCODE) == 0)
2331 fxp_load_ucode(sc);
2332 }
2333
2334 /*
2335 * Set IFF_ALLMULTI status. It's needed in configure action
2336 * command.
2337 */
2338 fxp_mc_addrs(sc);
2339
2340 /*
2341 * We temporarily use memory that contains the TxCB list to
2342 * construct the config CB. The TxCB list memory is rebuilt
2343 * later.
2344 */
2345 cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2346
2347 /*
2348 * This bcopy is kind of disgusting, but there are a bunch of must be
2349 * zero and must be one bits in this structure and this is the easiest
2350 * way to initialize them all to proper values.
2351 */
2352 bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2353
2354 cbp->cb_status = 0;
2355 cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG |
2356 FXP_CB_COMMAND_EL);
2357 cbp->link_addr = 0xffffffff; /* (no) next command */
2358 cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2359 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2360 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2361 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2362 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2363 cbp->type_enable = 0; /* actually reserved */
2364 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2365 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2366 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2367 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2368 cbp->dma_mbce = 0; /* (disable) dma max counters */
2369 cbp->late_scb = 0; /* (don't) defer SCB update */
2370 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2371 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2372 cbp->ci_int = 1; /* interrupt on CU idle */
2373 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2374 cbp->ext_stats_dis = 1; /* disable extended counters */
2375 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2376 cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2377 cbp->disc_short_rx = !prm; /* discard short packets */
2378 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2379 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2380 cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2381 cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2382 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2383 cbp->csma_dis = 0; /* (don't) disable link */
2384 cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2385 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) ? 1 : 0;
2386 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2387 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2388 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2389 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2390 cbp->nsai = 1; /* (don't) disable source addr insert */
2391 cbp->preamble_length = 2; /* (7 byte) preamble */
2392 cbp->loopback = 0; /* (don't) loopback */
2393 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2394 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2395 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2396 cbp->promiscuous = prm; /* promiscuous mode */
2397 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2398 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2399 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2400 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2401 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2402
2403 cbp->stripping = !prm; /* truncate rx packet to byte count */
2404 cbp->padding = 1; /* (do) pad short tx packets */
2405 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2406 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2407 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2408 cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2409 cbp->force_fdx = 0; /* (don't) force full duplex */
2410 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2411 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2412 cbp->mc_all = if_getflags(ifp) & IFF_ALLMULTI ? 1 : prm;
2413 cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2414 cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2415 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2416
2417 if (sc->revision == FXP_REV_82557) {
2418 /*
2419 * The 82557 has no hardware flow control, the values
2420 * below are the defaults for the chip.
2421 */
2422 cbp->fc_delay_lsb = 0;
2423 cbp->fc_delay_msb = 0x40;
2424 cbp->pri_fc_thresh = 3;
2425 cbp->tx_fc_dis = 0;
2426 cbp->rx_fc_restop = 0;
2427 cbp->rx_fc_restart = 0;
2428 cbp->fc_filter = 0;
2429 cbp->pri_fc_loc = 1;
2430 } else {
2431 /* Set pause RX FIFO threshold to 1KB. */
2432 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);
2433 /* Set pause time. */
2434 cbp->fc_delay_lsb = 0xff;
2435 cbp->fc_delay_msb = 0xff;
2436 cbp->pri_fc_thresh = 3;
2437 mii = device_get_softc(sc->miibus);
2438 if ((IFM_OPTIONS(mii->mii_media_active) &
2439 IFM_ETH_TXPAUSE) != 0)
2440 /* enable transmit FC */
2441 cbp->tx_fc_dis = 0;
2442 else
2443 /* disable transmit FC */
2444 cbp->tx_fc_dis = 1;
2445 if ((IFM_OPTIONS(mii->mii_media_active) &
2446 IFM_ETH_RXPAUSE) != 0) {
2447 /* enable FC restart/restop frames */
2448 cbp->rx_fc_restart = 1;
2449 cbp->rx_fc_restop = 1;
2450 } else {
2451 /* disable FC restart/restop frames */
2452 cbp->rx_fc_restart = 0;
2453 cbp->rx_fc_restop = 0;
2454 }
2455 cbp->fc_filter = !prm; /* drop FC frames to host */
2456 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2457 }
2458
2459 /* Enable 82558 and 82559 extended statistics functionality. */
2460 if (sc->revision >= FXP_REV_82558_A4) {
2461 if (sc->revision >= FXP_REV_82559_A0) {
2462 /*
2463 * Extend configuration table size to 32
2464 * to include TCO configuration.
2465 */
2466 cbp->byte_count = 32;
2467 cbp->ext_stats_dis = 1;
2468 /* Enable TCO stats. */
2469 cbp->tno_int_or_tco_en = 1;
2470 cbp->gamla_rx = 1;
2471 } else
2472 cbp->ext_stats_dis = 0;
2473 }
2474
2475 /*
2476 * Start the config command/DMA.
2477 */
2478 fxp_scb_wait(sc);
2479 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2480 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2481 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2482 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2483 /* ...and wait for it to complete. */
2484 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2485
2486 /*
2487 * Now initialize the station address. Temporarily use the TxCB
2488 * memory area like we did above for the config CB.
2489 */
2490 cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2491 cb_ias->cb_status = 0;
2492 cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL);
2493 cb_ias->link_addr = 0xffffffff;
2494 bcopy(if_getlladdr(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2495
2496 /*
2497 * Start the IAS (Individual Address Setup) command/DMA.
2498 */
2499 fxp_scb_wait(sc);
2500 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2501 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2502 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2503 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2504 /* ...and wait for it to complete. */
2505 fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2506
2507 /*
2508 * Initialize the multicast address list.
2509 */
2510 fxp_mc_setup(sc);
2511
2512 /*
2513 * Initialize transmit control block (TxCB) list.
2514 */
2515 txp = sc->fxp_desc.tx_list;
2516 tcbp = sc->fxp_desc.cbl_list;
2517 bzero(tcbp, FXP_TXCB_SZ);
2518 for (i = 0; i < FXP_NTXCB; i++) {
2519 txp[i].tx_mbuf = NULL;
2520 tcbp[i].cb_status = htole16(FXP_CB_STATUS_C | FXP_CB_STATUS_OK);
2521 tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2522 tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2523 (((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2524 if (sc->flags & FXP_FLAG_EXT_TXCB)
2525 tcbp[i].tbd_array_addr =
2526 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2527 else
2528 tcbp[i].tbd_array_addr =
2529 htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2530 txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2531 }
2532 /*
2533 * Set the suspend flag on the first TxCB and start the control
2534 * unit. It will execute the NOP and then suspend.
2535 */
2536 tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S);
2537 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2538 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2539 sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2540 sc->tx_queued = 1;
2541
2542 fxp_scb_wait(sc);
2543 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2544 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2545
2546 /*
2547 * Initialize receiver buffer area - RFA.
2548 */
2549 fxp_scb_wait(sc);
2550 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2551 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2552
2553 if (sc->miibus != NULL && setmedia != 0)
2554 mii_mediachg(device_get_softc(sc->miibus));
2555
2556 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
2557
2558 /*
2559 * Enable interrupts.
2560 */
2561 #ifdef DEVICE_POLLING
2562 /*
2563 * ... but only do that if we are not polling. And because (presumably)
2564 * the default is interrupts on, we need to disable them explicitly!
2565 */
2566 if (if_getcapenable(ifp) & IFCAP_POLLING )
2567 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2568 else
2569 #endif /* DEVICE_POLLING */
2570 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2571
2572 /*
2573 * Start stats updater.
2574 */
2575 callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2576 }
2577
2578 static int
fxp_serial_ifmedia_upd(if_t ifp)2579 fxp_serial_ifmedia_upd(if_t ifp)
2580 {
2581
2582 return (0);
2583 }
2584
2585 static void
fxp_serial_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2586 fxp_serial_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2587 {
2588
2589 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
2590 }
2591
2592 /*
2593 * Change media according to request.
2594 */
2595 static int
fxp_ifmedia_upd(if_t ifp)2596 fxp_ifmedia_upd(if_t ifp)
2597 {
2598 struct fxp_softc *sc = if_getsoftc(ifp);
2599 struct mii_data *mii;
2600 struct mii_softc *miisc;
2601
2602 mii = device_get_softc(sc->miibus);
2603 FXP_LOCK(sc);
2604 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2605 PHY_RESET(miisc);
2606 mii_mediachg(mii);
2607 FXP_UNLOCK(sc);
2608 return (0);
2609 }
2610
2611 /*
2612 * Notify the world which media we're using.
2613 */
2614 static void
fxp_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2615 fxp_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2616 {
2617 struct fxp_softc *sc = if_getsoftc(ifp);
2618 struct mii_data *mii;
2619
2620 mii = device_get_softc(sc->miibus);
2621 FXP_LOCK(sc);
2622 mii_pollstat(mii);
2623 ifmr->ifm_active = mii->mii_media_active;
2624 ifmr->ifm_status = mii->mii_media_status;
2625 FXP_UNLOCK(sc);
2626 }
2627
2628 /*
2629 * Add a buffer to the end of the RFA buffer list.
2630 * Return 0 if successful, 1 for failure. A failure results in
2631 * reusing the RFA buffer.
2632 * The RFA struct is stuck at the beginning of mbuf cluster and the
2633 * data pointer is fixed up to point just past it.
2634 */
2635 static int
fxp_new_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2636 fxp_new_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2637 {
2638 struct mbuf *m;
2639 struct fxp_rfa *rfa;
2640 bus_dmamap_t tmp_map;
2641 int error;
2642
2643 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2644 if (m == NULL)
2645 return (ENOBUFS);
2646
2647 /*
2648 * Move the data pointer up so that the incoming data packet
2649 * will be 32-bit aligned.
2650 */
2651 m->m_data += RFA_ALIGNMENT_FUDGE;
2652
2653 /*
2654 * Get a pointer to the base of the mbuf cluster and move
2655 * data start past it.
2656 */
2657 rfa = mtod(m, struct fxp_rfa *);
2658 m->m_data += sc->rfa_size;
2659 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2660
2661 rfa->rfa_status = 0;
2662 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2663 rfa->actual_size = 0;
2664 m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2665 sc->rfa_size;
2666
2667 /*
2668 * Initialize the rest of the RFA. Note that since the RFA
2669 * is misaligned, we cannot store values directly. We're thus
2670 * using the le32enc() function which handles endianness and
2671 * is also alignment-safe.
2672 */
2673 le32enc(&rfa->link_addr, 0xffffffff);
2674 le32enc(&rfa->rbd_addr, 0xffffffff);
2675
2676 /* Map the RFA into DMA memory. */
2677 error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2678 MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2679 &rxp->rx_addr, BUS_DMA_NOWAIT);
2680 if (error) {
2681 m_freem(m);
2682 return (error);
2683 }
2684
2685 if (rxp->rx_mbuf != NULL)
2686 bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2687 tmp_map = sc->spare_map;
2688 sc->spare_map = rxp->rx_map;
2689 rxp->rx_map = tmp_map;
2690 rxp->rx_mbuf = m;
2691
2692 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2693 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2694 return (0);
2695 }
2696
2697 static void
fxp_add_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2698 fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2699 {
2700 struct fxp_rfa *p_rfa;
2701 struct fxp_rx *p_rx;
2702
2703 /*
2704 * If there are other buffers already on the list, attach this
2705 * one to the end by fixing up the tail to point to this one.
2706 */
2707 if (sc->fxp_desc.rx_head != NULL) {
2708 p_rx = sc->fxp_desc.rx_tail;
2709 p_rfa = (struct fxp_rfa *)
2710 (p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2711 p_rx->rx_next = rxp;
2712 le32enc(&p_rfa->link_addr, rxp->rx_addr);
2713 p_rfa->rfa_control = 0;
2714 bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2715 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2716 } else {
2717 rxp->rx_next = NULL;
2718 sc->fxp_desc.rx_head = rxp;
2719 }
2720 sc->fxp_desc.rx_tail = rxp;
2721 }
2722
2723 static void
fxp_discard_rfabuf(struct fxp_softc * sc,struct fxp_rx * rxp)2724 fxp_discard_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp)
2725 {
2726 struct mbuf *m;
2727 struct fxp_rfa *rfa;
2728
2729 m = rxp->rx_mbuf;
2730 m->m_data = m->m_ext.ext_buf;
2731 /*
2732 * Move the data pointer up so that the incoming data packet
2733 * will be 32-bit aligned.
2734 */
2735 m->m_data += RFA_ALIGNMENT_FUDGE;
2736
2737 /*
2738 * Get a pointer to the base of the mbuf cluster and move
2739 * data start past it.
2740 */
2741 rfa = mtod(m, struct fxp_rfa *);
2742 m->m_data += sc->rfa_size;
2743 rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2744
2745 rfa->rfa_status = 0;
2746 rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2747 rfa->actual_size = 0;
2748
2749 /*
2750 * Initialize the rest of the RFA. Note that since the RFA
2751 * is misaligned, we cannot store values directly. We're thus
2752 * using the le32enc() function which handles endianness and
2753 * is also alignment-safe.
2754 */
2755 le32enc(&rfa->link_addr, 0xffffffff);
2756 le32enc(&rfa->rbd_addr, 0xffffffff);
2757
2758 bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2759 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2760 }
2761
2762 static int
fxp_miibus_readreg(device_t dev,int phy,int reg)2763 fxp_miibus_readreg(device_t dev, int phy, int reg)
2764 {
2765 struct fxp_softc *sc = device_get_softc(dev);
2766 int count = 10000;
2767 int value;
2768
2769 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2770 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2771
2772 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2773 && count--)
2774 DELAY(10);
2775
2776 if (count <= 0)
2777 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2778
2779 return (value & 0xffff);
2780 }
2781
2782 static int
fxp_miibus_writereg(device_t dev,int phy,int reg,int value)2783 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2784 {
2785 struct fxp_softc *sc = device_get_softc(dev);
2786 int count = 10000;
2787
2788 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2789 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2790 (value & 0xffff));
2791
2792 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2793 count--)
2794 DELAY(10);
2795
2796 if (count <= 0)
2797 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2798 return (0);
2799 }
2800
2801 static void
fxp_miibus_statchg(device_t dev)2802 fxp_miibus_statchg(device_t dev)
2803 {
2804 struct fxp_softc *sc;
2805 struct mii_data *mii;
2806 if_t ifp;
2807
2808 sc = device_get_softc(dev);
2809 mii = device_get_softc(sc->miibus);
2810 ifp = sc->ifp;
2811 if (mii == NULL || ifp == (void *)NULL ||
2812 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 ||
2813 (mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) !=
2814 (IFM_AVALID | IFM_ACTIVE))
2815 return;
2816
2817 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T &&
2818 sc->flags & FXP_FLAG_CU_RESUME_BUG)
2819 sc->cu_resume_bug = 1;
2820 else
2821 sc->cu_resume_bug = 0;
2822 /*
2823 * Call fxp_init_body in order to adjust the flow control settings.
2824 * Note that the 82557 doesn't support hardware flow control.
2825 */
2826 if (sc->revision == FXP_REV_82557)
2827 return;
2828 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2829 fxp_init_body(sc, 0);
2830 }
2831
2832 static int
fxp_ioctl(if_t ifp,u_long command,caddr_t data)2833 fxp_ioctl(if_t ifp, u_long command, caddr_t data)
2834 {
2835 struct fxp_softc *sc = if_getsoftc(ifp);
2836 struct ifreq *ifr = (struct ifreq *)data;
2837 struct mii_data *mii;
2838 int flag, mask, error = 0, reinit;
2839
2840 switch (command) {
2841 case SIOCSIFFLAGS:
2842 FXP_LOCK(sc);
2843 /*
2844 * If interface is marked up and not running, then start it.
2845 * If it is marked down and running, stop it.
2846 * XXX If it's up then re-initialize it. This is so flags
2847 * such as IFF_PROMISC are handled.
2848 */
2849 if (if_getflags(ifp) & IFF_UP) {
2850 if (((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) &&
2851 ((if_getflags(ifp) ^ sc->if_flags) &
2852 (IFF_PROMISC | IFF_ALLMULTI | IFF_LINK0)) != 0) {
2853 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2854 fxp_init_body(sc, 0);
2855 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
2856 fxp_init_body(sc, 1);
2857 } else {
2858 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2859 fxp_stop(sc);
2860 }
2861 sc->if_flags = if_getflags(ifp);
2862 FXP_UNLOCK(sc);
2863 break;
2864
2865 case SIOCADDMULTI:
2866 case SIOCDELMULTI:
2867 FXP_LOCK(sc);
2868 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2869 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2870 fxp_init_body(sc, 0);
2871 }
2872 FXP_UNLOCK(sc);
2873 break;
2874
2875 case SIOCSIFMEDIA:
2876 case SIOCGIFMEDIA:
2877 if (sc->miibus != NULL) {
2878 mii = device_get_softc(sc->miibus);
2879 error = ifmedia_ioctl(ifp, ifr,
2880 &mii->mii_media, command);
2881 } else {
2882 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2883 }
2884 break;
2885
2886 case SIOCSIFCAP:
2887 reinit = 0;
2888 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
2889 #ifdef DEVICE_POLLING
2890 if (mask & IFCAP_POLLING) {
2891 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2892 error = ether_poll_register(fxp_poll, ifp);
2893 if (error)
2894 return(error);
2895 FXP_LOCK(sc);
2896 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2897 FXP_SCB_INTR_DISABLE);
2898 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
2899 FXP_UNLOCK(sc);
2900 } else {
2901 error = ether_poll_deregister(ifp);
2902 /* Enable interrupts in any case */
2903 FXP_LOCK(sc);
2904 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2905 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
2906 FXP_UNLOCK(sc);
2907 }
2908 }
2909 #endif
2910 FXP_LOCK(sc);
2911 if ((mask & IFCAP_TXCSUM) != 0 &&
2912 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
2913 if_togglecapenable(ifp, IFCAP_TXCSUM);
2914 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
2915 if_sethwassistbits(ifp, FXP_CSUM_FEATURES, 0);
2916 else
2917 if_sethwassistbits(ifp, 0, FXP_CSUM_FEATURES);
2918 }
2919 if ((mask & IFCAP_RXCSUM) != 0 &&
2920 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
2921 if_togglecapenable(ifp, IFCAP_RXCSUM);
2922 if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2923 reinit++;
2924 }
2925 if ((mask & IFCAP_TSO4) != 0 &&
2926 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
2927 if_togglecapenable(ifp, IFCAP_TSO4);
2928 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
2929 if_sethwassistbits(ifp, CSUM_TSO, 0);
2930 else
2931 if_sethwassistbits(ifp, 0, CSUM_TSO);
2932 }
2933 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2934 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
2935 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2936 if ((mask & IFCAP_VLAN_MTU) != 0 &&
2937 (if_getcapabilities(ifp) & IFCAP_VLAN_MTU) != 0) {
2938 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
2939 if (sc->revision != FXP_REV_82557)
2940 flag = FXP_FLAG_LONG_PKT_EN;
2941 else /* a hack to get long frames on the old chip */
2942 flag = FXP_FLAG_SAVE_BAD;
2943 sc->flags ^= flag;
2944 if (if_getflags(ifp) & IFF_UP)
2945 reinit++;
2946 }
2947 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2948 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2949 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2950 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2951 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
2952 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2953 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2954 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2955 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2956 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
2957 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO |
2958 IFCAP_VLAN_HWCSUM);
2959 reinit++;
2960 }
2961 if (reinit > 0 &&
2962 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2963 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2964 fxp_init_body(sc, 0);
2965 }
2966 FXP_UNLOCK(sc);
2967 if_vlancap(ifp);
2968 break;
2969
2970 default:
2971 error = ether_ioctl(ifp, command, data);
2972 }
2973 return (error);
2974 }
2975
2976 static u_int
fxp_setup_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)2977 fxp_setup_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2978 {
2979 struct fxp_softc *sc = arg;
2980 struct fxp_cb_mcs *mcsp = sc->mcsp;
2981
2982 if (mcsp->mc_cnt < MAXMCADDR)
2983 bcopy(LLADDR(sdl), mcsp->mc_addr[mcsp->mc_cnt * ETHER_ADDR_LEN],
2984 ETHER_ADDR_LEN);
2985 mcsp->mc_cnt++;
2986 return (1);
2987 }
2988
2989 /*
2990 * Fill in the multicast address list and return number of entries.
2991 */
2992 static void
fxp_mc_addrs(struct fxp_softc * sc)2993 fxp_mc_addrs(struct fxp_softc *sc)
2994 {
2995 struct fxp_cb_mcs *mcsp = sc->mcsp;
2996 if_t ifp = sc->ifp;
2997
2998 if ((if_getflags(ifp) & IFF_ALLMULTI) == 0) {
2999 mcsp->mc_cnt = 0;
3000 if_foreach_llmaddr(sc->ifp, fxp_setup_maddr, sc);
3001 if (mcsp->mc_cnt >= MAXMCADDR) {
3002 if_setflagbits(ifp, IFF_ALLMULTI, 0);
3003 mcsp->mc_cnt = 0;
3004 }
3005 }
3006 mcsp->mc_cnt = htole16(mcsp->mc_cnt * ETHER_ADDR_LEN);
3007 }
3008
3009 /*
3010 * Program the multicast filter.
3011 *
3012 * We have an artificial restriction that the multicast setup command
3013 * must be the first command in the chain, so we take steps to ensure
3014 * this. By requiring this, it allows us to keep up the performance of
3015 * the pre-initialized command ring (esp. link pointers) by not actually
3016 * inserting the mcsetup command in the ring - i.e. its link pointer
3017 * points to the TxCB ring, but the mcsetup descriptor itself is not part
3018 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
3019 * lead into the regular TxCB ring when it completes.
3020 */
3021 static void
fxp_mc_setup(struct fxp_softc * sc)3022 fxp_mc_setup(struct fxp_softc *sc)
3023 {
3024 struct fxp_cb_mcs *mcsp;
3025 int count;
3026
3027 FXP_LOCK_ASSERT(sc, MA_OWNED);
3028
3029 mcsp = sc->mcsp;
3030 mcsp->cb_status = 0;
3031 mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL);
3032 mcsp->link_addr = 0xffffffff;
3033 fxp_mc_addrs(sc);
3034
3035 /*
3036 * Wait until command unit is idle. This should never be the
3037 * case when nothing is queued, but make sure anyway.
3038 */
3039 count = 100;
3040 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
3041 FXP_SCB_CUS_IDLE && --count)
3042 DELAY(10);
3043 if (count == 0) {
3044 device_printf(sc->dev, "command queue timeout\n");
3045 return;
3046 }
3047
3048 /*
3049 * Start the multicast setup command.
3050 */
3051 fxp_scb_wait(sc);
3052 bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
3053 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3054 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
3055 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3056 /* ...and wait for it to complete. */
3057 fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
3058 }
3059
3060 static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
3061 static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
3062 static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
3063 static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
3064 static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
3065 static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
3066 static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
3067
3068 #define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
3069
3070 static const struct ucode {
3071 uint32_t revision;
3072 uint32_t *ucode;
3073 int length;
3074 u_short int_delay_offset;
3075 u_short bundle_max_offset;
3076 } ucode_table[] = {
3077 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3078 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3079 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
3080 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
3081 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
3082 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
3083 { FXP_REV_82550, UCODE(fxp_ucode_d102),
3084 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
3085 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
3086 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
3087 { FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
3088 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3089 { FXP_REV_82551_10, UCODE(fxp_ucode_d102e),
3090 D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3091 { 0, NULL, 0, 0, 0 }
3092 };
3093
3094 static void
fxp_load_ucode(struct fxp_softc * sc)3095 fxp_load_ucode(struct fxp_softc *sc)
3096 {
3097 const struct ucode *uc;
3098 struct fxp_cb_ucode *cbp;
3099 int i;
3100
3101 if (sc->flags & FXP_FLAG_NO_UCODE)
3102 return;
3103
3104 for (uc = ucode_table; uc->ucode != NULL; uc++)
3105 if (sc->revision == uc->revision)
3106 break;
3107 if (uc->ucode == NULL)
3108 return;
3109 cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3110 cbp->cb_status = 0;
3111 cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
3112 cbp->link_addr = 0xffffffff; /* (no) next command */
3113 for (i = 0; i < uc->length; i++)
3114 cbp->ucode[i] = htole32(uc->ucode[i]);
3115 if (uc->int_delay_offset)
3116 *(uint16_t *)&cbp->ucode[uc->int_delay_offset] =
3117 htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3118 if (uc->bundle_max_offset)
3119 *(uint16_t *)&cbp->ucode[uc->bundle_max_offset] =
3120 htole16(sc->tunable_bundle_max);
3121 /*
3122 * Download the ucode to the chip.
3123 */
3124 fxp_scb_wait(sc);
3125 bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3126 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3127 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3128 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3129 /* ...and wait for it to complete. */
3130 fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3131 device_printf(sc->dev,
3132 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
3133 sc->tunable_int_delay,
3134 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3135 sc->flags |= FXP_FLAG_UCODE;
3136 bzero(cbp, FXP_TXCB_SZ);
3137 }
3138
3139 #define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \
3140 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3141
3142 static void
fxp_sysctl_node(struct fxp_softc * sc)3143 fxp_sysctl_node(struct fxp_softc *sc)
3144 {
3145 struct sysctl_ctx_list *ctx;
3146 struct sysctl_oid_list *child, *parent;
3147 struct sysctl_oid *tree;
3148 struct fxp_hwstats *hsp;
3149
3150 ctx = device_get_sysctl_ctx(sc->dev);
3151 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3152
3153 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_delay",
3154 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
3155 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3156 "FXP driver receive interrupt microcode bundling delay");
3157 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "bundle_max",
3158 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
3159 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3160 "FXP driver receive interrupt microcode bundle size limit");
3161 SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3162 "FXP RNR events");
3163
3164 /*
3165 * Pull in device tunables.
3166 */
3167 sc->tunable_int_delay = TUNABLE_INT_DELAY;
3168 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3169 (void) resource_int_value(device_get_name(sc->dev),
3170 device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3171 (void) resource_int_value(device_get_name(sc->dev),
3172 device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3173 sc->rnr = 0;
3174
3175 hsp = &sc->fxp_hwstats;
3176 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
3177 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "FXP statistics");
3178 parent = SYSCTL_CHILDREN(tree);
3179
3180 /* Rx MAC statistics. */
3181 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
3182 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
3183 child = SYSCTL_CHILDREN(tree);
3184 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3185 &hsp->rx_good, "Good frames");
3186 FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3187 &hsp->rx_crc_errors, "CRC errors");
3188 FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3189 &hsp->rx_alignment_errors, "Alignment errors");
3190 FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3191 &hsp->rx_rnr_errors, "RNR errors");
3192 FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3193 &hsp->rx_overrun_errors, "Overrun errors");
3194 FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3195 &hsp->rx_cdt_errors, "Collision detect errors");
3196 FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3197 &hsp->rx_shortframes, "Short frame errors");
3198 if (sc->revision >= FXP_REV_82558_A4) {
3199 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3200 &hsp->rx_pause, "Pause frames");
3201 FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3202 &hsp->rx_controls, "Unsupported control frames");
3203 }
3204 if (sc->revision >= FXP_REV_82559_A0)
3205 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3206 &hsp->rx_tco, "TCO frames");
3207
3208 /* Tx MAC statistics. */
3209 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
3210 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
3211 child = SYSCTL_CHILDREN(tree);
3212 FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3213 &hsp->tx_good, "Good frames");
3214 FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3215 &hsp->tx_maxcols, "Maximum collisions errors");
3216 FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3217 &hsp->tx_latecols, "Late collisions errors");
3218 FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3219 &hsp->tx_underruns, "Underrun errors");
3220 FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3221 &hsp->tx_lostcrs, "Lost carrier sense");
3222 FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3223 &hsp->tx_deffered, "Deferred");
3224 FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3225 &hsp->tx_single_collisions, "Single collisions");
3226 FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3227 &hsp->tx_multiple_collisions, "Multiple collisions");
3228 FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3229 &hsp->tx_total_collisions, "Total collisions");
3230 if (sc->revision >= FXP_REV_82558_A4)
3231 FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3232 &hsp->tx_pause, "Pause frames");
3233 if (sc->revision >= FXP_REV_82559_A0)
3234 FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3235 &hsp->tx_tco, "TCO frames");
3236 }
3237
3238 #undef FXP_SYSCTL_STAT_ADD
3239
3240 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3241 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3242 {
3243 int error, value;
3244
3245 value = *(int *)arg1;
3246 error = sysctl_handle_int(oidp, &value, 0, req);
3247 if (error || !req->newptr)
3248 return (error);
3249 if (value < low || value > high)
3250 return (EINVAL);
3251 *(int *)arg1 = value;
3252 return (0);
3253 }
3254
3255 /*
3256 * Interrupt delay is expressed in microseconds, a multiplier is used
3257 * to convert this to the appropriate clock ticks before using.
3258 */
3259 static int
sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)3260 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3261 {
3262
3263 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3264 }
3265
3266 static int
sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)3267 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3268 {
3269
3270 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
3271 }
3272