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39
40
41 /**
42 * cvmx-pcm-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon pcm.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_PCM_DEFS_H__
53 #define __CVMX_PCM_DEFS_H__
54
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCM_CLKX_CFG(unsigned long offset)56 static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
57 {
58 if (!(
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
63 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
64 cvmx_warn("CVMX_PCM_CLKX_CFG(%lu) is invalid on this chip\n", offset);
65 return CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384;
66 }
67 #else
68 #define CVMX_PCM_CLKX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384)
69 #endif
70 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCM_CLKX_DBG(unsigned long offset)71 static inline uint64_t CVMX_PCM_CLKX_DBG(unsigned long offset)
72 {
73 if (!(
74 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
75 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
76 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
77 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
78 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
79 cvmx_warn("CVMX_PCM_CLKX_DBG(%lu) is invalid on this chip\n", offset);
80 return CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384;
81 }
82 #else
83 #define CVMX_PCM_CLKX_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384)
84 #endif
85 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_PCM_CLKX_GEN(unsigned long offset)86 static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
87 {
88 if (!(
89 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
90 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
91 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
92 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
93 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
94 cvmx_warn("CVMX_PCM_CLKX_GEN(%lu) is invalid on this chip\n", offset);
95 return CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384;
96 }
97 #else
98 #define CVMX_PCM_CLKX_GEN(offset) (CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384)
99 #endif
100
101 /**
102 * cvmx_pcm_clk#_cfg
103 */
104 union cvmx_pcm_clkx_cfg {
105 uint64_t u64;
106 struct cvmx_pcm_clkx_cfg_s {
107 #ifdef __BIG_ENDIAN_BITFIELD
108 uint64_t fsyncgood : 1; /**< FSYNC status | NS
109 If 1, the last frame had a correctly positioned
110 fsync pulse
111 If 0, none/extra fsync pulse seen on most recent
112 frame
113 NOTE: this is intended for startup. the FSYNCEXTRA
114 and FSYNCMISSING interrupts are intended for
115 detecting loss of sync during normal operation. */
116 uint64_t reserved_48_62 : 15;
117 uint64_t fsyncsamp : 16; /**< Number of ECLKs from internal BCLK edge to | NS
118 sample FSYNC
119 NOTE: used to sync to the start of a frame and to
120 check for FSYNC errors. */
121 uint64_t reserved_26_31 : 6;
122 uint64_t fsynclen : 5; /**< Number of 1/2 BCLKs FSYNC is asserted for | NS
123 NOTE: only used when GEN==1 */
124 uint64_t fsyncloc : 5; /**< FSYNC location, in 1/2 BCLKS before timeslot 0, | NS
125 bit 0.
126 NOTE: also used to detect framing errors and
127 therefore must have a correct value even if GEN==0 */
128 uint64_t numslots : 10; /**< Number of 8-bit slots in a frame | NS
129 NOTE: this, along with EXTRABIT and Fbclk
130 determines FSYNC frequency when GEN == 1
131 NOTE: also used to detect framing errors and
132 therefore must have a correct value even if GEN==0 */
133 uint64_t extrabit : 1; /**< If 0, no frame bit | NS
134 If 1, add one extra bit time for frame bit
135 NOTE: if GEN == 1, then FSYNC will be delayed one
136 extra bit time.
137 NOTE: also used to detect framing errors and
138 therefore must have a correct value even if GEN==0
139 NOTE: the extra bit comes from the LSB/MSB of the
140 first byte of the frame in the transmit memory
141 region. LSB vs MSB is determined from the setting
142 of PCMn_TDM_CFG[LSBFIRST]. */
143 uint64_t bitlen : 2; /**< Number of BCLKs in a bit time. | NS
144 0 : 1 BCLK
145 1 : 2 BCLKs
146 2 : 4 BCLKs
147 3 : operation undefined */
148 uint64_t bclkpol : 1; /**< If 0, BCLK rise edge is start of bit time | NS
149 If 1, BCLK fall edge is start of bit time
150 NOTE: also used to detect framing errors and
151 therefore must have a correct value even if GEN==0 */
152 uint64_t fsyncpol : 1; /**< If 0, FSYNC idles low, asserts high | NS
153 If 1, FSYNC idles high, asserts low
154 NOTE: also used to detect framing errors and
155 therefore must have a correct value even if GEN==0 */
156 uint64_t ena : 1; /**< If 0, Clock receiving logic is doing nothing | NS
157 1, Clock receiving logic is looking for sync */
158 #else
159 uint64_t ena : 1;
160 uint64_t fsyncpol : 1;
161 uint64_t bclkpol : 1;
162 uint64_t bitlen : 2;
163 uint64_t extrabit : 1;
164 uint64_t numslots : 10;
165 uint64_t fsyncloc : 5;
166 uint64_t fsynclen : 5;
167 uint64_t reserved_26_31 : 6;
168 uint64_t fsyncsamp : 16;
169 uint64_t reserved_48_62 : 15;
170 uint64_t fsyncgood : 1;
171 #endif
172 } s;
173 struct cvmx_pcm_clkx_cfg_s cn30xx;
174 struct cvmx_pcm_clkx_cfg_s cn31xx;
175 struct cvmx_pcm_clkx_cfg_s cn50xx;
176 struct cvmx_pcm_clkx_cfg_s cn61xx;
177 struct cvmx_pcm_clkx_cfg_s cnf71xx;
178 };
179 typedef union cvmx_pcm_clkx_cfg cvmx_pcm_clkx_cfg_t;
180
181 /**
182 * cvmx_pcm_clk#_dbg
183 */
184 union cvmx_pcm_clkx_dbg {
185 uint64_t u64;
186 struct cvmx_pcm_clkx_dbg_s {
187 #ifdef __BIG_ENDIAN_BITFIELD
188 uint64_t debuginfo : 64; /**< Miscellaneous debug information | NS */
189 #else
190 uint64_t debuginfo : 64;
191 #endif
192 } s;
193 struct cvmx_pcm_clkx_dbg_s cn30xx;
194 struct cvmx_pcm_clkx_dbg_s cn31xx;
195 struct cvmx_pcm_clkx_dbg_s cn50xx;
196 struct cvmx_pcm_clkx_dbg_s cn61xx;
197 struct cvmx_pcm_clkx_dbg_s cnf71xx;
198 };
199 typedef union cvmx_pcm_clkx_dbg cvmx_pcm_clkx_dbg_t;
200
201 /**
202 * cvmx_pcm_clk#_gen
203 */
204 union cvmx_pcm_clkx_gen {
205 uint64_t u64;
206 struct cvmx_pcm_clkx_gen_s {
207 #ifdef __BIG_ENDIAN_BITFIELD
208 uint64_t deltasamp : 16; /**< Signed number of ECLKs to move sampled BCLK edge | NS
209 NOTE: the complete number of ECLKs to move is:
210 NUMSAMP + 2 + 1 + DELTASAMP
211 NUMSAMP to compensate for sampling delay
212 + 2 to compensate for dual-rank synchronizer
213 + 1 for uncertainity
214 + DELTASAMP to CMA/debugging */
215 uint64_t numsamp : 16; /**< Number of ECLK samples to detect BCLK change when | NS
216 receiving clock. */
217 uint64_t n : 32; /**< Determines BCLK frequency when generating clock | NS
218 NOTE: Fbclk = Feclk * N / 2^32
219 N = (Fbclk / Feclk) * 2^32
220 NOTE: writing N == 0 stops the clock generator, and
221 causes bclk and fsync to be RECEIVED */
222 #else
223 uint64_t n : 32;
224 uint64_t numsamp : 16;
225 uint64_t deltasamp : 16;
226 #endif
227 } s;
228 struct cvmx_pcm_clkx_gen_s cn30xx;
229 struct cvmx_pcm_clkx_gen_s cn31xx;
230 struct cvmx_pcm_clkx_gen_s cn50xx;
231 struct cvmx_pcm_clkx_gen_s cn61xx;
232 struct cvmx_pcm_clkx_gen_s cnf71xx;
233 };
234 typedef union cvmx_pcm_clkx_gen cvmx_pcm_clkx_gen_t;
235
236 #endif
237