1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Sepherosa Ziehau <[email protected]>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in
17 * the documentation and/or other materials provided with the
18 * distribution.
19 * 3. Neither the name of The DragonFly Project nor the names of its
20 * contributors may be used to endorse or promote products derived
21 * from this software without specific, prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $
37 */
38
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
41
42 #include "opt_inet.h"
43 #include "opt_bwi.h"
44 #include "opt_wlan.h"
45
46 #include <sys/param.h>
47 #include <sys/endian.h>
48 #include <sys/kernel.h>
49 #include <sys/bus.h>
50 #include <sys/malloc.h>
51 #include <sys/proc.h>
52 #include <sys/rman.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 #include <sys/sysctl.h>
56 #include <sys/systm.h>
57 #include <sys/taskqueue.h>
58
59 #include <net/if.h>
60 #include <net/if_var.h>
61 #include <net/if_dl.h>
62 #include <net/if_media.h>
63 #include <net/if_types.h>
64 #include <net/if_arp.h>
65 #include <net/ethernet.h>
66 #include <net/if_llc.h>
67
68 #include <net80211/ieee80211_var.h>
69 #include <net80211/ieee80211_radiotap.h>
70 #include <net80211/ieee80211_regdomain.h>
71 #include <net80211/ieee80211_phy.h>
72 #include <net80211/ieee80211_ratectl.h>
73
74 #include <net/bpf.h>
75
76 #ifdef INET
77 #include <netinet/in.h>
78 #include <netinet/if_ether.h>
79 #endif
80
81 #include <machine/bus.h>
82
83 #include <dev/pci/pcivar.h>
84 #include <dev/pci/pcireg.h>
85
86 #include <dev/bwi/bitops.h>
87 #include <dev/bwi/if_bwireg.h>
88 #include <dev/bwi/if_bwivar.h>
89 #include <dev/bwi/bwimac.h>
90 #include <dev/bwi/bwirf.h>
91
92 struct bwi_clock_freq {
93 u_int clkfreq_min;
94 u_int clkfreq_max;
95 };
96
97 struct bwi_myaddr_bssid {
98 uint8_t myaddr[IEEE80211_ADDR_LEN];
99 uint8_t bssid[IEEE80211_ADDR_LEN];
100 } __packed;
101
102 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *,
103 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
104 const uint8_t [IEEE80211_ADDR_LEN],
105 const uint8_t [IEEE80211_ADDR_LEN]);
106 static void bwi_vap_delete(struct ieee80211vap *);
107 static void bwi_init(struct bwi_softc *);
108 static void bwi_parent(struct ieee80211com *);
109 static int bwi_transmit(struct ieee80211com *, struct mbuf *);
110 static void bwi_start_locked(struct bwi_softc *);
111 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *,
112 const struct ieee80211_bpf_params *);
113 static void bwi_watchdog(void *);
114 static void bwi_scan_start(struct ieee80211com *);
115 static void bwi_getradiocaps(struct ieee80211com *, int, int *,
116 struct ieee80211_channel[]);
117 static void bwi_set_channel(struct ieee80211com *);
118 static void bwi_scan_end(struct ieee80211com *);
119 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int);
120 static void bwi_updateslot(struct ieee80211com *);
121 static int bwi_media_change(struct ifnet *);
122
123 static void bwi_calibrate(void *);
124
125 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
126 static int bwi_calc_noise(struct bwi_softc *);
127 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype);
128 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
129 struct bwi_rxbuf_hdr *, const void *, int, int, int);
130
131 static void bwi_restart(void *, int);
132 static void bwi_init_statechg(struct bwi_softc *, int);
133 static void bwi_stop(struct bwi_softc *, int);
134 static void bwi_stop_locked(struct bwi_softc *, int);
135 static int bwi_newbuf(struct bwi_softc *, int, int);
136 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
137 struct ieee80211_node *);
138 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *,
139 struct ieee80211_node *,
140 const struct ieee80211_bpf_params *);
141
142 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
143 bus_addr_t, int, int);
144 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
145
146 static int bwi_init_tx_ring32(struct bwi_softc *, int);
147 static int bwi_init_rx_ring32(struct bwi_softc *);
148 static int bwi_init_txstats32(struct bwi_softc *);
149 static void bwi_free_tx_ring32(struct bwi_softc *, int);
150 static void bwi_free_rx_ring32(struct bwi_softc *);
151 static void bwi_free_txstats32(struct bwi_softc *);
152 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
153 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
154 int, bus_addr_t, int);
155 static int bwi_rxeof32(struct bwi_softc *);
156 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
157 static void bwi_txeof_status32(struct bwi_softc *);
158
159 static int bwi_init_tx_ring64(struct bwi_softc *, int);
160 static int bwi_init_rx_ring64(struct bwi_softc *);
161 static int bwi_init_txstats64(struct bwi_softc *);
162 static void bwi_free_tx_ring64(struct bwi_softc *, int);
163 static void bwi_free_rx_ring64(struct bwi_softc *);
164 static void bwi_free_txstats64(struct bwi_softc *);
165 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
166 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
167 int, bus_addr_t, int);
168 static int bwi_rxeof64(struct bwi_softc *);
169 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
170 static void bwi_txeof_status64(struct bwi_softc *);
171
172 static int bwi_rxeof(struct bwi_softc *, int);
173 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
174 static void bwi_txeof(struct bwi_softc *);
175 static void bwi_txeof_status(struct bwi_softc *, int);
176 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
177 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
178
179 static int bwi_dma_alloc(struct bwi_softc *);
180 static void bwi_dma_free(struct bwi_softc *);
181 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
182 struct bwi_ring_data *, bus_size_t,
183 uint32_t);
184 static int bwi_dma_mbuf_create(struct bwi_softc *);
185 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
186 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
187 static void bwi_dma_txstats_free(struct bwi_softc *);
188 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
189 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
190 bus_size_t, int);
191
192 static void bwi_power_on(struct bwi_softc *, int);
193 static int bwi_power_off(struct bwi_softc *, int);
194 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
195 static int bwi_set_clock_delay(struct bwi_softc *);
196 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
197 static int bwi_get_pwron_delay(struct bwi_softc *sc);
198 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
199 const uint8_t *);
200 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
201
202 static void bwi_get_card_flags(struct bwi_softc *);
203 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
204
205 static int bwi_bus_attach(struct bwi_softc *);
206 static int bwi_bbp_attach(struct bwi_softc *);
207 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
208 static void bwi_bbp_power_off(struct bwi_softc *);
209
210 static const char *bwi_regwin_name(const struct bwi_regwin *);
211 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
212 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
213 static int bwi_regwin_select(struct bwi_softc *, int);
214
215 static void bwi_led_attach(struct bwi_softc *);
216 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
217 static void bwi_led_event(struct bwi_softc *, int);
218 static void bwi_led_blink_start(struct bwi_softc *, int, int);
219 static void bwi_led_blink_next(void *);
220 static void bwi_led_blink_end(void *);
221
222 static const struct {
223 uint16_t did_min;
224 uint16_t did_max;
225 uint16_t bbp_id;
226 } bwi_bbpid_map[] = {
227 { 0x4301, 0x4301, 0x4301 },
228 { 0x4305, 0x4307, 0x4307 },
229 { 0x4402, 0x4403, 0x4402 },
230 { 0x4610, 0x4615, 0x4610 },
231 { 0x4710, 0x4715, 0x4710 },
232 { 0x4720, 0x4725, 0x4309 }
233 };
234
235 static const struct {
236 uint16_t bbp_id;
237 int nregwin;
238 } bwi_regwin_count[] = {
239 { 0x4301, 5 },
240 { 0x4306, 6 },
241 { 0x4307, 5 },
242 { 0x4310, 8 },
243 { 0x4401, 3 },
244 { 0x4402, 3 },
245 { 0x4610, 9 },
246 { 0x4704, 9 },
247 { 0x4710, 9 },
248 { 0x5365, 7 }
249 };
250
251 #define CLKSRC(src) \
252 [BWI_CLKSRC_ ## src] = { \
253 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
254 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
255 }
256
257 static const struct {
258 u_int freq_min;
259 u_int freq_max;
260 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
261 CLKSRC(LP_OSC),
262 CLKSRC(CS_OSC),
263 CLKSRC(PCI)
264 };
265
266 #undef CLKSRC
267
268 #define VENDOR_LED_ACT(vendor) \
269 { \
270 .vid = PCI_VENDOR_##vendor, \
271 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
272 }
273
274 static const struct {
275 #define PCI_VENDOR_COMPAQ 0x0e11
276 #define PCI_VENDOR_LINKSYS 0x1737
277 uint16_t vid;
278 uint8_t led_act[BWI_LED_MAX];
279 } bwi_vendor_led_act[] = {
280 VENDOR_LED_ACT(COMPAQ),
281 VENDOR_LED_ACT(LINKSYS)
282 #undef PCI_VENDOR_LINKSYS
283 #undef PCI_VENDOR_COMPAQ
284 };
285
286 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
287 { BWI_VENDOR_LED_ACT_DEFAULT };
288
289 #undef VENDOR_LED_ACT
290
291 static const struct {
292 int on_dur;
293 int off_dur;
294 } bwi_led_duration[109] = {
295 [0] = { 400, 100 },
296 [2] = { 150, 75 },
297 [4] = { 90, 45 },
298 [11] = { 66, 34 },
299 [12] = { 53, 26 },
300 [18] = { 42, 21 },
301 [22] = { 35, 17 },
302 [24] = { 32, 16 },
303 [36] = { 21, 10 },
304 [48] = { 16, 8 },
305 [72] = { 11, 5 },
306 [96] = { 9, 4 },
307 [108] = { 7, 3 }
308 };
309
310 #ifdef BWI_DEBUG
311 #ifdef BWI_DEBUG_VERBOSE
312 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
313 #else
314 static uint32_t bwi_debug;
315 #endif
316 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
317 #endif /* BWI_DEBUG */
318
319 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
320
321 uint16_t
bwi_read_sprom(struct bwi_softc * sc,uint16_t ofs)322 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
323 {
324 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
325 }
326
327 static __inline void
bwi_setup_desc32(struct bwi_softc * sc,struct bwi_desc32 * desc_array,int ndesc,int desc_idx,bus_addr_t paddr,int buf_len,int tx)328 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
329 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
330 int tx)
331 {
332 struct bwi_desc32 *desc = &desc_array[desc_idx];
333 uint32_t ctrl, addr, addr_hi, addr_lo;
334
335 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
336 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
337
338 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
339 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
340
341 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
342 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
343 if (desc_idx == ndesc - 1)
344 ctrl |= BWI_DESC32_C_EOR;
345 if (tx) {
346 /* XXX */
347 ctrl |= BWI_DESC32_C_FRAME_START |
348 BWI_DESC32_C_FRAME_END |
349 BWI_DESC32_C_INTR;
350 }
351
352 desc->addr = htole32(addr);
353 desc->ctrl = htole32(ctrl);
354 }
355
356 int
bwi_attach(struct bwi_softc * sc)357 bwi_attach(struct bwi_softc *sc)
358 {
359 struct ieee80211com *ic = &sc->sc_ic;
360 device_t dev = sc->sc_dev;
361 struct bwi_mac *mac;
362 struct bwi_phy *phy;
363 int i, error;
364
365 BWI_LOCK_INIT(sc);
366
367 /*
368 * Initialize taskq and various tasks
369 */
370 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO,
371 taskqueue_thread_enqueue, &sc->sc_tq);
372 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
373 device_get_nameunit(dev));
374 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc);
375 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0);
376 mbufq_init(&sc->sc_snd, ifqmaxlen);
377
378 /*
379 * Initialize sysctl variables
380 */
381 sc->sc_fw_version = BWI_FW_VERSION3;
382 sc->sc_led_idle = (2350 * hz) / 1000;
383 sc->sc_led_ticks = ticks - sc->sc_led_idle;
384 sc->sc_led_blink = 1;
385 sc->sc_txpwr_calib = 1;
386 #ifdef BWI_DEBUG
387 sc->sc_debug = bwi_debug;
388 #endif
389 bwi_power_on(sc, 1);
390
391 error = bwi_bbp_attach(sc);
392 if (error)
393 goto fail;
394
395 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
396 if (error)
397 goto fail;
398
399 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
400 error = bwi_set_clock_delay(sc);
401 if (error)
402 goto fail;
403
404 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
405 if (error)
406 goto fail;
407
408 error = bwi_get_pwron_delay(sc);
409 if (error)
410 goto fail;
411 }
412
413 error = bwi_bus_attach(sc);
414 if (error)
415 goto fail;
416
417 bwi_get_card_flags(sc);
418
419 bwi_led_attach(sc);
420
421 for (i = 0; i < sc->sc_nmac; ++i) {
422 struct bwi_regwin *old;
423
424 mac = &sc->sc_mac[i];
425 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
426 if (error)
427 goto fail;
428
429 error = bwi_mac_lateattach(mac);
430 if (error)
431 goto fail;
432
433 error = bwi_regwin_switch(sc, old, NULL);
434 if (error)
435 goto fail;
436 }
437
438 /*
439 * XXX First MAC is known to exist
440 * TODO2
441 */
442 mac = &sc->sc_mac[0];
443 phy = &mac->mac_phy;
444
445 bwi_bbp_power_off(sc);
446
447 error = bwi_dma_alloc(sc);
448 if (error)
449 goto fail;
450
451 error = bwi_mac_fw_alloc(mac);
452 if (error)
453 goto fail;
454
455 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0);
456
457 /*
458 * Setup ratesets, phytype, channels and get MAC address
459 */
460 if (phy->phy_mode == IEEE80211_MODE_11B ||
461 phy->phy_mode == IEEE80211_MODE_11G) {
462 if (phy->phy_mode == IEEE80211_MODE_11B) {
463 ic->ic_phytype = IEEE80211_T_DS;
464 } else {
465 ic->ic_phytype = IEEE80211_T_OFDM;
466 }
467
468 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr);
469 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) {
470 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr);
471 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) {
472 device_printf(dev,
473 "invalid MAC address: %6D\n",
474 ic->ic_macaddr, ":");
475 }
476 }
477 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
478 /* TODO:11A */
479 error = ENXIO;
480 goto fail;
481 } else {
482 panic("unknown phymode %d\n", phy->phy_mode);
483 }
484
485 /* Get locale */
486 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
487 BWI_SPROM_CARD_INFO_LOCALE);
488 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
489 /* XXX use locale */
490
491 ic->ic_softc = sc;
492
493 bwi_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
494 ic->ic_channels);
495
496 ic->ic_name = device_get_nameunit(dev);
497 ic->ic_caps = IEEE80211_C_STA |
498 IEEE80211_C_SHSLOT |
499 IEEE80211_C_SHPREAMBLE |
500 IEEE80211_C_WPA |
501 IEEE80211_C_BGSCAN |
502 IEEE80211_C_MONITOR;
503 ic->ic_opmode = IEEE80211_M_STA;
504 ieee80211_ifattach(ic);
505
506 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
507
508 /* override default methods */
509 ic->ic_vap_create = bwi_vap_create;
510 ic->ic_vap_delete = bwi_vap_delete;
511 ic->ic_raw_xmit = bwi_raw_xmit;
512 ic->ic_updateslot = bwi_updateslot;
513 ic->ic_scan_start = bwi_scan_start;
514 ic->ic_scan_end = bwi_scan_end;
515 ic->ic_getradiocaps = bwi_getradiocaps;
516 ic->ic_set_channel = bwi_set_channel;
517 ic->ic_transmit = bwi_transmit;
518 ic->ic_parent = bwi_parent;
519
520 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan);
521
522 ieee80211_radiotap_attach(ic,
523 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
524 BWI_TX_RADIOTAP_PRESENT,
525 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
526 BWI_RX_RADIOTAP_PRESENT);
527
528 /*
529 * Add sysctl nodes
530 */
531 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
532 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
533 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
534 "Firmware version");
535 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
536 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
537 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
538 "# ticks before LED enters idle state");
539 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
540 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
541 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
542 "Allow LED to blink");
543 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
544 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
545 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
546 "Enable software TX power calibration");
547 #ifdef BWI_DEBUG
548 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
549 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
550 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
551 #endif
552 if (bootverbose)
553 ieee80211_announce(ic);
554
555 return (0);
556 fail:
557 BWI_LOCK_DESTROY(sc);
558 return (error);
559 }
560
561 int
bwi_detach(struct bwi_softc * sc)562 bwi_detach(struct bwi_softc *sc)
563 {
564 struct ieee80211com *ic = &sc->sc_ic;
565 int i;
566
567 bwi_stop(sc, 1);
568 callout_drain(&sc->sc_led_blink_ch);
569 callout_drain(&sc->sc_calib_ch);
570 callout_drain(&sc->sc_watchdog_timer);
571 ieee80211_ifdetach(ic);
572
573 for (i = 0; i < sc->sc_nmac; ++i)
574 bwi_mac_detach(&sc->sc_mac[i]);
575 bwi_dma_free(sc);
576 taskqueue_free(sc->sc_tq);
577 mbufq_drain(&sc->sc_snd);
578
579 BWI_LOCK_DESTROY(sc);
580
581 return (0);
582 }
583
584 static struct ieee80211vap *
bwi_vap_create(struct ieee80211com * ic,const char name[IFNAMSIZ],int unit,enum ieee80211_opmode opmode,int flags,const uint8_t bssid[IEEE80211_ADDR_LEN],const uint8_t mac[IEEE80211_ADDR_LEN])585 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
586 enum ieee80211_opmode opmode, int flags,
587 const uint8_t bssid[IEEE80211_ADDR_LEN],
588 const uint8_t mac[IEEE80211_ADDR_LEN])
589 {
590 struct bwi_vap *bvp;
591 struct ieee80211vap *vap;
592
593 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
594 return NULL;
595 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO);
596 vap = &bvp->bv_vap;
597 /* enable s/w bmiss handling for sta mode */
598 ieee80211_vap_setup(ic, vap, name, unit, opmode,
599 flags | IEEE80211_CLONE_NOBEACONS, bssid);
600
601 /* override default methods */
602 bvp->bv_newstate = vap->iv_newstate;
603 vap->iv_newstate = bwi_newstate;
604 #if 0
605 vap->iv_update_beacon = bwi_beacon_update;
606 #endif
607 ieee80211_ratectl_init(vap);
608
609 /* complete setup */
610 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status,
611 mac);
612 ic->ic_opmode = opmode;
613 return vap;
614 }
615
616 static void
bwi_vap_delete(struct ieee80211vap * vap)617 bwi_vap_delete(struct ieee80211vap *vap)
618 {
619 struct bwi_vap *bvp = BWI_VAP(vap);
620
621 ieee80211_ratectl_deinit(vap);
622 ieee80211_vap_detach(vap);
623 free(bvp, M_80211_VAP);
624 }
625
626 void
bwi_suspend(struct bwi_softc * sc)627 bwi_suspend(struct bwi_softc *sc)
628 {
629 bwi_stop(sc, 1);
630 }
631
632 void
bwi_resume(struct bwi_softc * sc)633 bwi_resume(struct bwi_softc *sc)
634 {
635
636 if (sc->sc_ic.ic_nrunning > 0)
637 bwi_init(sc);
638 }
639
640 int
bwi_shutdown(struct bwi_softc * sc)641 bwi_shutdown(struct bwi_softc *sc)
642 {
643 bwi_stop(sc, 1);
644 return 0;
645 }
646
647 static void
bwi_power_on(struct bwi_softc * sc,int with_pll)648 bwi_power_on(struct bwi_softc *sc, int with_pll)
649 {
650 uint32_t gpio_in, gpio_out, gpio_en;
651 uint16_t status;
652
653 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
654 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
655 goto back;
656
657 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
658 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
659
660 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
661 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
662 if (with_pll) {
663 /* Turn off PLL first */
664 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
665 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
666 }
667
668 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
669 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
670 DELAY(1000);
671
672 if (with_pll) {
673 /* Turn on PLL */
674 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
675 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
676 DELAY(5000);
677 }
678
679 back:
680 /* Clear "Signaled Target Abort" */
681 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
682 status &= ~PCIM_STATUS_STABORT;
683 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
684 }
685
686 static int
bwi_power_off(struct bwi_softc * sc,int with_pll)687 bwi_power_off(struct bwi_softc *sc, int with_pll)
688 {
689 uint32_t gpio_out, gpio_en;
690
691 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
692 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
693 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
694
695 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
696 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
697 if (with_pll) {
698 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
699 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
700 }
701
702 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
703 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
704 return 0;
705 }
706
707 int
bwi_regwin_switch(struct bwi_softc * sc,struct bwi_regwin * rw,struct bwi_regwin ** old_rw)708 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
709 struct bwi_regwin **old_rw)
710 {
711 int error;
712
713 if (old_rw != NULL)
714 *old_rw = NULL;
715
716 if (!BWI_REGWIN_EXIST(rw))
717 return EINVAL;
718
719 if (sc->sc_cur_regwin != rw) {
720 error = bwi_regwin_select(sc, rw->rw_id);
721 if (error) {
722 device_printf(sc->sc_dev, "can't select regwin %d\n",
723 rw->rw_id);
724 return error;
725 }
726 }
727
728 if (old_rw != NULL)
729 *old_rw = sc->sc_cur_regwin;
730 sc->sc_cur_regwin = rw;
731 return 0;
732 }
733
734 static int
bwi_regwin_select(struct bwi_softc * sc,int id)735 bwi_regwin_select(struct bwi_softc *sc, int id)
736 {
737 uint32_t win = BWI_PCIM_REGWIN(id);
738 int i;
739
740 #define RETRY_MAX 50
741 for (i = 0; i < RETRY_MAX; ++i) {
742 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
743 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
744 return 0;
745 DELAY(10);
746 }
747 #undef RETRY_MAX
748
749 return ENXIO;
750 }
751
752 static void
bwi_regwin_info(struct bwi_softc * sc,uint16_t * type,uint8_t * rev)753 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
754 {
755 uint32_t val;
756
757 val = CSR_READ_4(sc, BWI_ID_HI);
758 *type = BWI_ID_HI_REGWIN_TYPE(val);
759 *rev = BWI_ID_HI_REGWIN_REV(val);
760
761 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
762 "vendor 0x%04x\n", *type, *rev,
763 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
764 }
765
766 static int
bwi_bbp_attach(struct bwi_softc * sc)767 bwi_bbp_attach(struct bwi_softc *sc)
768 {
769 uint16_t bbp_id, rw_type;
770 uint8_t rw_rev;
771 uint32_t info;
772 int error, nregwin, i;
773
774 /*
775 * Get 0th regwin information
776 * NOTE: 0th regwin should exist
777 */
778 error = bwi_regwin_select(sc, 0);
779 if (error) {
780 device_printf(sc->sc_dev, "can't select regwin 0\n");
781 return error;
782 }
783 bwi_regwin_info(sc, &rw_type, &rw_rev);
784
785 /*
786 * Find out BBP id
787 */
788 bbp_id = 0;
789 info = 0;
790 if (rw_type == BWI_REGWIN_T_COM) {
791 info = CSR_READ_4(sc, BWI_INFO);
792 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
793
794 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
795
796 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
797 } else {
798 for (i = 0; i < nitems(bwi_bbpid_map); ++i) {
799 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min &&
800 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) {
801 bbp_id = bwi_bbpid_map[i].bbp_id;
802 break;
803 }
804 }
805 if (bbp_id == 0) {
806 device_printf(sc->sc_dev, "no BBP id for device id "
807 "0x%04x\n", sc->sc_pci_did);
808 return ENXIO;
809 }
810
811 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) |
812 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
813 }
814
815 /*
816 * Find out number of regwins
817 */
818 nregwin = 0;
819 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
820 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
821 } else {
822 for (i = 0; i < nitems(bwi_regwin_count); ++i) {
823 if (bwi_regwin_count[i].bbp_id == bbp_id) {
824 nregwin = bwi_regwin_count[i].nregwin;
825 break;
826 }
827 }
828 if (nregwin == 0) {
829 device_printf(sc->sc_dev, "no number of win for "
830 "BBP id 0x%04x\n", bbp_id);
831 return ENXIO;
832 }
833 }
834
835 /* Record BBP id/rev for later using */
836 sc->sc_bbp_id = bbp_id;
837 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
838 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
839 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
840 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
841
842 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
843 nregwin, sc->sc_cap);
844
845 /*
846 * Create rest of the regwins
847 */
848
849 /* Don't re-create common regwin, if it is already created */
850 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
851
852 for (; i < nregwin; ++i) {
853 /*
854 * Get regwin information
855 */
856 error = bwi_regwin_select(sc, i);
857 if (error) {
858 device_printf(sc->sc_dev,
859 "can't select regwin %d\n", i);
860 return error;
861 }
862 bwi_regwin_info(sc, &rw_type, &rw_rev);
863
864 /*
865 * Try attach:
866 * 1) Bus (PCI/PCIE) regwin
867 * 2) MAC regwin
868 * Ignore rest types of regwin
869 */
870 if (rw_type == BWI_REGWIN_T_BUSPCI ||
871 rw_type == BWI_REGWIN_T_BUSPCIE) {
872 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
873 device_printf(sc->sc_dev,
874 "bus regwin already exists\n");
875 } else {
876 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
877 rw_type, rw_rev);
878 }
879 } else if (rw_type == BWI_REGWIN_T_MAC) {
880 /* XXX ignore return value */
881 bwi_mac_attach(sc, i, rw_rev);
882 }
883 }
884
885 /* At least one MAC shold exist */
886 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
887 device_printf(sc->sc_dev, "no MAC was found\n");
888 return ENXIO;
889 }
890 KASSERT(sc->sc_nmac > 0, ("no mac's"));
891
892 /* Bus regwin must exist */
893 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
894 device_printf(sc->sc_dev, "no bus regwin was found\n");
895 return ENXIO;
896 }
897
898 /* Start with first MAC */
899 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
900 if (error)
901 return error;
902
903 return 0;
904 }
905
906 int
bwi_bus_init(struct bwi_softc * sc,struct bwi_mac * mac)907 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
908 {
909 struct bwi_regwin *old, *bus;
910 uint32_t val;
911 int error;
912
913 bus = &sc->sc_bus_regwin;
914 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin"));
915
916 /*
917 * Tell bus to generate requested interrupts
918 */
919 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
920 /*
921 * NOTE: Read BWI_FLAGS from MAC regwin
922 */
923 val = CSR_READ_4(sc, BWI_FLAGS);
924
925 error = bwi_regwin_switch(sc, bus, &old);
926 if (error)
927 return error;
928
929 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
930 } else {
931 uint32_t mac_mask;
932
933 mac_mask = 1 << mac->mac_id;
934
935 error = bwi_regwin_switch(sc, bus, &old);
936 if (error)
937 return error;
938
939 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
940 val |= mac_mask << 8;
941 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
942 }
943
944 if (sc->sc_flags & BWI_F_BUS_INITED)
945 goto back;
946
947 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
948 /*
949 * Enable prefetch and burst
950 */
951 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
952 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
953
954 if (bus->rw_rev < 5) {
955 struct bwi_regwin *com = &sc->sc_com_regwin;
956
957 /*
958 * Configure timeouts for bus operation
959 */
960
961 /*
962 * Set service timeout and request timeout
963 */
964 CSR_SETBITS_4(sc, BWI_CONF_LO,
965 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
966 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
967
968 /*
969 * If there is common regwin, we switch to that regwin
970 * and switch back to bus regwin once we have done.
971 */
972 if (BWI_REGWIN_EXIST(com)) {
973 error = bwi_regwin_switch(sc, com, NULL);
974 if (error)
975 return error;
976 }
977
978 /* Let bus know what we have changed */
979 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
980 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
981 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
982 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
983
984 if (BWI_REGWIN_EXIST(com)) {
985 error = bwi_regwin_switch(sc, bus, NULL);
986 if (error)
987 return error;
988 }
989 } else if (bus->rw_rev >= 11) {
990 /*
991 * Enable memory read multiple
992 */
993 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
994 }
995 } else {
996 /* TODO:PCIE */
997 }
998
999 sc->sc_flags |= BWI_F_BUS_INITED;
1000 back:
1001 return bwi_regwin_switch(sc, old, NULL);
1002 }
1003
1004 static void
bwi_get_card_flags(struct bwi_softc * sc)1005 bwi_get_card_flags(struct bwi_softc *sc)
1006 {
1007 #define PCI_VENDOR_APPLE 0x106b
1008 #define PCI_VENDOR_DELL 0x1028
1009 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1010 if (sc->sc_card_flags == 0xffff)
1011 sc->sc_card_flags = 0;
1012
1013 if (sc->sc_pci_subvid == PCI_VENDOR_DELL &&
1014 sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1015 sc->sc_pci_revid == 0x74)
1016 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST;
1017
1018 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1019 sc->sc_pci_subdid == 0x4e && /* XXX */
1020 sc->sc_pci_revid > 0x40)
1021 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1022
1023 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1024 #undef PCI_VENDOR_DELL
1025 #undef PCI_VENDOR_APPLE
1026 }
1027
1028 static void
bwi_get_eaddr(struct bwi_softc * sc,uint16_t eaddr_ofs,uint8_t * eaddr)1029 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1030 {
1031 int i;
1032
1033 for (i = 0; i < 3; ++i) {
1034 *((uint16_t *)eaddr + i) =
1035 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1036 }
1037 }
1038
1039 static void
bwi_get_clock_freq(struct bwi_softc * sc,struct bwi_clock_freq * freq)1040 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1041 {
1042 struct bwi_regwin *com;
1043 uint32_t val;
1044 u_int div;
1045 int src;
1046
1047 bzero(freq, sizeof(*freq));
1048 com = &sc->sc_com_regwin;
1049
1050 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist"));
1051 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin"));
1052 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode"));
1053
1054 /*
1055 * Calculate clock frequency
1056 */
1057 src = -1;
1058 div = 0;
1059 if (com->rw_rev < 6) {
1060 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1061 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1062 src = BWI_CLKSRC_PCI;
1063 div = 64;
1064 } else {
1065 src = BWI_CLKSRC_CS_OSC;
1066 div = 32;
1067 }
1068 } else if (com->rw_rev < 10) {
1069 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1070
1071 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1072 if (src == BWI_CLKSRC_LP_OSC) {
1073 div = 1;
1074 } else {
1075 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1076
1077 /* Unknown source */
1078 if (src >= BWI_CLKSRC_MAX)
1079 src = BWI_CLKSRC_CS_OSC;
1080 }
1081 } else {
1082 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1083
1084 src = BWI_CLKSRC_CS_OSC;
1085 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1086 }
1087
1088 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src));
1089 KASSERT(div != 0, ("div zero"));
1090
1091 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1092 src == BWI_CLKSRC_PCI ? "PCI" :
1093 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1094
1095 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1096 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1097
1098 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1099 freq->clkfreq_min, freq->clkfreq_max);
1100 }
1101
1102 static int
bwi_set_clock_mode(struct bwi_softc * sc,enum bwi_clock_mode clk_mode)1103 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1104 {
1105 struct bwi_regwin *old, *com;
1106 uint32_t clk_ctrl, clk_src;
1107 int error, pwr_off = 0;
1108
1109 com = &sc->sc_com_regwin;
1110 if (!BWI_REGWIN_EXIST(com))
1111 return 0;
1112
1113 if (com->rw_rev >= 10 || com->rw_rev < 6)
1114 return 0;
1115
1116 /*
1117 * For common regwin whose rev is [6, 10), the chip
1118 * must be capable to change clock mode.
1119 */
1120 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1121 return 0;
1122
1123 error = bwi_regwin_switch(sc, com, &old);
1124 if (error)
1125 return error;
1126
1127 if (clk_mode == BWI_CLOCK_MODE_FAST)
1128 bwi_power_on(sc, 0); /* Don't turn on PLL */
1129
1130 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1131 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1132
1133 switch (clk_mode) {
1134 case BWI_CLOCK_MODE_FAST:
1135 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1136 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1137 break;
1138 case BWI_CLOCK_MODE_SLOW:
1139 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1140 break;
1141 case BWI_CLOCK_MODE_DYN:
1142 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1143 BWI_CLOCK_CTRL_IGNPLL |
1144 BWI_CLOCK_CTRL_NODYN);
1145 if (clk_src != BWI_CLKSRC_CS_OSC) {
1146 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1147 pwr_off = 1;
1148 }
1149 break;
1150 }
1151 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1152
1153 if (pwr_off)
1154 bwi_power_off(sc, 0); /* Leave PLL as it is */
1155
1156 return bwi_regwin_switch(sc, old, NULL);
1157 }
1158
1159 static int
bwi_set_clock_delay(struct bwi_softc * sc)1160 bwi_set_clock_delay(struct bwi_softc *sc)
1161 {
1162 struct bwi_regwin *old, *com;
1163 int error;
1164
1165 com = &sc->sc_com_regwin;
1166 if (!BWI_REGWIN_EXIST(com))
1167 return 0;
1168
1169 error = bwi_regwin_switch(sc, com, &old);
1170 if (error)
1171 return error;
1172
1173 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1174 if (sc->sc_bbp_rev == 0)
1175 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1176 else if (sc->sc_bbp_rev == 1)
1177 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1178 }
1179
1180 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1181 if (com->rw_rev >= 10) {
1182 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1183 } else {
1184 struct bwi_clock_freq freq;
1185
1186 bwi_get_clock_freq(sc, &freq);
1187 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1188 howmany(freq.clkfreq_max * 150, 1000000));
1189 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1190 howmany(freq.clkfreq_max * 15, 1000000));
1191 }
1192 }
1193
1194 return bwi_regwin_switch(sc, old, NULL);
1195 }
1196
1197 static void
bwi_init(struct bwi_softc * sc)1198 bwi_init(struct bwi_softc *sc)
1199 {
1200 struct ieee80211com *ic = &sc->sc_ic;
1201
1202 BWI_LOCK(sc);
1203 bwi_init_statechg(sc, 1);
1204 BWI_UNLOCK(sc);
1205
1206 if (sc->sc_flags & BWI_F_RUNNING)
1207 ieee80211_start_all(ic); /* start all vap's */
1208 }
1209
1210 static void
bwi_init_statechg(struct bwi_softc * sc,int statechg)1211 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1212 {
1213 struct bwi_mac *mac;
1214 int error;
1215
1216 BWI_ASSERT_LOCKED(sc);
1217
1218 bwi_stop_locked(sc, statechg);
1219
1220 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1221
1222 /* TODO: 2 MAC */
1223
1224 mac = &sc->sc_mac[0];
1225 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1226 if (error) {
1227 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n",
1228 __func__, error);
1229 goto bad;
1230 }
1231 error = bwi_mac_init(mac);
1232 if (error) {
1233 device_printf(sc->sc_dev, "%s: error %d on MAC init\n",
1234 __func__, error);
1235 goto bad;
1236 }
1237
1238 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1239
1240 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1241 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr);
1242
1243 bwi_mac_reset_hwkeys(mac);
1244
1245 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1246 int i;
1247
1248 #define NRETRY 1000
1249 /*
1250 * Drain any possible pending TX status
1251 */
1252 for (i = 0; i < NRETRY; ++i) {
1253 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1254 BWI_TXSTATUS0_VALID) == 0)
1255 break;
1256 CSR_READ_4(sc, BWI_TXSTATUS1);
1257 }
1258 if (i == NRETRY)
1259 device_printf(sc->sc_dev,
1260 "%s: can't drain TX status\n", __func__);
1261 #undef NRETRY
1262 }
1263
1264 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1265 bwi_mac_updateslot(mac, 1);
1266
1267 /* Start MAC */
1268 error = bwi_mac_start(mac);
1269 if (error) {
1270 device_printf(sc->sc_dev, "%s: error %d starting MAC\n",
1271 __func__, error);
1272 goto bad;
1273 }
1274
1275 /* Clear stop flag before enabling interrupt */
1276 sc->sc_flags &= ~BWI_F_STOP;
1277 sc->sc_flags |= BWI_F_RUNNING;
1278 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1279
1280 /* Enable intrs */
1281 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1282 return;
1283 bad:
1284 bwi_stop_locked(sc, 1);
1285 }
1286
1287 static void
bwi_parent(struct ieee80211com * ic)1288 bwi_parent(struct ieee80211com *ic)
1289 {
1290 struct bwi_softc *sc = ic->ic_softc;
1291 int startall = 0;
1292
1293 BWI_LOCK(sc);
1294 if (ic->ic_nrunning > 0) {
1295 struct bwi_mac *mac;
1296 int promisc = -1;
1297
1298 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1299 ("current regwin type %d",
1300 sc->sc_cur_regwin->rw_type));
1301 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1302
1303 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) {
1304 promisc = 1;
1305 sc->sc_flags |= BWI_F_PROMISC;
1306 } else if (ic->ic_promisc == 0 &&
1307 (sc->sc_flags & BWI_F_PROMISC) != 0) {
1308 promisc = 0;
1309 sc->sc_flags &= ~BWI_F_PROMISC;
1310 }
1311
1312 if (promisc >= 0)
1313 bwi_mac_set_promisc(mac, promisc);
1314 }
1315 if (ic->ic_nrunning > 0) {
1316 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1317 bwi_init_statechg(sc, 1);
1318 startall = 1;
1319 }
1320 } else if (sc->sc_flags & BWI_F_RUNNING)
1321 bwi_stop_locked(sc, 1);
1322 BWI_UNLOCK(sc);
1323 if (startall)
1324 ieee80211_start_all(ic);
1325 }
1326
1327 static int
bwi_transmit(struct ieee80211com * ic,struct mbuf * m)1328 bwi_transmit(struct ieee80211com *ic, struct mbuf *m)
1329 {
1330 struct bwi_softc *sc = ic->ic_softc;
1331 int error;
1332
1333 BWI_LOCK(sc);
1334 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1335 BWI_UNLOCK(sc);
1336 return (ENXIO);
1337 }
1338 error = mbufq_enqueue(&sc->sc_snd, m);
1339 if (error) {
1340 BWI_UNLOCK(sc);
1341 return (error);
1342 }
1343 bwi_start_locked(sc);
1344 BWI_UNLOCK(sc);
1345 return (0);
1346 }
1347
1348 static void
bwi_start_locked(struct bwi_softc * sc)1349 bwi_start_locked(struct bwi_softc *sc)
1350 {
1351 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1352 struct ieee80211_frame *wh;
1353 struct ieee80211_node *ni;
1354 struct mbuf *m;
1355 int trans, idx;
1356
1357 BWI_ASSERT_LOCKED(sc);
1358
1359 trans = 0;
1360 idx = tbd->tbd_idx;
1361
1362 while (tbd->tbd_buf[idx].tb_mbuf == NULL &&
1363 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC &&
1364 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1365 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1366 wh = mtod(m, struct ieee80211_frame *);
1367 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 &&
1368 ieee80211_crypto_encap(ni, m) == NULL) {
1369 if_inc_counter(ni->ni_vap->iv_ifp,
1370 IFCOUNTER_OERRORS, 1);
1371 ieee80211_free_node(ni);
1372 m_freem(m);
1373 continue;
1374 }
1375 if (bwi_encap(sc, idx, m, ni) != 0) {
1376 /* 'm' is freed in bwi_encap() if we reach here */
1377 if (ni != NULL) {
1378 if_inc_counter(ni->ni_vap->iv_ifp,
1379 IFCOUNTER_OERRORS, 1);
1380 ieee80211_free_node(ni);
1381 } else
1382 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1383 continue;
1384 }
1385 trans = 1;
1386 tbd->tbd_used++;
1387 idx = (idx + 1) % BWI_TX_NDESC;
1388 }
1389
1390 tbd->tbd_idx = idx;
1391 if (trans)
1392 sc->sc_tx_timer = 5;
1393 }
1394
1395 static int
bwi_raw_xmit(struct ieee80211_node * ni,struct mbuf * m,const struct ieee80211_bpf_params * params)1396 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1397 const struct ieee80211_bpf_params *params)
1398 {
1399 struct ieee80211com *ic = ni->ni_ic;
1400 struct bwi_softc *sc = ic->ic_softc;
1401 /* XXX wme? */
1402 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1403 int idx, error;
1404
1405 if ((sc->sc_flags & BWI_F_RUNNING) == 0) {
1406 m_freem(m);
1407 return ENETDOWN;
1408 }
1409
1410 BWI_LOCK(sc);
1411 idx = tbd->tbd_idx;
1412 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx));
1413 if (params == NULL) {
1414 /*
1415 * Legacy path; interpret frame contents to decide
1416 * precisely how to send the frame.
1417 */
1418 error = bwi_encap(sc, idx, m, ni);
1419 } else {
1420 /*
1421 * Caller supplied explicit parameters to use in
1422 * sending the frame.
1423 */
1424 error = bwi_encap_raw(sc, idx, m, ni, params);
1425 }
1426 if (error == 0) {
1427 tbd->tbd_used++;
1428 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC;
1429 sc->sc_tx_timer = 5;
1430 }
1431 BWI_UNLOCK(sc);
1432 return error;
1433 }
1434
1435 static void
bwi_watchdog(void * arg)1436 bwi_watchdog(void *arg)
1437 {
1438 struct bwi_softc *sc;
1439
1440 sc = arg;
1441 BWI_ASSERT_LOCKED(sc);
1442 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) {
1443 device_printf(sc->sc_dev, "watchdog timeout\n");
1444 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1445 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1446 }
1447 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1448 }
1449
1450 static void
bwi_stop(struct bwi_softc * sc,int statechg)1451 bwi_stop(struct bwi_softc *sc, int statechg)
1452 {
1453 BWI_LOCK(sc);
1454 bwi_stop_locked(sc, statechg);
1455 BWI_UNLOCK(sc);
1456 }
1457
1458 static void
bwi_stop_locked(struct bwi_softc * sc,int statechg)1459 bwi_stop_locked(struct bwi_softc *sc, int statechg)
1460 {
1461 struct bwi_mac *mac;
1462 int i, error, pwr_off = 0;
1463
1464 BWI_ASSERT_LOCKED(sc);
1465
1466 callout_stop(&sc->sc_calib_ch);
1467 callout_stop(&sc->sc_led_blink_ch);
1468 sc->sc_led_blinking = 0;
1469 sc->sc_flags |= BWI_F_STOP;
1470
1471 if (sc->sc_flags & BWI_F_RUNNING) {
1472 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1473 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1474 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1475
1476 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1477 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1478 bwi_mac_stop(mac);
1479 }
1480
1481 for (i = 0; i < sc->sc_nmac; ++i) {
1482 struct bwi_regwin *old_rw;
1483
1484 mac = &sc->sc_mac[i];
1485 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1486 continue;
1487
1488 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1489 if (error)
1490 continue;
1491
1492 bwi_mac_shutdown(mac);
1493 pwr_off = 1;
1494
1495 bwi_regwin_switch(sc, old_rw, NULL);
1496 }
1497
1498 if (pwr_off)
1499 bwi_bbp_power_off(sc);
1500
1501 sc->sc_tx_timer = 0;
1502 callout_stop(&sc->sc_watchdog_timer);
1503 sc->sc_flags &= ~BWI_F_RUNNING;
1504 }
1505
1506 void
bwi_intr(void * xsc)1507 bwi_intr(void *xsc)
1508 {
1509 struct bwi_softc *sc = xsc;
1510 struct bwi_mac *mac;
1511 uint32_t intr_status;
1512 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1513 int i, txrx_error, tx = 0, rx_data = -1;
1514
1515 BWI_LOCK(sc);
1516
1517 if ((sc->sc_flags & BWI_F_RUNNING) == 0 ||
1518 (sc->sc_flags & BWI_F_STOP)) {
1519 BWI_UNLOCK(sc);
1520 return;
1521 }
1522 /*
1523 * Get interrupt status
1524 */
1525 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1526 if (intr_status == 0xffffffff) { /* Not for us */
1527 BWI_UNLOCK(sc);
1528 return;
1529 }
1530
1531 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1532
1533 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1534 if (intr_status == 0) { /* Nothing is interesting */
1535 BWI_UNLOCK(sc);
1536 return;
1537 }
1538
1539 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1540 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1541 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1542
1543 txrx_error = 0;
1544 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1545 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1546 uint32_t mask;
1547
1548 if (BWI_TXRX_IS_RX(i))
1549 mask = BWI_TXRX_RX_INTRS;
1550 else
1551 mask = BWI_TXRX_TX_INTRS;
1552
1553 txrx_intr_status[i] =
1554 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1555
1556 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1557 i, txrx_intr_status[i]);
1558
1559 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1560 device_printf(sc->sc_dev,
1561 "%s: intr fatal TX/RX (%d) error 0x%08x\n",
1562 __func__, i, txrx_intr_status[i]);
1563 txrx_error = 1;
1564 }
1565 }
1566 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1567
1568 /*
1569 * Acknowledge interrupt
1570 */
1571 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1572
1573 for (i = 0; i < BWI_TXRX_NRING; ++i)
1574 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1575
1576 /* Disable all interrupts */
1577 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1578
1579 /*
1580 * http://bcm-specs.sipsolutions.net/Interrupts
1581 * Says for this bit (0x800):
1582 * "Fatal Error
1583 *
1584 * We got this one while testing things when by accident the
1585 * template ram wasn't set to big endian when it should have
1586 * been after writing the initial values. It keeps on being
1587 * triggered, the only way to stop it seems to shut down the
1588 * chip."
1589 *
1590 * Suggesting that we should never get it and if we do we're not
1591 * feeding TX packets into the MAC correctly if we do... Apparently,
1592 * it is valid only on mac version 5 and higher, but I couldn't
1593 * find a reference for that... Since I see them from time to time
1594 * on my card, this suggests an error in the tx path still...
1595 */
1596 if (intr_status & BWI_INTR_PHY_TXERR) {
1597 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1598 device_printf(sc->sc_dev, "%s: intr PHY TX error\n",
1599 __func__);
1600 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1601 BWI_UNLOCK(sc);
1602 return;
1603 }
1604 }
1605
1606 if (txrx_error) {
1607 /* TODO: reset device */
1608 }
1609
1610 if (intr_status & BWI_INTR_TBTT)
1611 bwi_mac_config_ps(mac);
1612
1613 if (intr_status & BWI_INTR_EO_ATIM)
1614 device_printf(sc->sc_dev, "EO_ATIM\n");
1615
1616 if (intr_status & BWI_INTR_PMQ) {
1617 for (;;) {
1618 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1619 break;
1620 }
1621 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1622 }
1623
1624 if (intr_status & BWI_INTR_NOISE)
1625 device_printf(sc->sc_dev, "intr noise\n");
1626
1627 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) {
1628 rx_data = sc->sc_rxeof(sc);
1629 if (sc->sc_flags & BWI_F_STOP) {
1630 BWI_UNLOCK(sc);
1631 return;
1632 }
1633 }
1634
1635 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1636 sc->sc_txeof_status(sc);
1637 tx = 1;
1638 }
1639
1640 if (intr_status & BWI_INTR_TX_DONE) {
1641 bwi_txeof(sc);
1642 tx = 1;
1643 }
1644
1645 /* Re-enable interrupts */
1646 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1647
1648 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1649 int evt = BWI_LED_EVENT_NONE;
1650
1651 if (tx && rx_data > 0) {
1652 if (sc->sc_rx_rate > sc->sc_tx_rate)
1653 evt = BWI_LED_EVENT_RX;
1654 else
1655 evt = BWI_LED_EVENT_TX;
1656 } else if (tx) {
1657 evt = BWI_LED_EVENT_TX;
1658 } else if (rx_data > 0) {
1659 evt = BWI_LED_EVENT_RX;
1660 } else if (rx_data == 0) {
1661 evt = BWI_LED_EVENT_POLL;
1662 }
1663
1664 if (evt != BWI_LED_EVENT_NONE)
1665 bwi_led_event(sc, evt);
1666 }
1667
1668 BWI_UNLOCK(sc);
1669 }
1670
1671 static void
bwi_scan_start(struct ieee80211com * ic)1672 bwi_scan_start(struct ieee80211com *ic)
1673 {
1674 struct bwi_softc *sc = ic->ic_softc;
1675
1676 BWI_LOCK(sc);
1677 /* Enable MAC beacon promiscuity */
1678 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1679 BWI_UNLOCK(sc);
1680 }
1681
1682 static void
bwi_getradiocaps(struct ieee80211com * ic,int maxchans,int * nchans,struct ieee80211_channel chans[])1683 bwi_getradiocaps(struct ieee80211com *ic,
1684 int maxchans, int *nchans, struct ieee80211_channel chans[])
1685 {
1686 struct bwi_softc *sc = ic->ic_softc;
1687 struct bwi_mac *mac;
1688 struct bwi_phy *phy;
1689 uint8_t bands[IEEE80211_MODE_BYTES];
1690
1691 /*
1692 * XXX First MAC is known to exist
1693 * TODO2
1694 */
1695 mac = &sc->sc_mac[0];
1696 phy = &mac->mac_phy;
1697
1698 memset(bands, 0, sizeof(bands));
1699 switch (phy->phy_mode) {
1700 case IEEE80211_MODE_11G:
1701 setbit(bands, IEEE80211_MODE_11G);
1702 /* FALLTHROUGH */
1703 case IEEE80211_MODE_11B:
1704 setbit(bands, IEEE80211_MODE_11B);
1705 break;
1706 case IEEE80211_MODE_11A:
1707 /* TODO:11A */
1708 setbit(bands, IEEE80211_MODE_11A);
1709 device_printf(sc->sc_dev, "no 11a support\n");
1710 return;
1711 default:
1712 panic("unknown phymode %d\n", phy->phy_mode);
1713 }
1714
1715 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
1716 }
1717
1718 static void
bwi_set_channel(struct ieee80211com * ic)1719 bwi_set_channel(struct ieee80211com *ic)
1720 {
1721 struct bwi_softc *sc = ic->ic_softc;
1722 struct ieee80211_channel *c = ic->ic_curchan;
1723 struct bwi_mac *mac;
1724
1725 BWI_LOCK(sc);
1726 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1727 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1728 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1729 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0);
1730
1731 sc->sc_rates = ieee80211_get_ratetable(c);
1732 BWI_UNLOCK(sc);
1733 }
1734
1735 static void
bwi_scan_end(struct ieee80211com * ic)1736 bwi_scan_end(struct ieee80211com *ic)
1737 {
1738 struct bwi_softc *sc = ic->ic_softc;
1739
1740 BWI_LOCK(sc);
1741 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1742 BWI_UNLOCK(sc);
1743 }
1744
1745 static int
bwi_newstate(struct ieee80211vap * vap,enum ieee80211_state nstate,int arg)1746 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1747 {
1748 struct bwi_vap *bvp = BWI_VAP(vap);
1749 struct ieee80211com *ic= vap->iv_ic;
1750 struct bwi_softc *sc = ic->ic_softc;
1751 enum ieee80211_state ostate = vap->iv_state;
1752 struct bwi_mac *mac;
1753 int error;
1754
1755 BWI_LOCK(sc);
1756
1757 callout_stop(&sc->sc_calib_ch);
1758
1759 if (nstate == IEEE80211_S_INIT)
1760 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1761
1762 bwi_led_newstate(sc, nstate);
1763
1764 error = bvp->bv_newstate(vap, nstate, arg);
1765 if (error != 0)
1766 goto back;
1767
1768 /*
1769 * Clear the BSSID when we stop a STA
1770 */
1771 if (vap->iv_opmode == IEEE80211_M_STA) {
1772 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
1773 /*
1774 * Clear out the BSSID. If we reassociate to
1775 * the same AP, this will reinialize things
1776 * correctly...
1777 */
1778 if (ic->ic_opmode == IEEE80211_M_STA &&
1779 !(sc->sc_flags & BWI_F_STOP))
1780 bwi_set_bssid(sc, bwi_zero_addr);
1781 }
1782 }
1783
1784 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1785 /* Nothing to do */
1786 } else if (nstate == IEEE80211_S_RUN) {
1787 bwi_set_bssid(sc, vap->iv_bss->ni_bssid);
1788
1789 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1790 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1791 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1792
1793 /* Initial TX power calibration */
1794 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1795 #ifdef notyet
1796 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1797 #else
1798 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1799 #endif
1800
1801 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1802 }
1803 back:
1804 BWI_UNLOCK(sc);
1805
1806 return error;
1807 }
1808
1809 static int
bwi_media_change(struct ifnet * ifp)1810 bwi_media_change(struct ifnet *ifp)
1811 {
1812 int error = ieee80211_media_change(ifp);
1813 /* NB: only the fixed rate can change and that doesn't need a reset */
1814 return (error == ENETRESET ? 0 : error);
1815 }
1816
1817 static int
bwi_dma_alloc(struct bwi_softc * sc)1818 bwi_dma_alloc(struct bwi_softc *sc)
1819 {
1820 int error, i, has_txstats;
1821 bus_addr_t lowaddr = 0;
1822 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1823 uint32_t txrx_ctrl_step = 0;
1824
1825 has_txstats = 0;
1826 for (i = 0; i < sc->sc_nmac; ++i) {
1827 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1828 has_txstats = 1;
1829 break;
1830 }
1831 }
1832
1833 switch (sc->sc_bus_space) {
1834 case BWI_BUS_SPACE_30BIT:
1835 case BWI_BUS_SPACE_32BIT:
1836 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1837 lowaddr = BWI_BUS_SPACE_MAXADDR;
1838 else
1839 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1840 desc_sz = sizeof(struct bwi_desc32);
1841 txrx_ctrl_step = 0x20;
1842
1843 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1844 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1845 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1846 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1847 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1848 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1849 sc->sc_rxeof = bwi_rxeof32;
1850 sc->sc_start_tx = bwi_start_tx32;
1851 if (has_txstats) {
1852 sc->sc_init_txstats = bwi_init_txstats32;
1853 sc->sc_free_txstats = bwi_free_txstats32;
1854 sc->sc_txeof_status = bwi_txeof_status32;
1855 }
1856 break;
1857
1858 case BWI_BUS_SPACE_64BIT:
1859 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1860 desc_sz = sizeof(struct bwi_desc64);
1861 txrx_ctrl_step = 0x40;
1862
1863 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1864 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1865 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1866 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1867 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1868 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1869 sc->sc_rxeof = bwi_rxeof64;
1870 sc->sc_start_tx = bwi_start_tx64;
1871 if (has_txstats) {
1872 sc->sc_init_txstats = bwi_init_txstats64;
1873 sc->sc_free_txstats = bwi_free_txstats64;
1874 sc->sc_txeof_status = bwi_txeof_status64;
1875 }
1876 break;
1877 }
1878
1879 KASSERT(lowaddr != 0, ("lowaddr zero"));
1880 KASSERT(desc_sz != 0, ("desc_sz zero"));
1881 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero"));
1882
1883 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1884 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1885
1886 /*
1887 * Create top level DMA tag
1888 */
1889 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1890 BWI_ALIGN, 0, /* alignment, bounds */
1891 lowaddr, /* lowaddr */
1892 BUS_SPACE_MAXADDR, /* highaddr */
1893 NULL, NULL, /* filter, filterarg */
1894 BUS_SPACE_MAXSIZE, /* maxsize */
1895 BUS_SPACE_UNRESTRICTED, /* nsegments */
1896 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1897 0, /* flags */
1898 NULL, NULL, /* lockfunc, lockarg */
1899 &sc->sc_parent_dtag);
1900 if (error) {
1901 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
1902 return error;
1903 }
1904
1905 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
1906
1907 /*
1908 * Create TX ring DMA stuffs
1909 */
1910 error = bus_dma_tag_create(sc->sc_parent_dtag,
1911 BWI_RING_ALIGN, 0,
1912 BUS_SPACE_MAXADDR,
1913 BUS_SPACE_MAXADDR,
1914 NULL, NULL,
1915 tx_ring_sz,
1916 1,
1917 tx_ring_sz,
1918 0,
1919 NULL, NULL,
1920 &sc->sc_txring_dtag);
1921 if (error) {
1922 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
1923 return error;
1924 }
1925
1926 for (i = 0; i < BWI_TX_NRING; ++i) {
1927 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
1928 &sc->sc_tx_rdata[i], tx_ring_sz,
1929 TXRX_CTRL(i));
1930 if (error) {
1931 device_printf(sc->sc_dev, "%dth TX ring "
1932 "DMA alloc failed\n", i);
1933 return error;
1934 }
1935 }
1936
1937 /*
1938 * Create RX ring DMA stuffs
1939 */
1940 error = bus_dma_tag_create(sc->sc_parent_dtag,
1941 BWI_RING_ALIGN, 0,
1942 BUS_SPACE_MAXADDR,
1943 BUS_SPACE_MAXADDR,
1944 NULL, NULL,
1945 rx_ring_sz,
1946 1,
1947 rx_ring_sz,
1948 0,
1949 NULL, NULL,
1950 &sc->sc_rxring_dtag);
1951 if (error) {
1952 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
1953 return error;
1954 }
1955
1956 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
1957 rx_ring_sz, TXRX_CTRL(0));
1958 if (error) {
1959 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
1960 return error;
1961 }
1962
1963 if (has_txstats) {
1964 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
1965 if (error) {
1966 device_printf(sc->sc_dev,
1967 "TX stats DMA alloc failed\n");
1968 return error;
1969 }
1970 }
1971
1972 #undef TXRX_CTRL
1973
1974 return bwi_dma_mbuf_create(sc);
1975 }
1976
1977 static void
bwi_dma_free(struct bwi_softc * sc)1978 bwi_dma_free(struct bwi_softc *sc)
1979 {
1980 if (sc->sc_txring_dtag != NULL) {
1981 int i;
1982
1983 for (i = 0; i < BWI_TX_NRING; ++i) {
1984 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
1985
1986 if (rd->rdata_desc != NULL) {
1987 bus_dmamap_unload(sc->sc_txring_dtag,
1988 rd->rdata_dmap);
1989 bus_dmamem_free(sc->sc_txring_dtag,
1990 rd->rdata_desc,
1991 rd->rdata_dmap);
1992 }
1993 }
1994 bus_dma_tag_destroy(sc->sc_txring_dtag);
1995 }
1996
1997 if (sc->sc_rxring_dtag != NULL) {
1998 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
1999
2000 if (rd->rdata_desc != NULL) {
2001 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2002 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2003 rd->rdata_dmap);
2004 }
2005 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2006 }
2007
2008 bwi_dma_txstats_free(sc);
2009 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2010
2011 if (sc->sc_parent_dtag != NULL)
2012 bus_dma_tag_destroy(sc->sc_parent_dtag);
2013 }
2014
2015 static int
bwi_dma_ring_alloc(struct bwi_softc * sc,bus_dma_tag_t dtag,struct bwi_ring_data * rd,bus_size_t size,uint32_t txrx_ctrl)2016 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2017 struct bwi_ring_data *rd, bus_size_t size,
2018 uint32_t txrx_ctrl)
2019 {
2020 int error;
2021
2022 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2023 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2024 &rd->rdata_dmap);
2025 if (error) {
2026 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2027 return error;
2028 }
2029
2030 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2031 bwi_dma_ring_addr, &rd->rdata_paddr,
2032 BUS_DMA_NOWAIT);
2033 if (error) {
2034 device_printf(sc->sc_dev, "can't load DMA mem\n");
2035 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2036 rd->rdata_desc = NULL;
2037 return error;
2038 }
2039
2040 rd->rdata_txrx_ctrl = txrx_ctrl;
2041 return 0;
2042 }
2043
2044 static int
bwi_dma_txstats_alloc(struct bwi_softc * sc,uint32_t ctrl_base,bus_size_t desc_sz)2045 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2046 bus_size_t desc_sz)
2047 {
2048 struct bwi_txstats_data *st;
2049 bus_size_t dma_size;
2050 int error;
2051
2052 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO);
2053 if (st == NULL) {
2054 device_printf(sc->sc_dev, "can't allocate txstats data\n");
2055 return ENOMEM;
2056 }
2057 sc->sc_txstats = st;
2058
2059 /*
2060 * Create TX stats descriptor DMA stuffs
2061 */
2062 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2063
2064 error = bus_dma_tag_create(sc->sc_parent_dtag,
2065 BWI_RING_ALIGN,
2066 0,
2067 BUS_SPACE_MAXADDR,
2068 BUS_SPACE_MAXADDR,
2069 NULL, NULL,
2070 dma_size,
2071 1,
2072 dma_size,
2073 0,
2074 NULL, NULL,
2075 &st->stats_ring_dtag);
2076 if (error) {
2077 device_printf(sc->sc_dev, "can't create txstats ring "
2078 "DMA tag\n");
2079 return error;
2080 }
2081
2082 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2083 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2084 &st->stats_ring_dmap);
2085 if (error) {
2086 device_printf(sc->sc_dev, "can't allocate txstats ring "
2087 "DMA mem\n");
2088 bus_dma_tag_destroy(st->stats_ring_dtag);
2089 st->stats_ring_dtag = NULL;
2090 return error;
2091 }
2092
2093 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2094 st->stats_ring, dma_size,
2095 bwi_dma_ring_addr, &st->stats_ring_paddr,
2096 BUS_DMA_NOWAIT);
2097 if (error) {
2098 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2099 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2100 st->stats_ring_dmap);
2101 bus_dma_tag_destroy(st->stats_ring_dtag);
2102 st->stats_ring_dtag = NULL;
2103 return error;
2104 }
2105
2106 /*
2107 * Create TX stats DMA stuffs
2108 */
2109 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2110 BWI_ALIGN);
2111
2112 error = bus_dma_tag_create(sc->sc_parent_dtag,
2113 BWI_ALIGN,
2114 0,
2115 BUS_SPACE_MAXADDR,
2116 BUS_SPACE_MAXADDR,
2117 NULL, NULL,
2118 dma_size,
2119 1,
2120 dma_size,
2121 0,
2122 NULL, NULL,
2123 &st->stats_dtag);
2124 if (error) {
2125 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2126 return error;
2127 }
2128
2129 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2130 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2131 &st->stats_dmap);
2132 if (error) {
2133 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2134 bus_dma_tag_destroy(st->stats_dtag);
2135 st->stats_dtag = NULL;
2136 return error;
2137 }
2138
2139 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2140 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2141 BUS_DMA_NOWAIT);
2142 if (error) {
2143 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2144 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2145 bus_dma_tag_destroy(st->stats_dtag);
2146 st->stats_dtag = NULL;
2147 return error;
2148 }
2149
2150 st->stats_ctrl_base = ctrl_base;
2151 return 0;
2152 }
2153
2154 static void
bwi_dma_txstats_free(struct bwi_softc * sc)2155 bwi_dma_txstats_free(struct bwi_softc *sc)
2156 {
2157 struct bwi_txstats_data *st;
2158
2159 if (sc->sc_txstats == NULL)
2160 return;
2161 st = sc->sc_txstats;
2162
2163 if (st->stats_ring_dtag != NULL) {
2164 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2165 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2166 st->stats_ring_dmap);
2167 bus_dma_tag_destroy(st->stats_ring_dtag);
2168 }
2169
2170 if (st->stats_dtag != NULL) {
2171 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2172 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2173 bus_dma_tag_destroy(st->stats_dtag);
2174 }
2175
2176 free(st, M_DEVBUF);
2177 }
2178
2179 static void
bwi_dma_ring_addr(void * arg,bus_dma_segment_t * seg,int nseg,int error)2180 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2181 {
2182 KASSERT(nseg == 1, ("too many segments\n"));
2183 *((bus_addr_t *)arg) = seg->ds_addr;
2184 }
2185
2186 static int
bwi_dma_mbuf_create(struct bwi_softc * sc)2187 bwi_dma_mbuf_create(struct bwi_softc *sc)
2188 {
2189 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2190 int i, j, k, ntx, error;
2191
2192 /*
2193 * Create TX/RX mbuf DMA tag
2194 */
2195 error = bus_dma_tag_create(sc->sc_parent_dtag,
2196 1,
2197 0,
2198 BUS_SPACE_MAXADDR,
2199 BUS_SPACE_MAXADDR,
2200 NULL, NULL,
2201 MCLBYTES,
2202 1,
2203 MCLBYTES,
2204 BUS_DMA_ALLOCNOW,
2205 NULL, NULL,
2206 &sc->sc_buf_dtag);
2207 if (error) {
2208 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2209 return error;
2210 }
2211
2212 ntx = 0;
2213
2214 /*
2215 * Create TX mbuf DMA map
2216 */
2217 for (i = 0; i < BWI_TX_NRING; ++i) {
2218 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2219
2220 for (j = 0; j < BWI_TX_NDESC; ++j) {
2221 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2222 &tbd->tbd_buf[j].tb_dmap);
2223 if (error) {
2224 device_printf(sc->sc_dev, "can't create "
2225 "%dth tbd, %dth DMA map\n", i, j);
2226
2227 ntx = i;
2228 for (k = 0; k < j; ++k) {
2229 bus_dmamap_destroy(sc->sc_buf_dtag,
2230 tbd->tbd_buf[k].tb_dmap);
2231 }
2232 goto fail;
2233 }
2234 }
2235 }
2236 ntx = BWI_TX_NRING;
2237
2238 /*
2239 * Create RX mbuf DMA map and a spare DMA map
2240 */
2241 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2242 &rbd->rbd_tmp_dmap);
2243 if (error) {
2244 device_printf(sc->sc_dev,
2245 "can't create spare RX buf DMA map\n");
2246 goto fail;
2247 }
2248
2249 for (j = 0; j < BWI_RX_NDESC; ++j) {
2250 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2251 &rbd->rbd_buf[j].rb_dmap);
2252 if (error) {
2253 device_printf(sc->sc_dev, "can't create %dth "
2254 "RX buf DMA map\n", j);
2255
2256 for (k = 0; k < j; ++k) {
2257 bus_dmamap_destroy(sc->sc_buf_dtag,
2258 rbd->rbd_buf[j].rb_dmap);
2259 }
2260 bus_dmamap_destroy(sc->sc_buf_dtag,
2261 rbd->rbd_tmp_dmap);
2262 goto fail;
2263 }
2264 }
2265
2266 return 0;
2267 fail:
2268 bwi_dma_mbuf_destroy(sc, ntx, 0);
2269 return error;
2270 }
2271
2272 static void
bwi_dma_mbuf_destroy(struct bwi_softc * sc,int ntx,int nrx)2273 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2274 {
2275 int i, j;
2276
2277 if (sc->sc_buf_dtag == NULL)
2278 return;
2279
2280 for (i = 0; i < ntx; ++i) {
2281 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2282
2283 for (j = 0; j < BWI_TX_NDESC; ++j) {
2284 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2285
2286 if (tb->tb_mbuf != NULL) {
2287 bus_dmamap_unload(sc->sc_buf_dtag,
2288 tb->tb_dmap);
2289 m_freem(tb->tb_mbuf);
2290 }
2291 if (tb->tb_ni != NULL)
2292 ieee80211_free_node(tb->tb_ni);
2293 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2294 }
2295 }
2296
2297 if (nrx) {
2298 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2299
2300 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2301 for (j = 0; j < BWI_RX_NDESC; ++j) {
2302 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2303
2304 if (rb->rb_mbuf != NULL) {
2305 bus_dmamap_unload(sc->sc_buf_dtag,
2306 rb->rb_dmap);
2307 m_freem(rb->rb_mbuf);
2308 }
2309 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2310 }
2311 }
2312
2313 bus_dma_tag_destroy(sc->sc_buf_dtag);
2314 sc->sc_buf_dtag = NULL;
2315 }
2316
2317 static void
bwi_enable_intrs(struct bwi_softc * sc,uint32_t enable_intrs)2318 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2319 {
2320 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2321 }
2322
2323 static void
bwi_disable_intrs(struct bwi_softc * sc,uint32_t disable_intrs)2324 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2325 {
2326 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2327 }
2328
2329 static int
bwi_init_tx_ring32(struct bwi_softc * sc,int ring_idx)2330 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2331 {
2332 struct bwi_ring_data *rd;
2333 struct bwi_txbuf_data *tbd;
2334 uint32_t val, addr_hi, addr_lo;
2335
2336 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2337 rd = &sc->sc_tx_rdata[ring_idx];
2338 tbd = &sc->sc_tx_bdata[ring_idx];
2339
2340 tbd->tbd_idx = 0;
2341 tbd->tbd_used = 0;
2342
2343 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2344 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2345 BUS_DMASYNC_PREWRITE);
2346
2347 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2348 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2349
2350 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2351 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2352 BWI_TXRX32_RINGINFO_FUNC_MASK);
2353 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2354
2355 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2356 BWI_TXRX32_CTRL_ENABLE;
2357 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2358
2359 return 0;
2360 }
2361
2362 static void
bwi_init_rxdesc_ring32(struct bwi_softc * sc,uint32_t ctrl_base,bus_addr_t paddr,int hdr_size,int ndesc)2363 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2364 bus_addr_t paddr, int hdr_size, int ndesc)
2365 {
2366 uint32_t val, addr_hi, addr_lo;
2367
2368 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2369 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2370
2371 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2372 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2373 BWI_TXRX32_RINGINFO_FUNC_MASK);
2374 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2375
2376 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2377 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2378 BWI_TXRX32_CTRL_ENABLE;
2379 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2380
2381 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2382 (ndesc - 1) * sizeof(struct bwi_desc32));
2383 }
2384
2385 static int
bwi_init_rx_ring32(struct bwi_softc * sc)2386 bwi_init_rx_ring32(struct bwi_softc *sc)
2387 {
2388 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2389 int i, error;
2390
2391 sc->sc_rx_bdata.rbd_idx = 0;
2392
2393 for (i = 0; i < BWI_RX_NDESC; ++i) {
2394 error = bwi_newbuf(sc, i, 1);
2395 if (error) {
2396 device_printf(sc->sc_dev,
2397 "can't allocate %dth RX buffer\n", i);
2398 return error;
2399 }
2400 }
2401 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2402 BUS_DMASYNC_PREWRITE);
2403
2404 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2405 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2406 return 0;
2407 }
2408
2409 static int
bwi_init_txstats32(struct bwi_softc * sc)2410 bwi_init_txstats32(struct bwi_softc *sc)
2411 {
2412 struct bwi_txstats_data *st = sc->sc_txstats;
2413 bus_addr_t stats_paddr;
2414 int i;
2415
2416 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2417 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2418
2419 st->stats_idx = 0;
2420
2421 stats_paddr = st->stats_paddr;
2422 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2423 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2424 stats_paddr, sizeof(struct bwi_txstats), 0);
2425 stats_paddr += sizeof(struct bwi_txstats);
2426 }
2427 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2428 BUS_DMASYNC_PREWRITE);
2429
2430 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2431 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2432 return 0;
2433 }
2434
2435 static void
bwi_setup_rx_desc32(struct bwi_softc * sc,int buf_idx,bus_addr_t paddr,int buf_len)2436 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2437 int buf_len)
2438 {
2439 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2440
2441 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2442 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2443 paddr, buf_len, 0);
2444 }
2445
2446 static void
bwi_setup_tx_desc32(struct bwi_softc * sc,struct bwi_ring_data * rd,int buf_idx,bus_addr_t paddr,int buf_len)2447 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2448 int buf_idx, bus_addr_t paddr, int buf_len)
2449 {
2450 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
2451 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2452 paddr, buf_len, 1);
2453 }
2454
2455 static int
bwi_init_tx_ring64(struct bwi_softc * sc,int ring_idx)2456 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2457 {
2458 /* TODO:64 */
2459 return EOPNOTSUPP;
2460 }
2461
2462 static int
bwi_init_rx_ring64(struct bwi_softc * sc)2463 bwi_init_rx_ring64(struct bwi_softc *sc)
2464 {
2465 /* TODO:64 */
2466 return EOPNOTSUPP;
2467 }
2468
2469 static int
bwi_init_txstats64(struct bwi_softc * sc)2470 bwi_init_txstats64(struct bwi_softc *sc)
2471 {
2472 /* TODO:64 */
2473 return EOPNOTSUPP;
2474 }
2475
2476 static void
bwi_setup_rx_desc64(struct bwi_softc * sc,int buf_idx,bus_addr_t paddr,int buf_len)2477 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2478 int buf_len)
2479 {
2480 /* TODO:64 */
2481 }
2482
2483 static void
bwi_setup_tx_desc64(struct bwi_softc * sc,struct bwi_ring_data * rd,int buf_idx,bus_addr_t paddr,int buf_len)2484 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2485 int buf_idx, bus_addr_t paddr, int buf_len)
2486 {
2487 /* TODO:64 */
2488 }
2489
2490 static void
bwi_dma_buf_addr(void * arg,bus_dma_segment_t * seg,int nseg,bus_size_t mapsz __unused,int error)2491 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2492 bus_size_t mapsz __unused, int error)
2493 {
2494 if (!error) {
2495 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2496 *((bus_addr_t *)arg) = seg->ds_addr;
2497 }
2498 }
2499
2500 static int
bwi_newbuf(struct bwi_softc * sc,int buf_idx,int init)2501 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2502 {
2503 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2504 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2505 struct bwi_rxbuf_hdr *hdr;
2506 bus_dmamap_t map;
2507 bus_addr_t paddr;
2508 struct mbuf *m;
2509 int error;
2510
2511 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2512
2513 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2514 if (m == NULL) {
2515 error = ENOBUFS;
2516
2517 /*
2518 * If the NIC is up and running, we need to:
2519 * - Clear RX buffer's header.
2520 * - Restore RX descriptor settings.
2521 */
2522 if (init)
2523 return error;
2524 else
2525 goto back;
2526 }
2527 m->m_len = m->m_pkthdr.len = MCLBYTES;
2528
2529 /*
2530 * Try to load RX buf into temporary DMA map
2531 */
2532 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2533 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
2534 if (error) {
2535 m_freem(m);
2536
2537 /*
2538 * See the comment above
2539 */
2540 if (init)
2541 return error;
2542 else
2543 goto back;
2544 }
2545
2546 if (!init)
2547 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2548 rxbuf->rb_mbuf = m;
2549 rxbuf->rb_paddr = paddr;
2550
2551 /*
2552 * Swap RX buf's DMA map with the loaded temporary one
2553 */
2554 map = rxbuf->rb_dmap;
2555 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2556 rbd->rbd_tmp_dmap = map;
2557
2558 back:
2559 /*
2560 * Clear RX buf header
2561 */
2562 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2563 bzero(hdr, sizeof(*hdr));
2564 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2565
2566 /*
2567 * Setup RX buf descriptor
2568 */
2569 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2570 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2571 return error;
2572 }
2573
2574 static void
bwi_set_addr_filter(struct bwi_softc * sc,uint16_t addr_ofs,const uint8_t * addr)2575 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2576 const uint8_t *addr)
2577 {
2578 int i;
2579
2580 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2581 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2582
2583 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2584 uint16_t addr_val;
2585
2586 addr_val = (uint16_t)addr[i * 2] |
2587 (((uint16_t)addr[(i * 2) + 1]) << 8);
2588 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2589 }
2590 }
2591
2592 static int
bwi_rxeof(struct bwi_softc * sc,int end_idx)2593 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2594 {
2595 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2596 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2597 struct ieee80211com *ic = &sc->sc_ic;
2598 int idx, rx_data = 0;
2599
2600 idx = rbd->rbd_idx;
2601 while (idx != end_idx) {
2602 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2603 struct bwi_rxbuf_hdr *hdr;
2604 struct ieee80211_frame_min *wh;
2605 struct ieee80211_node *ni;
2606 struct mbuf *m;
2607 uint32_t plcp;
2608 uint16_t flags2;
2609 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate;
2610
2611 m = rb->rb_mbuf;
2612 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2613 BUS_DMASYNC_POSTREAD);
2614
2615 if (bwi_newbuf(sc, idx, 0)) {
2616 counter_u64_add(ic->ic_ierrors, 1);
2617 goto next;
2618 }
2619
2620 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2621 flags2 = le16toh(hdr->rxh_flags2);
2622
2623 hdr_extra = 0;
2624 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2625 hdr_extra = 2;
2626 wh_ofs = hdr_extra + 6; /* XXX magic number */
2627
2628 buflen = le16toh(hdr->rxh_buflen);
2629 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2630 device_printf(sc->sc_dev,
2631 "%s: zero length data, hdr_extra %d\n",
2632 __func__, hdr_extra);
2633 counter_u64_add(ic->ic_ierrors, 1);
2634 m_freem(m);
2635 goto next;
2636 }
2637
2638 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp));
2639 rssi = bwi_calc_rssi(sc, hdr);
2640 noise = bwi_calc_noise(sc);
2641
2642 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2643 m_adj(m, sizeof(*hdr) + wh_ofs);
2644
2645 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2646 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM);
2647 else
2648 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK);
2649
2650 /* RX radio tap */
2651 if (ieee80211_radiotap_active(ic))
2652 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise);
2653
2654 m_adj(m, -IEEE80211_CRC_LEN);
2655
2656 BWI_UNLOCK(sc);
2657
2658 wh = mtod(m, struct ieee80211_frame_min *);
2659 ni = ieee80211_find_rxnode(ic, wh);
2660 if (ni != NULL) {
2661 type = ieee80211_input(ni, m, rssi - noise, noise);
2662 ieee80211_free_node(ni);
2663 } else
2664 type = ieee80211_input_all(ic, m, rssi - noise, noise);
2665 if (type == IEEE80211_FC0_TYPE_DATA) {
2666 rx_data = 1;
2667 sc->sc_rx_rate = rate;
2668 }
2669
2670 BWI_LOCK(sc);
2671 next:
2672 idx = (idx + 1) % BWI_RX_NDESC;
2673
2674 if (sc->sc_flags & BWI_F_STOP) {
2675 /*
2676 * Take the fast lane, don't do
2677 * any damage to softc
2678 */
2679 return -1;
2680 }
2681 }
2682
2683 rbd->rbd_idx = idx;
2684 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2685 BUS_DMASYNC_PREWRITE);
2686
2687 return rx_data;
2688 }
2689
2690 static int
bwi_rxeof32(struct bwi_softc * sc)2691 bwi_rxeof32(struct bwi_softc *sc)
2692 {
2693 uint32_t val, rx_ctrl;
2694 int end_idx, rx_data;
2695
2696 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2697
2698 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2699 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2700 sizeof(struct bwi_desc32);
2701
2702 rx_data = bwi_rxeof(sc, end_idx);
2703 if (rx_data >= 0) {
2704 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2705 end_idx * sizeof(struct bwi_desc32));
2706 }
2707 return rx_data;
2708 }
2709
2710 static int
bwi_rxeof64(struct bwi_softc * sc)2711 bwi_rxeof64(struct bwi_softc *sc)
2712 {
2713 /* TODO:64 */
2714 return 0;
2715 }
2716
2717 static void
bwi_reset_rx_ring32(struct bwi_softc * sc,uint32_t rx_ctrl)2718 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2719 {
2720 int i;
2721
2722 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2723
2724 #define NRETRY 10
2725
2726 for (i = 0; i < NRETRY; ++i) {
2727 uint32_t status;
2728
2729 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2730 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2731 BWI_RX32_STATUS_STATE_DISABLED)
2732 break;
2733
2734 DELAY(1000);
2735 }
2736 if (i == NRETRY)
2737 device_printf(sc->sc_dev, "reset rx ring timedout\n");
2738
2739 #undef NRETRY
2740
2741 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2742 }
2743
2744 static void
bwi_free_txstats32(struct bwi_softc * sc)2745 bwi_free_txstats32(struct bwi_softc *sc)
2746 {
2747 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2748 }
2749
2750 static void
bwi_free_rx_ring32(struct bwi_softc * sc)2751 bwi_free_rx_ring32(struct bwi_softc *sc)
2752 {
2753 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2754 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2755 int i;
2756
2757 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2758
2759 for (i = 0; i < BWI_RX_NDESC; ++i) {
2760 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2761
2762 if (rb->rb_mbuf != NULL) {
2763 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2764 m_freem(rb->rb_mbuf);
2765 rb->rb_mbuf = NULL;
2766 }
2767 }
2768 }
2769
2770 static void
bwi_free_tx_ring32(struct bwi_softc * sc,int ring_idx)2771 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2772 {
2773 struct bwi_ring_data *rd;
2774 struct bwi_txbuf_data *tbd;
2775 uint32_t state, val;
2776 int i;
2777
2778 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2779 rd = &sc->sc_tx_rdata[ring_idx];
2780 tbd = &sc->sc_tx_bdata[ring_idx];
2781
2782 #define NRETRY 10
2783
2784 for (i = 0; i < NRETRY; ++i) {
2785 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2786 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2787 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2788 state == BWI_TX32_STATUS_STATE_IDLE ||
2789 state == BWI_TX32_STATUS_STATE_STOPPED)
2790 break;
2791
2792 DELAY(1000);
2793 }
2794 if (i == NRETRY) {
2795 device_printf(sc->sc_dev,
2796 "%s: wait for TX ring(%d) stable timed out\n",
2797 __func__, ring_idx);
2798 }
2799
2800 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2801 for (i = 0; i < NRETRY; ++i) {
2802 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2803 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2804 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2805 break;
2806
2807 DELAY(1000);
2808 }
2809 if (i == NRETRY)
2810 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n",
2811 __func__, ring_idx);
2812
2813 #undef NRETRY
2814
2815 DELAY(1000);
2816
2817 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2818
2819 for (i = 0; i < BWI_TX_NDESC; ++i) {
2820 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2821
2822 if (tb->tb_mbuf != NULL) {
2823 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2824 m_freem(tb->tb_mbuf);
2825 tb->tb_mbuf = NULL;
2826 }
2827 if (tb->tb_ni != NULL) {
2828 ieee80211_free_node(tb->tb_ni);
2829 tb->tb_ni = NULL;
2830 }
2831 }
2832 }
2833
2834 static void
bwi_free_txstats64(struct bwi_softc * sc)2835 bwi_free_txstats64(struct bwi_softc *sc)
2836 {
2837 /* TODO:64 */
2838 }
2839
2840 static void
bwi_free_rx_ring64(struct bwi_softc * sc)2841 bwi_free_rx_ring64(struct bwi_softc *sc)
2842 {
2843 /* TODO:64 */
2844 }
2845
2846 static void
bwi_free_tx_ring64(struct bwi_softc * sc,int ring_idx)2847 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2848 {
2849 /* TODO:64 */
2850 }
2851
2852 /* XXX does not belong here */
2853 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
2854 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
2855
2856 static __inline void
bwi_ofdm_plcp_header(uint32_t * plcp0,int pkt_len,uint8_t rate)2857 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
2858 {
2859 uint32_t plcp;
2860
2861 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM),
2862 IEEE80211_OFDM_PLCP_RATE_MASK) |
2863 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
2864 *plcp0 = htole32(plcp);
2865 }
2866
2867 static __inline void
bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr * plcp,int pkt_len,uint8_t rate)2868 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
2869 uint8_t rate)
2870 {
2871 int len, service, pkt_bitlen;
2872
2873 pkt_bitlen = pkt_len * NBBY;
2874 len = howmany(pkt_bitlen * 2, rate);
2875
2876 service = IEEE80211_PLCP_SERVICE_LOCKED;
2877 if (rate == (11 * 2)) {
2878 int pkt_bitlen1;
2879
2880 /*
2881 * PLCP service field needs to be adjusted,
2882 * if TX rate is 11Mbytes/s
2883 */
2884 pkt_bitlen1 = len * 11;
2885 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
2886 service |= IEEE80211_PLCP_SERVICE_LENEXT7;
2887 }
2888
2889 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK);
2890 plcp->i_service = service;
2891 plcp->i_length = htole16(len);
2892 /* NOTE: do NOT touch i_crc */
2893 }
2894
2895 static __inline void
bwi_plcp_header(const struct ieee80211_rate_table * rt,void * plcp,int pkt_len,uint8_t rate)2896 bwi_plcp_header(const struct ieee80211_rate_table *rt,
2897 void *plcp, int pkt_len, uint8_t rate)
2898 {
2899 enum ieee80211_phytype modtype;
2900
2901 /*
2902 * Assume caller has zeroed 'plcp'
2903 */
2904 modtype = ieee80211_rate2phytype(rt, rate);
2905 if (modtype == IEEE80211_T_OFDM)
2906 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
2907 else if (modtype == IEEE80211_T_DS)
2908 bwi_ds_plcp_header(plcp, pkt_len, rate);
2909 else
2910 panic("unsupport modulation type %u\n", modtype);
2911 }
2912
2913 static int
bwi_encap(struct bwi_softc * sc,int idx,struct mbuf * m,struct ieee80211_node * ni)2914 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2915 struct ieee80211_node *ni)
2916 {
2917 struct ieee80211vap *vap = ni->ni_vap;
2918 struct ieee80211com *ic = &sc->sc_ic;
2919 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2920 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2921 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2922 struct bwi_mac *mac;
2923 struct bwi_txbuf_hdr *hdr;
2924 struct ieee80211_frame *wh;
2925 const struct ieee80211_txparam *tp = ni->ni_txparms;
2926 uint8_t rate, rate_fb;
2927 uint32_t mac_ctrl;
2928 uint16_t phy_ctrl;
2929 bus_addr_t paddr;
2930 int type, ismcast, pkt_len, error, rix;
2931 #if 0
2932 const uint8_t *p;
2933 int i;
2934 #endif
2935
2936 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
2937 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
2938 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2939
2940 wh = mtod(m, struct ieee80211_frame *);
2941 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2942 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2943
2944 /* Get 802.11 frame len before prepending TX header */
2945 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2946
2947 /*
2948 * Find TX rate
2949 */
2950 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) {
2951 rate = rate_fb = tp->mgmtrate;
2952 } else if (ismcast) {
2953 rate = rate_fb = tp->mcastrate;
2954 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
2955 rate = rate_fb = tp->ucastrate;
2956 } else {
2957 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len);
2958 rate = ni->ni_txrate;
2959
2960 if (rix > 0) {
2961 rate_fb = ni->ni_rates.rs_rates[rix-1] &
2962 IEEE80211_RATE_VAL;
2963 } else {
2964 rate_fb = rate;
2965 }
2966 }
2967 tb->tb_rate[0] = rate;
2968 tb->tb_rate[1] = rate_fb;
2969 sc->sc_tx_rate = rate;
2970
2971 /*
2972 * TX radio tap
2973 */
2974 if (ieee80211_radiotap_active_vap(vap)) {
2975 sc->sc_tx_th.wt_flags = 0;
2976 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
2977 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2978 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS &&
2979 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
2980 rate != (1 * 2)) {
2981 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2982 }
2983 sc->sc_tx_th.wt_rate = rate;
2984
2985 ieee80211_radiotap_tx(vap, m);
2986 }
2987
2988 /*
2989 * Setup the embedded TX header
2990 */
2991 M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
2992 if (m == NULL) {
2993 device_printf(sc->sc_dev, "%s: prepend TX header failed\n",
2994 __func__);
2995 return ENOBUFS;
2996 }
2997 hdr = mtod(m, struct bwi_txbuf_hdr *);
2998
2999 bzero(hdr, sizeof(*hdr));
3000
3001 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3002 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3003
3004 if (!ismcast) {
3005 uint16_t dur;
3006
3007 dur = ieee80211_ack_duration(sc->sc_rates, rate,
3008 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3009
3010 hdr->txh_fb_duration = htole16(dur);
3011 }
3012
3013 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3014 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3015
3016 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3017 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3018
3019 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3020 BWI_TXH_PHY_C_ANTMODE_MASK);
3021 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM)
3022 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3023 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3024 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3025
3026 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3027 if (!ismcast)
3028 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3029 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM)
3030 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3031
3032 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3033 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3034
3035 /* Catch any further usage */
3036 hdr = NULL;
3037 wh = NULL;
3038
3039 /* DMA load */
3040 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3041 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3042 if (error && error != EFBIG) {
3043 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
3044 __func__, error);
3045 goto back;
3046 }
3047
3048 if (error) { /* error == EFBIG */
3049 struct mbuf *m_new;
3050
3051 m_new = m_defrag(m, M_NOWAIT);
3052 if (m_new == NULL) {
3053 device_printf(sc->sc_dev,
3054 "%s: can't defrag TX buffer\n", __func__);
3055 error = ENOBUFS;
3056 goto back;
3057 } else {
3058 m = m_new;
3059 }
3060
3061 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3062 bwi_dma_buf_addr, &paddr,
3063 BUS_DMA_NOWAIT);
3064 if (error) {
3065 device_printf(sc->sc_dev,
3066 "%s: can't load TX buffer (2) %d\n",
3067 __func__, error);
3068 goto back;
3069 }
3070 }
3071 error = 0;
3072
3073 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3074
3075 tb->tb_mbuf = m;
3076 tb->tb_ni = ni;
3077
3078 #if 0
3079 p = mtod(m, const uint8_t *);
3080 for (i = 0; i < m->m_pkthdr.len; ++i) {
3081 if (i != 0 && i % 8 == 0)
3082 printf("\n");
3083 printf("%02x ", p[i]);
3084 }
3085 printf("\n");
3086 #endif
3087 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3088 idx, pkt_len, m->m_pkthdr.len);
3089
3090 /* Setup TX descriptor */
3091 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3092 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3093 BUS_DMASYNC_PREWRITE);
3094
3095 /* Kick start */
3096 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3097
3098 back:
3099 if (error)
3100 m_freem(m);
3101 return error;
3102 }
3103
3104 static int
bwi_encap_raw(struct bwi_softc * sc,int idx,struct mbuf * m,struct ieee80211_node * ni,const struct ieee80211_bpf_params * params)3105 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m,
3106 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3107 {
3108 struct ieee80211vap *vap = ni->ni_vap;
3109 struct ieee80211com *ic = ni->ni_ic;
3110 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3111 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3112 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3113 struct bwi_mac *mac;
3114 struct bwi_txbuf_hdr *hdr;
3115 struct ieee80211_frame *wh;
3116 uint8_t rate, rate_fb;
3117 uint32_t mac_ctrl;
3118 uint16_t phy_ctrl;
3119 bus_addr_t paddr;
3120 int ismcast, pkt_len, error;
3121
3122 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3123 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3124 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3125
3126 wh = mtod(m, struct ieee80211_frame *);
3127 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3128
3129 /* Get 802.11 frame len before prepending TX header */
3130 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3131
3132 /*
3133 * Find TX rate
3134 */
3135 rate = params->ibp_rate0;
3136 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3137 /* XXX fall back to mcast/mgmt rate? */
3138 m_freem(m);
3139 return EINVAL;
3140 }
3141 if (params->ibp_try1 != 0) {
3142 rate_fb = params->ibp_rate1;
3143 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) {
3144 /* XXX fall back to rate0? */
3145 m_freem(m);
3146 return EINVAL;
3147 }
3148 } else
3149 rate_fb = rate;
3150 tb->tb_rate[0] = rate;
3151 tb->tb_rate[1] = rate_fb;
3152 sc->sc_tx_rate = rate;
3153
3154 /*
3155 * TX radio tap
3156 */
3157 if (ieee80211_radiotap_active_vap(vap)) {
3158 sc->sc_tx_th.wt_flags = 0;
3159 /* XXX IEEE80211_BPF_CRYPTO */
3160 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3161 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3162 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3163 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3164 sc->sc_tx_th.wt_rate = rate;
3165
3166 ieee80211_radiotap_tx(vap, m);
3167 }
3168
3169 /*
3170 * Setup the embedded TX header
3171 */
3172 M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
3173 if (m == NULL) {
3174 device_printf(sc->sc_dev, "%s: prepend TX header failed\n",
3175 __func__);
3176 return ENOBUFS;
3177 }
3178 hdr = mtod(m, struct bwi_txbuf_hdr *);
3179
3180 bzero(hdr, sizeof(*hdr));
3181
3182 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3183 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3184
3185 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3186 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
3187 uint16_t dur;
3188
3189 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0);
3190
3191 hdr->txh_fb_duration = htole16(dur);
3192 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3193 }
3194
3195 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3196 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3197
3198 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3199 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3200
3201 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3202 BWI_TXH_PHY_C_ANTMODE_MASK);
3203 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) {
3204 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3205 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3206 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3207 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3208
3209 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3210 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3211
3212 /* Catch any further usage */
3213 hdr = NULL;
3214 wh = NULL;
3215
3216 /* DMA load */
3217 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3218 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3219 if (error != 0) {
3220 struct mbuf *m_new;
3221
3222 if (error != EFBIG) {
3223 device_printf(sc->sc_dev,
3224 "%s: can't load TX buffer (1) %d\n",
3225 __func__, error);
3226 goto back;
3227 }
3228 m_new = m_defrag(m, M_NOWAIT);
3229 if (m_new == NULL) {
3230 device_printf(sc->sc_dev,
3231 "%s: can't defrag TX buffer\n", __func__);
3232 error = ENOBUFS;
3233 goto back;
3234 }
3235 m = m_new;
3236 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3237 bwi_dma_buf_addr, &paddr,
3238 BUS_DMA_NOWAIT);
3239 if (error) {
3240 device_printf(sc->sc_dev,
3241 "%s: can't load TX buffer (2) %d\n",
3242 __func__, error);
3243 goto back;
3244 }
3245 }
3246
3247 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3248
3249 tb->tb_mbuf = m;
3250 tb->tb_ni = ni;
3251
3252 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3253 idx, pkt_len, m->m_pkthdr.len);
3254
3255 /* Setup TX descriptor */
3256 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3257 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3258 BUS_DMASYNC_PREWRITE);
3259
3260 /* Kick start */
3261 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3262 back:
3263 if (error)
3264 m_freem(m);
3265 return error;
3266 }
3267
3268 static void
bwi_start_tx32(struct bwi_softc * sc,uint32_t tx_ctrl,int idx)3269 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3270 {
3271 idx = (idx + 1) % BWI_TX_NDESC;
3272 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3273 idx * sizeof(struct bwi_desc32));
3274 }
3275
3276 static void
bwi_start_tx64(struct bwi_softc * sc,uint32_t tx_ctrl,int idx)3277 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3278 {
3279 /* TODO:64 */
3280 }
3281
3282 static void
bwi_txeof_status32(struct bwi_softc * sc)3283 bwi_txeof_status32(struct bwi_softc *sc)
3284 {
3285 uint32_t val, ctrl_base;
3286 int end_idx;
3287
3288 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3289
3290 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3291 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3292 sizeof(struct bwi_desc32);
3293
3294 bwi_txeof_status(sc, end_idx);
3295
3296 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3297 end_idx * sizeof(struct bwi_desc32));
3298
3299 bwi_start_locked(sc);
3300 }
3301
3302 static void
bwi_txeof_status64(struct bwi_softc * sc)3303 bwi_txeof_status64(struct bwi_softc *sc)
3304 {
3305 /* TODO:64 */
3306 }
3307
3308 static void
_bwi_txeof(struct bwi_softc * sc,uint16_t tx_id,int acked,int data_txcnt)3309 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3310 {
3311 struct bwi_txbuf_data *tbd;
3312 struct bwi_txbuf *tb;
3313 int ring_idx, buf_idx;
3314 struct ieee80211_node *ni;
3315
3316 if (tx_id == 0) {
3317 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__);
3318 return;
3319 }
3320
3321 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3322 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3323
3324 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx));
3325 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
3326
3327 tbd = &sc->sc_tx_bdata[ring_idx];
3328 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used));
3329 tbd->tbd_used--;
3330
3331 tb = &tbd->tbd_buf[buf_idx];
3332 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3333 "acked %d, data_txcnt %d, ni %p\n",
3334 buf_idx, acked, data_txcnt, tb->tb_ni);
3335
3336 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3337
3338 if ((ni = tb->tb_ni) != NULL) {
3339 const struct bwi_txbuf_hdr *hdr =
3340 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *);
3341 struct ieee80211_ratectl_tx_status txs;
3342
3343 /* NB: update rate control only for unicast frames */
3344 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) {
3345 /*
3346 * Feed back 'acked and data_txcnt'. Note that the
3347 * generic AMRR code only understands one tx rate
3348 * and the estimator doesn't handle real retry counts
3349 * well so to avoid over-aggressive downshifting we
3350 * treat any number of retries as "1".
3351 */
3352 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY;
3353 txs.long_retries = acked;
3354 if (data_txcnt > 1)
3355 txs.status = IEEE80211_RATECTL_TX_SUCCESS;
3356 else {
3357 txs.status =
3358 IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
3359 }
3360 ieee80211_ratectl_tx_complete(ni, &txs);
3361 }
3362 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked);
3363 tb->tb_ni = NULL;
3364 } else
3365 m_freem(tb->tb_mbuf);
3366 tb->tb_mbuf = NULL;
3367
3368 if (tbd->tbd_used == 0)
3369 sc->sc_tx_timer = 0;
3370 }
3371
3372 static void
bwi_txeof_status(struct bwi_softc * sc,int end_idx)3373 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3374 {
3375 struct bwi_txstats_data *st = sc->sc_txstats;
3376 int idx;
3377
3378 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3379
3380 idx = st->stats_idx;
3381 while (idx != end_idx) {
3382 const struct bwi_txstats *stats = &st->stats[idx];
3383
3384 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3385 int data_txcnt;
3386
3387 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3388 BWI_TXS_TXCNT_DATA);
3389 _bwi_txeof(sc, le16toh(stats->txs_id),
3390 stats->txs_flags & BWI_TXS_F_ACKED,
3391 data_txcnt);
3392 }
3393 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3394 }
3395 st->stats_idx = idx;
3396 }
3397
3398 static void
bwi_txeof(struct bwi_softc * sc)3399 bwi_txeof(struct bwi_softc *sc)
3400 {
3401
3402 for (;;) {
3403 uint32_t tx_status0, tx_status1;
3404 uint16_t tx_id;
3405 int data_txcnt;
3406
3407 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3408 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3409 break;
3410 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3411
3412 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3413 data_txcnt = __SHIFTOUT(tx_status0,
3414 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3415
3416 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3417 continue;
3418
3419 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED,
3420 data_txcnt);
3421 }
3422
3423 bwi_start_locked(sc);
3424 }
3425
3426 static int
bwi_bbp_power_on(struct bwi_softc * sc,enum bwi_clock_mode clk_mode)3427 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3428 {
3429 bwi_power_on(sc, 1);
3430 return bwi_set_clock_mode(sc, clk_mode);
3431 }
3432
3433 static void
bwi_bbp_power_off(struct bwi_softc * sc)3434 bwi_bbp_power_off(struct bwi_softc *sc)
3435 {
3436 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3437 bwi_power_off(sc, 1);
3438 }
3439
3440 static int
bwi_get_pwron_delay(struct bwi_softc * sc)3441 bwi_get_pwron_delay(struct bwi_softc *sc)
3442 {
3443 struct bwi_regwin *com, *old;
3444 struct bwi_clock_freq freq;
3445 uint32_t val;
3446 int error;
3447
3448 com = &sc->sc_com_regwin;
3449 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin"));
3450
3451 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3452 return 0;
3453
3454 error = bwi_regwin_switch(sc, com, &old);
3455 if (error)
3456 return error;
3457
3458 bwi_get_clock_freq(sc, &freq);
3459
3460 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3461 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3462 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3463
3464 return bwi_regwin_switch(sc, old, NULL);
3465 }
3466
3467 static int
bwi_bus_attach(struct bwi_softc * sc)3468 bwi_bus_attach(struct bwi_softc *sc)
3469 {
3470 struct bwi_regwin *bus, *old;
3471 int error;
3472
3473 bus = &sc->sc_bus_regwin;
3474
3475 error = bwi_regwin_switch(sc, bus, &old);
3476 if (error)
3477 return error;
3478
3479 if (!bwi_regwin_is_enabled(sc, bus))
3480 bwi_regwin_enable(sc, bus, 0);
3481
3482 /* Disable interripts */
3483 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3484
3485 return bwi_regwin_switch(sc, old, NULL);
3486 }
3487
3488 static const char *
bwi_regwin_name(const struct bwi_regwin * rw)3489 bwi_regwin_name(const struct bwi_regwin *rw)
3490 {
3491 switch (rw->rw_type) {
3492 case BWI_REGWIN_T_COM:
3493 return "COM";
3494 case BWI_REGWIN_T_BUSPCI:
3495 return "PCI";
3496 case BWI_REGWIN_T_MAC:
3497 return "MAC";
3498 case BWI_REGWIN_T_BUSPCIE:
3499 return "PCIE";
3500 }
3501 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3502 return NULL;
3503 }
3504
3505 static uint32_t
bwi_regwin_disable_bits(struct bwi_softc * sc)3506 bwi_regwin_disable_bits(struct bwi_softc *sc)
3507 {
3508 uint32_t busrev;
3509
3510 /* XXX cache this */
3511 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3512 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3513 "bus rev %u\n", busrev);
3514
3515 if (busrev == BWI_BUSREV_0)
3516 return BWI_STATE_LO_DISABLE1;
3517 else if (busrev == BWI_BUSREV_1)
3518 return BWI_STATE_LO_DISABLE2;
3519 else
3520 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3521 }
3522
3523 int
bwi_regwin_is_enabled(struct bwi_softc * sc,struct bwi_regwin * rw)3524 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3525 {
3526 uint32_t val, disable_bits;
3527
3528 disable_bits = bwi_regwin_disable_bits(sc);
3529 val = CSR_READ_4(sc, BWI_STATE_LO);
3530
3531 if ((val & (BWI_STATE_LO_CLOCK |
3532 BWI_STATE_LO_RESET |
3533 disable_bits)) == BWI_STATE_LO_CLOCK) {
3534 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3535 bwi_regwin_name(rw));
3536 return 1;
3537 } else {
3538 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3539 bwi_regwin_name(rw));
3540 return 0;
3541 }
3542 }
3543
3544 void
bwi_regwin_disable(struct bwi_softc * sc,struct bwi_regwin * rw,uint32_t flags)3545 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3546 {
3547 uint32_t state_lo, disable_bits;
3548 int i;
3549
3550 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3551
3552 /*
3553 * If current regwin is in 'reset' state, it was already disabled.
3554 */
3555 if (state_lo & BWI_STATE_LO_RESET) {
3556 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3557 "%s was already disabled\n", bwi_regwin_name(rw));
3558 return;
3559 }
3560
3561 disable_bits = bwi_regwin_disable_bits(sc);
3562
3563 /*
3564 * Disable normal clock
3565 */
3566 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3567 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3568
3569 /*
3570 * Wait until normal clock is disabled
3571 */
3572 #define NRETRY 1000
3573 for (i = 0; i < NRETRY; ++i) {
3574 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3575 if (state_lo & disable_bits)
3576 break;
3577 DELAY(10);
3578 }
3579 if (i == NRETRY) {
3580 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3581 bwi_regwin_name(rw));
3582 }
3583
3584 for (i = 0; i < NRETRY; ++i) {
3585 uint32_t state_hi;
3586
3587 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3588 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3589 break;
3590 DELAY(10);
3591 }
3592 if (i == NRETRY) {
3593 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3594 bwi_regwin_name(rw));
3595 }
3596 #undef NRETRY
3597
3598 /*
3599 * Reset and disable regwin with gated clock
3600 */
3601 state_lo = BWI_STATE_LO_RESET | disable_bits |
3602 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3603 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3604 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3605
3606 /* Flush pending bus write */
3607 CSR_READ_4(sc, BWI_STATE_LO);
3608 DELAY(1);
3609
3610 /* Reset and disable regwin */
3611 state_lo = BWI_STATE_LO_RESET | disable_bits |
3612 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3613 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3614
3615 /* Flush pending bus write */
3616 CSR_READ_4(sc, BWI_STATE_LO);
3617 DELAY(1);
3618 }
3619
3620 void
bwi_regwin_enable(struct bwi_softc * sc,struct bwi_regwin * rw,uint32_t flags)3621 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3622 {
3623 uint32_t state_lo, state_hi, imstate;
3624
3625 bwi_regwin_disable(sc, rw, flags);
3626
3627 /* Reset regwin with gated clock */
3628 state_lo = BWI_STATE_LO_RESET |
3629 BWI_STATE_LO_CLOCK |
3630 BWI_STATE_LO_GATED_CLOCK |
3631 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3632 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3633
3634 /* Flush pending bus write */
3635 CSR_READ_4(sc, BWI_STATE_LO);
3636 DELAY(1);
3637
3638 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3639 if (state_hi & BWI_STATE_HI_SERROR)
3640 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3641
3642 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3643 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3644 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3645 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3646 }
3647
3648 /* Enable regwin with gated clock */
3649 state_lo = BWI_STATE_LO_CLOCK |
3650 BWI_STATE_LO_GATED_CLOCK |
3651 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3652 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3653
3654 /* Flush pending bus write */
3655 CSR_READ_4(sc, BWI_STATE_LO);
3656 DELAY(1);
3657
3658 /* Enable regwin with normal clock */
3659 state_lo = BWI_STATE_LO_CLOCK |
3660 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3661 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3662
3663 /* Flush pending bus write */
3664 CSR_READ_4(sc, BWI_STATE_LO);
3665 DELAY(1);
3666 }
3667
3668 static void
bwi_set_bssid(struct bwi_softc * sc,const uint8_t * bssid)3669 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3670 {
3671 struct bwi_mac *mac;
3672 struct bwi_myaddr_bssid buf;
3673 const uint8_t *p;
3674 uint32_t val;
3675 int n, i;
3676
3677 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3678 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3679 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3680
3681 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3682
3683 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr));
3684 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3685
3686 n = sizeof(buf) / sizeof(val);
3687 p = (const uint8_t *)&buf;
3688 for (i = 0; i < n; ++i) {
3689 int j;
3690
3691 val = 0;
3692 for (j = 0; j < sizeof(val); ++j)
3693 val |= ((uint32_t)(*p++)) << (j * 8);
3694
3695 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3696 }
3697 }
3698
3699 static void
bwi_updateslot(struct ieee80211com * ic)3700 bwi_updateslot(struct ieee80211com *ic)
3701 {
3702 struct bwi_softc *sc = ic->ic_softc;
3703 struct bwi_mac *mac;
3704
3705 BWI_LOCK(sc);
3706 if (sc->sc_flags & BWI_F_RUNNING) {
3707 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3708
3709 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3710 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3711 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3712
3713 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3714 }
3715 BWI_UNLOCK(sc);
3716 }
3717
3718 static void
bwi_calibrate(void * xsc)3719 bwi_calibrate(void *xsc)
3720 {
3721 struct bwi_softc *sc = xsc;
3722 struct bwi_mac *mac;
3723
3724 BWI_ASSERT_LOCKED(sc);
3725
3726 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR,
3727 ("opmode %d", sc->sc_ic.ic_opmode));
3728
3729 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3730 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3731 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3732
3733 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3734 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3735
3736 /* XXX 15 seconds */
3737 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3738 }
3739
3740 static int
bwi_calc_rssi(struct bwi_softc * sc,const struct bwi_rxbuf_hdr * hdr)3741 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3742 {
3743 struct bwi_mac *mac;
3744
3745 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3746 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3747 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3748
3749 return bwi_rf_calc_rssi(mac, hdr);
3750 }
3751
3752 static int
bwi_calc_noise(struct bwi_softc * sc)3753 bwi_calc_noise(struct bwi_softc *sc)
3754 {
3755 struct bwi_mac *mac;
3756
3757 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3758 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3759 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3760
3761 return bwi_rf_calc_noise(mac);
3762 }
3763
3764 static __inline uint8_t
bwi_plcp2rate(const uint32_t plcp0,enum ieee80211_phytype type)3765 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type)
3766 {
3767 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK;
3768 return (ieee80211_plcp2rate(plcp, type));
3769 }
3770
3771 static void
bwi_rx_radiotap(struct bwi_softc * sc,struct mbuf * m,struct bwi_rxbuf_hdr * hdr,const void * plcp,int rate,int rssi,int noise)3772 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3773 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise)
3774 {
3775 const struct ieee80211_frame_min *wh;
3776
3777 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3778 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3779 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3780
3781 wh = mtod(m, const struct ieee80211_frame_min *);
3782 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3783 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3784
3785 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian conversion */
3786 sc->sc_rx_th.wr_rate = rate;
3787 sc->sc_rx_th.wr_antsignal = rssi;
3788 sc->sc_rx_th.wr_antnoise = noise;
3789 }
3790
3791 static void
bwi_led_attach(struct bwi_softc * sc)3792 bwi_led_attach(struct bwi_softc *sc)
3793 {
3794 const uint8_t *led_act = NULL;
3795 uint16_t gpio, val[BWI_LED_MAX];
3796 int i;
3797
3798 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) {
3799 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3800 led_act = bwi_vendor_led_act[i].led_act;
3801 break;
3802 }
3803 }
3804 if (led_act == NULL)
3805 led_act = bwi_default_led_act;
3806
3807 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3808 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3809 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3810
3811 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3812 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3813 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3814
3815 for (i = 0; i < BWI_LED_MAX; ++i) {
3816 struct bwi_led *led = &sc->sc_leds[i];
3817
3818 if (val[i] == 0xff) {
3819 led->l_act = led_act[i];
3820 } else {
3821 if (val[i] & BWI_LED_ACT_LOW)
3822 led->l_flags |= BWI_LED_F_ACTLOW;
3823 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3824 }
3825 led->l_mask = (1 << i);
3826
3827 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3828 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3829 led->l_act == BWI_LED_ACT_BLINK) {
3830 led->l_flags |= BWI_LED_F_BLINK;
3831 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3832 led->l_flags |= BWI_LED_F_POLLABLE;
3833 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3834 led->l_flags |= BWI_LED_F_SLOW;
3835
3836 if (sc->sc_blink_led == NULL) {
3837 sc->sc_blink_led = led;
3838 if (led->l_flags & BWI_LED_F_SLOW)
3839 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3840 }
3841 }
3842
3843 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3844 "%dth led, act %d, lowact %d\n", i,
3845 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3846 }
3847 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
3848 }
3849
3850 static __inline uint16_t
bwi_led_onoff(const struct bwi_led * led,uint16_t val,int on)3851 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3852 {
3853 if (led->l_flags & BWI_LED_F_ACTLOW)
3854 on = !on;
3855 if (on)
3856 val |= led->l_mask;
3857 else
3858 val &= ~led->l_mask;
3859 return val;
3860 }
3861
3862 static void
bwi_led_newstate(struct bwi_softc * sc,enum ieee80211_state nstate)3863 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3864 {
3865 struct ieee80211com *ic = &sc->sc_ic;
3866 uint16_t val;
3867 int i;
3868
3869 if (nstate == IEEE80211_S_INIT) {
3870 callout_stop(&sc->sc_led_blink_ch);
3871 sc->sc_led_blinking = 0;
3872 }
3873
3874 if ((sc->sc_flags & BWI_F_RUNNING) == 0)
3875 return;
3876
3877 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3878 for (i = 0; i < BWI_LED_MAX; ++i) {
3879 struct bwi_led *led = &sc->sc_leds[i];
3880 int on;
3881
3882 if (led->l_act == BWI_LED_ACT_UNKN ||
3883 led->l_act == BWI_LED_ACT_NULL)
3884 continue;
3885
3886 if ((led->l_flags & BWI_LED_F_BLINK) &&
3887 nstate != IEEE80211_S_INIT)
3888 continue;
3889
3890 switch (led->l_act) {
3891 case BWI_LED_ACT_ON: /* Always on */
3892 on = 1;
3893 break;
3894 case BWI_LED_ACT_OFF: /* Always off */
3895 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3896 on = 0;
3897 break;
3898 default:
3899 on = 1;
3900 switch (nstate) {
3901 case IEEE80211_S_INIT:
3902 on = 0;
3903 break;
3904 case IEEE80211_S_RUN:
3905 if (led->l_act == BWI_LED_ACT_11G &&
3906 ic->ic_curmode != IEEE80211_MODE_11G)
3907 on = 0;
3908 break;
3909 default:
3910 if (led->l_act == BWI_LED_ACT_ASSOC)
3911 on = 0;
3912 break;
3913 }
3914 break;
3915 }
3916
3917 val = bwi_led_onoff(led, val, on);
3918 }
3919 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3920 }
3921 static void
bwi_led_event(struct bwi_softc * sc,int event)3922 bwi_led_event(struct bwi_softc *sc, int event)
3923 {
3924 struct bwi_led *led = sc->sc_blink_led;
3925 int rate;
3926
3927 if (event == BWI_LED_EVENT_POLL) {
3928 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3929 return;
3930 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3931 return;
3932 }
3933
3934 sc->sc_led_ticks = ticks;
3935 if (sc->sc_led_blinking)
3936 return;
3937
3938 switch (event) {
3939 case BWI_LED_EVENT_RX:
3940 rate = sc->sc_rx_rate;
3941 break;
3942 case BWI_LED_EVENT_TX:
3943 rate = sc->sc_tx_rate;
3944 break;
3945 case BWI_LED_EVENT_POLL:
3946 rate = 0;
3947 break;
3948 default:
3949 panic("unknown LED event %d\n", event);
3950 break;
3951 }
3952 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3953 bwi_led_duration[rate].off_dur);
3954 }
3955
3956 static void
bwi_led_blink_start(struct bwi_softc * sc,int on_dur,int off_dur)3957 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3958 {
3959 struct bwi_led *led = sc->sc_blink_led;
3960 uint16_t val;
3961
3962 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3963 val = bwi_led_onoff(led, val, 1);
3964 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3965
3966 if (led->l_flags & BWI_LED_F_SLOW) {
3967 BWI_LED_SLOWDOWN(on_dur);
3968 BWI_LED_SLOWDOWN(off_dur);
3969 }
3970
3971 sc->sc_led_blinking = 1;
3972 sc->sc_led_blink_offdur = off_dur;
3973
3974 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3975 }
3976
3977 static void
bwi_led_blink_next(void * xsc)3978 bwi_led_blink_next(void *xsc)
3979 {
3980 struct bwi_softc *sc = xsc;
3981 uint16_t val;
3982
3983 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3984 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3985 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3986
3987 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3988 bwi_led_blink_end, sc);
3989 }
3990
3991 static void
bwi_led_blink_end(void * xsc)3992 bwi_led_blink_end(void *xsc)
3993 {
3994 struct bwi_softc *sc = xsc;
3995 sc->sc_led_blinking = 0;
3996 }
3997
3998 static void
bwi_restart(void * xsc,int pending)3999 bwi_restart(void *xsc, int pending)
4000 {
4001 struct bwi_softc *sc = xsc;
4002
4003 device_printf(sc->sc_dev, "%s begin, help!\n", __func__);
4004 BWI_LOCK(sc);
4005 bwi_init_statechg(sc, 0);
4006 #if 0
4007 bwi_start_locked(sc);
4008 #endif
4009 BWI_UNLOCK(sc);
4010 }
4011