1 /*-
2 * Copyright (c) 2016 Michal Meloun <[email protected]>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 /*
31 * Nvidia Integrated PCI/PCI-Express controller driver.
32 */
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/devmap.h>
38 #include <sys/proc.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
43 #include <sys/rman.h>
44
45 #include <machine/intr.h>
46
47 #include <vm/vm.h>
48 #include <vm/vm_extern.h>
49 #include <vm/vm_kern.h>
50 #include <vm/pmap.h>
51
52 #include <dev/extres/clk/clk.h>
53 #include <dev/extres/hwreset/hwreset.h>
54 #include <dev/extres/phy/phy.h>
55 #include <dev/extres/regulator/regulator.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
58 #include <dev/ofw/ofw_pci.h>
59 #include <dev/ofw/ofwpci.h>
60 #include <dev/pci/pcivar.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcib_private.h>
63
64 #include <machine/resource.h>
65 #include <machine/bus.h>
66
67 #include <arm/nvidia/tegra_pmc.h>
68
69 #include "ofw_bus_if.h"
70 #include "msi_if.h"
71 #include "pcib_if.h"
72 #include "pic_if.h"
73
74
75 #define AFI_AXI_BAR0_SZ 0x000
76 #define AFI_AXI_BAR1_SZ 0x004
77 #define AFI_AXI_BAR2_SZ 0x008
78 #define AFI_AXI_BAR3_SZ 0x00c
79 #define AFI_AXI_BAR4_SZ 0x010
80 #define AFI_AXI_BAR5_SZ 0x014
81 #define AFI_AXI_BAR0_START 0x018
82 #define AFI_AXI_BAR1_START 0x01c
83 #define AFI_AXI_BAR2_START 0x020
84 #define AFI_AXI_BAR3_START 0x024
85 #define AFI_AXI_BAR4_START 0x028
86 #define AFI_AXI_BAR5_START 0x02c
87 #define AFI_FPCI_BAR0 0x030
88 #define AFI_FPCI_BAR1 0x034
89 #define AFI_FPCI_BAR2 0x038
90 #define AFI_FPCI_BAR3 0x03c
91 #define AFI_FPCI_BAR4 0x040
92 #define AFI_FPCI_BAR5 0x044
93 #define AFI_MSI_BAR_SZ 0x060
94 #define AFI_MSI_FPCI_BAR_ST 0x064
95 #define AFI_MSI_AXI_BAR_ST 0x068
96 #define AFI_MSI_VEC(x) (0x06c + 4 * (x))
97 #define AFI_MSI_EN_VEC(x) (0x08c + 4 * (x))
98 #define AFI_MSI_INTR_IN_REG 32
99 #define AFI_MSI_REGS 8
100
101 #define AFI_CONFIGURATION 0x0ac
102 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
103
104 #define AFI_FPCI_ERROR_MASKS 0x0b0
105 #define AFI_INTR_MASK 0x0b4
106 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
107 #define AFI_INTR_MASK_INT_MASK (1 << 0)
108
109 #define AFI_INTR_CODE 0x0b8
110 #define AFI_INTR_CODE_MASK 0xf
111 #define AFI_INTR_CODE_INT_CODE_INI_SLVERR 1
112 #define AFI_INTR_CODE_INT_CODE_INI_DECERR 2
113 #define AFI_INTR_CODE_INT_CODE_TGT_SLVERR 3
114 #define AFI_INTR_CODE_INT_CODE_TGT_DECERR 4
115 #define AFI_INTR_CODE_INT_CODE_TGT_WRERR 5
116 #define AFI_INTR_CODE_INT_CODE_SM_MSG 6
117 #define AFI_INTR_CODE_INT_CODE_DFPCI_DECERR 7
118 #define AFI_INTR_CODE_INT_CODE_AXI_DECERR 8
119 #define AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT 9
120 #define AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE 10
121 #define AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE 11
122 #define AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE 12
123 #define AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE 13
124 #define AFI_INTR_CODE_INT_CODE_P2P_ERROR 14
125
126
127 #define AFI_INTR_SIGNATURE 0x0bc
128 #define AFI_UPPER_FPCI_ADDRESS 0x0c0
129 #define AFI_SM_INTR_ENABLE 0x0c4
130 #define AFI_SM_INTR_RP_DEASSERT (1 << 14)
131 #define AFI_SM_INTR_RP_ASSERT (1 << 13)
132 #define AFI_SM_INTR_HOTPLUG (1 << 12)
133 #define AFI_SM_INTR_PME (1 << 11)
134 #define AFI_SM_INTR_FATAL_ERROR (1 << 10)
135 #define AFI_SM_INTR_UNCORR_ERROR (1 << 9)
136 #define AFI_SM_INTR_CORR_ERROR (1 << 8)
137 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
138 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
139 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
140 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
141 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
142 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
143 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
144 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
145
146 #define AFI_AFI_INTR_ENABLE 0x0c8
147 #define AFI_AFI_INTR_ENABLE_CODE(code) (1 << (code))
148
149 #define AFI_PCIE_CONFIG 0x0f8
150 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
151 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0x6
152 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
153 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1 (0x0 << 20)
154 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1 (0x1 << 20)
155
156 #define AFI_FUSE 0x104
157 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
158
159 #define AFI_PEX0_CTRL 0x110
160 #define AFI_PEX1_CTRL 0x118
161 #define AFI_PEX2_CTRL 0x128
162 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
163 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
164 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
165 #define AFI_PEX_CTRL_RST_L (1 << 0)
166
167 #define AFI_AXI_BAR6_SZ 0x134
168 #define AFI_AXI_BAR7_SZ 0x138
169 #define AFI_AXI_BAR8_SZ 0x13c
170 #define AFI_AXI_BAR6_START 0x140
171 #define AFI_AXI_BAR7_START 0x144
172 #define AFI_AXI_BAR8_START 0x148
173 #define AFI_FPCI_BAR6 0x14c
174 #define AFI_FPCI_BAR7 0x150
175 #define AFI_FPCI_BAR8 0x154
176 #define AFI_PLLE_CONTROL 0x160
177 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
178 #define AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL (1 << 8)
179 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
180 #define AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN (1 << 0)
181
182 #define AFI_PEXBIAS_CTRL 0x168
183
184 /* FPCI Address space */
185 #define FPCI_MAP_IO 0xfdfc000000ULL
186 #define FPCI_MAP_TYPE0_CONFIG 0xfdfc000000ULL
187 #define FPCI_MAP_TYPE1_CONFIG 0xfdff000000ULL
188 #define FPCI_MAP_EXT_TYPE0_CONFIG 0xfe00000000ULL
189 #define FPCI_MAP_EXT_TYPE1_CONFIG 0xfe10000000ULL
190
191 /* Configuration space */
192 #define RP_VEND_XP 0x00000F00
193 #define RP_VEND_XP_DL_UP (1 << 30)
194
195 #define RP_PRIV_MISC 0x00000FE0
196 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
197 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
198
199 #define RP_LINK_CONTROL_STATUS 0x00000090
200 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
201 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
202
203 /* Wait 50 ms (per port) for link. */
204 #define TEGRA_PCIE_LINKUP_TIMEOUT 50000
205
206 #define TEGRA_PCIB_MSI_ENABLE
207
208 #define DEBUG
209 #ifdef DEBUG
210 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
211 #else
212 #define debugf(fmt, args...)
213 #endif
214
215 /*
216 * Configuration space format:
217 * [27:24] extended register
218 * [23:16] bus
219 * [15:11] slot (device)
220 * [10: 8] function
221 * [ 7: 0] register
222 */
223 #define PCI_CFG_EXT_REG(reg) ((((reg) >> 8) & 0x0f) << 24)
224 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
225 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
226 #define PCI_CFG_FUN(fun) (((fun) & 0x07) << 8)
227 #define PCI_CFG_BASE_REG(reg) ((reg) & 0xff)
228
229 #define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)-pads_mem_res, (_r), (_v))
230 #define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r))
231 #define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v))
232 #define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r))
233
234 static struct {
235 bus_size_t axi_start;
236 bus_size_t fpci_start;
237 bus_size_t size;
238 } bars[] = {
239 {AFI_AXI_BAR0_START, AFI_FPCI_BAR0, AFI_AXI_BAR0_SZ}, /* BAR 0 */
240 {AFI_AXI_BAR1_START, AFI_FPCI_BAR1, AFI_AXI_BAR1_SZ}, /* BAR 1 */
241 {AFI_AXI_BAR2_START, AFI_FPCI_BAR2, AFI_AXI_BAR2_SZ}, /* BAR 2 */
242 {AFI_AXI_BAR3_START, AFI_FPCI_BAR3, AFI_AXI_BAR3_SZ}, /* BAR 3 */
243 {AFI_AXI_BAR4_START, AFI_FPCI_BAR4, AFI_AXI_BAR4_SZ}, /* BAR 4 */
244 {AFI_AXI_BAR5_START, AFI_FPCI_BAR5, AFI_AXI_BAR5_SZ}, /* BAR 5 */
245 {AFI_AXI_BAR6_START, AFI_FPCI_BAR6, AFI_AXI_BAR6_SZ}, /* BAR 6 */
246 {AFI_AXI_BAR7_START, AFI_FPCI_BAR7, AFI_AXI_BAR7_SZ}, /* BAR 7 */
247 {AFI_AXI_BAR8_START, AFI_FPCI_BAR8, AFI_AXI_BAR8_SZ}, /* BAR 8 */
248 {AFI_MSI_AXI_BAR_ST, AFI_MSI_FPCI_BAR_ST, AFI_MSI_BAR_SZ}, /* MSI 9 */
249 };
250
251 /* Compatible devices. */
252 static struct ofw_compat_data compat_data[] = {
253 {"nvidia,tegra124-pcie", 1},
254 {NULL, 0},
255 };
256
257 #define TEGRA_FLAG_MSI_USED 0x0001
258 struct tegra_pcib_irqsrc {
259 struct intr_irqsrc isrc;
260 u_int irq;
261 u_int flags;
262 };
263
264 struct tegra_pcib_port {
265 int enabled;
266 int port_idx; /* chip port index */
267 int num_lanes; /* number of lanes */
268 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */
269 phy_t phy; /* port phy */
270
271 /* Config space properties. */
272 bus_addr_t rp_base_addr; /* PA of config window */
273 bus_size_t rp_size; /* size of config window */
274 bus_space_handle_t cfg_handle; /* handle of config window */
275 };
276
277 #define TEGRA_PCIB_MAX_PORTS 3
278 #define TEGRA_PCIB_MAX_MSI AFI_MSI_INTR_IN_REG * AFI_MSI_REGS
279 struct tegra_pcib_softc {
280 struct ofw_pci_softc ofw_pci;
281 device_t dev;
282 struct mtx mtx;
283 struct resource *pads_mem_res;
284 struct resource *afi_mem_res;
285 struct resource *cfg_mem_res;
286 struct resource *irq_res;
287 struct resource *msi_irq_res;
288 void *intr_cookie;
289 void *msi_intr_cookie;
290
291 struct ofw_pci_range mem_range;
292 struct ofw_pci_range pref_mem_range;
293 struct ofw_pci_range io_range;
294
295 clk_t clk_pex;
296 clk_t clk_afi;
297 clk_t clk_pll_e;
298 clk_t clk_cml;
299 hwreset_t hwreset_pex;
300 hwreset_t hwreset_afi;
301 hwreset_t hwreset_pcie_x;
302 regulator_t supply_avddio_pex;
303 regulator_t supply_dvddio_pex;
304 regulator_t supply_avdd_pex_pll;
305 regulator_t supply_hvdd_pex;
306 regulator_t supply_hvdd_pex_pll_e;
307 regulator_t supply_vddio_pex_ctl;
308 regulator_t supply_avdd_pll_erefe;
309
310 vm_offset_t msi_page; /* VA of MSI page */
311 bus_addr_t cfg_base_addr; /* base address of config */
312 bus_size_t cfg_cur_offs; /* currently mapped window */
313 bus_space_handle_t cfg_handle; /* handle of config window */
314 bus_space_tag_t bus_tag; /* tag of config window */
315 int lanes_cfg;
316 int num_ports;
317 struct tegra_pcib_port *ports[TEGRA_PCIB_MAX_PORTS];
318 struct tegra_pcib_irqsrc *isrcs;
319 };
320
321 static int
tegra_pcib_maxslots(device_t dev)322 tegra_pcib_maxslots(device_t dev)
323 {
324 return (16);
325 }
326
327 static int
tegra_pcib_route_interrupt(device_t bus,device_t dev,int pin)328 tegra_pcib_route_interrupt(device_t bus, device_t dev, int pin)
329 {
330 struct tegra_pcib_softc *sc;
331 u_int irq;
332
333 sc = device_get_softc(bus);
334 irq = intr_map_clone_irq(rman_get_start(sc->irq_res));
335 device_printf(bus, "route pin %d for device %d.%d to %u\n",
336 pin, pci_get_slot(dev), pci_get_function(dev),
337 irq);
338
339 return (irq);
340 }
341
342 static int
tegra_pcbib_map_cfg(struct tegra_pcib_softc * sc,u_int bus,u_int slot,u_int func,u_int reg)343 tegra_pcbib_map_cfg(struct tegra_pcib_softc *sc, u_int bus, u_int slot,
344 u_int func, u_int reg)
345 {
346 bus_size_t offs;
347 int rv;
348
349 offs = sc->cfg_base_addr;
350 offs |= PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | PCI_CFG_FUN(func) |
351 PCI_CFG_EXT_REG(reg);
352 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs))
353 return (0);
354 if (sc->cfg_handle != 0)
355 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800);
356
357 rv = bus_space_map(sc->bus_tag, offs, 0x800, 0, &sc->cfg_handle);
358 if (rv != 0)
359 device_printf(sc->dev, "Cannot map config space\n");
360 else
361 sc->cfg_cur_offs = offs;
362 return (rv);
363 }
364
365 static uint32_t
tegra_pcib_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)366 tegra_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
367 u_int reg, int bytes)
368 {
369 struct tegra_pcib_softc *sc;
370 bus_space_handle_t hndl;
371 uint32_t off;
372 uint32_t val;
373 int rv, i;
374
375 sc = device_get_softc(dev);
376 if (bus == 0) {
377 if (func != 0)
378 return (0xFFFFFFFF);
379 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
380 if ((sc->ports[i] != NULL) &&
381 (sc->ports[i]->port_idx == slot)) {
382 hndl = sc->ports[i]->cfg_handle;
383 off = reg & 0xFFF;
384 break;
385 }
386 }
387 if (i >= TEGRA_PCIB_MAX_PORTS)
388 return (0xFFFFFFFF);
389 } else {
390 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg);
391 if (rv != 0)
392 return (0xFFFFFFFF);
393 hndl = sc->cfg_handle;
394 off = PCI_CFG_BASE_REG(reg);
395 }
396
397 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
398 switch (bytes) {
399 case 4:
400 break;
401 case 2:
402 if (off & 3)
403 val >>= 16;
404 val &= 0xffff;
405 break;
406 case 1:
407 val >>= ((off & 3) << 3);
408 val &= 0xff;
409 break;
410 }
411 return val;
412 }
413
414 static void
tegra_pcib_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t val,int bytes)415 tegra_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
416 u_int reg, uint32_t val, int bytes)
417 {
418 struct tegra_pcib_softc *sc;
419 bus_space_handle_t hndl;
420 uint32_t off;
421 uint32_t val2;
422 int rv, i;
423
424 sc = device_get_softc(dev);
425 if (bus == 0) {
426 if (func != 0)
427 return;
428 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
429 if ((sc->ports[i] != NULL) &&
430 (sc->ports[i]->port_idx == slot)) {
431 hndl = sc->ports[i]->cfg_handle;
432 off = reg & 0xFFF;
433 break;
434 }
435 }
436 if (i >= TEGRA_PCIB_MAX_PORTS)
437 return;
438 } else {
439 rv = tegra_pcbib_map_cfg(sc, bus, slot, func, reg);
440 if (rv != 0)
441 return;
442 hndl = sc->cfg_handle;
443 off = PCI_CFG_BASE_REG(reg);
444 }
445
446 switch (bytes) {
447 case 4:
448 bus_space_write_4(sc->bus_tag, hndl, off, val);
449 break;
450 case 2:
451 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
452 val2 &= ~(0xffff << ((off & 3) << 3));
453 val2 |= ((val & 0xffff) << ((off & 3) << 3));
454 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2);
455 break;
456 case 1:
457 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3);
458 val2 &= ~(0xff << ((off & 3) << 3));
459 val2 |= ((val & 0xff) << ((off & 3) << 3));
460 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2);
461 break;
462 }
463 }
464
tegra_pci_intr(void * arg)465 static int tegra_pci_intr(void *arg)
466 {
467 struct tegra_pcib_softc *sc = arg;
468 uint32_t code, signature;
469
470 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
471 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE);
472 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0);
473 if (code == AFI_INTR_CODE_INT_CODE_SM_MSG)
474 return(FILTER_STRAY);
475
476 printf("tegra_pci_intr: code %x sig %x\n", code, signature);
477 return (FILTER_HANDLED);
478 }
479
480 /* -----------------------------------------------------------------------
481 *
482 * PCI MSI interface
483 */
484 static int
tegra_pcib_alloc_msi(device_t pci,device_t child,int count,int maxcount,int * irqs)485 tegra_pcib_alloc_msi(device_t pci, device_t child, int count, int maxcount,
486 int *irqs)
487 {
488 phandle_t msi_parent;
489
490 /* XXXX ofw_bus_msimap() don't works for Tegra DT.
491 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
492 NULL);
493 */
494 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
495 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount,
496 irqs));
497 }
498
499 static int
tegra_pcib_release_msi(device_t pci,device_t child,int count,int * irqs)500 tegra_pcib_release_msi(device_t pci, device_t child, int count, int *irqs)
501 {
502 phandle_t msi_parent;
503
504 /* XXXX ofw_bus_msimap() don't works for Tegra DT.
505 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
506 NULL);
507 */
508 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
509 return (intr_release_msi(pci, child, msi_parent, count, irqs));
510 }
511
512 static int
tegra_pcib_map_msi(device_t pci,device_t child,int irq,uint64_t * addr,uint32_t * data)513 tegra_pcib_map_msi(device_t pci, device_t child, int irq, uint64_t *addr,
514 uint32_t *data)
515 {
516 phandle_t msi_parent;
517
518 /* XXXX ofw_bus_msimap() don't works for Tegra DT.
519 ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent,
520 NULL);
521 */
522 msi_parent = OF_xref_from_node(ofw_bus_get_node(pci));
523 return (intr_map_msi(pci, child, msi_parent, irq, addr, data));
524 }
525
526 #ifdef TEGRA_PCIB_MSI_ENABLE
527
528 /* --------------------------------------------------------------------------
529 *
530 * Interrupts
531 *
532 */
533
534 static inline void
tegra_pcib_isrc_mask(struct tegra_pcib_softc * sc,struct tegra_pcib_irqsrc * tgi,uint32_t val)535 tegra_pcib_isrc_mask(struct tegra_pcib_softc *sc,
536 struct tegra_pcib_irqsrc *tgi, uint32_t val)
537 {
538 uint32_t reg;
539 int offs, bit;
540
541 offs = tgi->irq / AFI_MSI_INTR_IN_REG;
542 bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG);
543
544 if (val != 0)
545 AFI_WR4(sc, AFI_MSI_VEC(offs), bit);
546 reg = AFI_RD4(sc, AFI_MSI_EN_VEC(offs));
547 if (val != 0)
548 reg |= bit;
549 else
550 reg &= ~bit;
551 AFI_WR4(sc, AFI_MSI_EN_VEC(offs), reg);
552 }
553
554 static int
tegra_pcib_msi_intr(void * arg)555 tegra_pcib_msi_intr(void *arg)
556 {
557 u_int irq, i, bit, reg;
558 struct tegra_pcib_softc *sc;
559 struct trapframe *tf;
560 struct tegra_pcib_irqsrc *tgi;
561
562 sc = (struct tegra_pcib_softc *)arg;
563 tf = curthread->td_intr_frame;
564
565 for (i = 0; i < AFI_MSI_REGS; i++) {
566 reg = AFI_RD4(sc, AFI_MSI_VEC(i));
567 /* Handle one vector. */
568 while (reg != 0) {
569 bit = ffs(reg) - 1;
570 /* Send EOI */
571 AFI_WR4(sc, AFI_MSI_VEC(i), 1 << bit);
572 irq = i * AFI_MSI_INTR_IN_REG + bit;
573 tgi = &sc->isrcs[irq];
574 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) {
575 /* Disable stray. */
576 tegra_pcib_isrc_mask(sc, tgi, 0);
577 device_printf(sc->dev,
578 "Stray irq %u disabled\n", irq);
579 }
580 reg = AFI_RD4(sc, AFI_MSI_VEC(i));
581 }
582 }
583 return (FILTER_HANDLED);
584 }
585
586 static int
tegra_pcib_msi_attach(struct tegra_pcib_softc * sc)587 tegra_pcib_msi_attach(struct tegra_pcib_softc *sc)
588 {
589 int error;
590 uint32_t irq;
591 const char *name;
592
593 sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF,
594 M_WAITOK | M_ZERO);
595
596 name = device_get_nameunit(sc->dev);
597 for (irq = 0; irq < TEGRA_PCIB_MAX_MSI; irq++) {
598 sc->isrcs[irq].irq = irq;
599 error = intr_isrc_register(&sc->isrcs[irq].isrc,
600 sc->dev, 0, "%s,%u", name, irq);
601 if (error != 0)
602 return (error); /* XXX deregister ISRCs */
603 }
604 if (intr_msi_register(sc->dev,
605 OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0)
606 return (ENXIO);
607
608 return (0);
609 }
610
611 static int
tegra_pcib_msi_detach(struct tegra_pcib_softc * sc)612 tegra_pcib_msi_detach(struct tegra_pcib_softc *sc)
613 {
614
615 /*
616 * There has not been established any procedure yet
617 * how to detach PIC from living system correctly.
618 */
619 device_printf(sc->dev, "%s: not implemented yet\n", __func__);
620 return (EBUSY);
621 }
622
623
624 static void
tegra_pcib_msi_disable_intr(device_t dev,struct intr_irqsrc * isrc)625 tegra_pcib_msi_disable_intr(device_t dev, struct intr_irqsrc *isrc)
626 {
627 struct tegra_pcib_softc *sc;
628 struct tegra_pcib_irqsrc *tgi;
629
630 sc = device_get_softc(dev);
631 tgi = (struct tegra_pcib_irqsrc *)isrc;
632 tegra_pcib_isrc_mask(sc, tgi, 0);
633 }
634
635 static void
tegra_pcib_msi_enable_intr(device_t dev,struct intr_irqsrc * isrc)636 tegra_pcib_msi_enable_intr(device_t dev, struct intr_irqsrc *isrc)
637 {
638 struct tegra_pcib_softc *sc;
639 struct tegra_pcib_irqsrc *tgi;
640
641 sc = device_get_softc(dev);
642 tgi = (struct tegra_pcib_irqsrc *)isrc;
643 tegra_pcib_isrc_mask(sc, tgi, 1);
644 }
645
646 /* MSI interrupts are edge trigered -> do nothing */
647 static void
tegra_pcib_msi_post_filter(device_t dev,struct intr_irqsrc * isrc)648 tegra_pcib_msi_post_filter(device_t dev, struct intr_irqsrc *isrc)
649 {
650 }
651
652 static void
tegra_pcib_msi_post_ithread(device_t dev,struct intr_irqsrc * isrc)653 tegra_pcib_msi_post_ithread(device_t dev, struct intr_irqsrc *isrc)
654 {
655 }
656
657 static void
tegra_pcib_msi_pre_ithread(device_t dev,struct intr_irqsrc * isrc)658 tegra_pcib_msi_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
659 {
660 }
661
662 static int
tegra_pcib_msi_setup_intr(device_t dev,struct intr_irqsrc * isrc,struct resource * res,struct intr_map_data * data)663 tegra_pcib_msi_setup_intr(device_t dev, struct intr_irqsrc *isrc,
664 struct resource *res, struct intr_map_data *data)
665 {
666 struct tegra_pcib_softc *sc;
667 struct tegra_pcib_irqsrc *tgi;
668
669 sc = device_get_softc(dev);
670 tgi = (struct tegra_pcib_irqsrc *)isrc;
671
672 if (data == NULL || data->type != INTR_MAP_DATA_MSI)
673 return (ENOTSUP);
674
675 if (isrc->isrc_handlers == 0)
676 tegra_pcib_msi_enable_intr(dev, isrc);
677
678 return (0);
679 }
680
681 static int
tegra_pcib_msi_teardown_intr(device_t dev,struct intr_irqsrc * isrc,struct resource * res,struct intr_map_data * data)682 tegra_pcib_msi_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
683 struct resource *res, struct intr_map_data *data)
684 {
685 struct tegra_pcib_softc *sc;
686 struct tegra_pcib_irqsrc *tgi;
687
688 sc = device_get_softc(dev);
689 tgi = (struct tegra_pcib_irqsrc *)isrc;
690
691 if (isrc->isrc_handlers == 0)
692 tegra_pcib_isrc_mask(sc, tgi, 0);
693 return (0);
694 }
695
696
697 static int
tegra_pcib_msi_alloc_msi(device_t dev,device_t child,int count,int maxcount,device_t * pic,struct intr_irqsrc ** srcs)698 tegra_pcib_msi_alloc_msi(device_t dev, device_t child, int count, int maxcount,
699 device_t *pic, struct intr_irqsrc **srcs)
700 {
701 struct tegra_pcib_softc *sc;
702 int i, irq, end_irq;
703 bool found;
704
705 KASSERT(powerof2(count), ("%s: bad count", __func__));
706 KASSERT(powerof2(maxcount), ("%s: bad maxcount", __func__));
707
708 sc = device_get_softc(dev);
709 mtx_lock(&sc->mtx);
710
711 found = false;
712 for (irq = 0; (irq + count - 1) < TEGRA_PCIB_MAX_MSI; irq++) {
713 /* Start on an aligned interrupt */
714 if ((irq & (maxcount - 1)) != 0)
715 continue;
716
717 /* Assume we found a valid range until shown otherwise */
718 found = true;
719
720 /* Check this range is valid */
721 for (end_irq = irq; end_irq < irq + count; end_irq++) {
722 /* This is already used */
723 if ((sc->isrcs[end_irq].flags & TEGRA_FLAG_MSI_USED) ==
724 TEGRA_FLAG_MSI_USED) {
725 found = false;
726 break;
727 }
728 }
729
730 if (found)
731 break;
732 }
733
734 /* Not enough interrupts were found */
735 if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) {
736 mtx_unlock(&sc->mtx);
737 return (ENXIO);
738 }
739
740 for (i = 0; i < count; i++) {
741 /* Mark the interrupt as used */
742 sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED;
743
744 }
745 mtx_unlock(&sc->mtx);
746
747 for (i = 0; i < count; i++)
748 srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i];
749 *pic = device_get_parent(dev);
750 return (0);
751 }
752
753 static int
tegra_pcib_msi_release_msi(device_t dev,device_t child,int count,struct intr_irqsrc ** isrc)754 tegra_pcib_msi_release_msi(device_t dev, device_t child, int count,
755 struct intr_irqsrc **isrc)
756 {
757 struct tegra_pcib_softc *sc;
758 struct tegra_pcib_irqsrc *ti;
759 int i;
760
761 sc = device_get_softc(dev);
762 mtx_lock(&sc->mtx);
763 for (i = 0; i < count; i++) {
764 ti = (struct tegra_pcib_irqsrc *)isrc[i];
765
766 KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED,
767 ("%s: Trying to release an unused MSI-X interrupt",
768 __func__));
769
770 ti->flags &= ~TEGRA_FLAG_MSI_USED;
771 }
772 mtx_unlock(&sc->mtx);
773 return (0);
774 }
775
776 static int
tegra_pcib_msi_map_msi(device_t dev,device_t child,struct intr_irqsrc * isrc,uint64_t * addr,uint32_t * data)777 tegra_pcib_msi_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
778 uint64_t *addr, uint32_t *data)
779 {
780 struct tegra_pcib_softc *sc = device_get_softc(dev);
781 struct tegra_pcib_irqsrc *ti = (struct tegra_pcib_irqsrc *)isrc;
782
783 *addr = vtophys(sc->msi_page);
784 *data = ti->irq;
785 return (0);
786 }
787 #endif
788
789 /* ------------------------------------------------------------------- */
790 static bus_size_t
tegra_pcib_pex_ctrl(struct tegra_pcib_softc * sc,int port)791 tegra_pcib_pex_ctrl(struct tegra_pcib_softc *sc, int port)
792 {
793 if (port >= TEGRA_PCIB_MAX_PORTS)
794 panic("invalid port number: %d\n", port);
795
796 if (port == 0)
797 return (AFI_PEX0_CTRL);
798 else if (port == 1)
799 return (AFI_PEX1_CTRL);
800 else if (port == 2)
801 return (AFI_PEX2_CTRL);
802 else
803 panic("invalid port number: %d\n", port);
804 }
805
806 static int
tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc * sc)807 tegra_pcib_enable_fdt_resources(struct tegra_pcib_softc *sc)
808 {
809 int rv;
810
811 rv = hwreset_assert(sc->hwreset_pcie_x);
812 if (rv != 0) {
813 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n");
814 return (rv);
815 }
816 rv = hwreset_assert(sc->hwreset_afi);
817 if (rv != 0) {
818 device_printf(sc->dev, "Cannot assert 'afi' reset\n");
819 return (rv);
820 }
821 rv = hwreset_assert(sc->hwreset_pex);
822 if (rv != 0) {
823 device_printf(sc->dev, "Cannot assert 'pex' reset\n");
824 return (rv);
825 }
826
827 tegra_powergate_power_off(TEGRA_POWERGATE_PCX);
828
829 /* Power supplies. */
830 rv = regulator_enable(sc->supply_avddio_pex);
831 if (rv != 0) {
832 device_printf(sc->dev,
833 "Cannot enable 'avddio_pex' regulator\n");
834 return (rv);
835 }
836 rv = regulator_enable(sc->supply_dvddio_pex);
837 if (rv != 0) {
838 device_printf(sc->dev,
839 "Cannot enable 'dvddio_pex' regulator\n");
840 return (rv);
841 }
842 rv = regulator_enable(sc->supply_avdd_pex_pll);
843 if (rv != 0) {
844 device_printf(sc->dev,
845 "Cannot enable 'avdd-pex-pll' regulator\n");
846 return (rv);
847 }
848 rv = regulator_enable(sc->supply_hvdd_pex);
849 if (rv != 0) {
850 device_printf(sc->dev,
851 "Cannot enable 'hvdd-pex-supply' regulator\n");
852 return (rv);
853 }
854 rv = regulator_enable(sc->supply_hvdd_pex_pll_e);
855 if (rv != 0) {
856 device_printf(sc->dev,
857 "Cannot enable 'hvdd-pex-pll-e-supply' regulator\n");
858 return (rv);
859 }
860 rv = regulator_enable(sc->supply_vddio_pex_ctl);
861 if (rv != 0) {
862 device_printf(sc->dev,
863 "Cannot enable 'vddio-pex-ctl' regulator\n");
864 return (rv);
865 }
866 rv = regulator_enable(sc->supply_avdd_pll_erefe);
867 if (rv != 0) {
868 device_printf(sc->dev,
869 "Cannot enable 'avdd-pll-erefe-supply' regulator\n");
870 return (rv);
871 }
872
873 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCX,
874 sc->clk_pex, sc->hwreset_pex);
875 if (rv != 0) {
876 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n");
877 return (rv);
878 }
879
880 rv = hwreset_deassert(sc->hwreset_afi);
881 if (rv != 0) {
882 device_printf(sc->dev, "Cannot unreset 'afi' reset\n");
883 return (rv);
884 }
885
886 rv = clk_enable(sc->clk_afi);
887 if (rv != 0) {
888 device_printf(sc->dev, "Cannot enable 'afi' clock\n");
889 return (rv);
890 }
891 rv = clk_enable(sc->clk_cml);
892 if (rv != 0) {
893 device_printf(sc->dev, "Cannot enable 'cml' clock\n");
894 return (rv);
895 }
896 rv = clk_enable(sc->clk_pll_e);
897 if (rv != 0) {
898 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n");
899 return (rv);
900 }
901 return (0);
902 }
903
904 static struct tegra_pcib_port *
tegra_pcib_parse_port(struct tegra_pcib_softc * sc,phandle_t node)905 tegra_pcib_parse_port(struct tegra_pcib_softc *sc, phandle_t node)
906 {
907 struct tegra_pcib_port *port;
908 uint32_t tmp[5];
909 char tmpstr[6];
910 int rv;
911
912 port = malloc(sizeof(struct tegra_pcib_port), M_DEVBUF, M_WAITOK);
913
914 rv = OF_getprop(node, "status", tmpstr, sizeof(tmpstr));
915 if (rv <= 0 || strcmp(tmpstr, "okay") == 0 ||
916 strcmp(tmpstr, "ok") == 0)
917 port->enabled = 1;
918 else
919 port->enabled = 0;
920
921 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp));
922 if (rv != sizeof(tmp)) {
923 device_printf(sc->dev, "Cannot parse assigned-address: %d\n",
924 rv);
925 goto fail;
926 }
927 port->rp_base_addr = tmp[2];
928 port->rp_size = tmp[4];
929 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1;
930 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) {
931 device_printf(sc->dev, "Invalid port index: %d\n",
932 port->port_idx);
933 goto fail;
934 }
935 /* XXX - TODO:
936 * Implement proper function for parsing pci "reg" property:
937 * - it have PCI bus format
938 * - its relative to matching "assigned-addresses"
939 */
940 rv = OF_getencprop(node, "reg", tmp, sizeof(tmp));
941 if (rv != sizeof(tmp)) {
942 device_printf(sc->dev, "Cannot parse reg: %d\n", rv);
943 goto fail;
944 }
945 port->rp_base_addr += tmp[2];
946
947 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes,
948 sizeof(port->num_lanes));
949 if (rv != sizeof(port->num_lanes)) {
950 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n",
951 rv);
952 goto fail;
953 }
954 if (port->num_lanes > 4) {
955 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n",
956 port->num_lanes);
957 goto fail;
958 }
959
960 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx);
961 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx);
962
963 /* Phy. */
964 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy);
965 if (rv != 0) {
966 device_printf(sc->dev,
967 "Cannot get 'pcie-0' phy for port %d\n",
968 port->port_idx);
969 goto fail;
970 }
971
972 return (port);
973 fail:
974 free(port, M_DEVBUF);
975 return (NULL);
976 }
977
978
979 static int
tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc * sc,phandle_t node)980 tegra_pcib_parse_fdt_resources(struct tegra_pcib_softc *sc, phandle_t node)
981 {
982 phandle_t child;
983 struct tegra_pcib_port *port;
984 int rv;
985
986 /* Power supplies. */
987 rv = regulator_get_by_ofw_property(sc->dev, 0, "avddio-pex-supply",
988 &sc->supply_avddio_pex);
989 if (rv != 0) {
990 device_printf(sc->dev,
991 "Cannot get 'avddio-pex' regulator\n");
992 return (ENXIO);
993 }
994 rv = regulator_get_by_ofw_property(sc->dev, 0, "dvddio-pex-supply",
995 &sc->supply_dvddio_pex);
996 if (rv != 0) {
997 device_printf(sc->dev,
998 "Cannot get 'dvddio-pex' regulator\n");
999 return (ENXIO);
1000 }
1001 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pex-pll-supply",
1002 &sc->supply_avdd_pex_pll);
1003 if (rv != 0) {
1004 device_printf(sc->dev,
1005 "Cannot get 'avdd-pex-pll' regulator\n");
1006 return (ENXIO);
1007 }
1008 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-supply",
1009 &sc->supply_hvdd_pex);
1010 if (rv != 0) {
1011 device_printf(sc->dev,
1012 "Cannot get 'hvdd-pex' regulator\n");
1013 return (ENXIO);
1014 }
1015 rv = regulator_get_by_ofw_property(sc->dev, 0, "hvdd-pex-pll-e-supply",
1016 &sc->supply_hvdd_pex_pll_e);
1017 if (rv != 0) {
1018 device_printf(sc->dev,
1019 "Cannot get 'hvdd-pex-pll-e' regulator\n");
1020 return (ENXIO);
1021 }
1022 rv = regulator_get_by_ofw_property(sc->dev, 0, "vddio-pex-ctl-supply",
1023 &sc->supply_vddio_pex_ctl);
1024 if (rv != 0) {
1025 device_printf(sc->dev,
1026 "Cannot get 'vddio-pex-ctl' regulator\n");
1027 return (ENXIO);
1028 }
1029 rv = regulator_get_by_ofw_property(sc->dev, 0, "avdd-pll-erefe-supply",
1030 &sc->supply_avdd_pll_erefe);
1031 if (rv != 0) {
1032 device_printf(sc->dev,
1033 "Cannot get 'avdd-pll-erefe' regulator\n");
1034 return (ENXIO);
1035 }
1036
1037 /* Resets. */
1038 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex);
1039 if (rv != 0) {
1040 device_printf(sc->dev, "Cannot get 'pex' reset\n");
1041 return (ENXIO);
1042 }
1043 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi);
1044 if (rv != 0) {
1045 device_printf(sc->dev, "Cannot get 'afi' reset\n");
1046 return (ENXIO);
1047 }
1048 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x);
1049 if (rv != 0) {
1050 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n");
1051 return (ENXIO);
1052 }
1053
1054 /* Clocks. */
1055 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex);
1056 if (rv != 0) {
1057 device_printf(sc->dev, "Cannot get 'pex' clock\n");
1058 return (ENXIO);
1059 }
1060 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi);
1061 if (rv != 0) {
1062 device_printf(sc->dev, "Cannot get 'afi' clock\n");
1063 return (ENXIO);
1064 }
1065 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e);
1066 if (rv != 0) {
1067 device_printf(sc->dev, "Cannot get 'pll_e' clock\n");
1068 return (ENXIO);
1069 }
1070 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml);
1071 if (rv != 0) {
1072 device_printf(sc->dev, "Cannot get 'cml' clock\n");
1073 return (ENXIO);
1074 }
1075
1076 /* Ports */
1077 sc->num_ports = 0;
1078 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
1079 port = tegra_pcib_parse_port(sc, child);
1080 if (port == NULL) {
1081 device_printf(sc->dev, "Cannot parse PCIe port node\n");
1082 return (ENXIO);
1083 }
1084 sc->ports[sc->num_ports++] = port;
1085 }
1086
1087 return (0);
1088 }
1089
1090 static int
tegra_pcib_decode_ranges(struct tegra_pcib_softc * sc,struct ofw_pci_range * ranges,int nranges)1091 tegra_pcib_decode_ranges(struct tegra_pcib_softc *sc,
1092 struct ofw_pci_range *ranges, int nranges)
1093 {
1094 int i;
1095
1096 for (i = 2; i < nranges; i++) {
1097 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
1098 OFW_PCI_PHYS_HI_SPACE_IO) {
1099 if (sc->io_range.size != 0) {
1100 device_printf(sc->dev,
1101 "Duplicated IO range found in DT\n");
1102 return (ENXIO);
1103 }
1104 sc->io_range = ranges[i];
1105 }
1106 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) ==
1107 OFW_PCI_PHYS_HI_SPACE_MEM32)) {
1108 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) {
1109 if (sc->pref_mem_range.size != 0) {
1110 device_printf(sc->dev,
1111 "Duplicated memory range found "
1112 "in DT\n");
1113 return (ENXIO);
1114 }
1115 sc->pref_mem_range = ranges[i];
1116 } else {
1117 if (sc->mem_range.size != 0) {
1118 device_printf(sc->dev,
1119 "Duplicated memory range found "
1120 "in DT\n");
1121 return (ENXIO);
1122 }
1123 sc->mem_range = ranges[i];
1124 }
1125 }
1126 }
1127 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0)
1128 || (sc->pref_mem_range.size == 0)) {
1129 device_printf(sc->dev,
1130 " Not all required ranges are found in DT\n");
1131 return (ENXIO);
1132 }
1133 return (0);
1134 }
1135
1136 /*
1137 * Hardware config.
1138 */
1139 static int
tegra_pcib_wait_for_link(struct tegra_pcib_softc * sc,struct tegra_pcib_port * port)1140 tegra_pcib_wait_for_link(struct tegra_pcib_softc *sc,
1141 struct tegra_pcib_port *port)
1142 {
1143 uint32_t reg;
1144 int i;
1145
1146
1147 /* Setup link detection. */
1148 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
1149 RP_PRIV_MISC, 4);
1150 reg &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
1151 reg |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
1152 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0,
1153 RP_PRIV_MISC, reg, 4);
1154
1155 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) {
1156 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
1157 RP_VEND_XP, 4);
1158 if (reg & RP_VEND_XP_DL_UP)
1159 break;
1160 DELAY(1);
1161
1162 }
1163 if (i <= 0)
1164 return (ETIMEDOUT);
1165
1166 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) {
1167 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0,
1168 RP_LINK_CONTROL_STATUS, 4);
1169 if (reg & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
1170 break;
1171
1172 DELAY(1);
1173 }
1174 if (i <= 0)
1175 return (ETIMEDOUT);
1176 return (0);
1177 }
1178
1179 static void
tegra_pcib_port_enable(struct tegra_pcib_softc * sc,int port_num)1180 tegra_pcib_port_enable(struct tegra_pcib_softc *sc, int port_num)
1181 {
1182 struct tegra_pcib_port *port;
1183 uint32_t reg;
1184 int rv;
1185
1186 port = sc->ports[port_num];
1187
1188 /* Put port to reset. */
1189 reg = AFI_RD4(sc, port->afi_pex_ctrl);
1190 reg &= ~AFI_PEX_CTRL_RST_L;
1191 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1192 AFI_RD4(sc, port->afi_pex_ctrl);
1193 DELAY(10);
1194
1195 /* Enable clocks. */
1196 reg |= AFI_PEX_CTRL_REFCLK_EN;
1197 reg |= AFI_PEX_CTRL_CLKREQ_EN;
1198 reg |= AFI_PEX_CTRL_OVERRIDE_EN;
1199 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1200 AFI_RD4(sc, port->afi_pex_ctrl);
1201 DELAY(100);
1202
1203 /* Release reset. */
1204 reg |= AFI_PEX_CTRL_RST_L;
1205 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1206
1207 rv = tegra_pcib_wait_for_link(sc, port);
1208 if (bootverbose)
1209 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n",
1210 port->port_idx, port->num_lanes,
1211 port->num_lanes > 1 ? "s": "",
1212 rv == 0 ? "up": "down");
1213 }
1214
1215
1216 static void
tegra_pcib_port_disable(struct tegra_pcib_softc * sc,uint32_t port_num)1217 tegra_pcib_port_disable(struct tegra_pcib_softc *sc, uint32_t port_num)
1218 {
1219 struct tegra_pcib_port *port;
1220 uint32_t reg;
1221
1222 port = sc->ports[port_num];
1223
1224 /* Put port to reset. */
1225 reg = AFI_RD4(sc, port->afi_pex_ctrl);
1226 reg &= ~AFI_PEX_CTRL_RST_L;
1227 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1228 AFI_RD4(sc, port->afi_pex_ctrl);
1229 DELAY(10);
1230
1231 /* Disable clocks. */
1232 reg &= ~AFI_PEX_CTRL_CLKREQ_EN;
1233 reg &= ~AFI_PEX_CTRL_REFCLK_EN;
1234 AFI_WR4(sc, port->afi_pex_ctrl, reg);
1235
1236 if (bootverbose)
1237 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n",
1238 port->port_idx, port->num_lanes,
1239 port->num_lanes > 1 ? "s": "");
1240 }
1241
1242 static void
tegra_pcib_set_bar(struct tegra_pcib_softc * sc,int bar,uint32_t axi,uint64_t fpci,uint32_t size,int is_memory)1243 tegra_pcib_set_bar(struct tegra_pcib_softc *sc, int bar, uint32_t axi,
1244 uint64_t fpci, uint32_t size, int is_memory)
1245 {
1246 uint32_t fpci_reg;
1247 uint32_t axi_reg;
1248 uint32_t size_reg;
1249
1250 axi_reg = axi & ~0xFFF;
1251 size_reg = size >> 12;
1252 fpci_reg = (uint32_t)(fpci >> 8) & ~0xF;
1253 fpci_reg |= is_memory ? 0x1 : 0x0;
1254 AFI_WR4(sc, bars[bar].axi_start, axi_reg);
1255 AFI_WR4(sc, bars[bar].size, size_reg);
1256 AFI_WR4(sc, bars[bar].fpci_start, fpci_reg);
1257 }
1258
1259 static int
tegra_pcib_enable(struct tegra_pcib_softc * sc)1260 tegra_pcib_enable(struct tegra_pcib_softc *sc)
1261 {
1262 int rv;
1263 int i;
1264 uint32_t reg;
1265
1266 rv = tegra_pcib_enable_fdt_resources(sc);
1267 if (rv != 0) {
1268 device_printf(sc->dev, "Cannot enable FDT resources\n");
1269 return (rv);
1270 }
1271 /* Enable PLLE control. */
1272 reg = AFI_RD4(sc, AFI_PLLE_CONTROL);
1273 reg &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
1274 reg |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
1275 AFI_WR4(sc, AFI_PLLE_CONTROL, reg);
1276
1277 /* Set bias pad. */
1278 AFI_WR4(sc, AFI_PEXBIAS_CTRL, 0);
1279
1280 /* Configure mode and ports. */
1281 reg = AFI_RD4(sc, AFI_PCIE_CONFIG);
1282 reg &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
1283 if (sc->lanes_cfg == 0x14) {
1284 if (bootverbose)
1285 device_printf(sc->dev,
1286 "Using x1,x4 configuration\n");
1287 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR4_1;
1288 } else if (sc->lanes_cfg == 0x12) {
1289 if (bootverbose)
1290 device_printf(sc->dev,
1291 "Using x1,x2 configuration\n");
1292 reg |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_XBAR2_1;
1293 } else {
1294 device_printf(sc->dev,
1295 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg);
1296 }
1297 reg |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL;
1298 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
1299 if ((sc->ports[i] != NULL))
1300 reg &=
1301 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx);
1302 }
1303 AFI_WR4(sc, AFI_PCIE_CONFIG, reg);
1304
1305 /* Enable Gen2 support. */
1306 reg = AFI_RD4(sc, AFI_FUSE);
1307 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
1308 AFI_WR4(sc, AFI_FUSE, reg);
1309
1310 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
1311 if (sc->ports[i] != NULL) {
1312 rv = phy_enable(sc->ports[i]->phy);
1313 if (rv != 0) {
1314 device_printf(sc->dev,
1315 "Cannot enable phy for port %d\n",
1316 sc->ports[i]->port_idx);
1317 return (rv);
1318 }
1319 }
1320 }
1321
1322
1323 rv = hwreset_deassert(sc->hwreset_pcie_x);
1324 if (rv != 0) {
1325 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n");
1326 return (rv);
1327 }
1328
1329 /* Enable config space. */
1330 reg = AFI_RD4(sc, AFI_CONFIGURATION);
1331 reg |= AFI_CONFIGURATION_EN_FPCI;
1332 AFI_WR4(sc, AFI_CONFIGURATION, reg);
1333
1334 /* Enable AFI errors. */
1335 reg = 0;
1336 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_SLVERR);
1337 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_INI_DECERR);
1338 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_SLVERR);
1339 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_DECERR);
1340 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_TGT_WRERR);
1341 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_SM_MSG);
1342 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_DFPCI_DECERR);
1343 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_AXI_DECERR);
1344 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_FPCI_TIMEOUT);
1345 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_PRSNT_SENSE);
1346 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_PE_CLKREQ_SENSE);
1347 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_CLKCLAMP_SENSE);
1348 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_RDY4PD_SENSE);
1349 reg |= AFI_AFI_INTR_ENABLE_CODE(AFI_INTR_CODE_INT_CODE_P2P_ERROR);
1350 AFI_WR4(sc, AFI_AFI_INTR_ENABLE, reg);
1351 AFI_WR4(sc, AFI_SM_INTR_ENABLE, 0xffffffff);
1352
1353 /* Enable INT, disable MSI. */
1354 AFI_WR4(sc, AFI_INTR_MASK, AFI_INTR_MASK_INT_MASK);
1355
1356 /* Mask all FPCI errors. */
1357 AFI_WR4(sc, AFI_FPCI_ERROR_MASKS, 0);
1358
1359 /* Setup AFI translation windows. */
1360 /* BAR 0 - type 1 extended configuration. */
1361 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res),
1362 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0);
1363
1364 /* BAR 1 - downstream I/O. */
1365 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO,
1366 sc->io_range.size, 0);
1367
1368 /* BAR 2 - downstream prefetchable memory 1:1. */
1369 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host,
1370 sc->pref_mem_range.host, sc->pref_mem_range.size, 1);
1371
1372 /* BAR 3 - downstream not prefetchable memory 1:1 .*/
1373 tegra_pcib_set_bar(sc, 3, sc->mem_range.host,
1374 sc->mem_range.host, sc->mem_range.size, 1);
1375
1376 /* BAR 3-8 clear. */
1377 tegra_pcib_set_bar(sc, 4, 0, 0, 0, 0);
1378 tegra_pcib_set_bar(sc, 5, 0, 0, 0, 0);
1379 tegra_pcib_set_bar(sc, 6, 0, 0, 0, 0);
1380 tegra_pcib_set_bar(sc, 7, 0, 0, 0, 0);
1381 tegra_pcib_set_bar(sc, 8, 0, 0, 0, 0);
1382
1383 /* MSI BAR - clear. */
1384 tegra_pcib_set_bar(sc, 9, 0, 0, 0, 0);
1385 return(0);
1386 }
1387
1388 #ifdef TEGRA_PCIB_MSI_ENABLE
1389 static int
tegra_pcib_attach_msi(device_t dev)1390 tegra_pcib_attach_msi(device_t dev)
1391 {
1392 struct tegra_pcib_softc *sc;
1393 uint32_t reg;
1394 int i, rv;
1395
1396 sc = device_get_softc(dev);
1397
1398 sc->msi_page = kmem_alloc_contig(PAGE_SIZE, M_WAITOK, 0,
1399 BUS_SPACE_MAXADDR, PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
1400
1401 /* MSI BAR */
1402 tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page),
1403 PAGE_SIZE, 0);
1404
1405 /* Disble and clear all interrupts. */
1406 for (i = 0; i < AFI_MSI_REGS; i++) {
1407 AFI_WR4(sc, AFI_MSI_EN_VEC(i), 0);
1408 AFI_WR4(sc, AFI_MSI_VEC(i), 0xFFFFFFFF);
1409 }
1410 rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1411 tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie);
1412 if (rv != 0) {
1413 device_printf(dev, "cannot setup MSI interrupt handler\n");
1414 rv = ENXIO;
1415 goto out;
1416 }
1417
1418 if (tegra_pcib_msi_attach(sc) != 0) {
1419 device_printf(dev, "WARNING: unable to attach PIC\n");
1420 tegra_pcib_msi_detach(sc);
1421 goto out;
1422 }
1423
1424 /* Unmask MSI interrupt. */
1425 reg = AFI_RD4(sc, AFI_INTR_MASK);
1426 reg |= AFI_INTR_MASK_MSI_MASK;
1427 AFI_WR4(sc, AFI_INTR_MASK, reg);
1428
1429 out:
1430 return (rv);
1431 }
1432 #endif
1433
1434 static int
tegra_pcib_probe(device_t dev)1435 tegra_pcib_probe(device_t dev)
1436 {
1437 if (!ofw_bus_status_okay(dev))
1438 return (ENXIO);
1439
1440 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
1441 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller");
1442 return (BUS_PROBE_DEFAULT);
1443 }
1444 return (ENXIO);
1445 }
1446
1447 static int
tegra_pcib_attach(device_t dev)1448 tegra_pcib_attach(device_t dev)
1449 {
1450 struct tegra_pcib_softc *sc;
1451 phandle_t node;
1452 int rv;
1453 int rid;
1454 struct tegra_pcib_port *port;
1455 int i;
1456
1457 sc = device_get_softc(dev);
1458 sc->dev = dev;
1459 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF);
1460
1461 node = ofw_bus_get_node(dev);
1462
1463 rv = tegra_pcib_parse_fdt_resources(sc, node);
1464 if (rv != 0) {
1465 device_printf(dev, "Cannot get FDT resources\n");
1466 return (rv);
1467 }
1468
1469 /* Allocate bus_space resources. */
1470 rid = 0;
1471 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1472 RF_ACTIVE);
1473 if (sc->pads_mem_res == NULL) {
1474 device_printf(dev, "Cannot allocate PADS register\n");
1475 rv = ENXIO;
1476 goto out;
1477 }
1478 /*
1479 * XXX - FIXME
1480 * tag for config space is not filled when RF_ALLOCATED flag is used.
1481 */
1482 sc->bus_tag = rman_get_bustag(sc->pads_mem_res);
1483
1484 rid = 1;
1485 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1486 RF_ACTIVE);
1487 if (sc->afi_mem_res == NULL) {
1488 device_printf(dev, "Cannot allocate AFI register\n");
1489 rv = ENXIO;
1490 goto out;
1491 }
1492
1493 rid = 2;
1494 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1495 RF_ALLOCATED);
1496 if (sc->cfg_mem_res == NULL) {
1497 device_printf(dev, "Cannot allocate config space memory\n");
1498 rv = ENXIO;
1499 goto out;
1500 }
1501 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res);
1502
1503
1504 /* Map RP slots */
1505 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
1506 if (sc->ports[i] == NULL)
1507 continue;
1508 port = sc->ports[i];
1509 rv = bus_space_map(sc->bus_tag, port->rp_base_addr,
1510 port->rp_size, 0, &port->cfg_handle);
1511 if (rv != 0) {
1512 device_printf(sc->dev, "Cannot allocate memory for "
1513 "port: %d\n", i);
1514 rv = ENXIO;
1515 goto out;
1516 }
1517 }
1518
1519 /*
1520 * Get PCI interrupt
1521 */
1522 rid = 0;
1523 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1524 RF_ACTIVE | RF_SHAREABLE);
1525 if (sc->irq_res == NULL) {
1526 device_printf(dev, "Cannot allocate IRQ resources\n");
1527 rv = ENXIO;
1528 goto out;
1529 }
1530
1531 rid = 1;
1532 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1533 RF_ACTIVE);
1534 if (sc->irq_res == NULL) {
1535 device_printf(dev, "Cannot allocate MSI IRQ resources\n");
1536 rv = ENXIO;
1537 goto out;
1538 }
1539
1540 sc->ofw_pci.sc_range_mask = 0x3;
1541 rv = ofw_pci_init(dev);
1542 if (rv != 0)
1543 goto out;
1544
1545 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range,
1546 sc->ofw_pci.sc_nrange);
1547 if (rv != 0)
1548 goto out;
1549
1550 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
1551 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) {
1552 device_printf(dev, "cannot setup interrupt handler\n");
1553 rv = ENXIO;
1554 goto out;
1555 }
1556
1557 /*
1558 * Enable PCIE device.
1559 */
1560 rv = tegra_pcib_enable(sc);
1561 if (rv != 0)
1562 goto out;
1563 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) {
1564 if (sc->ports[i] == NULL)
1565 continue;
1566 if (sc->ports[i]->enabled)
1567 tegra_pcib_port_enable(sc, i);
1568 else
1569 tegra_pcib_port_disable(sc, i);
1570 }
1571
1572 #ifdef TEGRA_PCIB_MSI_ENABLE
1573 rv = tegra_pcib_attach_msi(dev);
1574 if (rv != 0)
1575 goto out;
1576 #endif
1577 device_add_child(dev, "pci", -1);
1578
1579 return (bus_generic_attach(dev));
1580
1581 out:
1582
1583 return (rv);
1584 }
1585
1586
1587 static device_method_t tegra_pcib_methods[] = {
1588 /* Device interface */
1589 DEVMETHOD(device_probe, tegra_pcib_probe),
1590 DEVMETHOD(device_attach, tegra_pcib_attach),
1591
1592 /* Bus interface */
1593 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1594 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1595
1596 /* pcib interface */
1597 DEVMETHOD(pcib_maxslots, tegra_pcib_maxslots),
1598 DEVMETHOD(pcib_read_config, tegra_pcib_read_config),
1599 DEVMETHOD(pcib_write_config, tegra_pcib_write_config),
1600 DEVMETHOD(pcib_route_interrupt, tegra_pcib_route_interrupt),
1601 DEVMETHOD(pcib_alloc_msi, tegra_pcib_alloc_msi),
1602 DEVMETHOD(pcib_release_msi, tegra_pcib_release_msi),
1603 DEVMETHOD(pcib_map_msi, tegra_pcib_map_msi),
1604 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
1605
1606 #ifdef TEGRA_PCIB_MSI_ENABLE
1607 /* MSI/MSI-X */
1608 DEVMETHOD(msi_alloc_msi, tegra_pcib_msi_alloc_msi),
1609 DEVMETHOD(msi_release_msi, tegra_pcib_msi_release_msi),
1610 DEVMETHOD(msi_map_msi, tegra_pcib_msi_map_msi),
1611
1612 /* Interrupt controller interface */
1613 DEVMETHOD(pic_disable_intr, tegra_pcib_msi_disable_intr),
1614 DEVMETHOD(pic_enable_intr, tegra_pcib_msi_enable_intr),
1615 DEVMETHOD(pic_setup_intr, tegra_pcib_msi_setup_intr),
1616 DEVMETHOD(pic_teardown_intr, tegra_pcib_msi_teardown_intr),
1617 DEVMETHOD(pic_post_filter, tegra_pcib_msi_post_filter),
1618 DEVMETHOD(pic_post_ithread, tegra_pcib_msi_post_ithread),
1619 DEVMETHOD(pic_pre_ithread, tegra_pcib_msi_pre_ithread),
1620 #endif
1621
1622 /* OFW bus interface */
1623 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
1624 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
1625 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
1626 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
1627 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
1628
1629 DEVMETHOD_END
1630 };
1631
1632 static devclass_t pcib_devclass;
1633 DEFINE_CLASS_1(pcib, tegra_pcib_driver, tegra_pcib_methods,
1634 sizeof(struct tegra_pcib_softc), ofw_pci_driver);
1635 DRIVER_MODULE(pcib, simplebus, tegra_pcib_driver, pcib_devclass,
1636 NULL, NULL);
1637