1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC 4 * 5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Sandeep Sheriker M <[email protected]> 8 */ 9 10#include <dt-bindings/dma/at91.h> 11#include <dt-bindings/pinctrl/at91.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/clock/at91.h> 15#include <dt-bindings/mfd/atmel-flexcom.h> 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 model = "Microchip SAM9X60 SoC"; 21 compatible = "microchip,sam9x60"; 22 interrupt-parent = <&aic>; 23 24 aliases { 25 serial0 = &dbgu; 26 gpio0 = &pioA; 27 gpio1 = &pioB; 28 gpio2 = &pioC; 29 gpio3 = &pioD; 30 tcb0 = &tcb0; 31 tcb1 = &tcb1; 32 }; 33 34 cpus { 35 #address-cells = <0>; 36 #size-cells = <0>; 37 38 cpu { 39 compatible = "arm,arm926ej-s"; 40 device_type = "cpu"; 41 }; 42 }; 43 44 memory { 45 device_type = "memory"; 46 reg = <0x20000000 0x10000000>; 47 }; 48 49 clocks { 50 slow_xtal: slow_xtal { 51 compatible = "fixed-clock"; 52 #clock-cells = <0>; 53 }; 54 55 main_xtal: main_xtal { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 }; 59 }; 60 61 sram: sram@300000 { 62 compatible = "mmio-sram"; 63 reg = <0x00300000 0x100000>; 64 }; 65 66 ahb { 67 compatible = "simple-bus"; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 ranges; 71 72 usb1: ohci@600000 { 73 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 74 reg = <0x00600000 0x100000>; 75 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 76 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; 77 clock-names = "ohci_clk", "hclk", "uhpck"; 78 status = "disabled"; 79 }; 80 81 usb2: ehci@700000 { 82 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 83 reg = <0x00700000 0x100000>; 84 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 85 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; 86 clock-names = "usb_clk", "ehci_clk"; 87 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; 88 assigned-clock-rates = <480000000>; 89 status = "disabled"; 90 }; 91 92 ebi: ebi@10000000 { 93 compatible = "microchip,sam9x60-ebi"; 94 #address-cells = <2>; 95 #size-cells = <1>; 96 atmel,smc = <&smc>; 97 microchip,sfr = <&sfr>; 98 reg = <0x10000000 0x60000000>; 99 ranges = <0x0 0x0 0x10000000 0x10000000 100 0x1 0x0 0x20000000 0x10000000 101 0x2 0x0 0x30000000 0x10000000 102 0x3 0x0 0x40000000 0x10000000 103 0x4 0x0 0x50000000 0x10000000 104 0x5 0x0 0x60000000 0x10000000>; 105 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 106 status = "disabled"; 107 108 nand_controller: nand-controller { 109 compatible = "microchip,sam9x60-nand-controller"; 110 ecc-engine = <&pmecc>; 111 #address-cells = <2>; 112 #size-cells = <1>; 113 ranges; 114 status = "disabled"; 115 }; 116 }; 117 118 sdmmc0: sdio-host@80000000 { 119 compatible = "microchip,sam9x60-sdhci"; 120 reg = <0x80000000 0x300>; 121 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 122 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; 123 clock-names = "hclock", "multclk"; 124 assigned-clocks = <&pmc PMC_TYPE_GCK 12>; 125 assigned-clock-rates = <100000000>; 126 status = "disabled"; 127 }; 128 129 sdmmc1: sdio-host@90000000 { 130 compatible = "microchip,sam9x60-sdhci"; 131 reg = <0x90000000 0x300>; 132 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 133 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; 134 clock-names = "hclock", "multclk"; 135 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 136 assigned-clock-rates = <100000000>; 137 status = "disabled"; 138 }; 139 140 apb { 141 compatible = "simple-bus"; 142 #address-cells = <1>; 143 #size-cells = <1>; 144 ranges; 145 146 flx4: flexcom@f0000000 { 147 compatible = "atmel,sama5d2-flexcom"; 148 reg = <0xf0000000 0x200>; 149 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 ranges = <0x0 0xf0000000 0x800>; 153 status = "disabled"; 154 }; 155 156 flx5: flexcom@f0004000 { 157 compatible = "atmel,sama5d2-flexcom"; 158 reg = <0xf0004000 0x200>; 159 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 ranges = <0x0 0xf0004000 0x800>; 163 status = "disabled"; 164 }; 165 166 dma0: dma-controller@f0008000 { 167 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma"; 168 reg = <0xf0008000 0x1000>; 169 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 170 #dma-cells = <1>; 171 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 172 clock-names = "dma_clk"; 173 }; 174 175 ssc: ssc@f0010000 { 176 compatible = "atmel,at91sam9g45-ssc"; 177 reg = <0xf0010000 0x4000>; 178 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 179 dmas = <&dma0 180 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 181 AT91_XDMAC_DT_PERID(38))>, 182 <&dma0 183 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 184 AT91_XDMAC_DT_PERID(39))>; 185 dma-names = "tx", "rx"; 186 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 187 clock-names = "pclk"; 188 status = "disabled"; 189 }; 190 191 qspi: spi@f0014000 { 192 compatible = "microchip,sam9x60-qspi"; 193 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; 194 reg-names = "qspi_base", "qspi_mmap"; 195 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; 196 dmas = <&dma0 197 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 198 AT91_XDMAC_DT_PERID(26))>, 199 <&dma0 200 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 201 AT91_XDMAC_DT_PERID(27))>; 202 dma-names = "tx", "rx"; 203 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>; 204 clock-names = "pclk", "qspick"; 205 atmel,pmc = <&pmc>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 status = "disabled"; 209 }; 210 211 i2s: i2s@f001c000 { 212 compatible = "microchip,sam9x60-i2smcc"; 213 reg = <0xf001c000 0x100>; 214 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 215 dmas = <&dma0 216 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 217 AT91_XDMAC_DT_PERID(36))>, 218 <&dma0 219 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 220 AT91_XDMAC_DT_PERID(37))>; 221 dma-names = "tx", "rx"; 222 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; 223 clock-names = "pclk", "gclk"; 224 status = "disabled"; 225 }; 226 227 flx11: flexcom@f0020000 { 228 compatible = "atmel,sama5d2-flexcom"; 229 reg = <0xf0020000 0x200>; 230 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 ranges = <0x0 0xf0020000 0x800>; 234 status = "disabled"; 235 }; 236 237 flx12: flexcom@f0024000 { 238 compatible = "atmel,sama5d2-flexcom"; 239 reg = <0xf0024000 0x200>; 240 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 241 #address-cells = <1>; 242 #size-cells = <1>; 243 ranges = <0x0 0xf0024000 0x800>; 244 status = "disabled"; 245 }; 246 247 pit64b: timer@f0028000 { 248 compatible = "microchip,sam9x60-pit64b"; 249 reg = <0xf0028000 0x100>; 250 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; 251 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; 252 clock-names = "pclk", "gclk"; 253 }; 254 255 sha: sha@f002c000 { 256 compatible = "atmel,at91sam9g46-sha"; 257 reg = <0xf002c000 0x100>; 258 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 259 dmas = <&dma0 260 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 261 AT91_XDMAC_DT_PERID(34))>; 262 dma-names = "tx"; 263 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 264 clock-names = "sha_clk"; 265 status = "okay"; 266 }; 267 268 trng: trng@f0030000 { 269 compatible = "microchip,sam9x60-trng"; 270 reg = <0xf0030000 0x100>; 271 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; 272 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 273 status = "okay"; 274 }; 275 276 aes: aes@f0034000 { 277 compatible = "atmel,at91sam9g46-aes"; 278 reg = <0xf0034000 0x100>; 279 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; 280 dmas = <&dma0 281 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 282 AT91_XDMAC_DT_PERID(32))>, 283 <&dma0 284 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 285 AT91_XDMAC_DT_PERID(33))>; 286 dma-names = "tx", "rx"; 287 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 288 clock-names = "aes_clk"; 289 status = "okay"; 290 }; 291 292 tdes: tdes@f0038000 { 293 compatible = "atmel,at91sam9g46-tdes"; 294 reg = <0xf0038000 0x100>; 295 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 296 dmas = <&dma0 297 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 298 AT91_XDMAC_DT_PERID(31))>, 299 <&dma0 300 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 301 AT91_XDMAC_DT_PERID(30))>; 302 dma-names = "tx", "rx"; 303 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 304 clock-names = "tdes_clk"; 305 status = "okay"; 306 }; 307 308 classd: classd@f003c000 { 309 compatible = "atmel,sama5d2-classd"; 310 reg = <0xf003c000 0x100>; 311 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; 312 dmas = <&dma0 313 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 314 AT91_XDMAC_DT_PERID(35))>; 315 dma-names = "tx"; 316 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; 317 clock-names = "pclk", "gclk"; 318 status = "disabled"; 319 }; 320 321 can0: can@f8000000 { 322 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; 323 reg = <0xf8000000 0x300>; 324 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; 325 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 326 clock-names = "can_clk"; 327 status = "disabled"; 328 }; 329 330 can1: can@f8004000 { 331 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; 332 reg = <0xf8004000 0x300>; 333 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; 334 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 335 clock-names = "can_clk"; 336 status = "disabled"; 337 }; 338 339 tcb0: timer@f8008000 { 340 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 reg = <0xf8008000 0x100>; 344 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 345 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; 346 clock-names = "t0_clk", "slow_clk"; 347 }; 348 349 tcb1: timer@f800c000 { 350 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 reg = <0xf800c000 0x100>; 354 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 355 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>; 356 clock-names = "t0_clk", "slow_clk"; 357 }; 358 359 flx6: flexcom@f8010000 { 360 compatible = "atmel,sama5d2-flexcom"; 361 reg = <0xf8010000 0x200>; 362 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 363 #address-cells = <1>; 364 #size-cells = <1>; 365 ranges = <0x0 0xf8010000 0x800>; 366 status = "disabled"; 367 }; 368 369 flx7: flexcom@f8014000 { 370 compatible = "atmel,sama5d2-flexcom"; 371 reg = <0xf8014000 0x200>; 372 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 373 #address-cells = <1>; 374 #size-cells = <1>; 375 ranges = <0x0 0xf8014000 0x800>; 376 status = "disabled"; 377 }; 378 379 flx8: flexcom@f8018000 { 380 compatible = "atmel,sama5d2-flexcom"; 381 reg = <0xf8018000 0x200>; 382 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 383 #address-cells = <1>; 384 #size-cells = <1>; 385 ranges = <0x0 0xf8018000 0x800>; 386 status = "disabled"; 387 }; 388 389 flx0: flexcom@f801c000 { 390 compatible = "atmel,sama5d2-flexcom"; 391 reg = <0xf801c000 0x200>; 392 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 393 #address-cells = <1>; 394 #size-cells = <1>; 395 ranges = <0x0 0xf801c000 0x800>; 396 status = "disabled"; 397 }; 398 399 flx1: flexcom@f8020000 { 400 compatible = "atmel,sama5d2-flexcom"; 401 reg = <0xf8020000 0x200>; 402 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 403 #address-cells = <1>; 404 #size-cells = <1>; 405 ranges = <0x0 0xf8020000 0x800>; 406 status = "disabled"; 407 }; 408 409 flx2: flexcom@f8024000 { 410 compatible = "atmel,sama5d2-flexcom"; 411 reg = <0xf8024000 0x200>; 412 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 413 #address-cells = <1>; 414 #size-cells = <1>; 415 ranges = <0x0 0xf8024000 0x800>; 416 status = "disabled"; 417 }; 418 419 flx3: flexcom@f8028000 { 420 compatible = "atmel,sama5d2-flexcom"; 421 reg = <0xf8028000 0x200>; 422 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 423 #address-cells = <1>; 424 #size-cells = <1>; 425 ranges = <0x0 0xf8028000 0x800>; 426 status = "disabled"; 427 }; 428 429 macb0: ethernet@f802c000 { 430 compatible = "cdns,sam9x60-macb", "cdns,macb"; 431 reg = <0xf802c000 0x1000>; 432 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 433 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; 434 clock-names = "hclk", "pclk"; 435 status = "disabled"; 436 }; 437 438 macb1: ethernet@f8030000 { 439 compatible = "cdns,sam9x60-macb", "cdns,macb"; 440 reg = <0xf8030000 0x1000>; 441 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; 442 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; 443 clock-names = "hclk", "pclk"; 444 status = "disabled"; 445 }; 446 447 pwm0: pwm@f8034000 { 448 compatible = "microchip,sam9x60-pwm"; 449 reg = <0xf8034000 0x300>; 450 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 451 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 452 #pwm-cells = <3>; 453 status="disabled"; 454 }; 455 456 hlcdc: hlcdc@f8038000 { 457 compatible = "microchip,sam9x60-hlcdc"; 458 reg = <0xf8038000 0x4000>; 459 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; 460 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; 461 clock-names = "periph_clk","sys_clk", "slow_clk"; 462 assigned-clocks = <&pmc PMC_TYPE_GCK 25>; 463 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>; 464 status = "disabled"; 465 466 hlcdc-display-controller { 467 compatible = "atmel,hlcdc-display-controller"; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 471 port@0 { 472 #address-cells = <1>; 473 #size-cells = <0>; 474 reg = <0>; 475 }; 476 }; 477 478 hlcdc_pwm: hlcdc-pwm { 479 compatible = "atmel,hlcdc-pwm"; 480 #pwm-cells = <3>; 481 }; 482 }; 483 484 flx9: flexcom@f8040000 { 485 compatible = "atmel,sama5d2-flexcom"; 486 reg = <0xf8040000 0x200>; 487 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 488 #address-cells = <1>; 489 #size-cells = <1>; 490 ranges = <0x0 0xf8040000 0x800>; 491 status = "disabled"; 492 }; 493 494 flx10: flexcom@f8044000 { 495 compatible = "atmel,sama5d2-flexcom"; 496 reg = <0xf8044000 0x200>; 497 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 498 #address-cells = <1>; 499 #size-cells = <1>; 500 ranges = <0x0 0xf8044000 0x800>; 501 status = "disabled"; 502 }; 503 504 isi: isi@f8048000 { 505 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi"; 506 reg = <0xf8048000 0x100>; 507 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>; 508 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 509 clock-names = "isi_clk"; 510 status = "disabled"; 511 port { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 }; 515 }; 516 517 adc: adc@f804c000 { 518 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc"; 519 reg = <0xf804c000 0x100>; 520 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 521 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 522 clock-names = "adc_clk"; 523 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>; 524 dma-names = "rx"; 525 atmel,min-sample-rate-hz = <200000>; 526 atmel,max-sample-rate-hz = <20000000>; 527 atmel,startup-time-ms = <4>; 528 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 529 #io-channel-cells = <1>; 530 status = "disabled"; 531 }; 532 533 sfr: sfr@f8050000 { 534 compatible = "microchip,sam9x60-sfr", "syscon"; 535 reg = <0xf8050000 0x100>; 536 }; 537 538 matrix: matrix@ffffde00 { 539 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon"; 540 reg = <0xffffde00 0x200>; 541 }; 542 543 pmecc: ecc-engine@ffffe000 { 544 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; 545 reg = <0xffffe000 0x300>, 546 <0xffffe600 0x100>; 547 }; 548 549 mpddrc: mpddrc@ffffe800 { 550 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; 551 reg = <0xffffe800 0x200>; 552 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; 553 clock-names = "ddrck", "mpddr"; 554 }; 555 556 smc: smc@ffffea00 { 557 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; 558 reg = <0xffffea00 0x100>; 559 }; 560 561 aic: interrupt-controller@fffff100 { 562 compatible = "microchip,sam9x60-aic"; 563 #interrupt-cells = <3>; 564 interrupt-controller; 565 reg = <0xfffff100 0x100>; 566 atmel,external-irqs = <31>; 567 }; 568 569 dbgu: serial@fffff200 { 570 compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 571 reg = <0xfffff200 0x200>; 572 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; 573 dmas = <&dma0 574 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 575 AT91_XDMAC_DT_PERID(28))>, 576 <&dma0 577 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 578 AT91_XDMAC_DT_PERID(29))>; 579 dma-names = "tx", "rx"; 580 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 581 clock-names = "usart"; 582 status = "disabled"; 583 }; 584 585 pinctrl: pinctrl@fffff400 { 586 #address-cells = <1>; 587 #size-cells = <1>; 588 compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; 589 ranges = <0xfffff400 0xfffff400 0x800>; 590 591 pioA: gpio@fffff400 { 592 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 593 reg = <0xfffff400 0x200>; 594 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 595 #gpio-cells = <2>; 596 gpio-controller; 597 interrupt-controller; 598 #interrupt-cells = <2>; 599 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 600 }; 601 602 pioB: gpio@fffff600 { 603 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 604 reg = <0xfffff600 0x200>; 605 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 606 #gpio-cells = <2>; 607 gpio-controller; 608 #gpio-lines = <26>; 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 612 }; 613 614 pioC: gpio@fffff800 { 615 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 616 reg = <0xfffff800 0x200>; 617 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 618 #gpio-cells = <2>; 619 gpio-controller; 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 623 }; 624 625 pioD: gpio@fffffa00 { 626 compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 627 reg = <0xfffffa00 0x200>; 628 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; 629 #gpio-cells = <2>; 630 gpio-controller; 631 #gpio-lines = <22>; 632 interrupt-controller; 633 #interrupt-cells = <2>; 634 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 635 }; 636 }; 637 638 pmc: pmc@fffffc00 { 639 compatible = "microchip,sam9x60-pmc", "syscon"; 640 reg = <0xfffffc00 0x200>; 641 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 642 #clock-cells = <2>; 643 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 644 clock-names = "td_slck", "md_slck", "main_xtal"; 645 }; 646 647 reset_controller: rstc@fffffe00 { 648 compatible = "microchip,sam9x60-rstc"; 649 reg = <0xfffffe00 0x10>; 650 clocks = <&clk32k 0>; 651 }; 652 653 shutdown_controller: shdwc@fffffe10 { 654 compatible = "microchip,sam9x60-shdwc"; 655 reg = <0xfffffe10 0x10>; 656 clocks = <&clk32k 0>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 atmel,wakeup-rtc-timer; 660 atmel,wakeup-rtt-timer; 661 status = "disabled"; 662 }; 663 664 rtt: rtt@fffffe20 { 665 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 666 reg = <0xfffffe20 0x20>; 667 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 668 clocks = <&clk32k 0>; 669 }; 670 671 pit: timer@fffffe40 { 672 compatible = "atmel,at91sam9260-pit"; 673 reg = <0xfffffe40 0x10>; 674 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 675 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 676 }; 677 678 clk32k: sckc@fffffe50 { 679 compatible = "microchip,sam9x60-sckc"; 680 reg = <0xfffffe50 0x4>; 681 clocks = <&slow_xtal>; 682 #clock-cells = <1>; 683 }; 684 685 gpbr: syscon@fffffe60 { 686 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon"; 687 reg = <0xfffffe60 0x10>; 688 }; 689 690 rtc: rtc@fffffea8 { 691 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc"; 692 reg = <0xfffffea8 0x100>; 693 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 694 clocks = <&clk32k 0>; 695 }; 696 697 watchdog: watchdog@ffffff80 { 698 compatible = "microchip,sam9x60-wdt"; 699 reg = <0xffffff80 0x24>; 700 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 701 clocks = <&clk32k 0>; 702 status = "disabled"; 703 }; 704 }; 705 }; 706}; 707