1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Thomas Skibo
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Zynq-7000 Devcfg driver. This allows programming the PL (FPGA) section
31 * of Zynq.
32 *
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
34 * (v1.4) November 16, 2012. Xilinx doc UG585. PL Configuration is
35 * covered in section 6.4.5.
36 */
37
38 #include <sys/cdefs.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/conf.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/sysctl.h>
45 #include <sys/lock.h>
46 #include <sys/mutex.h>
47 #include <sys/resource.h>
48 #include <sys/rman.h>
49 #include <sys/uio.h>
50
51 #include <machine/bus.h>
52 #include <machine/resource.h>
53 #include <machine/stdarg.h>
54
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
57
58 #include <arm/xilinx/zy7_slcr.h>
59
60 struct zy7_devcfg_softc {
61 device_t dev;
62 struct mtx sc_mtx;
63 struct resource *mem_res;
64 struct resource *irq_res;
65 struct cdev *sc_ctl_dev;
66 void *intrhandle;
67
68 bus_dma_tag_t dma_tag;
69 bus_dmamap_t dma_map;
70
71 int is_open;
72
73 struct sysctl_ctx_list sysctl_tree;
74 struct sysctl_oid *sysctl_tree_top;
75 };
76
77 static struct zy7_devcfg_softc *zy7_devcfg_softc_p;
78
79 #define FCLK_NUM 4
80
81 struct zy7_fclk_config {
82 int source;
83 int frequency;
84 int actual_frequency;
85 };
86
87 static struct zy7_fclk_config fclk_configs[FCLK_NUM];
88
89 #define DEVCFG_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
90 #define DEVCFG_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
91 #define DEVCFG_SC_LOCK_INIT(sc) \
92 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
93 "zy7_devcfg", MTX_DEF)
94 #define DEVCFG_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx);
95 #define DEVCFG_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED);
96
97 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
98 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
99
100 SYSCTL_NODE(_hw, OID_AUTO, fpga, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
101 "Xilinx Zynq-7000 PL (FPGA) section");
102
103 static int zy7_devcfg_sysctl_pl_done(SYSCTL_HANDLER_ARGS);
104 SYSCTL_PROC(_hw_fpga, OID_AUTO, pl_done,
105 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, NULL, 0,
106 zy7_devcfg_sysctl_pl_done, "I",
107 "PL section config DONE signal");
108
109 static int zy7_en_level_shifters = 1;
110 SYSCTL_INT(_hw_fpga, OID_AUTO, en_level_shifters, CTLFLAG_RW,
111 &zy7_en_level_shifters, 0,
112 "Enable PS-PL level shifters after device config");
113
114 static int zy7_ps_vers = 0;
115 SYSCTL_INT(_hw, OID_AUTO, ps_vers, CTLFLAG_RD, &zy7_ps_vers, 0,
116 "Zynq-7000 PS version");
117
118 static int zy7_devcfg_fclk_sysctl_level_shifters(SYSCTL_HANDLER_ARGS);
119 SYSCTL_PROC(_hw_fpga, OID_AUTO, level_shifters,
120 CTLFLAG_RW | CTLTYPE_INT | CTLFLAG_NEEDGIANT, NULL, 0,
121 zy7_devcfg_fclk_sysctl_level_shifters, "I",
122 "Enable/disable level shifters");
123
124 /* cdev entry points. */
125 static int zy7_devcfg_open(struct cdev *, int, int, struct thread *);
126 static int zy7_devcfg_write(struct cdev *, struct uio *, int);
127 static int zy7_devcfg_close(struct cdev *, int, int, struct thread *);
128
129 struct cdevsw zy7_devcfg_cdevsw = {
130 .d_version = D_VERSION,
131 .d_open = zy7_devcfg_open,
132 .d_write = zy7_devcfg_write,
133 .d_close = zy7_devcfg_close,
134 .d_name = "devcfg",
135 };
136
137 /* Devcfg block registers. */
138 #define ZY7_DEVCFG_CTRL 0x0000
139 #define ZY7_DEVCFG_CTRL_FORCE_RST (1<<31)
140 #define ZY7_DEVCFG_CTRL_PCFG_PROG_B (1<<30)
141 #define ZY7_DEVCFG_CTRL_PCFG_POR_CNT_4K (1<<29)
142 #define ZY7_DEVCFG_CTRL_PCAP_PR (1<<27)
143 #define ZY7_DEVCFG_CTRL_PCAP_MODE (1<<26)
144 #define ZY7_DEVCFG_CTRL_QTR_PCAP_RATE_EN (1<<25)
145 #define ZY7_DEVCFG_CTRL_MULTIBOOT_EN (1<<24)
146 #define ZY7_DEVCFG_CTRL_JTAG_CHAIN_DIS (1<<23)
147 #define ZY7_DEVCFG_CTRL_USER_MODE (1<<15)
148 #define ZY7_DEVCFG_CTRL_RESVD_WR11 (3<<13) /* always write 11 */
149 #define ZY7_DEVCFG_CTRL_PCFG_AES_FUSE (1<<12)
150 #define ZY7_DEVCFG_CTRL_PCFG_AES_EN_MASK (7<<9) /* all 1's or 0's */
151 #define ZY7_DEVCFG_CTRL_SEU_EN (1<<8)
152 #define ZY7_DEVCFG_CTRL_SEC_EN (1<<7)
153 #define ZY7_DEVCFG_CTRL_SPNIDEN (1<<6)
154 #define ZY7_DEVCFG_CTRL_SPIDEN (1<<5)
155 #define ZY7_DEVCFG_CTRL_NIDEN (1<<4)
156 #define ZY7_DEVCFG_CTRL_DBGEN (1<<3)
157 #define ZY7_DEVCFG_CTRL_DAP_EN_MASK (7<<0) /* all 1's to enable */
158
159 #define ZY7_DEVCFG_LOCK 0x004
160 #define ZY7_DEVCFG_LOCK_AES_FUSE_LOCK (1<<4)
161 #define ZY7_DEVCFG_LOCK_AES_EN (1<<3)
162 #define ZY7_DEVCFG_LOCK_SEU_LOCK (1<<2)
163 #define ZY7_DEVCFG_LOCK_SEC_LOCK (1<<1)
164 #define ZY7_DEVCFG_LOCK_DBG_LOCK (1<<0)
165
166 #define ZY7_DEVCFG_CFG 0x008
167 #define ZY7_DEVCFG_CFG_RFIFO_TH_MASK (3<<10)
168 #define ZY7_DEVCFG_CFG_WFIFO_TH_MASK (3<<8)
169 #define ZY7_DEVCFG_CFG_RCLK_EDGE (1<<7)
170 #define ZY7_DEVCFG_CFG_WCLK_EDGE (1<<6)
171 #define ZY7_DEVCFG_CFG_DIS_SRC_INC (1<<5)
172 #define ZY7_DEVCFG_CFG_DIS_DST_INC (1<<4)
173
174 #define ZY7_DEVCFG_INT_STATUS 0x00C
175 #define ZY7_DEVCFG_INT_MASK 0x010
176 #define ZY7_DEVCFG_INT_PSS_GTS_USR_B (1<<31)
177 #define ZY7_DEVCFG_INT_PSS_FST_CFG_B (1<<30)
178 #define ZY7_DEVCFG_INT_PSS_GPWRDWN_B (1<<29)
179 #define ZY7_DEVCFG_INT_PSS_GTS_CFG_B (1<<28)
180 #define ZY7_DEVCFG_INT_CFG_RESET_B (1<<27)
181 #define ZY7_DEVCFG_INT_AXI_WTO (1<<23) /* axi write timeout */
182 #define ZY7_DEVCFG_INT_AXI_WERR (1<<22) /* axi write err */
183 #define ZY7_DEVCFG_INT_AXI_RTO (1<<21) /* axi read timeout */
184 #define ZY7_DEVCFG_INT_AXI_RERR (1<<20) /* axi read err */
185 #define ZY7_DEVCFG_INT_RX_FIFO_OV (1<<18) /* rx fifo overflow */
186 #define ZY7_DEVCFG_INT_WR_FIFO_LVL (1<<17) /* wr fifo < level */
187 #define ZY7_DEVCFG_INT_RD_FIFO_LVL (1<<16) /* rd fifo >= level */
188 #define ZY7_DEVCFG_INT_DMA_CMD_ERR (1<<15)
189 #define ZY7_DEVCFG_INT_DMA_Q_OV (1<<14)
190 #define ZY7_DEVCFG_INT_DMA_DONE (1<<13)
191 #define ZY7_DEVCFG_INT_DMA_PCAP_DONE (1<<12)
192 #define ZY7_DEVCFG_INT_P2D_LEN_ERR (1<<11)
193 #define ZY7_DEVCFG_INT_PCFG_HMAC_ERR (1<<6)
194 #define ZY7_DEVCFG_INT_PCFG_SEU_ERR (1<<5)
195 #define ZY7_DEVCFG_INT_PCFG_POR_B (1<<4)
196 #define ZY7_DEVCFG_INT_PCFG_CFG_RST (1<<3)
197 #define ZY7_DEVCFG_INT_PCFG_DONE (1<<2)
198 #define ZY7_DEVCFG_INT_PCFG_INIT_PE (1<<1)
199 #define ZY7_DEVCFG_INT_PCFG_INIT_NE (1<<0)
200 #define ZY7_DEVCFG_INT_ERRORS 0x00f0f860
201 #define ZY7_DEVCFG_INT_ALL 0xf8f7f87f
202
203 #define ZY7_DEVCFG_STATUS 0x014
204 #define ZY7_DEVCFG_STATUS_DMA_CMD_Q_F (1<<31) /* cmd queue full */
205 #define ZY7_DEVCFG_STATUS_DMA_CMD_Q_E (1<<30) /* cmd queue empty */
206 #define ZY7_DEVCFG_STATUS_DONE_COUNT_MASK (3<<28)
207 #define ZY7_DEVCFG_STATUS_DONE_COUNT_SHIFT 28
208 #define ZY7_DEVCFG_STATUS_RX_FIFO_LVL_MASK (0x1f<<20)
209 #define ZY7_DEVCFG_STATUS_RX_FIFO_LVL_SHIFT 20
210 #define ZY7_DEVCFG_STATUS_TX_FIFO_LVL_MASK (0x7f<<12)
211 #define ZY7_DEVCFG_STATUS_TX_FIFO_LVL_SHIFT 12
212 #define ZY7_DEVCFG_STATUS_PSS_GTS_USR_B (1<<11)
213 #define ZY7_DEVCFG_STATUS_PSS_FST_CFG_B (1<<10)
214 #define ZY7_DEVCFG_STATUS_PSS_GPWRDWN_B (1<<9)
215 #define ZY7_DEVCFG_STATUS_PSS_GTS_CFG_B (1<<8)
216 #define ZY7_DEVCFG_STATUS_ILL_APB_ACCE (1<<6)
217 #define ZY7_DEVCFG_STATUS_PSS_CFG_RESET_B (1<<5)
218 #define ZY7_DEVCFG_STATUS_PCFG_INIT (1<<4)
219 #define ZY7_DEVCFG_STATUS_EFUSE_BBRAM_KEY_DIS (1<<3)
220 #define ZY7_DEVCFG_STATUS_EFUSE_SEC_EN (1<<2)
221 #define ZY7_DEVCFG_STATUS_EFUSE_JTAG_DIS (1<<1)
222
223 #define ZY7_DEVCFG_DMA_SRC_ADDR 0x018
224 #define ZY7_DEVCFG_DMA_DST_ADDR 0x01c
225 #define ZY7_DEVCFG_DMA_ADDR_WAIT_PCAP 1
226 #define ZY7_DEVCFG_DMA_ADDR_ILLEGAL 0xffffffff
227
228 #define ZY7_DEVCFG_DMA_SRC_LEN 0x020 /* in 4-byte words. */
229 #define ZY7_DEVCFG_DMA_SRC_LEN_MAX 0x7ffffff
230 #define ZY7_DEVCFG_DMA_DST_LEN 0x024
231 #define ZY7_DEVCFG_ROM_SHADOW 0x028
232 #define ZY7_DEVCFG_MULTIBOOT_ADDR 0x02c
233 #define ZY7_DEVCFG_SW_ID 0x030
234 #define ZY7_DEVCFG_UNLOCK 0x034
235 #define ZY7_DEVCFG_UNLOCK_MAGIC 0x757bdf0d
236 #define ZY7_DEVCFG_MCTRL 0x080
237 #define ZY7_DEVCFG_MCTRL_PS_VERS_MASK (0xf<<28)
238 #define ZY7_DEVCFG_MCTRL_PS_VERS_SHIFT 28
239 #define ZY7_DEVCFG_MCTRL_PCFG_POR_B (1<<8)
240 #define ZY7_DEVCFG_MCTRL_INT_PCAP_LPBK (1<<4)
241 #define ZY7_DEVCFG_XADCIF_CFG 0x100
242 #define ZY7_DEVCFG_XADCIF_INT_STAT 0x104
243 #define ZY7_DEVCFG_XADCIF_INT_MASK 0x108
244 #define ZY7_DEVCFG_XADCIF_MSTS 0x10c
245 #define ZY7_DEVCFG_XADCIF_CMD_FIFO 0x110
246 #define ZY7_DEVCFG_XADCIF_RD_FIFO 0x114
247 #define ZY7_DEVCFG_XADCIF_MCTL 0x118
248
249 static int
zy7_devcfg_fclk_sysctl_source(SYSCTL_HANDLER_ARGS)250 zy7_devcfg_fclk_sysctl_source(SYSCTL_HANDLER_ARGS)
251 {
252 char buf[4];
253 struct zy7_fclk_config *cfg;
254 int unit;
255 int error;
256
257 cfg = arg1;
258 unit = arg2;
259
260 switch (cfg->source) {
261 case ZY7_PL_FCLK_SRC_IO:
262 case ZY7_PL_FCLK_SRC_IO_ALT:
263 strncpy(buf, "IO", sizeof(buf));
264 break;
265 case ZY7_PL_FCLK_SRC_DDR:
266 strncpy(buf, "DDR", sizeof(buf));
267 break;
268 case ZY7_PL_FCLK_SRC_ARM:
269 strncpy(buf, "ARM", sizeof(buf));
270 break;
271 default:
272 strncpy(buf, "???", sizeof(buf));
273 break;
274 }
275
276 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
277 if (error != 0 || req->newptr == NULL)
278 return (error);
279
280 if (strcasecmp(buf, "io") == 0)
281 cfg->source = ZY7_PL_FCLK_SRC_IO;
282 else if (strcasecmp(buf, "ddr") == 0)
283 cfg->source = ZY7_PL_FCLK_SRC_DDR;
284 else if (strcasecmp(buf, "arm") == 0)
285 cfg->source = ZY7_PL_FCLK_SRC_ARM;
286 else
287 return (EINVAL);
288
289 zy7_pl_fclk_set_source(unit, cfg->source);
290 if (cfg->frequency > 0)
291 cfg->actual_frequency = zy7_pl_fclk_get_freq(unit);
292
293 return (0);
294 }
295
296 static int
zy7_devcfg_fclk_sysctl_freq(SYSCTL_HANDLER_ARGS)297 zy7_devcfg_fclk_sysctl_freq(SYSCTL_HANDLER_ARGS)
298 {
299 struct zy7_fclk_config *cfg;
300 int unit;
301 int error;
302 int freq;
303 int new_actual_freq;
304
305 cfg = arg1;
306 unit = arg2;
307
308 freq = cfg->frequency;
309
310 error = sysctl_handle_int(oidp, &freq, 0, req);
311 if (error != 0 || req->newptr == NULL)
312 return (error);
313
314 if (freq > 0) {
315 new_actual_freq = zy7_pl_fclk_set_freq(unit, freq);
316 if (new_actual_freq < 0)
317 return (EINVAL);
318 if (!zy7_pl_fclk_enabled(unit))
319 zy7_pl_fclk_enable(unit);
320 }
321 else {
322 zy7_pl_fclk_disable(unit);
323 new_actual_freq = 0;
324 }
325
326 cfg->frequency = freq;
327 cfg->actual_frequency = new_actual_freq;
328
329 return (0);
330 }
331
332 static int
zy7_devcfg_fclk_sysctl_level_shifters(SYSCTL_HANDLER_ARGS)333 zy7_devcfg_fclk_sysctl_level_shifters(SYSCTL_HANDLER_ARGS)
334 {
335 int error, enabled;
336
337 enabled = zy7_pl_level_shifters_enabled();
338
339 error = sysctl_handle_int(oidp, &enabled, 0, req);
340 if (error != 0 || req->newptr == NULL)
341 return (error);
342
343 if (enabled)
344 zy7_pl_level_shifters_enable();
345 else
346 zy7_pl_level_shifters_disable();
347
348 return (0);
349 }
350
351 static int
zy7_devcfg_init_fclk_sysctl(struct zy7_devcfg_softc * sc)352 zy7_devcfg_init_fclk_sysctl(struct zy7_devcfg_softc *sc)
353 {
354 struct sysctl_oid *fclk_node;
355 char fclk_num[4];
356 int i;
357
358 sysctl_ctx_init(&sc->sysctl_tree);
359 sc->sysctl_tree_top = SYSCTL_ADD_NODE(&sc->sysctl_tree,
360 SYSCTL_STATIC_CHILDREN(_hw_fpga), OID_AUTO, "fclk",
361 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "");
362 if (sc->sysctl_tree_top == NULL) {
363 sysctl_ctx_free(&sc->sysctl_tree);
364 return (-1);
365 }
366
367 for (i = 0; i < FCLK_NUM; i++) {
368 snprintf(fclk_num, sizeof(fclk_num), "%d", i);
369 fclk_node = SYSCTL_ADD_NODE(&sc->sysctl_tree,
370 SYSCTL_CHILDREN(sc->sysctl_tree_top), OID_AUTO, fclk_num,
371 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "");
372
373 SYSCTL_ADD_INT(&sc->sysctl_tree,
374 SYSCTL_CHILDREN(fclk_node), OID_AUTO,
375 "actual_freq", CTLFLAG_RD,
376 &fclk_configs[i].actual_frequency, i,
377 "Actual frequency");
378 SYSCTL_ADD_PROC(&sc->sysctl_tree,
379 SYSCTL_CHILDREN(fclk_node), OID_AUTO,
380 "freq", CTLFLAG_RW | CTLTYPE_INT | CTLFLAG_NEEDGIANT,
381 &fclk_configs[i], i,
382 zy7_devcfg_fclk_sysctl_freq,
383 "I", "Configured frequency");
384 SYSCTL_ADD_PROC(&sc->sysctl_tree,
385 SYSCTL_CHILDREN(fclk_node), OID_AUTO,
386 "source", CTLFLAG_RW | CTLTYPE_STRING | CTLFLAG_NEEDGIANT,
387 &fclk_configs[i], i,
388 zy7_devcfg_fclk_sysctl_source,
389 "A", "Clock source");
390 }
391
392 return (0);
393 }
394
395 /* Enable programming the PL through PCAP. */
396 static void
zy7_devcfg_init_hw(struct zy7_devcfg_softc * sc)397 zy7_devcfg_init_hw(struct zy7_devcfg_softc *sc)
398 {
399
400 DEVCFG_SC_ASSERT_LOCKED(sc);
401
402 /* Set devcfg control register. */
403 WR4(sc, ZY7_DEVCFG_CTRL,
404 ZY7_DEVCFG_CTRL_PCFG_PROG_B |
405 ZY7_DEVCFG_CTRL_PCAP_PR |
406 ZY7_DEVCFG_CTRL_PCAP_MODE |
407 ZY7_DEVCFG_CTRL_USER_MODE |
408 ZY7_DEVCFG_CTRL_RESVD_WR11 |
409 ZY7_DEVCFG_CTRL_SPNIDEN |
410 ZY7_DEVCFG_CTRL_SPIDEN |
411 ZY7_DEVCFG_CTRL_NIDEN |
412 ZY7_DEVCFG_CTRL_DBGEN |
413 ZY7_DEVCFG_CTRL_DAP_EN_MASK);
414
415 /* Turn off internal PCAP loopback. */
416 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) &
417 ~ZY7_DEVCFG_MCTRL_INT_PCAP_LPBK);
418 }
419
420 /* Clear previous configuration of the PL by asserting PROG_B. */
421 static int
zy7_devcfg_reset_pl(struct zy7_devcfg_softc * sc)422 zy7_devcfg_reset_pl(struct zy7_devcfg_softc *sc)
423 {
424 uint32_t devcfg_ctl;
425 int tries, err;
426
427 DEVCFG_SC_ASSERT_LOCKED(sc);
428
429 devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL);
430
431 /* Clear sticky bits and set up INIT signal positive edge interrupt. */
432 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
433 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE);
434
435 /* Deassert PROG_B (active low). */
436 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B;
437 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
438
439 /*
440 * Wait for INIT to assert. If it is already asserted, we may not get
441 * an edge interrupt so cancel it and continue.
442 */
443 if ((RD4(sc, ZY7_DEVCFG_STATUS) &
444 ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) {
445 /* Already asserted. Cancel interrupt. */
446 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0);
447 }
448 else {
449 /* Wait for positive edge interrupt. */
450 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i1", hz);
451 if (err != 0)
452 return (err);
453 }
454
455 /* Reassert PROG_B (active low). */
456 devcfg_ctl &= ~ZY7_DEVCFG_CTRL_PCFG_PROG_B;
457 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
458
459 /* Wait for INIT deasserted. This happens almost instantly. */
460 tries = 0;
461 while ((RD4(sc, ZY7_DEVCFG_STATUS) &
462 ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) {
463 if (++tries >= 100)
464 return (EIO);
465 DELAY(5);
466 }
467
468 /* Clear sticky bits and set up INIT positive edge interrupt. */
469 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
470 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE);
471
472 /* Deassert PROG_B again. */
473 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B;
474 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl);
475
476 /*
477 * Wait for INIT asserted indicating FPGA internal initialization
478 * is complete.
479 */
480 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i2", hz);
481 if (err != 0)
482 return (err);
483
484 /* Clear sticky DONE bit in interrupt status. */
485 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
486
487 return (0);
488 }
489
490 /* Callback function for bus_dmamap_load(). */
491 static void
zy7_dma_cb2(void * arg,bus_dma_segment_t * seg,int nsegs,int error)492 zy7_dma_cb2(void *arg, bus_dma_segment_t *seg, int nsegs, int error)
493 {
494 if (!error && nsegs == 1)
495 *(bus_addr_t *)arg = seg[0].ds_addr;
496 }
497
498 static int
zy7_devcfg_open(struct cdev * dev,int oflags,int devtype,struct thread * td)499 zy7_devcfg_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
500 {
501 struct zy7_devcfg_softc *sc = dev->si_drv1;
502 int err;
503
504 DEVCFG_SC_LOCK(sc);
505 if (sc->is_open) {
506 DEVCFG_SC_UNLOCK(sc);
507 return (EBUSY);
508 }
509
510 sc->dma_map = NULL;
511 err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 4, 0,
512 BUS_SPACE_MAXADDR_32BIT,
513 BUS_SPACE_MAXADDR,
514 NULL, NULL,
515 PAGE_SIZE,
516 1,
517 PAGE_SIZE,
518 0,
519 busdma_lock_mutex,
520 &sc->sc_mtx,
521 &sc->dma_tag);
522 if (err) {
523 DEVCFG_SC_UNLOCK(sc);
524 return (err);
525 }
526
527 sc->is_open = 1;
528 DEVCFG_SC_UNLOCK(sc);
529 return (0);
530 }
531
532 static int
zy7_devcfg_write(struct cdev * dev,struct uio * uio,int ioflag)533 zy7_devcfg_write(struct cdev *dev, struct uio *uio, int ioflag)
534 {
535 struct zy7_devcfg_softc *sc = dev->si_drv1;
536 void *dma_mem;
537 bus_addr_t dma_physaddr;
538 int segsz, err;
539
540 DEVCFG_SC_LOCK(sc);
541
542 /* First write? Reset PL. */
543 if (uio->uio_offset == 0 && uio->uio_resid > 0) {
544 zy7_devcfg_init_hw(sc);
545 zy7_slcr_preload_pl();
546 err = zy7_devcfg_reset_pl(sc);
547 if (err != 0) {
548 DEVCFG_SC_UNLOCK(sc);
549 return (err);
550 }
551 }
552
553 /* Allocate dma memory and load. */
554 err = bus_dmamem_alloc(sc->dma_tag, &dma_mem, BUS_DMA_NOWAIT,
555 &sc->dma_map);
556 if (err != 0) {
557 DEVCFG_SC_UNLOCK(sc);
558 return (err);
559 }
560 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, dma_mem, PAGE_SIZE,
561 zy7_dma_cb2, &dma_physaddr, 0);
562 if (err != 0) {
563 bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map);
564 DEVCFG_SC_UNLOCK(sc);
565 return (err);
566 }
567
568 while (uio->uio_resid > 0) {
569 /* If DONE signal has been set, we shouldn't write anymore. */
570 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
571 ZY7_DEVCFG_INT_PCFG_DONE) != 0) {
572 err = EIO;
573 break;
574 }
575
576 /* uiomove the data from user buffer to our dma map. */
577 segsz = MIN(PAGE_SIZE, uio->uio_resid);
578 DEVCFG_SC_UNLOCK(sc);
579 err = uiomove(dma_mem, segsz, uio);
580 DEVCFG_SC_LOCK(sc);
581 if (err != 0)
582 break;
583
584 /* Flush the cache to memory. */
585 bus_dmamap_sync(sc->dma_tag, sc->dma_map,
586 BUS_DMASYNC_PREWRITE);
587
588 /* Program devcfg's DMA engine. The ordering of these
589 * register writes is critical.
590 */
591 if (uio->uio_resid > segsz)
592 WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR,
593 (uint32_t) dma_physaddr);
594 else
595 WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR,
596 (uint32_t) dma_physaddr |
597 ZY7_DEVCFG_DMA_ADDR_WAIT_PCAP);
598 WR4(sc, ZY7_DEVCFG_DMA_DST_ADDR, ZY7_DEVCFG_DMA_ADDR_ILLEGAL);
599 WR4(sc, ZY7_DEVCFG_DMA_SRC_LEN, (segsz+3)/4);
600 WR4(sc, ZY7_DEVCFG_DMA_DST_LEN, 0);
601
602 /* Now clear done bit and set up DMA done interrupt. */
603 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
604 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_DMA_DONE);
605
606 /* Wait for DMA done interrupt. */
607 err = mtx_sleep(sc->dma_map, &sc->sc_mtx, PCATCH,
608 "zy7dma", hz);
609 if (err != 0)
610 break;
611
612 bus_dmamap_sync(sc->dma_tag, sc->dma_map,
613 BUS_DMASYNC_POSTWRITE);
614
615 /* Check DONE signal. */
616 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
617 ZY7_DEVCFG_INT_PCFG_DONE) != 0)
618 zy7_slcr_postload_pl(zy7_en_level_shifters);
619 }
620
621 bus_dmamap_unload(sc->dma_tag, sc->dma_map);
622 bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map);
623 DEVCFG_SC_UNLOCK(sc);
624 return (err);
625 }
626
627 static int
zy7_devcfg_close(struct cdev * dev,int fflag,int devtype,struct thread * td)628 zy7_devcfg_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
629 {
630 struct zy7_devcfg_softc *sc = dev->si_drv1;
631
632 DEVCFG_SC_LOCK(sc);
633 sc->is_open = 0;
634 bus_dma_tag_destroy(sc->dma_tag);
635 DEVCFG_SC_UNLOCK(sc);
636
637 zy7_slcr_postload_pl(zy7_en_level_shifters);
638
639 return (0);
640 }
641
642 static void
zy7_devcfg_intr(void * arg)643 zy7_devcfg_intr(void *arg)
644 {
645 struct zy7_devcfg_softc *sc = (struct zy7_devcfg_softc *)arg;
646 uint32_t istatus, imask;
647
648 DEVCFG_SC_LOCK(sc);
649
650 istatus = RD4(sc, ZY7_DEVCFG_INT_STATUS);
651 imask = ~RD4(sc, ZY7_DEVCFG_INT_MASK);
652
653 /* Turn interrupt off. */
654 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0);
655
656 if ((istatus & imask) == 0) {
657 DEVCFG_SC_UNLOCK(sc);
658 return;
659 }
660
661 /* DMA done? */
662 if ((istatus & ZY7_DEVCFG_INT_DMA_DONE) != 0)
663 wakeup(sc->dma_map);
664
665 /* INIT_B positive edge? */
666 if ((istatus & ZY7_DEVCFG_INT_PCFG_INIT_PE) != 0)
667 wakeup(sc);
668
669 DEVCFG_SC_UNLOCK(sc);
670 }
671
672 /* zy7_devcfg_sysctl_pl_done() returns status of the PL_DONE signal.
673 */
674 static int
zy7_devcfg_sysctl_pl_done(SYSCTL_HANDLER_ARGS)675 zy7_devcfg_sysctl_pl_done(SYSCTL_HANDLER_ARGS)
676 {
677 struct zy7_devcfg_softc *sc = zy7_devcfg_softc_p;
678 int pl_done = 0;
679
680 if (sc) {
681 DEVCFG_SC_LOCK(sc);
682
683 /* PCFG_DONE bit is sticky. Clear it before checking it. */
684 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_PCFG_DONE);
685 pl_done = ((RD4(sc, ZY7_DEVCFG_INT_STATUS) &
686 ZY7_DEVCFG_INT_PCFG_DONE) != 0);
687
688 DEVCFG_SC_UNLOCK(sc);
689 }
690 return (sysctl_handle_int(oidp, &pl_done, 0, req));
691 }
692
693 static int
zy7_devcfg_probe(device_t dev)694 zy7_devcfg_probe(device_t dev)
695 {
696
697 if (!ofw_bus_status_okay(dev))
698 return (ENXIO);
699
700 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_devcfg"))
701 return (ENXIO);
702
703 device_set_desc(dev, "Zynq devcfg block");
704 return (0);
705 }
706
707 static int zy7_devcfg_detach(device_t dev);
708
709 static int
zy7_devcfg_attach(device_t dev)710 zy7_devcfg_attach(device_t dev)
711 {
712 struct zy7_devcfg_softc *sc = device_get_softc(dev);
713 int i;
714 int rid, err;
715
716 /* Allow only one attach. */
717 if (zy7_devcfg_softc_p != NULL)
718 return (ENXIO);
719
720 sc->dev = dev;
721
722 DEVCFG_SC_LOCK_INIT(sc);
723
724 /* Get memory resource. */
725 rid = 0;
726 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
727 RF_ACTIVE);
728 if (sc->mem_res == NULL) {
729 device_printf(dev, "could not allocate memory resources.\n");
730 zy7_devcfg_detach(dev);
731 return (ENOMEM);
732 }
733
734 /* Allocate IRQ. */
735 rid = 0;
736 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
737 RF_ACTIVE);
738 if (sc->irq_res == NULL) {
739 device_printf(dev, "cannot allocate IRQ\n");
740 zy7_devcfg_detach(dev);
741 return (ENOMEM);
742 }
743
744 /* Activate the interrupt. */
745 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
746 NULL, zy7_devcfg_intr, sc, &sc->intrhandle);
747 if (err) {
748 device_printf(dev, "cannot setup IRQ\n");
749 zy7_devcfg_detach(dev);
750 return (err);
751 }
752
753 /* Create /dev/devcfg */
754 sc->sc_ctl_dev = make_dev(&zy7_devcfg_cdevsw, 0,
755 UID_ROOT, GID_WHEEL, 0600, "devcfg");
756 if (sc->sc_ctl_dev == NULL) {
757 device_printf(dev, "failed to create /dev/devcfg");
758 zy7_devcfg_detach(dev);
759 return (ENXIO);
760 }
761 sc->sc_ctl_dev->si_drv1 = sc;
762
763 zy7_devcfg_softc_p = sc;
764
765 /* Unlock devcfg registers. */
766 WR4(sc, ZY7_DEVCFG_UNLOCK, ZY7_DEVCFG_UNLOCK_MAGIC);
767
768 /* Make sure interrupts are completely disabled. */
769 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL);
770 WR4(sc, ZY7_DEVCFG_INT_MASK, 0xffffffff);
771
772 /* Get PS_VERS for SYSCTL. */
773 zy7_ps_vers = (RD4(sc, ZY7_DEVCFG_MCTRL) &
774 ZY7_DEVCFG_MCTRL_PS_VERS_MASK) >>
775 ZY7_DEVCFG_MCTRL_PS_VERS_SHIFT;
776
777 for (i = 0; i < FCLK_NUM; i++) {
778 fclk_configs[i].source = zy7_pl_fclk_get_source(i);
779 fclk_configs[i].actual_frequency =
780 zy7_pl_fclk_enabled(i) ? zy7_pl_fclk_get_freq(i) : 0;
781 /* Initially assume actual frequency is the configure one */
782 fclk_configs[i].frequency = fclk_configs[i].actual_frequency;
783 }
784
785 if (zy7_devcfg_init_fclk_sysctl(sc) < 0)
786 device_printf(dev, "failed to initialized sysctl tree\n");
787
788 return (0);
789 }
790
791 static int
zy7_devcfg_detach(device_t dev)792 zy7_devcfg_detach(device_t dev)
793 {
794 struct zy7_devcfg_softc *sc = device_get_softc(dev);
795
796 if (sc->sysctl_tree_top != NULL) {
797 sysctl_ctx_free(&sc->sysctl_tree);
798 sc->sysctl_tree_top = NULL;
799 }
800
801 if (device_is_attached(dev))
802 bus_generic_detach(dev);
803
804 /* Get rid of /dev/devcfg0. */
805 if (sc->sc_ctl_dev != NULL)
806 destroy_dev(sc->sc_ctl_dev);
807
808 /* Teardown and release interrupt. */
809 if (sc->irq_res != NULL) {
810 if (sc->intrhandle)
811 bus_teardown_intr(dev, sc->irq_res, sc->intrhandle);
812 bus_release_resource(dev, SYS_RES_IRQ,
813 rman_get_rid(sc->irq_res), sc->irq_res);
814 }
815
816 /* Release memory resource. */
817 if (sc->mem_res != NULL)
818 bus_release_resource(dev, SYS_RES_MEMORY,
819 rman_get_rid(sc->mem_res), sc->mem_res);
820
821 zy7_devcfg_softc_p = NULL;
822
823 DEVCFG_SC_LOCK_DESTROY(sc);
824
825 return (0);
826 }
827
828 static device_method_t zy7_devcfg_methods[] = {
829 /* device_if */
830 DEVMETHOD(device_probe, zy7_devcfg_probe),
831 DEVMETHOD(device_attach, zy7_devcfg_attach),
832 DEVMETHOD(device_detach, zy7_devcfg_detach),
833
834 DEVMETHOD_END
835 };
836
837 static driver_t zy7_devcfg_driver = {
838 "zy7_devcfg",
839 zy7_devcfg_methods,
840 sizeof(struct zy7_devcfg_softc),
841 };
842
843 DRIVER_MODULE(zy7_devcfg, simplebus, zy7_devcfg_driver, 0, 0);
844 MODULE_DEPEND(zy7_devcfg, zy7_slcr, 1, 1, 1);
845