1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <[email protected]>
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30
31 #include <dev/drm2/drmP.h>
32 #include <dev/drm2/i915/i915_drv.h>
33 #include <dev/drm2/i915/intel_drv.h>
34 #include <sys/kdb.h>
35 #include <machine/clock.h>
36
37 #define FORCEWAKE_ACK_TIMEOUT_MS 2
38
39 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
40 * framebuffer contents in-memory, aiming at reducing the required bandwidth
41 * during in-memory transfers and, therefore, reduce the power packet.
42 *
43 * The benefits of FBC are mostly visible with solid backgrounds and
44 * variation-less patterns.
45 *
46 * FBC-related functionality can be enabled by the means of the
47 * i915.i915_enable_fbc parameter
48 */
49
intel_crtc_active(struct drm_crtc * crtc)50 static bool intel_crtc_active(struct drm_crtc *crtc)
51 {
52 /* Be paranoid as we can arrive here with only partial
53 * state retrieved from the hardware during setup.
54 */
55 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
56 }
57
i8xx_disable_fbc(struct drm_device * dev)58 static void i8xx_disable_fbc(struct drm_device *dev)
59 {
60 struct drm_i915_private *dev_priv = dev->dev_private;
61 u32 fbc_ctl;
62
63 /* Disable compression */
64 fbc_ctl = I915_READ(FBC_CONTROL);
65 if ((fbc_ctl & FBC_CTL_EN) == 0)
66 return;
67
68 fbc_ctl &= ~FBC_CTL_EN;
69 I915_WRITE(FBC_CONTROL, fbc_ctl);
70
71 /* Wait for compressing bit to clear */
72 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
73 DRM_DEBUG_KMS("FBC idle timed out\n");
74 return;
75 }
76
77 DRM_DEBUG_KMS("disabled FBC\n");
78 }
79
i8xx_enable_fbc(struct drm_crtc * crtc,unsigned long interval)80 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
81 {
82 struct drm_device *dev = crtc->dev;
83 struct drm_i915_private *dev_priv = dev->dev_private;
84 struct drm_framebuffer *fb = crtc->fb;
85 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
86 struct drm_i915_gem_object *obj = intel_fb->obj;
87 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
88 int cfb_pitch;
89 int plane, i;
90 u32 fbc_ctl, fbc_ctl2;
91
92 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
93 if (fb->pitches[0] < cfb_pitch)
94 cfb_pitch = fb->pitches[0];
95
96 /* FBC_CTL wants 64B units */
97 cfb_pitch = (cfb_pitch / 64) - 1;
98 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
99
100 /* Clear old tags */
101 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
102 I915_WRITE(FBC_TAG + (i * 4), 0);
103
104 /* Set it up... */
105 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
106 fbc_ctl2 |= plane;
107 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
108 I915_WRITE(FBC_FENCE_OFF, crtc->y);
109
110 /* enable it... */
111 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
112 if (IS_I945GM(dev))
113 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
114 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
115 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
116 fbc_ctl |= obj->fence_reg;
117 I915_WRITE(FBC_CONTROL, fbc_ctl);
118
119 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
120 cfb_pitch, crtc->y, intel_crtc->plane);
121 }
122
i8xx_fbc_enabled(struct drm_device * dev)123 static bool i8xx_fbc_enabled(struct drm_device *dev)
124 {
125 struct drm_i915_private *dev_priv = dev->dev_private;
126
127 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
128 }
129
g4x_enable_fbc(struct drm_crtc * crtc,unsigned long interval)130 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
131 {
132 struct drm_device *dev = crtc->dev;
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 struct drm_framebuffer *fb = crtc->fb;
135 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
136 struct drm_i915_gem_object *obj = intel_fb->obj;
137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
138 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
139 unsigned long stall_watermark = 200;
140 u32 dpfc_ctl;
141
142 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
143 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
144 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
145
146 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
147 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
148 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
149 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
150
151 /* enable it... */
152 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
153
154 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
155 }
156
g4x_disable_fbc(struct drm_device * dev)157 static void g4x_disable_fbc(struct drm_device *dev)
158 {
159 struct drm_i915_private *dev_priv = dev->dev_private;
160 u32 dpfc_ctl;
161
162 /* Disable compression */
163 dpfc_ctl = I915_READ(DPFC_CONTROL);
164 if (dpfc_ctl & DPFC_CTL_EN) {
165 dpfc_ctl &= ~DPFC_CTL_EN;
166 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
167
168 DRM_DEBUG_KMS("disabled FBC\n");
169 }
170 }
171
g4x_fbc_enabled(struct drm_device * dev)172 static bool g4x_fbc_enabled(struct drm_device *dev)
173 {
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
177 }
178
sandybridge_blit_fbc_update(struct drm_device * dev)179 static void sandybridge_blit_fbc_update(struct drm_device *dev)
180 {
181 struct drm_i915_private *dev_priv = dev->dev_private;
182 u32 blt_ecoskpd;
183
184 /* Make sure blitter notifies FBC of writes */
185 gen6_gt_force_wake_get(dev_priv);
186 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
187 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
188 GEN6_BLITTER_LOCK_SHIFT;
189 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
190 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
193 GEN6_BLITTER_LOCK_SHIFT);
194 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
195 POSTING_READ(GEN6_BLITTER_ECOSKPD);
196 gen6_gt_force_wake_put(dev_priv);
197 }
198
ironlake_enable_fbc(struct drm_crtc * crtc,unsigned long interval)199 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
200 {
201 struct drm_device *dev = crtc->dev;
202 struct drm_i915_private *dev_priv = dev->dev_private;
203 struct drm_framebuffer *fb = crtc->fb;
204 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
205 struct drm_i915_gem_object *obj = intel_fb->obj;
206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
207 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
208 unsigned long stall_watermark = 200;
209 u32 dpfc_ctl;
210
211 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
212 dpfc_ctl &= DPFC_RESERVED;
213 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
214 /* Set persistent mode for front-buffer rendering, ala X. */
215 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
216 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
217 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
218
219 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
220 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
221 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
222 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
223 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
224 /* enable it... */
225 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
226
227 if (IS_GEN6(dev)) {
228 I915_WRITE(SNB_DPFC_CTL_SA,
229 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
230 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
231 sandybridge_blit_fbc_update(dev);
232 }
233
234 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
235 }
236
ironlake_disable_fbc(struct drm_device * dev)237 static void ironlake_disable_fbc(struct drm_device *dev)
238 {
239 struct drm_i915_private *dev_priv = dev->dev_private;
240 u32 dpfc_ctl;
241
242 /* Disable compression */
243 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
244 if (dpfc_ctl & DPFC_CTL_EN) {
245 dpfc_ctl &= ~DPFC_CTL_EN;
246 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
247
248 DRM_DEBUG_KMS("disabled FBC\n");
249 }
250 }
251
ironlake_fbc_enabled(struct drm_device * dev)252 static bool ironlake_fbc_enabled(struct drm_device *dev)
253 {
254 struct drm_i915_private *dev_priv = dev->dev_private;
255
256 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
257 }
258
intel_fbc_enabled(struct drm_device * dev)259 bool intel_fbc_enabled(struct drm_device *dev)
260 {
261 struct drm_i915_private *dev_priv = dev->dev_private;
262
263 if (!dev_priv->display.fbc_enabled)
264 return false;
265
266 return dev_priv->display.fbc_enabled(dev);
267 }
268
intel_fbc_work_fn(void * arg,int pending)269 static void intel_fbc_work_fn(void *arg, int pending)
270 {
271 struct intel_fbc_work *work = arg;
272 struct drm_device *dev = work->crtc->dev;
273 struct drm_i915_private *dev_priv = dev->dev_private;
274
275 DRM_LOCK(dev);
276 if (work == dev_priv->fbc_work) {
277 /* Double check that we haven't switched fb without cancelling
278 * the prior work.
279 */
280 if (work->crtc->fb == work->fb) {
281 dev_priv->display.enable_fbc(work->crtc,
282 work->interval);
283
284 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
285 dev_priv->cfb_fb = work->crtc->fb->base.id;
286 dev_priv->cfb_y = work->crtc->y;
287 }
288
289 dev_priv->fbc_work = NULL;
290 }
291 DRM_UNLOCK(dev);
292
293 free(work, DRM_MEM_KMS);
294 }
295
intel_cancel_fbc_work(struct drm_i915_private * dev_priv)296 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
297 {
298 if (dev_priv->fbc_work == NULL)
299 return;
300
301 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
302
303 /* Synchronisation is provided by struct_mutex and checking of
304 * dev_priv->fbc_work, so we can perform the cancellation
305 * entirely asynchronously.
306 */
307 if (taskqueue_cancel_timeout(dev_priv->wq, &dev_priv->fbc_work->work,
308 NULL) == 0)
309 /* tasklet was killed before being run, clean up */
310 free(dev_priv->fbc_work, DRM_MEM_KMS);
311
312 /* Mark the work as no longer wanted so that if it does
313 * wake-up (because the work was already running and waiting
314 * for our mutex), it will discover that is no longer
315 * necessary to run.
316 */
317 dev_priv->fbc_work = NULL;
318 }
319
intel_enable_fbc(struct drm_crtc * crtc,unsigned long interval)320 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
321 {
322 struct intel_fbc_work *work;
323 struct drm_device *dev = crtc->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 if (!dev_priv->display.enable_fbc)
327 return;
328
329 intel_cancel_fbc_work(dev_priv);
330
331 work = malloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO);
332 if (work == NULL) {
333 dev_priv->display.enable_fbc(crtc, interval);
334 return;
335 }
336
337 work->crtc = crtc;
338 work->fb = crtc->fb;
339 work->interval = interval;
340 TIMEOUT_TASK_INIT(dev_priv->wq, &work->work, 0, intel_fbc_work_fn,
341 work);
342
343 dev_priv->fbc_work = work;
344
345 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
346
347 /* Delay the actual enabling to let pageflipping cease and the
348 * display to settle before starting the compression. Note that
349 * this delay also serves a second purpose: it allows for a
350 * vblank to pass after disabling the FBC before we attempt
351 * to modify the control registers.
352 *
353 * A more complicated solution would involve tracking vblanks
354 * following the termination of the page-flipping sequence
355 * and indeed performing the enable as a co-routine and not
356 * waiting synchronously upon the vblank.
357 */
358 taskqueue_enqueue_timeout(dev_priv->wq, &work->work,
359 msecs_to_jiffies(50));
360 }
361
intel_disable_fbc(struct drm_device * dev)362 void intel_disable_fbc(struct drm_device *dev)
363 {
364 struct drm_i915_private *dev_priv = dev->dev_private;
365
366 intel_cancel_fbc_work(dev_priv);
367
368 if (!dev_priv->display.disable_fbc)
369 return;
370
371 dev_priv->display.disable_fbc(dev);
372 dev_priv->cfb_plane = -1;
373 }
374
375 /**
376 * intel_update_fbc - enable/disable FBC as needed
377 * @dev: the drm_device
378 *
379 * Set up the framebuffer compression hardware at mode set time. We
380 * enable it if possible:
381 * - plane A only (on pre-965)
382 * - no pixel mulitply/line duplication
383 * - no alpha buffer discard
384 * - no dual wide
385 * - framebuffer <= 2048 in width, 1536 in height
386 *
387 * We can't assume that any compression will take place (worst case),
388 * so the compressed buffer has to be the same size as the uncompressed
389 * one. It also must reside (along with the line length buffer) in
390 * stolen memory.
391 *
392 * We need to enable/disable FBC on a global basis.
393 */
intel_update_fbc(struct drm_device * dev)394 void intel_update_fbc(struct drm_device *dev)
395 {
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 struct drm_crtc *crtc = NULL, *tmp_crtc;
398 struct intel_crtc *intel_crtc;
399 struct drm_framebuffer *fb;
400 struct intel_framebuffer *intel_fb;
401 struct drm_i915_gem_object *obj;
402 int enable_fbc;
403
404 if (!i915_powersave)
405 return;
406
407 if (!I915_HAS_FBC(dev))
408 return;
409
410 /*
411 * If FBC is already on, we just have to verify that we can
412 * keep it that way...
413 * Need to disable if:
414 * - more than one pipe is active
415 * - changing FBC params (stride, fence, mode)
416 * - new fb is too large to fit in compressed buffer
417 * - going to an unsupported config (interlace, pixel multiply, etc.)
418 */
419 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
420 if (intel_crtc_active(tmp_crtc) &&
421 !to_intel_crtc(tmp_crtc)->primary_disabled) {
422 if (crtc) {
423 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
424 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
425 goto out_disable;
426 }
427 crtc = tmp_crtc;
428 }
429 }
430
431 if (!crtc || crtc->fb == NULL) {
432 DRM_DEBUG_KMS("no output, disabling\n");
433 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
434 goto out_disable;
435 }
436
437 intel_crtc = to_intel_crtc(crtc);
438 fb = crtc->fb;
439 intel_fb = to_intel_framebuffer(fb);
440 obj = intel_fb->obj;
441
442 enable_fbc = i915_enable_fbc;
443 if (enable_fbc < 0) {
444 DRM_DEBUG_KMS("fbc set to per-chip default\n");
445 enable_fbc = 1;
446 if (INTEL_INFO(dev)->gen <= 6)
447 enable_fbc = 0;
448 }
449 if (!enable_fbc) {
450 DRM_DEBUG_KMS("fbc disabled per module param\n");
451 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
452 goto out_disable;
453 }
454 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
455 DRM_DEBUG_KMS("framebuffer too large, disabling "
456 "compression\n");
457 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
458 goto out_disable;
459 }
460 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
461 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
462 DRM_DEBUG_KMS("mode incompatible with compression, "
463 "disabling\n");
464 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
465 goto out_disable;
466 }
467 if ((crtc->mode.hdisplay > 2048) ||
468 (crtc->mode.vdisplay > 1536)) {
469 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
470 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
471 goto out_disable;
472 }
473 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
474 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
475 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
476 goto out_disable;
477 }
478
479 /* The use of a CPU fence is mandatory in order to detect writes
480 * by the CPU to the scanout and trigger updates to the FBC.
481 */
482 if (obj->tiling_mode != I915_TILING_X ||
483 obj->fence_reg == I915_FENCE_REG_NONE) {
484 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
485 dev_priv->no_fbc_reason = FBC_NOT_TILED;
486 goto out_disable;
487 }
488
489 /* If the kernel debugger is active, always disable compression */
490 if (kdb_active)
491 goto out_disable;
492
493 /* If the scanout has not changed, don't modify the FBC settings.
494 * Note that we make the fundamental assumption that the fb->obj
495 * cannot be unpinned (and have its GTT offset and fence revoked)
496 * without first being decoupled from the scanout and FBC disabled.
497 */
498 if (dev_priv->cfb_plane == intel_crtc->plane &&
499 dev_priv->cfb_fb == fb->base.id &&
500 dev_priv->cfb_y == crtc->y)
501 return;
502
503 if (intel_fbc_enabled(dev)) {
504 /* We update FBC along two paths, after changing fb/crtc
505 * configuration (modeswitching) and after page-flipping
506 * finishes. For the latter, we know that not only did
507 * we disable the FBC at the start of the page-flip
508 * sequence, but also more than one vblank has passed.
509 *
510 * For the former case of modeswitching, it is possible
511 * to switch between two FBC valid configurations
512 * instantaneously so we do need to disable the FBC
513 * before we can modify its control registers. We also
514 * have to wait for the next vblank for that to take
515 * effect. However, since we delay enabling FBC we can
516 * assume that a vblank has passed since disabling and
517 * that we can safely alter the registers in the deferred
518 * callback.
519 *
520 * In the scenario that we go from a valid to invalid
521 * and then back to valid FBC configuration we have
522 * no strict enforcement that a vblank occurred since
523 * disabling the FBC. However, along all current pipe
524 * disabling paths we do need to wait for a vblank at
525 * some point. And we wait before enabling FBC anyway.
526 */
527 DRM_DEBUG_KMS("disabling active FBC for update\n");
528 intel_disable_fbc(dev);
529 }
530
531 intel_enable_fbc(crtc, 500);
532 return;
533
534 out_disable:
535 /* Multiple disables should be harmless */
536 if (intel_fbc_enabled(dev)) {
537 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
538 intel_disable_fbc(dev);
539 }
540 }
541
i915_pineview_get_mem_freq(struct drm_device * dev)542 static void i915_pineview_get_mem_freq(struct drm_device *dev)
543 {
544 drm_i915_private_t *dev_priv = dev->dev_private;
545 u32 tmp;
546
547 tmp = I915_READ(CLKCFG);
548
549 switch (tmp & CLKCFG_FSB_MASK) {
550 case CLKCFG_FSB_533:
551 dev_priv->fsb_freq = 533; /* 133*4 */
552 break;
553 case CLKCFG_FSB_800:
554 dev_priv->fsb_freq = 800; /* 200*4 */
555 break;
556 case CLKCFG_FSB_667:
557 dev_priv->fsb_freq = 667; /* 167*4 */
558 break;
559 case CLKCFG_FSB_400:
560 dev_priv->fsb_freq = 400; /* 100*4 */
561 break;
562 }
563
564 switch (tmp & CLKCFG_MEM_MASK) {
565 case CLKCFG_MEM_533:
566 dev_priv->mem_freq = 533;
567 break;
568 case CLKCFG_MEM_667:
569 dev_priv->mem_freq = 667;
570 break;
571 case CLKCFG_MEM_800:
572 dev_priv->mem_freq = 800;
573 break;
574 }
575
576 /* detect pineview DDR3 setting */
577 tmp = I915_READ(CSHRDDR3CTL);
578 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
579 }
580
i915_ironlake_get_mem_freq(struct drm_device * dev)581 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
582 {
583 drm_i915_private_t *dev_priv = dev->dev_private;
584 u16 ddrpll, csipll;
585
586 ddrpll = I915_READ16(DDRMPLL1);
587 csipll = I915_READ16(CSIPLL0);
588
589 switch (ddrpll & 0xff) {
590 case 0xc:
591 dev_priv->mem_freq = 800;
592 break;
593 case 0x10:
594 dev_priv->mem_freq = 1066;
595 break;
596 case 0x14:
597 dev_priv->mem_freq = 1333;
598 break;
599 case 0x18:
600 dev_priv->mem_freq = 1600;
601 break;
602 default:
603 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
604 ddrpll & 0xff);
605 dev_priv->mem_freq = 0;
606 break;
607 }
608
609 dev_priv->ips.r_t = dev_priv->mem_freq;
610
611 switch (csipll & 0x3ff) {
612 case 0x00c:
613 dev_priv->fsb_freq = 3200;
614 break;
615 case 0x00e:
616 dev_priv->fsb_freq = 3733;
617 break;
618 case 0x010:
619 dev_priv->fsb_freq = 4266;
620 break;
621 case 0x012:
622 dev_priv->fsb_freq = 4800;
623 break;
624 case 0x014:
625 dev_priv->fsb_freq = 5333;
626 break;
627 case 0x016:
628 dev_priv->fsb_freq = 5866;
629 break;
630 case 0x018:
631 dev_priv->fsb_freq = 6400;
632 break;
633 default:
634 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
635 csipll & 0x3ff);
636 dev_priv->fsb_freq = 0;
637 break;
638 }
639
640 if (dev_priv->fsb_freq == 3200) {
641 dev_priv->ips.c_m = 0;
642 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
643 dev_priv->ips.c_m = 1;
644 } else {
645 dev_priv->ips.c_m = 2;
646 }
647 }
648
649 static const struct cxsr_latency cxsr_latency_table[] = {
650 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
651 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
652 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
653 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
654 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
655
656 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
657 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
658 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
659 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
660 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
661
662 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
663 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
664 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
665 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
666 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
667
668 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
669 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
670 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
671 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
672 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
673
674 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
675 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
676 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
677 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
678 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
679
680 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
681 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
682 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
683 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
684 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
685 };
686
intel_get_cxsr_latency(int is_desktop,int is_ddr3,int fsb,int mem)687 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
688 int is_ddr3,
689 int fsb,
690 int mem)
691 {
692 const struct cxsr_latency *latency;
693 int i;
694
695 if (fsb == 0 || mem == 0)
696 return NULL;
697
698 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
699 latency = &cxsr_latency_table[i];
700 if (is_desktop == latency->is_desktop &&
701 is_ddr3 == latency->is_ddr3 &&
702 fsb == latency->fsb_freq && mem == latency->mem_freq)
703 return latency;
704 }
705
706 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
707
708 return NULL;
709 }
710
pineview_disable_cxsr(struct drm_device * dev)711 static void pineview_disable_cxsr(struct drm_device *dev)
712 {
713 struct drm_i915_private *dev_priv = dev->dev_private;
714
715 /* deactivate cxsr */
716 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
717 }
718
719 /*
720 * Latency for FIFO fetches is dependent on several factors:
721 * - memory configuration (speed, channels)
722 * - chipset
723 * - current MCH state
724 * It can be fairly high in some situations, so here we assume a fairly
725 * pessimal value. It's a tradeoff between extra memory fetches (if we
726 * set this value too high, the FIFO will fetch frequently to stay full)
727 * and power consumption (set it too low to save power and we might see
728 * FIFO underruns and display "flicker").
729 *
730 * A value of 5us seems to be a good balance; safe for very low end
731 * platforms but not overly aggressive on lower latency configs.
732 */
733 static const int latency_ns = 5000;
734
i9xx_get_fifo_size(struct drm_device * dev,int plane)735 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
736 {
737 struct drm_i915_private *dev_priv = dev->dev_private;
738 uint32_t dsparb = I915_READ(DSPARB);
739 int size;
740
741 size = dsparb & 0x7f;
742 if (plane)
743 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
744
745 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
746 plane ? "B" : "A", size);
747
748 return size;
749 }
750
i85x_get_fifo_size(struct drm_device * dev,int plane)751 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
752 {
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 uint32_t dsparb = I915_READ(DSPARB);
755 int size;
756
757 size = dsparb & 0x1ff;
758 if (plane)
759 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
760 size >>= 1; /* Convert to cachelines */
761
762 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
763 plane ? "B" : "A", size);
764
765 return size;
766 }
767
i845_get_fifo_size(struct drm_device * dev,int plane)768 static int i845_get_fifo_size(struct drm_device *dev, int plane)
769 {
770 struct drm_i915_private *dev_priv = dev->dev_private;
771 uint32_t dsparb = I915_READ(DSPARB);
772 int size;
773
774 size = dsparb & 0x7f;
775 size >>= 2; /* Convert to cachelines */
776
777 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
778 plane ? "B" : "A",
779 size);
780
781 return size;
782 }
783
i830_get_fifo_size(struct drm_device * dev,int plane)784 static int i830_get_fifo_size(struct drm_device *dev, int plane)
785 {
786 struct drm_i915_private *dev_priv = dev->dev_private;
787 uint32_t dsparb = I915_READ(DSPARB);
788 int size;
789
790 size = dsparb & 0x7f;
791 size >>= 1; /* Convert to cachelines */
792
793 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
794 plane ? "B" : "A", size);
795
796 return size;
797 }
798
799 /* Pineview has different values for various configs */
800 static const struct intel_watermark_params pineview_display_wm = {
801 PINEVIEW_DISPLAY_FIFO,
802 PINEVIEW_MAX_WM,
803 PINEVIEW_DFT_WM,
804 PINEVIEW_GUARD_WM,
805 PINEVIEW_FIFO_LINE_SIZE
806 };
807 static const struct intel_watermark_params pineview_display_hplloff_wm = {
808 PINEVIEW_DISPLAY_FIFO,
809 PINEVIEW_MAX_WM,
810 PINEVIEW_DFT_HPLLOFF_WM,
811 PINEVIEW_GUARD_WM,
812 PINEVIEW_FIFO_LINE_SIZE
813 };
814 static const struct intel_watermark_params pineview_cursor_wm = {
815 PINEVIEW_CURSOR_FIFO,
816 PINEVIEW_CURSOR_MAX_WM,
817 PINEVIEW_CURSOR_DFT_WM,
818 PINEVIEW_CURSOR_GUARD_WM,
819 PINEVIEW_FIFO_LINE_SIZE,
820 };
821 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
822 PINEVIEW_CURSOR_FIFO,
823 PINEVIEW_CURSOR_MAX_WM,
824 PINEVIEW_CURSOR_DFT_WM,
825 PINEVIEW_CURSOR_GUARD_WM,
826 PINEVIEW_FIFO_LINE_SIZE
827 };
828 static const struct intel_watermark_params g4x_wm_info = {
829 G4X_FIFO_SIZE,
830 G4X_MAX_WM,
831 G4X_MAX_WM,
832 2,
833 G4X_FIFO_LINE_SIZE,
834 };
835 static const struct intel_watermark_params g4x_cursor_wm_info = {
836 I965_CURSOR_FIFO,
837 I965_CURSOR_MAX_WM,
838 I965_CURSOR_DFT_WM,
839 2,
840 G4X_FIFO_LINE_SIZE,
841 };
842 static const struct intel_watermark_params valleyview_wm_info = {
843 VALLEYVIEW_FIFO_SIZE,
844 VALLEYVIEW_MAX_WM,
845 VALLEYVIEW_MAX_WM,
846 2,
847 G4X_FIFO_LINE_SIZE,
848 };
849 static const struct intel_watermark_params valleyview_cursor_wm_info = {
850 I965_CURSOR_FIFO,
851 VALLEYVIEW_CURSOR_MAX_WM,
852 I965_CURSOR_DFT_WM,
853 2,
854 G4X_FIFO_LINE_SIZE,
855 };
856 static const struct intel_watermark_params i965_cursor_wm_info = {
857 I965_CURSOR_FIFO,
858 I965_CURSOR_MAX_WM,
859 I965_CURSOR_DFT_WM,
860 2,
861 I915_FIFO_LINE_SIZE,
862 };
863 static const struct intel_watermark_params i945_wm_info = {
864 I945_FIFO_SIZE,
865 I915_MAX_WM,
866 1,
867 2,
868 I915_FIFO_LINE_SIZE
869 };
870 static const struct intel_watermark_params i915_wm_info = {
871 I915_FIFO_SIZE,
872 I915_MAX_WM,
873 1,
874 2,
875 I915_FIFO_LINE_SIZE
876 };
877 static const struct intel_watermark_params i855_wm_info = {
878 I855GM_FIFO_SIZE,
879 I915_MAX_WM,
880 1,
881 2,
882 I830_FIFO_LINE_SIZE
883 };
884 static const struct intel_watermark_params i830_wm_info = {
885 I830_FIFO_SIZE,
886 I915_MAX_WM,
887 1,
888 2,
889 I830_FIFO_LINE_SIZE
890 };
891
892 static const struct intel_watermark_params ironlake_display_wm_info = {
893 ILK_DISPLAY_FIFO,
894 ILK_DISPLAY_MAXWM,
895 ILK_DISPLAY_DFTWM,
896 2,
897 ILK_FIFO_LINE_SIZE
898 };
899 static const struct intel_watermark_params ironlake_cursor_wm_info = {
900 ILK_CURSOR_FIFO,
901 ILK_CURSOR_MAXWM,
902 ILK_CURSOR_DFTWM,
903 2,
904 ILK_FIFO_LINE_SIZE
905 };
906 static const struct intel_watermark_params ironlake_display_srwm_info = {
907 ILK_DISPLAY_SR_FIFO,
908 ILK_DISPLAY_MAX_SRWM,
909 ILK_DISPLAY_DFT_SRWM,
910 2,
911 ILK_FIFO_LINE_SIZE
912 };
913 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
914 ILK_CURSOR_SR_FIFO,
915 ILK_CURSOR_MAX_SRWM,
916 ILK_CURSOR_DFT_SRWM,
917 2,
918 ILK_FIFO_LINE_SIZE
919 };
920
921 static const struct intel_watermark_params sandybridge_display_wm_info = {
922 SNB_DISPLAY_FIFO,
923 SNB_DISPLAY_MAXWM,
924 SNB_DISPLAY_DFTWM,
925 2,
926 SNB_FIFO_LINE_SIZE
927 };
928 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
929 SNB_CURSOR_FIFO,
930 SNB_CURSOR_MAXWM,
931 SNB_CURSOR_DFTWM,
932 2,
933 SNB_FIFO_LINE_SIZE
934 };
935 static const struct intel_watermark_params sandybridge_display_srwm_info = {
936 SNB_DISPLAY_SR_FIFO,
937 SNB_DISPLAY_MAX_SRWM,
938 SNB_DISPLAY_DFT_SRWM,
939 2,
940 SNB_FIFO_LINE_SIZE
941 };
942 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
943 SNB_CURSOR_SR_FIFO,
944 SNB_CURSOR_MAX_SRWM,
945 SNB_CURSOR_DFT_SRWM,
946 2,
947 SNB_FIFO_LINE_SIZE
948 };
949
950
951 /**
952 * intel_calculate_wm - calculate watermark level
953 * @clock_in_khz: pixel clock
954 * @wm: chip FIFO params
955 * @pixel_size: display pixel size
956 * @latency_ns: memory latency for the platform
957 *
958 * Calculate the watermark level (the level at which the display plane will
959 * start fetching from memory again). Each chip has a different display
960 * FIFO size and allocation, so the caller needs to figure that out and pass
961 * in the correct intel_watermark_params structure.
962 *
963 * As the pixel clock runs, the FIFO will be drained at a rate that depends
964 * on the pixel size. When it reaches the watermark level, it'll start
965 * fetching FIFO line sized based chunks from memory until the FIFO fills
966 * past the watermark point. If the FIFO drains completely, a FIFO underrun
967 * will occur, and a display engine hang could result.
968 */
intel_calculate_wm(unsigned long clock_in_khz,const struct intel_watermark_params * wm,int fifo_size,int pixel_size,unsigned long latency_ns)969 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
970 const struct intel_watermark_params *wm,
971 int fifo_size,
972 int pixel_size,
973 unsigned long latency_ns)
974 {
975 long entries_required, wm_size;
976
977 /*
978 * Note: we need to make sure we don't overflow for various clock &
979 * latency values.
980 * clocks go from a few thousand to several hundred thousand.
981 * latency is usually a few thousand
982 */
983 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
984 1000;
985 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
986
987 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
988
989 wm_size = fifo_size - (entries_required + wm->guard_size);
990
991 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
992
993 /* Don't promote wm_size to unsigned... */
994 if (wm_size > (long)wm->max_wm)
995 wm_size = wm->max_wm;
996 if (wm_size <= 0)
997 wm_size = wm->default_wm;
998 return wm_size;
999 }
1000
single_enabled_crtc(struct drm_device * dev)1001 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1002 {
1003 struct drm_crtc *crtc, *enabled = NULL;
1004
1005 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1006 if (intel_crtc_active(crtc)) {
1007 if (enabled)
1008 return NULL;
1009 enabled = crtc;
1010 }
1011 }
1012
1013 return enabled;
1014 }
1015
pineview_update_wm(struct drm_device * dev)1016 static void pineview_update_wm(struct drm_device *dev)
1017 {
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 struct drm_crtc *crtc;
1020 const struct cxsr_latency *latency;
1021 u32 reg;
1022 unsigned long wm;
1023
1024 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1025 dev_priv->fsb_freq, dev_priv->mem_freq);
1026 if (!latency) {
1027 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1028 pineview_disable_cxsr(dev);
1029 return;
1030 }
1031
1032 crtc = single_enabled_crtc(dev);
1033 if (crtc) {
1034 int clock = crtc->mode.clock;
1035 int pixel_size = crtc->fb->bits_per_pixel / 8;
1036
1037 /* Display SR */
1038 wm = intel_calculate_wm(clock, &pineview_display_wm,
1039 pineview_display_wm.fifo_size,
1040 pixel_size, latency->display_sr);
1041 reg = I915_READ(DSPFW1);
1042 reg &= ~DSPFW_SR_MASK;
1043 reg |= wm << DSPFW_SR_SHIFT;
1044 I915_WRITE(DSPFW1, reg);
1045 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1046
1047 /* cursor SR */
1048 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1049 pineview_display_wm.fifo_size,
1050 pixel_size, latency->cursor_sr);
1051 reg = I915_READ(DSPFW3);
1052 reg &= ~DSPFW_CURSOR_SR_MASK;
1053 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1054 I915_WRITE(DSPFW3, reg);
1055
1056 /* Display HPLL off SR */
1057 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1058 pineview_display_hplloff_wm.fifo_size,
1059 pixel_size, latency->display_hpll_disable);
1060 reg = I915_READ(DSPFW3);
1061 reg &= ~DSPFW_HPLL_SR_MASK;
1062 reg |= wm & DSPFW_HPLL_SR_MASK;
1063 I915_WRITE(DSPFW3, reg);
1064
1065 /* cursor HPLL off SR */
1066 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1067 pineview_display_hplloff_wm.fifo_size,
1068 pixel_size, latency->cursor_hpll_disable);
1069 reg = I915_READ(DSPFW3);
1070 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1071 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1072 I915_WRITE(DSPFW3, reg);
1073 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1074
1075 /* activate cxsr */
1076 I915_WRITE(DSPFW3,
1077 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1078 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1079 } else {
1080 pineview_disable_cxsr(dev);
1081 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1082 }
1083 }
1084
g4x_compute_wm0(struct drm_device * dev,int plane,const struct intel_watermark_params * display,int display_latency_ns,const struct intel_watermark_params * cursor,int cursor_latency_ns,int * plane_wm,int * cursor_wm)1085 static bool g4x_compute_wm0(struct drm_device *dev,
1086 int plane,
1087 const struct intel_watermark_params *display,
1088 int display_latency_ns,
1089 const struct intel_watermark_params *cursor,
1090 int cursor_latency_ns,
1091 int *plane_wm,
1092 int *cursor_wm)
1093 {
1094 struct drm_crtc *crtc;
1095 int htotal, hdisplay, clock, pixel_size;
1096 int line_time_us, line_count;
1097 int entries, tlb_miss;
1098
1099 crtc = intel_get_crtc_for_plane(dev, plane);
1100 if (!intel_crtc_active(crtc)) {
1101 *cursor_wm = cursor->guard_size;
1102 *plane_wm = display->guard_size;
1103 return false;
1104 }
1105
1106 htotal = crtc->mode.htotal;
1107 hdisplay = crtc->mode.hdisplay;
1108 clock = crtc->mode.clock;
1109 pixel_size = crtc->fb->bits_per_pixel / 8;
1110
1111 /* Use the small buffer method to calculate plane watermark */
1112 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1113 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1114 if (tlb_miss > 0)
1115 entries += tlb_miss;
1116 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1117 *plane_wm = entries + display->guard_size;
1118 if (*plane_wm > (int)display->max_wm)
1119 *plane_wm = display->max_wm;
1120
1121 /* Use the large buffer method to calculate cursor watermark */
1122 line_time_us = ((htotal * 1000) / clock);
1123 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1124 entries = line_count * 64 * pixel_size;
1125 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1126 if (tlb_miss > 0)
1127 entries += tlb_miss;
1128 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1129 *cursor_wm = entries + cursor->guard_size;
1130 if (*cursor_wm > (int)cursor->max_wm)
1131 *cursor_wm = (int)cursor->max_wm;
1132
1133 return true;
1134 }
1135
1136 /*
1137 * Check the wm result.
1138 *
1139 * If any calculated watermark values is larger than the maximum value that
1140 * can be programmed into the associated watermark register, that watermark
1141 * must be disabled.
1142 */
g4x_check_srwm(struct drm_device * dev,int display_wm,int cursor_wm,const struct intel_watermark_params * display,const struct intel_watermark_params * cursor)1143 static bool g4x_check_srwm(struct drm_device *dev,
1144 int display_wm, int cursor_wm,
1145 const struct intel_watermark_params *display,
1146 const struct intel_watermark_params *cursor)
1147 {
1148 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1149 display_wm, cursor_wm);
1150
1151 if (display_wm > display->max_wm) {
1152 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1153 display_wm, display->max_wm);
1154 return false;
1155 }
1156
1157 if (cursor_wm > cursor->max_wm) {
1158 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1159 cursor_wm, cursor->max_wm);
1160 return false;
1161 }
1162
1163 if (!(display_wm || cursor_wm)) {
1164 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1165 return false;
1166 }
1167
1168 return true;
1169 }
1170
g4x_compute_srwm(struct drm_device * dev,int plane,int latency_ns,const struct intel_watermark_params * display,const struct intel_watermark_params * cursor,int * display_wm,int * cursor_wm)1171 static bool g4x_compute_srwm(struct drm_device *dev,
1172 int plane,
1173 int latency_ns,
1174 const struct intel_watermark_params *display,
1175 const struct intel_watermark_params *cursor,
1176 int *display_wm, int *cursor_wm)
1177 {
1178 struct drm_crtc *crtc;
1179 int hdisplay, htotal, pixel_size, clock;
1180 unsigned long line_time_us;
1181 int line_count, line_size;
1182 int small, large;
1183 int entries;
1184
1185 if (!latency_ns) {
1186 *display_wm = *cursor_wm = 0;
1187 return false;
1188 }
1189
1190 crtc = intel_get_crtc_for_plane(dev, plane);
1191 hdisplay = crtc->mode.hdisplay;
1192 htotal = crtc->mode.htotal;
1193 clock = crtc->mode.clock;
1194 pixel_size = crtc->fb->bits_per_pixel / 8;
1195
1196 line_time_us = (htotal * 1000) / clock;
1197 line_count = (latency_ns / line_time_us + 1000) / 1000;
1198 line_size = hdisplay * pixel_size;
1199
1200 /* Use the minimum of the small and large buffer method for primary */
1201 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1202 large = line_count * line_size;
1203
1204 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1205 *display_wm = entries + display->guard_size;
1206
1207 /* calculate the self-refresh watermark for display cursor */
1208 entries = line_count * pixel_size * 64;
1209 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1210 *cursor_wm = entries + cursor->guard_size;
1211
1212 return g4x_check_srwm(dev,
1213 *display_wm, *cursor_wm,
1214 display, cursor);
1215 }
1216
vlv_compute_drain_latency(struct drm_device * dev,int plane,int * plane_prec_mult,int * plane_dl,int * cursor_prec_mult,int * cursor_dl)1217 static bool vlv_compute_drain_latency(struct drm_device *dev,
1218 int plane,
1219 int *plane_prec_mult,
1220 int *plane_dl,
1221 int *cursor_prec_mult,
1222 int *cursor_dl)
1223 {
1224 struct drm_crtc *crtc;
1225 int clock, pixel_size;
1226 int entries;
1227
1228 crtc = intel_get_crtc_for_plane(dev, plane);
1229 if (!intel_crtc_active(crtc))
1230 return false;
1231
1232 clock = crtc->mode.clock; /* VESA DOT Clock */
1233 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1234
1235 entries = (clock / 1000) * pixel_size;
1236 *plane_prec_mult = (entries > 256) ?
1237 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1238 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1239 pixel_size);
1240
1241 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1242 *cursor_prec_mult = (entries > 256) ?
1243 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1244 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1245
1246 return true;
1247 }
1248
1249 /*
1250 * Update drain latency registers of memory arbiter
1251 *
1252 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1253 * to be programmed. Each plane has a drain latency multiplier and a drain
1254 * latency value.
1255 */
1256
vlv_update_drain_latency(struct drm_device * dev)1257 static void vlv_update_drain_latency(struct drm_device *dev)
1258 {
1259 struct drm_i915_private *dev_priv = dev->dev_private;
1260 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1261 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1262 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1263 either 16 or 32 */
1264
1265 /* For plane A, Cursor A */
1266 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1267 &cursor_prec_mult, &cursora_dl)) {
1268 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1269 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1270 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1272
1273 I915_WRITE(VLV_DDL1, cursora_prec |
1274 (cursora_dl << DDL_CURSORA_SHIFT) |
1275 planea_prec | planea_dl);
1276 }
1277
1278 /* For plane B, Cursor B */
1279 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1280 &cursor_prec_mult, &cursorb_dl)) {
1281 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1282 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1283 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1284 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1285
1286 I915_WRITE(VLV_DDL2, cursorb_prec |
1287 (cursorb_dl << DDL_CURSORB_SHIFT) |
1288 planeb_prec | planeb_dl);
1289 }
1290 }
1291
1292 #define single_plane_enabled(mask) ((mask) != 0 && powerof2(mask))
1293
valleyview_update_wm(struct drm_device * dev)1294 static void valleyview_update_wm(struct drm_device *dev)
1295 {
1296 static const int sr_latency_ns = 12000;
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1299 int plane_sr, cursor_sr;
1300 int ignore_plane_sr, ignore_cursor_sr;
1301 unsigned int enabled = 0;
1302
1303 vlv_update_drain_latency(dev);
1304
1305 if (g4x_compute_wm0(dev, 0,
1306 &valleyview_wm_info, latency_ns,
1307 &valleyview_cursor_wm_info, latency_ns,
1308 &planea_wm, &cursora_wm))
1309 enabled |= 1;
1310
1311 if (g4x_compute_wm0(dev, 1,
1312 &valleyview_wm_info, latency_ns,
1313 &valleyview_cursor_wm_info, latency_ns,
1314 &planeb_wm, &cursorb_wm))
1315 enabled |= 2;
1316
1317 if (single_plane_enabled(enabled) &&
1318 g4x_compute_srwm(dev, ffs(enabled) - 1,
1319 sr_latency_ns,
1320 &valleyview_wm_info,
1321 &valleyview_cursor_wm_info,
1322 &plane_sr, &ignore_cursor_sr) &&
1323 g4x_compute_srwm(dev, ffs(enabled) - 1,
1324 2*sr_latency_ns,
1325 &valleyview_wm_info,
1326 &valleyview_cursor_wm_info,
1327 &ignore_plane_sr, &cursor_sr)) {
1328 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1329 } else {
1330 I915_WRITE(FW_BLC_SELF_VLV,
1331 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1332 plane_sr = cursor_sr = 0;
1333 }
1334
1335 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1336 planea_wm, cursora_wm,
1337 planeb_wm, cursorb_wm,
1338 plane_sr, cursor_sr);
1339
1340 I915_WRITE(DSPFW1,
1341 (plane_sr << DSPFW_SR_SHIFT) |
1342 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1343 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1344 planea_wm);
1345 I915_WRITE(DSPFW2,
1346 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1347 (cursora_wm << DSPFW_CURSORA_SHIFT));
1348 I915_WRITE(DSPFW3,
1349 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1350 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1351 }
1352
g4x_update_wm(struct drm_device * dev)1353 static void g4x_update_wm(struct drm_device *dev)
1354 {
1355 static const int sr_latency_ns = 12000;
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1358 int plane_sr, cursor_sr;
1359 unsigned int enabled = 0;
1360
1361 if (g4x_compute_wm0(dev, 0,
1362 &g4x_wm_info, latency_ns,
1363 &g4x_cursor_wm_info, latency_ns,
1364 &planea_wm, &cursora_wm))
1365 enabled |= 1;
1366
1367 if (g4x_compute_wm0(dev, 1,
1368 &g4x_wm_info, latency_ns,
1369 &g4x_cursor_wm_info, latency_ns,
1370 &planeb_wm, &cursorb_wm))
1371 enabled |= 2;
1372
1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1375 sr_latency_ns,
1376 &g4x_wm_info,
1377 &g4x_cursor_wm_info,
1378 &plane_sr, &cursor_sr)) {
1379 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1380 } else {
1381 I915_WRITE(FW_BLC_SELF,
1382 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1383 plane_sr = cursor_sr = 0;
1384 }
1385
1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1387 planea_wm, cursora_wm,
1388 planeb_wm, cursorb_wm,
1389 plane_sr, cursor_sr);
1390
1391 I915_WRITE(DSPFW1,
1392 (plane_sr << DSPFW_SR_SHIFT) |
1393 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1394 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1395 planea_wm);
1396 I915_WRITE(DSPFW2,
1397 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1398 (cursora_wm << DSPFW_CURSORA_SHIFT));
1399 /* HPLL off in SR has some issues on G4x... disable it */
1400 I915_WRITE(DSPFW3,
1401 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1402 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1403 }
1404
i965_update_wm(struct drm_device * dev)1405 static void i965_update_wm(struct drm_device *dev)
1406 {
1407 struct drm_i915_private *dev_priv = dev->dev_private;
1408 struct drm_crtc *crtc;
1409 int srwm = 1;
1410 int cursor_sr = 16;
1411
1412 /* Calc sr entries for one plane configs */
1413 crtc = single_enabled_crtc(dev);
1414 if (crtc) {
1415 /* self-refresh has much higher latency */
1416 static const int sr_latency_ns = 12000;
1417 int clock = crtc->mode.clock;
1418 int htotal = crtc->mode.htotal;
1419 int hdisplay = crtc->mode.hdisplay;
1420 int pixel_size = crtc->fb->bits_per_pixel / 8;
1421 unsigned long line_time_us;
1422 int entries;
1423
1424 line_time_us = ((htotal * 1000) / clock);
1425
1426 /* Use ns/us then divide to preserve precision */
1427 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1428 pixel_size * hdisplay;
1429 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1430 srwm = I965_FIFO_SIZE - entries;
1431 if (srwm < 0)
1432 srwm = 1;
1433 srwm &= 0x1ff;
1434 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1435 entries, srwm);
1436
1437 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1438 pixel_size * 64;
1439 entries = DIV_ROUND_UP(entries,
1440 i965_cursor_wm_info.cacheline_size);
1441 cursor_sr = i965_cursor_wm_info.fifo_size -
1442 (entries + i965_cursor_wm_info.guard_size);
1443
1444 if (cursor_sr > i965_cursor_wm_info.max_wm)
1445 cursor_sr = i965_cursor_wm_info.max_wm;
1446
1447 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1448 "cursor %d\n", srwm, cursor_sr);
1449
1450 if (IS_CRESTLINE(dev))
1451 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1452 } else {
1453 /* Turn off self refresh if both pipes are enabled */
1454 if (IS_CRESTLINE(dev))
1455 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1456 & ~FW_BLC_SELF_EN);
1457 }
1458
1459 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1460 srwm);
1461
1462 /* 965 has limitations... */
1463 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1464 (8 << 16) | (8 << 8) | (8 << 0));
1465 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1466 /* update cursor SR watermark */
1467 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1468 }
1469
i9xx_update_wm(struct drm_device * dev)1470 static void i9xx_update_wm(struct drm_device *dev)
1471 {
1472 struct drm_i915_private *dev_priv = dev->dev_private;
1473 const struct intel_watermark_params *wm_info;
1474 uint32_t fwater_lo;
1475 uint32_t fwater_hi;
1476 int cwm, srwm = 1;
1477 int fifo_size;
1478 int planea_wm, planeb_wm;
1479 struct drm_crtc *crtc, *enabled = NULL;
1480
1481 if (IS_I945GM(dev))
1482 wm_info = &i945_wm_info;
1483 else if (!IS_GEN2(dev))
1484 wm_info = &i915_wm_info;
1485 else
1486 wm_info = &i855_wm_info;
1487
1488 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1489 crtc = intel_get_crtc_for_plane(dev, 0);
1490 if (intel_crtc_active(crtc)) {
1491 int cpp = crtc->fb->bits_per_pixel / 8;
1492 if (IS_GEN2(dev))
1493 cpp = 4;
1494
1495 planea_wm = intel_calculate_wm(crtc->mode.clock,
1496 wm_info, fifo_size, cpp,
1497 latency_ns);
1498 enabled = crtc;
1499 } else
1500 planea_wm = fifo_size - wm_info->guard_size;
1501
1502 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1503 crtc = intel_get_crtc_for_plane(dev, 1);
1504 if (intel_crtc_active(crtc)) {
1505 int cpp = crtc->fb->bits_per_pixel / 8;
1506 if (IS_GEN2(dev))
1507 cpp = 4;
1508
1509 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1510 wm_info, fifo_size, cpp,
1511 latency_ns);
1512 if (enabled == NULL)
1513 enabled = crtc;
1514 else
1515 enabled = NULL;
1516 } else
1517 planeb_wm = fifo_size - wm_info->guard_size;
1518
1519 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1520
1521 /*
1522 * Overlay gets an aggressive default since video jitter is bad.
1523 */
1524 cwm = 2;
1525
1526 /* Play safe and disable self-refresh before adjusting watermarks. */
1527 if (IS_I945G(dev) || IS_I945GM(dev))
1528 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1529 else if (IS_I915GM(dev))
1530 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1531
1532 /* Calc sr entries for one plane configs */
1533 if (HAS_FW_BLC(dev) && enabled) {
1534 /* self-refresh has much higher latency */
1535 static const int sr_latency_ns = 6000;
1536 int clock = enabled->mode.clock;
1537 int htotal = enabled->mode.htotal;
1538 int hdisplay = enabled->mode.hdisplay;
1539 int pixel_size = enabled->fb->bits_per_pixel / 8;
1540 unsigned long line_time_us;
1541 int entries;
1542
1543 line_time_us = (htotal * 1000) / clock;
1544
1545 /* Use ns/us then divide to preserve precision */
1546 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1547 pixel_size * hdisplay;
1548 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1549 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1550 srwm = wm_info->fifo_size - entries;
1551 if (srwm < 0)
1552 srwm = 1;
1553
1554 if (IS_I945G(dev) || IS_I945GM(dev))
1555 I915_WRITE(FW_BLC_SELF,
1556 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1557 else if (IS_I915GM(dev))
1558 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1559 }
1560
1561 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1562 planea_wm, planeb_wm, cwm, srwm);
1563
1564 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1565 fwater_hi = (cwm & 0x1f);
1566
1567 /* Set request length to 8 cachelines per fetch */
1568 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1569 fwater_hi = fwater_hi | (1 << 8);
1570
1571 I915_WRITE(FW_BLC, fwater_lo);
1572 I915_WRITE(FW_BLC2, fwater_hi);
1573
1574 if (HAS_FW_BLC(dev)) {
1575 if (enabled) {
1576 if (IS_I945G(dev) || IS_I945GM(dev))
1577 I915_WRITE(FW_BLC_SELF,
1578 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1579 else if (IS_I915GM(dev))
1580 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1581 DRM_DEBUG_KMS("memory self refresh enabled\n");
1582 } else
1583 DRM_DEBUG_KMS("memory self refresh disabled\n");
1584 }
1585 }
1586
i830_update_wm(struct drm_device * dev)1587 static void i830_update_wm(struct drm_device *dev)
1588 {
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 struct drm_crtc *crtc;
1591 uint32_t fwater_lo;
1592 int planea_wm;
1593
1594 crtc = single_enabled_crtc(dev);
1595 if (crtc == NULL)
1596 return;
1597
1598 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1599 dev_priv->display.get_fifo_size(dev, 0),
1600 4, latency_ns);
1601 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1602 fwater_lo |= (3<<8) | planea_wm;
1603
1604 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1605
1606 I915_WRITE(FW_BLC, fwater_lo);
1607 }
1608
1609 #define ILK_LP0_PLANE_LATENCY 700
1610 #define ILK_LP0_CURSOR_LATENCY 1300
1611
1612 /*
1613 * Check the wm result.
1614 *
1615 * If any calculated watermark values is larger than the maximum value that
1616 * can be programmed into the associated watermark register, that watermark
1617 * must be disabled.
1618 */
ironlake_check_srwm(struct drm_device * dev,int level,int fbc_wm,int display_wm,int cursor_wm,const struct intel_watermark_params * display,const struct intel_watermark_params * cursor)1619 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1620 int fbc_wm, int display_wm, int cursor_wm,
1621 const struct intel_watermark_params *display,
1622 const struct intel_watermark_params *cursor)
1623 {
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625
1626 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1627 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1628
1629 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1630 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1631 fbc_wm, SNB_FBC_MAX_SRWM, level);
1632
1633 /* fbc has it's own way to disable FBC WM */
1634 I915_WRITE(DISP_ARB_CTL,
1635 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1636 return false;
1637 }
1638
1639 if (display_wm > display->max_wm) {
1640 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1641 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1642 return false;
1643 }
1644
1645 if (cursor_wm > cursor->max_wm) {
1646 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1647 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1648 return false;
1649 }
1650
1651 if (!(fbc_wm || display_wm || cursor_wm)) {
1652 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1653 return false;
1654 }
1655
1656 return true;
1657 }
1658
1659 /*
1660 * Compute watermark values of WM[1-3],
1661 */
ironlake_compute_srwm(struct drm_device * dev,int level,int plane,int latency_ns,const struct intel_watermark_params * display,const struct intel_watermark_params * cursor,int * fbc_wm,int * display_wm,int * cursor_wm)1662 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1663 int latency_ns,
1664 const struct intel_watermark_params *display,
1665 const struct intel_watermark_params *cursor,
1666 int *fbc_wm, int *display_wm, int *cursor_wm)
1667 {
1668 struct drm_crtc *crtc;
1669 unsigned long line_time_us;
1670 int hdisplay, htotal, pixel_size, clock;
1671 int line_count, line_size;
1672 int small, large;
1673 int entries;
1674
1675 if (!latency_ns) {
1676 *fbc_wm = *display_wm = *cursor_wm = 0;
1677 return false;
1678 }
1679
1680 crtc = intel_get_crtc_for_plane(dev, plane);
1681 hdisplay = crtc->mode.hdisplay;
1682 htotal = crtc->mode.htotal;
1683 clock = crtc->mode.clock;
1684 pixel_size = crtc->fb->bits_per_pixel / 8;
1685
1686 line_time_us = (htotal * 1000) / clock;
1687 line_count = (latency_ns / line_time_us + 1000) / 1000;
1688 line_size = hdisplay * pixel_size;
1689
1690 /* Use the minimum of the small and large buffer method for primary */
1691 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1692 large = line_count * line_size;
1693
1694 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1695 *display_wm = entries + display->guard_size;
1696
1697 /*
1698 * Spec says:
1699 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1700 */
1701 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1702
1703 /* calculate the self-refresh watermark for display cursor */
1704 entries = line_count * pixel_size * 64;
1705 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1706 *cursor_wm = entries + cursor->guard_size;
1707
1708 return ironlake_check_srwm(dev, level,
1709 *fbc_wm, *display_wm, *cursor_wm,
1710 display, cursor);
1711 }
1712
ironlake_update_wm(struct drm_device * dev)1713 static void ironlake_update_wm(struct drm_device *dev)
1714 {
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716 int fbc_wm, plane_wm, cursor_wm;
1717 unsigned int enabled;
1718
1719 enabled = 0;
1720 if (g4x_compute_wm0(dev, 0,
1721 &ironlake_display_wm_info,
1722 ILK_LP0_PLANE_LATENCY,
1723 &ironlake_cursor_wm_info,
1724 ILK_LP0_CURSOR_LATENCY,
1725 &plane_wm, &cursor_wm)) {
1726 I915_WRITE(WM0_PIPEA_ILK,
1727 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1728 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1729 " plane %d, " "cursor: %d\n",
1730 plane_wm, cursor_wm);
1731 enabled |= 1;
1732 }
1733
1734 if (g4x_compute_wm0(dev, 1,
1735 &ironlake_display_wm_info,
1736 ILK_LP0_PLANE_LATENCY,
1737 &ironlake_cursor_wm_info,
1738 ILK_LP0_CURSOR_LATENCY,
1739 &plane_wm, &cursor_wm)) {
1740 I915_WRITE(WM0_PIPEB_ILK,
1741 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1742 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1743 " plane %d, cursor: %d\n",
1744 plane_wm, cursor_wm);
1745 enabled |= 2;
1746 }
1747
1748 /*
1749 * Calculate and update the self-refresh watermark only when one
1750 * display plane is used.
1751 */
1752 I915_WRITE(WM3_LP_ILK, 0);
1753 I915_WRITE(WM2_LP_ILK, 0);
1754 I915_WRITE(WM1_LP_ILK, 0);
1755
1756 if (!single_plane_enabled(enabled))
1757 return;
1758 enabled = ffs(enabled) - 1;
1759
1760 /* WM1 */
1761 if (!ironlake_compute_srwm(dev, 1, enabled,
1762 ILK_READ_WM1_LATENCY() * 500,
1763 &ironlake_display_srwm_info,
1764 &ironlake_cursor_srwm_info,
1765 &fbc_wm, &plane_wm, &cursor_wm))
1766 return;
1767
1768 I915_WRITE(WM1_LP_ILK,
1769 WM1_LP_SR_EN |
1770 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1771 (fbc_wm << WM1_LP_FBC_SHIFT) |
1772 (plane_wm << WM1_LP_SR_SHIFT) |
1773 cursor_wm);
1774
1775 /* WM2 */
1776 if (!ironlake_compute_srwm(dev, 2, enabled,
1777 ILK_READ_WM2_LATENCY() * 500,
1778 &ironlake_display_srwm_info,
1779 &ironlake_cursor_srwm_info,
1780 &fbc_wm, &plane_wm, &cursor_wm))
1781 return;
1782
1783 I915_WRITE(WM2_LP_ILK,
1784 WM2_LP_EN |
1785 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1786 (fbc_wm << WM1_LP_FBC_SHIFT) |
1787 (plane_wm << WM1_LP_SR_SHIFT) |
1788 cursor_wm);
1789
1790 /*
1791 * WM3 is unsupported on ILK, probably because we don't have latency
1792 * data for that power state
1793 */
1794 }
1795
sandybridge_update_wm(struct drm_device * dev)1796 static void sandybridge_update_wm(struct drm_device *dev)
1797 {
1798 struct drm_i915_private *dev_priv = dev->dev_private;
1799 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1800 u32 val;
1801 int fbc_wm, plane_wm, cursor_wm;
1802 unsigned int enabled;
1803
1804 enabled = 0;
1805 if (g4x_compute_wm0(dev, 0,
1806 &sandybridge_display_wm_info, latency,
1807 &sandybridge_cursor_wm_info, latency,
1808 &plane_wm, &cursor_wm)) {
1809 val = I915_READ(WM0_PIPEA_ILK);
1810 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1811 I915_WRITE(WM0_PIPEA_ILK, val |
1812 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1813 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1814 " plane %d, " "cursor: %d\n",
1815 plane_wm, cursor_wm);
1816 enabled |= 1;
1817 }
1818
1819 if (g4x_compute_wm0(dev, 1,
1820 &sandybridge_display_wm_info, latency,
1821 &sandybridge_cursor_wm_info, latency,
1822 &plane_wm, &cursor_wm)) {
1823 val = I915_READ(WM0_PIPEB_ILK);
1824 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1825 I915_WRITE(WM0_PIPEB_ILK, val |
1826 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1827 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1828 " plane %d, cursor: %d\n",
1829 plane_wm, cursor_wm);
1830 enabled |= 2;
1831 }
1832
1833 /*
1834 * Calculate and update the self-refresh watermark only when one
1835 * display plane is used.
1836 *
1837 * SNB support 3 levels of watermark.
1838 *
1839 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1840 * and disabled in the descending order
1841 *
1842 */
1843 I915_WRITE(WM3_LP_ILK, 0);
1844 I915_WRITE(WM2_LP_ILK, 0);
1845 I915_WRITE(WM1_LP_ILK, 0);
1846
1847 if (!single_plane_enabled(enabled) ||
1848 dev_priv->sprite_scaling_enabled)
1849 return;
1850 enabled = ffs(enabled) - 1;
1851
1852 /* WM1 */
1853 if (!ironlake_compute_srwm(dev, 1, enabled,
1854 SNB_READ_WM1_LATENCY() * 500,
1855 &sandybridge_display_srwm_info,
1856 &sandybridge_cursor_srwm_info,
1857 &fbc_wm, &plane_wm, &cursor_wm))
1858 return;
1859
1860 I915_WRITE(WM1_LP_ILK,
1861 WM1_LP_SR_EN |
1862 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1863 (fbc_wm << WM1_LP_FBC_SHIFT) |
1864 (plane_wm << WM1_LP_SR_SHIFT) |
1865 cursor_wm);
1866
1867 /* WM2 */
1868 if (!ironlake_compute_srwm(dev, 2, enabled,
1869 SNB_READ_WM2_LATENCY() * 500,
1870 &sandybridge_display_srwm_info,
1871 &sandybridge_cursor_srwm_info,
1872 &fbc_wm, &plane_wm, &cursor_wm))
1873 return;
1874
1875 I915_WRITE(WM2_LP_ILK,
1876 WM2_LP_EN |
1877 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1878 (fbc_wm << WM1_LP_FBC_SHIFT) |
1879 (plane_wm << WM1_LP_SR_SHIFT) |
1880 cursor_wm);
1881
1882 /* WM3 */
1883 if (!ironlake_compute_srwm(dev, 3, enabled,
1884 SNB_READ_WM3_LATENCY() * 500,
1885 &sandybridge_display_srwm_info,
1886 &sandybridge_cursor_srwm_info,
1887 &fbc_wm, &plane_wm, &cursor_wm))
1888 return;
1889
1890 I915_WRITE(WM3_LP_ILK,
1891 WM3_LP_EN |
1892 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1893 (fbc_wm << WM1_LP_FBC_SHIFT) |
1894 (plane_wm << WM1_LP_SR_SHIFT) |
1895 cursor_wm);
1896 }
1897
ivybridge_update_wm(struct drm_device * dev)1898 static void ivybridge_update_wm(struct drm_device *dev)
1899 {
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1902 u32 val;
1903 int fbc_wm, plane_wm, cursor_wm;
1904 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1905 unsigned int enabled;
1906
1907 enabled = 0;
1908 if (g4x_compute_wm0(dev, 0,
1909 &sandybridge_display_wm_info, latency,
1910 &sandybridge_cursor_wm_info, latency,
1911 &plane_wm, &cursor_wm)) {
1912 val = I915_READ(WM0_PIPEA_ILK);
1913 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1914 I915_WRITE(WM0_PIPEA_ILK, val |
1915 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1916 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1917 " plane %d, " "cursor: %d\n",
1918 plane_wm, cursor_wm);
1919 enabled |= 1;
1920 }
1921
1922 if (g4x_compute_wm0(dev, 1,
1923 &sandybridge_display_wm_info, latency,
1924 &sandybridge_cursor_wm_info, latency,
1925 &plane_wm, &cursor_wm)) {
1926 val = I915_READ(WM0_PIPEB_ILK);
1927 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1928 I915_WRITE(WM0_PIPEB_ILK, val |
1929 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1930 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1931 " plane %d, cursor: %d\n",
1932 plane_wm, cursor_wm);
1933 enabled |= 2;
1934 }
1935
1936 if (g4x_compute_wm0(dev, 2,
1937 &sandybridge_display_wm_info, latency,
1938 &sandybridge_cursor_wm_info, latency,
1939 &plane_wm, &cursor_wm)) {
1940 val = I915_READ(WM0_PIPEC_IVB);
1941 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1942 I915_WRITE(WM0_PIPEC_IVB, val |
1943 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1944 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1945 " plane %d, cursor: %d\n",
1946 plane_wm, cursor_wm);
1947 enabled |= 3;
1948 }
1949
1950 /*
1951 * Calculate and update the self-refresh watermark only when one
1952 * display plane is used.
1953 *
1954 * SNB support 3 levels of watermark.
1955 *
1956 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1957 * and disabled in the descending order
1958 *
1959 */
1960 I915_WRITE(WM3_LP_ILK, 0);
1961 I915_WRITE(WM2_LP_ILK, 0);
1962 I915_WRITE(WM1_LP_ILK, 0);
1963
1964 if (!single_plane_enabled(enabled) ||
1965 dev_priv->sprite_scaling_enabled)
1966 return;
1967 enabled = ffs(enabled) - 1;
1968
1969 /* WM1 */
1970 if (!ironlake_compute_srwm(dev, 1, enabled,
1971 SNB_READ_WM1_LATENCY() * 500,
1972 &sandybridge_display_srwm_info,
1973 &sandybridge_cursor_srwm_info,
1974 &fbc_wm, &plane_wm, &cursor_wm))
1975 return;
1976
1977 I915_WRITE(WM1_LP_ILK,
1978 WM1_LP_SR_EN |
1979 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1980 (fbc_wm << WM1_LP_FBC_SHIFT) |
1981 (plane_wm << WM1_LP_SR_SHIFT) |
1982 cursor_wm);
1983
1984 /* WM2 */
1985 if (!ironlake_compute_srwm(dev, 2, enabled,
1986 SNB_READ_WM2_LATENCY() * 500,
1987 &sandybridge_display_srwm_info,
1988 &sandybridge_cursor_srwm_info,
1989 &fbc_wm, &plane_wm, &cursor_wm))
1990 return;
1991
1992 I915_WRITE(WM2_LP_ILK,
1993 WM2_LP_EN |
1994 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1995 (fbc_wm << WM1_LP_FBC_SHIFT) |
1996 (plane_wm << WM1_LP_SR_SHIFT) |
1997 cursor_wm);
1998
1999 /* WM3, note we have to correct the cursor latency */
2000 if (!ironlake_compute_srwm(dev, 3, enabled,
2001 SNB_READ_WM3_LATENCY() * 500,
2002 &sandybridge_display_srwm_info,
2003 &sandybridge_cursor_srwm_info,
2004 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2005 !ironlake_compute_srwm(dev, 3, enabled,
2006 2 * SNB_READ_WM3_LATENCY() * 500,
2007 &sandybridge_display_srwm_info,
2008 &sandybridge_cursor_srwm_info,
2009 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2010 return;
2011
2012 I915_WRITE(WM3_LP_ILK,
2013 WM3_LP_EN |
2014 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2015 (fbc_wm << WM1_LP_FBC_SHIFT) |
2016 (plane_wm << WM1_LP_SR_SHIFT) |
2017 cursor_wm);
2018 }
2019
2020 static void
haswell_update_linetime_wm(struct drm_device * dev,int pipe,struct drm_display_mode * mode)2021 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2022 struct drm_display_mode *mode)
2023 {
2024 struct drm_i915_private *dev_priv = dev->dev_private;
2025 u32 temp;
2026
2027 temp = I915_READ(PIPE_WM_LINETIME(pipe));
2028 temp &= ~PIPE_WM_LINETIME_MASK;
2029
2030 /* The WM are computed with base on how long it takes to fill a single
2031 * row at the given clock rate, multiplied by 8.
2032 * */
2033 temp |= PIPE_WM_LINETIME_TIME(
2034 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2035
2036 /* IPS watermarks are only used by pipe A, and are ignored by
2037 * pipes B and C. They are calculated similarly to the common
2038 * linetime values, except that we are using CD clock frequency
2039 * in MHz instead of pixel rate for the division.
2040 *
2041 * This is a placeholder for the IPS watermark calculation code.
2042 */
2043
2044 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2045 }
2046
2047 static bool
sandybridge_compute_sprite_wm(struct drm_device * dev,int plane,uint32_t sprite_width,int pixel_size,const struct intel_watermark_params * display,int display_latency_ns,int * sprite_wm)2048 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2049 uint32_t sprite_width, int pixel_size,
2050 const struct intel_watermark_params *display,
2051 int display_latency_ns, int *sprite_wm)
2052 {
2053 struct drm_crtc *crtc;
2054 int clock;
2055 int entries, tlb_miss;
2056
2057 crtc = intel_get_crtc_for_plane(dev, plane);
2058 if (!intel_crtc_active(crtc)) {
2059 *sprite_wm = display->guard_size;
2060 return false;
2061 }
2062
2063 clock = crtc->mode.clock;
2064
2065 /* Use the small buffer method to calculate the sprite watermark */
2066 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2067 tlb_miss = display->fifo_size*display->cacheline_size -
2068 sprite_width * 8;
2069 if (tlb_miss > 0)
2070 entries += tlb_miss;
2071 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2072 *sprite_wm = entries + display->guard_size;
2073 if (*sprite_wm > (int)display->max_wm)
2074 *sprite_wm = display->max_wm;
2075
2076 return true;
2077 }
2078
2079 static bool
sandybridge_compute_sprite_srwm(struct drm_device * dev,int plane,uint32_t sprite_width,int pixel_size,const struct intel_watermark_params * display,int latency_ns,int * sprite_wm)2080 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2081 uint32_t sprite_width, int pixel_size,
2082 const struct intel_watermark_params *display,
2083 int latency_ns, int *sprite_wm)
2084 {
2085 struct drm_crtc *crtc;
2086 unsigned long line_time_us;
2087 int clock;
2088 int line_count, line_size;
2089 int small, large;
2090 int entries;
2091
2092 if (!latency_ns) {
2093 *sprite_wm = 0;
2094 return false;
2095 }
2096
2097 crtc = intel_get_crtc_for_plane(dev, plane);
2098 clock = crtc->mode.clock;
2099 if (!clock) {
2100 *sprite_wm = 0;
2101 return false;
2102 }
2103
2104 line_time_us = (sprite_width * 1000) / clock;
2105 if (!line_time_us) {
2106 *sprite_wm = 0;
2107 return false;
2108 }
2109
2110 line_count = (latency_ns / line_time_us + 1000) / 1000;
2111 line_size = sprite_width * pixel_size;
2112
2113 /* Use the minimum of the small and large buffer method for primary */
2114 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2115 large = line_count * line_size;
2116
2117 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2118 *sprite_wm = entries + display->guard_size;
2119
2120 return *sprite_wm > 0x3ff ? false : true;
2121 }
2122
sandybridge_update_sprite_wm(struct drm_device * dev,int pipe,uint32_t sprite_width,int pixel_size)2123 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2124 uint32_t sprite_width, int pixel_size)
2125 {
2126 struct drm_i915_private *dev_priv = dev->dev_private;
2127 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2128 u32 val;
2129 int sprite_wm, reg;
2130 int ret;
2131
2132 switch (pipe) {
2133 case 0:
2134 reg = WM0_PIPEA_ILK;
2135 break;
2136 case 1:
2137 reg = WM0_PIPEB_ILK;
2138 break;
2139 case 2:
2140 reg = WM0_PIPEC_IVB;
2141 break;
2142 default:
2143 return; /* bad pipe */
2144 }
2145
2146 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2147 &sandybridge_display_wm_info,
2148 latency, &sprite_wm);
2149 if (!ret) {
2150 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2151 pipe);
2152 return;
2153 }
2154
2155 val = I915_READ(reg);
2156 val &= ~WM0_PIPE_SPRITE_MASK;
2157 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2158 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2159
2160
2161 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2162 pixel_size,
2163 &sandybridge_display_srwm_info,
2164 SNB_READ_WM1_LATENCY() * 500,
2165 &sprite_wm);
2166 if (!ret) {
2167 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2168 pipe);
2169 return;
2170 }
2171 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2172
2173 /* Only IVB has two more LP watermarks for sprite */
2174 if (!IS_IVYBRIDGE(dev))
2175 return;
2176
2177 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2178 pixel_size,
2179 &sandybridge_display_srwm_info,
2180 SNB_READ_WM2_LATENCY() * 500,
2181 &sprite_wm);
2182 if (!ret) {
2183 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2184 pipe);
2185 return;
2186 }
2187 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2188
2189 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2190 pixel_size,
2191 &sandybridge_display_srwm_info,
2192 SNB_READ_WM3_LATENCY() * 500,
2193 &sprite_wm);
2194 if (!ret) {
2195 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2196 pipe);
2197 return;
2198 }
2199 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2200 }
2201
2202 /**
2203 * intel_update_watermarks - update FIFO watermark values based on current modes
2204 *
2205 * Calculate watermark values for the various WM regs based on current mode
2206 * and plane configuration.
2207 *
2208 * There are several cases to deal with here:
2209 * - normal (i.e. non-self-refresh)
2210 * - self-refresh (SR) mode
2211 * - lines are large relative to FIFO size (buffer can hold up to 2)
2212 * - lines are small relative to FIFO size (buffer can hold more than 2
2213 * lines), so need to account for TLB latency
2214 *
2215 * The normal calculation is:
2216 * watermark = dotclock * bytes per pixel * latency
2217 * where latency is platform & configuration dependent (we assume pessimal
2218 * values here).
2219 *
2220 * The SR calculation is:
2221 * watermark = (trunc(latency/line time)+1) * surface width *
2222 * bytes per pixel
2223 * where
2224 * line time = htotal / dotclock
2225 * surface width = hdisplay for normal plane and 64 for cursor
2226 * and latency is assumed to be high, as above.
2227 *
2228 * The final value programmed to the register should always be rounded up,
2229 * and include an extra 2 entries to account for clock crossings.
2230 *
2231 * We don't use the sprite, so we can ignore that. And on Crestline we have
2232 * to set the non-SR watermarks to 8.
2233 */
intel_update_watermarks(struct drm_device * dev)2234 void intel_update_watermarks(struct drm_device *dev)
2235 {
2236 struct drm_i915_private *dev_priv = dev->dev_private;
2237
2238 if (dev_priv->display.update_wm)
2239 dev_priv->display.update_wm(dev);
2240 }
2241
intel_update_linetime_watermarks(struct drm_device * dev,int pipe,struct drm_display_mode * mode)2242 void intel_update_linetime_watermarks(struct drm_device *dev,
2243 int pipe, struct drm_display_mode *mode)
2244 {
2245 struct drm_i915_private *dev_priv = dev->dev_private;
2246
2247 if (dev_priv->display.update_linetime_wm)
2248 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2249 }
2250
intel_update_sprite_watermarks(struct drm_device * dev,int pipe,uint32_t sprite_width,int pixel_size)2251 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2252 uint32_t sprite_width, int pixel_size)
2253 {
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255
2256 if (dev_priv->display.update_sprite_wm)
2257 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2258 pixel_size);
2259 }
2260
2261 static struct drm_i915_gem_object *
intel_alloc_context_page(struct drm_device * dev)2262 intel_alloc_context_page(struct drm_device *dev)
2263 {
2264 struct drm_i915_gem_object *ctx;
2265 int ret;
2266
2267 DRM_LOCK_ASSERT(dev);
2268
2269 ctx = i915_gem_alloc_object(dev, 4096);
2270 if (!ctx) {
2271 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2272 return NULL;
2273 }
2274
2275 ret = i915_gem_object_pin(ctx, 4096, true, false);
2276 if (ret) {
2277 DRM_ERROR("failed to pin power context: %d\n", ret);
2278 goto err_unref;
2279 }
2280
2281 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2282 if (ret) {
2283 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2284 goto err_unpin;
2285 }
2286
2287 return ctx;
2288
2289 err_unpin:
2290 i915_gem_object_unpin(ctx);
2291 err_unref:
2292 drm_gem_object_unreference(&ctx->base);
2293 DRM_UNLOCK(dev);
2294 return NULL;
2295 }
2296
2297 /**
2298 * Lock protecting IPS related data structures
2299 */
2300 struct mtx mchdev_lock;
2301 MTX_SYSINIT(mchdev, &mchdev_lock, "mchdev", MTX_DEF);
2302
2303 /* Global for IPS driver to get at the current i915 device. Protected by
2304 * mchdev_lock. */
2305 static struct drm_i915_private *i915_mch_dev;
2306
ironlake_set_drps(struct drm_device * dev,u8 val)2307 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2308 {
2309 struct drm_i915_private *dev_priv = dev->dev_private;
2310 u16 rgvswctl;
2311
2312 mtx_assert(&mchdev_lock, MA_OWNED);
2313
2314 rgvswctl = I915_READ16(MEMSWCTL);
2315 if (rgvswctl & MEMCTL_CMD_STS) {
2316 DRM_DEBUG("gpu busy, RCS change rejected\n");
2317 return false; /* still busy with another command */
2318 }
2319
2320 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2321 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2322 I915_WRITE16(MEMSWCTL, rgvswctl);
2323 POSTING_READ16(MEMSWCTL);
2324
2325 rgvswctl |= MEMCTL_CMD_STS;
2326 I915_WRITE16(MEMSWCTL, rgvswctl);
2327
2328 return true;
2329 }
2330
ironlake_enable_drps(struct drm_device * dev)2331 static void ironlake_enable_drps(struct drm_device *dev)
2332 {
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 u32 rgvmodectl = I915_READ(MEMMODECTL);
2335 u8 fmax, fmin, fstart, vstart;
2336
2337 mtx_lock(&mchdev_lock);
2338
2339 /* Enable temp reporting */
2340 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2341 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2342
2343 /* 100ms RC evaluation intervals */
2344 I915_WRITE(RCUPEI, 100000);
2345 I915_WRITE(RCDNEI, 100000);
2346
2347 /* Set max/min thresholds to 90ms and 80ms respectively */
2348 I915_WRITE(RCBMAXAVG, 90000);
2349 I915_WRITE(RCBMINAVG, 80000);
2350
2351 I915_WRITE(MEMIHYST, 1);
2352
2353 /* Set up min, max, and cur for interrupt handling */
2354 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2355 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2356 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2357 MEMMODE_FSTART_SHIFT;
2358
2359 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2360 PXVFREQ_PX_SHIFT;
2361
2362 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2363 dev_priv->ips.fstart = fstart;
2364
2365 dev_priv->ips.max_delay = fstart;
2366 dev_priv->ips.min_delay = fmin;
2367 dev_priv->ips.cur_delay = fstart;
2368
2369 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2370 fmax, fmin, fstart);
2371
2372 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2373
2374 /*
2375 * Interrupts will be enabled in ironlake_irq_postinstall
2376 */
2377
2378 I915_WRITE(VIDSTART, vstart);
2379 POSTING_READ(VIDSTART);
2380
2381 rgvmodectl |= MEMMODE_SWMODE_EN;
2382 I915_WRITE(MEMMODECTL, rgvmodectl);
2383
2384 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2385 DRM_ERROR("stuck trying to change perf mode\n");
2386 mdelay(1);
2387
2388 ironlake_set_drps(dev, fstart);
2389
2390 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2391 I915_READ(0x112e0);
2392 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2393 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2394 getrawmonotonic(&dev_priv->ips.last_time2);
2395
2396 mtx_unlock(&mchdev_lock);
2397 }
2398
ironlake_disable_drps(struct drm_device * dev)2399 static void ironlake_disable_drps(struct drm_device *dev)
2400 {
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 u16 rgvswctl;
2403
2404 mtx_lock(&mchdev_lock);
2405
2406 rgvswctl = I915_READ16(MEMSWCTL);
2407
2408 /* Ack interrupts, disable EFC interrupt */
2409 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2410 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2411 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2412 I915_WRITE(DEIIR, DE_PCU_EVENT);
2413 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2414
2415 /* Go back to the starting frequency */
2416 ironlake_set_drps(dev, dev_priv->ips.fstart);
2417 mdelay(1);
2418 rgvswctl |= MEMCTL_CMD_STS;
2419 I915_WRITE(MEMSWCTL, rgvswctl);
2420 mdelay(1);
2421
2422 mtx_unlock(&mchdev_lock);
2423 }
2424
2425 /* There's a funny hw issue where the hw returns all 0 when reading from
2426 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2427 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2428 * all limits and the gpu stuck at whatever frequency it is at atm).
2429 */
gen6_rps_limits(struct drm_i915_private * dev_priv,u8 * val)2430 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2431 {
2432 u32 limits;
2433
2434 limits = 0;
2435
2436 if (*val >= dev_priv->rps.max_delay)
2437 *val = dev_priv->rps.max_delay;
2438 limits |= dev_priv->rps.max_delay << 24;
2439
2440 /* Only set the down limit when we've reached the lowest level to avoid
2441 * getting more interrupts, otherwise leave this clear. This prevents a
2442 * race in the hw when coming out of rc6: There's a tiny window where
2443 * the hw runs at the minimal clock before selecting the desired
2444 * frequency, if the down threshold expires in that window we will not
2445 * receive a down interrupt. */
2446 if (*val <= dev_priv->rps.min_delay) {
2447 *val = dev_priv->rps.min_delay;
2448 limits |= dev_priv->rps.min_delay << 16;
2449 }
2450
2451 return limits;
2452 }
2453
gen6_set_rps(struct drm_device * dev,u8 val)2454 void gen6_set_rps(struct drm_device *dev, u8 val)
2455 {
2456 struct drm_i915_private *dev_priv = dev->dev_private;
2457 u32 limits = gen6_rps_limits(dev_priv, &val);
2458
2459 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED);
2460 WARN_ON(val > dev_priv->rps.max_delay);
2461 WARN_ON(val < dev_priv->rps.min_delay);
2462
2463 if (val == dev_priv->rps.cur_delay)
2464 return;
2465
2466 I915_WRITE(GEN6_RPNSWREQ,
2467 GEN6_FREQUENCY(val) |
2468 GEN6_OFFSET(0) |
2469 GEN6_AGGRESSIVE_TURBO);
2470
2471 /* Make sure we continue to get interrupts
2472 * until we hit the minimum or maximum frequencies.
2473 */
2474 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2475
2476 POSTING_READ(GEN6_RPNSWREQ);
2477
2478 dev_priv->rps.cur_delay = val;
2479 }
2480
gen6_disable_rps(struct drm_device * dev)2481 static void gen6_disable_rps(struct drm_device *dev)
2482 {
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2484
2485 I915_WRITE(GEN6_RC_CONTROL, 0);
2486 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2487 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2488 I915_WRITE(GEN6_PMIER, 0);
2489 /* Complete PM interrupt masking here doesn't race with the rps work
2490 * item again unmasking PM interrupts because that is using a different
2491 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2492 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2493
2494 mtx_lock(&dev_priv->rps.lock);
2495 dev_priv->rps.pm_iir = 0;
2496 mtx_unlock(&dev_priv->rps.lock);
2497
2498 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2499 }
2500
intel_enable_rc6(const struct drm_device * dev)2501 int intel_enable_rc6(const struct drm_device *dev)
2502 {
2503 /* Respect the kernel parameter if it is set */
2504 if (i915_enable_rc6 >= 0)
2505 return i915_enable_rc6;
2506
2507 /* Disable RC6 on Ironlake */
2508 if (INTEL_INFO(dev)->gen == 5)
2509 return 0;
2510
2511 if (IS_HASWELL(dev)) {
2512 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2513 return INTEL_RC6_ENABLE;
2514 }
2515
2516 /* snb/ivb have more than one rc6 state. */
2517 if (INTEL_INFO(dev)->gen == 6) {
2518 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2519 return INTEL_RC6_ENABLE;
2520 }
2521
2522 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2523 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2524 }
2525
gen6_enable_rps(struct drm_device * dev)2526 static void gen6_enable_rps(struct drm_device *dev)
2527 {
2528 struct drm_i915_private *dev_priv = dev->dev_private;
2529 struct intel_ring_buffer *ring;
2530 u32 rp_state_cap;
2531 u32 gt_perf_status;
2532 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2533 u32 gtfifodbg;
2534 int rc6_mode;
2535 int i, ret;
2536
2537 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED);
2538
2539 /* Here begins a magic sequence of register writes to enable
2540 * auto-downclocking.
2541 *
2542 * Perhaps there might be some value in exposing these to
2543 * userspace...
2544 */
2545 I915_WRITE(GEN6_RC_STATE, 0);
2546
2547 /* Clear the DBG now so we don't confuse earlier errors */
2548 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2549 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2550 I915_WRITE(GTFIFODBG, gtfifodbg);
2551 }
2552
2553 gen6_gt_force_wake_get(dev_priv);
2554
2555 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2556 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2557
2558 /* In units of 100MHz */
2559 dev_priv->rps.max_delay = rp_state_cap & 0xff;
2560 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2561 dev_priv->rps.cur_delay = 0;
2562
2563 /* disable the counters and set deterministic thresholds */
2564 I915_WRITE(GEN6_RC_CONTROL, 0);
2565
2566 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2567 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2568 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2569 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2570 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2571
2572 for_each_ring(ring, dev_priv, i)
2573 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2574
2575 I915_WRITE(GEN6_RC_SLEEP, 0);
2576 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2577 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2578 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2579 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2580
2581 /* Check if we are enabling RC6 */
2582 rc6_mode = intel_enable_rc6(dev_priv->dev);
2583 if (rc6_mode & INTEL_RC6_ENABLE)
2584 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2585
2586 /* We don't use those on Haswell */
2587 if (!IS_HASWELL(dev)) {
2588 if (rc6_mode & INTEL_RC6p_ENABLE)
2589 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2590
2591 if (rc6_mode & INTEL_RC6pp_ENABLE)
2592 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2593 }
2594
2595 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2596 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2597 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2598 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2599
2600 I915_WRITE(GEN6_RC_CONTROL,
2601 rc6_mask |
2602 GEN6_RC_CTL_EI_MODE(1) |
2603 GEN6_RC_CTL_HW_ENABLE);
2604
2605 I915_WRITE(GEN6_RPNSWREQ,
2606 GEN6_FREQUENCY(10) |
2607 GEN6_OFFSET(0) |
2608 GEN6_AGGRESSIVE_TURBO);
2609 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2610 GEN6_FREQUENCY(12));
2611
2612 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2613 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2614 dev_priv->rps.max_delay << 24 |
2615 dev_priv->rps.min_delay << 16);
2616
2617 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2618 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2619 I915_WRITE(GEN6_RP_UP_EI, 66000);
2620 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2621
2622 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2623 I915_WRITE(GEN6_RP_CONTROL,
2624 GEN6_RP_MEDIA_TURBO |
2625 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2626 GEN6_RP_MEDIA_IS_GFX |
2627 GEN6_RP_ENABLE |
2628 GEN6_RP_UP_BUSY_AVG |
2629 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2630
2631 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2632 if (!ret) {
2633 pcu_mbox = 0;
2634 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2635 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2636 dev_priv->rps.max_delay = pcu_mbox & 0xff;
2637 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2638 }
2639 } else {
2640 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2641 }
2642
2643 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2644
2645 /* requires MSI enabled */
2646 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2647 mtx_lock(&dev_priv->rps.lock);
2648 WARN_ON(dev_priv->rps.pm_iir != 0);
2649 I915_WRITE(GEN6_PMIMR, 0);
2650 mtx_unlock(&dev_priv->rps.lock);
2651 /* enable all PM interrupts */
2652 I915_WRITE(GEN6_PMINTRMSK, 0);
2653
2654 rc6vids = 0;
2655 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2656 if (IS_GEN6(dev) && ret) {
2657 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2658 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2659 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2660 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2661 rc6vids &= 0xffff00;
2662 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2663 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2664 if (ret)
2665 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2666 }
2667
2668 gen6_gt_force_wake_put(dev_priv);
2669 }
2670
gen6_update_ring_freq(struct drm_device * dev)2671 static void gen6_update_ring_freq(struct drm_device *dev)
2672 {
2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674 int min_freq = 15;
2675 int gpu_freq;
2676 unsigned int ia_freq, max_ia_freq;
2677 int scaling_factor = 180;
2678
2679 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED);
2680
2681 #ifdef FREEBSD_WIP
2682 max_ia_freq = cpufreq_quick_get_max(0);
2683 /*
2684 * Default to measured freq if none found, PCU will ensure we don't go
2685 * over
2686 */
2687 if (!max_ia_freq)
2688 max_ia_freq = tsc_khz;
2689 #else
2690 uint64_t freq;
2691 freq = atomic_load_acq_64(&tsc_freq);
2692 max_ia_freq = freq / 1000;
2693 #endif /* FREEBSD_WIP */
2694
2695 /* Convert from kHz to MHz */
2696 max_ia_freq /= 1000;
2697
2698 /*
2699 * For each potential GPU frequency, load a ring frequency we'd like
2700 * to use for memory access. We do this by specifying the IA frequency
2701 * the PCU should use as a reference to determine the ring frequency.
2702 */
2703 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2704 gpu_freq--) {
2705 int diff = dev_priv->rps.max_delay - gpu_freq;
2706
2707 /*
2708 * For GPU frequencies less than 750MHz, just use the lowest
2709 * ring freq.
2710 */
2711 if (gpu_freq < min_freq)
2712 ia_freq = 800;
2713 else
2714 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2715 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2716 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2717
2718 sandybridge_pcode_write(dev_priv,
2719 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2720 ia_freq | gpu_freq);
2721 }
2722 }
2723
ironlake_teardown_rc6(struct drm_device * dev)2724 void ironlake_teardown_rc6(struct drm_device *dev)
2725 {
2726 struct drm_i915_private *dev_priv = dev->dev_private;
2727
2728 if (dev_priv->ips.renderctx) {
2729 i915_gem_object_unpin(dev_priv->ips.renderctx);
2730 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2731 dev_priv->ips.renderctx = NULL;
2732 }
2733
2734 if (dev_priv->ips.pwrctx) {
2735 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2736 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2737 dev_priv->ips.pwrctx = NULL;
2738 }
2739 }
2740
ironlake_disable_rc6(struct drm_device * dev)2741 static void ironlake_disable_rc6(struct drm_device *dev)
2742 {
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744
2745 if (I915_READ(PWRCTXA)) {
2746 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2747 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2748 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2749 50);
2750
2751 I915_WRITE(PWRCTXA, 0);
2752 POSTING_READ(PWRCTXA);
2753
2754 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2755 POSTING_READ(RSTDBYCTL);
2756 }
2757 }
2758
ironlake_setup_rc6(struct drm_device * dev)2759 static int ironlake_setup_rc6(struct drm_device *dev)
2760 {
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762
2763 if (dev_priv->ips.renderctx == NULL)
2764 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2765 if (!dev_priv->ips.renderctx)
2766 return -ENOMEM;
2767
2768 if (dev_priv->ips.pwrctx == NULL)
2769 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2770 if (!dev_priv->ips.pwrctx) {
2771 ironlake_teardown_rc6(dev);
2772 return -ENOMEM;
2773 }
2774
2775 return 0;
2776 }
2777
ironlake_enable_rc6(struct drm_device * dev)2778 static void ironlake_enable_rc6(struct drm_device *dev)
2779 {
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2782 bool was_interruptible;
2783 int ret;
2784
2785 /* rc6 disabled by default due to repeated reports of hanging during
2786 * boot and resume.
2787 */
2788 if (!intel_enable_rc6(dev))
2789 return;
2790
2791 DRM_LOCK_ASSERT(dev);
2792
2793 ret = ironlake_setup_rc6(dev);
2794 if (ret)
2795 return;
2796
2797 was_interruptible = dev_priv->mm.interruptible;
2798 dev_priv->mm.interruptible = false;
2799
2800 /*
2801 * GPU can automatically power down the render unit if given a page
2802 * to save state.
2803 */
2804 ret = intel_ring_begin(ring, 6);
2805 if (ret) {
2806 ironlake_teardown_rc6(dev);
2807 dev_priv->mm.interruptible = was_interruptible;
2808 return;
2809 }
2810
2811 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2812 intel_ring_emit(ring, MI_SET_CONTEXT);
2813 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
2814 MI_MM_SPACE_GTT |
2815 MI_SAVE_EXT_STATE_EN |
2816 MI_RESTORE_EXT_STATE_EN |
2817 MI_RESTORE_INHIBIT);
2818 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2819 intel_ring_emit(ring, MI_NOOP);
2820 intel_ring_emit(ring, MI_FLUSH);
2821 intel_ring_advance(ring);
2822
2823 /*
2824 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2825 * does an implicit flush, combined with MI_FLUSH above, it should be
2826 * safe to assume that renderctx is valid
2827 */
2828 ret = intel_ring_idle(ring);
2829 dev_priv->mm.interruptible = was_interruptible;
2830 if (ret) {
2831 DRM_ERROR("failed to enable ironlake power power savings\n");
2832 ironlake_teardown_rc6(dev);
2833 return;
2834 }
2835
2836 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2837 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2838 }
2839
intel_pxfreq(u32 vidfreq)2840 static unsigned long intel_pxfreq(u32 vidfreq)
2841 {
2842 unsigned long freq;
2843 int div = (vidfreq & 0x3f0000) >> 16;
2844 int post = (vidfreq & 0x3000) >> 12;
2845 int pre = (vidfreq & 0x7);
2846
2847 if (!pre)
2848 return 0;
2849
2850 freq = ((div * 133333) / ((1<<post) * pre));
2851
2852 return freq;
2853 }
2854
2855 static const struct cparams {
2856 u16 i;
2857 u16 t;
2858 u16 m;
2859 u16 c;
2860 } cparams[] = {
2861 { 1, 1333, 301, 28664 },
2862 { 1, 1066, 294, 24460 },
2863 { 1, 800, 294, 25192 },
2864 { 0, 1333, 276, 27605 },
2865 { 0, 1066, 276, 27605 },
2866 { 0, 800, 231, 23784 },
2867 };
2868
__i915_chipset_val(struct drm_i915_private * dev_priv)2869 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
2870 {
2871 u64 total_count, diff, ret;
2872 u32 count1, count2, count3, m = 0, c = 0;
2873 unsigned long now = jiffies_to_msecs(jiffies), diff1;
2874 int i;
2875
2876 mtx_assert(&mchdev_lock, MA_OWNED);
2877
2878 diff1 = now - dev_priv->ips.last_time1;
2879
2880 /* Prevent division-by-zero if we are asking too fast.
2881 * Also, we don't get interesting results if we are polling
2882 * faster than once in 10ms, so just return the saved value
2883 * in such cases.
2884 */
2885 if (diff1 <= 10)
2886 return dev_priv->ips.chipset_power;
2887
2888 count1 = I915_READ(DMIEC);
2889 count2 = I915_READ(DDREC);
2890 count3 = I915_READ(CSIEC);
2891
2892 total_count = count1 + count2 + count3;
2893
2894 /* FIXME: handle per-counter overflow */
2895 if (total_count < dev_priv->ips.last_count1) {
2896 diff = ~0UL - dev_priv->ips.last_count1;
2897 diff += total_count;
2898 } else {
2899 diff = total_count - dev_priv->ips.last_count1;
2900 }
2901
2902 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
2903 if (cparams[i].i == dev_priv->ips.c_m &&
2904 cparams[i].t == dev_priv->ips.r_t) {
2905 m = cparams[i].m;
2906 c = cparams[i].c;
2907 break;
2908 }
2909 }
2910
2911 diff = div_u64(diff, diff1);
2912 ret = ((m * diff) + c);
2913 ret = div_u64(ret, 10);
2914
2915 dev_priv->ips.last_count1 = total_count;
2916 dev_priv->ips.last_time1 = now;
2917
2918 dev_priv->ips.chipset_power = ret;
2919
2920 return ret;
2921 }
2922
i915_chipset_val(struct drm_i915_private * dev_priv)2923 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2924 {
2925 unsigned long val;
2926
2927 if (dev_priv->info->gen != 5)
2928 return 0;
2929
2930 mtx_lock(&mchdev_lock);
2931
2932 val = __i915_chipset_val(dev_priv);
2933
2934 mtx_unlock(&mchdev_lock);
2935
2936 return val;
2937 }
2938
i915_mch_val(struct drm_i915_private * dev_priv)2939 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2940 {
2941 unsigned long m, x, b;
2942 u32 tsfs;
2943
2944 tsfs = I915_READ(TSFS);
2945
2946 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2947 x = I915_READ8(I915_TR1);
2948
2949 b = tsfs & TSFS_INTR_MASK;
2950
2951 return ((m * x) / 127) - b;
2952 }
2953
pvid_to_extvid(struct drm_i915_private * dev_priv,u8 pxvid)2954 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2955 {
2956 static const struct v_table {
2957 u16 vd; /* in .1 mil */
2958 u16 vm; /* in .1 mil */
2959 } v_table[] = {
2960 { 0, 0, },
2961 { 375, 0, },
2962 { 500, 0, },
2963 { 625, 0, },
2964 { 750, 0, },
2965 { 875, 0, },
2966 { 1000, 0, },
2967 { 1125, 0, },
2968 { 4125, 3000, },
2969 { 4125, 3000, },
2970 { 4125, 3000, },
2971 { 4125, 3000, },
2972 { 4125, 3000, },
2973 { 4125, 3000, },
2974 { 4125, 3000, },
2975 { 4125, 3000, },
2976 { 4125, 3000, },
2977 { 4125, 3000, },
2978 { 4125, 3000, },
2979 { 4125, 3000, },
2980 { 4125, 3000, },
2981 { 4125, 3000, },
2982 { 4125, 3000, },
2983 { 4125, 3000, },
2984 { 4125, 3000, },
2985 { 4125, 3000, },
2986 { 4125, 3000, },
2987 { 4125, 3000, },
2988 { 4125, 3000, },
2989 { 4125, 3000, },
2990 { 4125, 3000, },
2991 { 4125, 3000, },
2992 { 4250, 3125, },
2993 { 4375, 3250, },
2994 { 4500, 3375, },
2995 { 4625, 3500, },
2996 { 4750, 3625, },
2997 { 4875, 3750, },
2998 { 5000, 3875, },
2999 { 5125, 4000, },
3000 { 5250, 4125, },
3001 { 5375, 4250, },
3002 { 5500, 4375, },
3003 { 5625, 4500, },
3004 { 5750, 4625, },
3005 { 5875, 4750, },
3006 { 6000, 4875, },
3007 { 6125, 5000, },
3008 { 6250, 5125, },
3009 { 6375, 5250, },
3010 { 6500, 5375, },
3011 { 6625, 5500, },
3012 { 6750, 5625, },
3013 { 6875, 5750, },
3014 { 7000, 5875, },
3015 { 7125, 6000, },
3016 { 7250, 6125, },
3017 { 7375, 6250, },
3018 { 7500, 6375, },
3019 { 7625, 6500, },
3020 { 7750, 6625, },
3021 { 7875, 6750, },
3022 { 8000, 6875, },
3023 { 8125, 7000, },
3024 { 8250, 7125, },
3025 { 8375, 7250, },
3026 { 8500, 7375, },
3027 { 8625, 7500, },
3028 { 8750, 7625, },
3029 { 8875, 7750, },
3030 { 9000, 7875, },
3031 { 9125, 8000, },
3032 { 9250, 8125, },
3033 { 9375, 8250, },
3034 { 9500, 8375, },
3035 { 9625, 8500, },
3036 { 9750, 8625, },
3037 { 9875, 8750, },
3038 { 10000, 8875, },
3039 { 10125, 9000, },
3040 { 10250, 9125, },
3041 { 10375, 9250, },
3042 { 10500, 9375, },
3043 { 10625, 9500, },
3044 { 10750, 9625, },
3045 { 10875, 9750, },
3046 { 11000, 9875, },
3047 { 11125, 10000, },
3048 { 11250, 10125, },
3049 { 11375, 10250, },
3050 { 11500, 10375, },
3051 { 11625, 10500, },
3052 { 11750, 10625, },
3053 { 11875, 10750, },
3054 { 12000, 10875, },
3055 { 12125, 11000, },
3056 { 12250, 11125, },
3057 { 12375, 11250, },
3058 { 12500, 11375, },
3059 { 12625, 11500, },
3060 { 12750, 11625, },
3061 { 12875, 11750, },
3062 { 13000, 11875, },
3063 { 13125, 12000, },
3064 { 13250, 12125, },
3065 { 13375, 12250, },
3066 { 13500, 12375, },
3067 { 13625, 12500, },
3068 { 13750, 12625, },
3069 { 13875, 12750, },
3070 { 14000, 12875, },
3071 { 14125, 13000, },
3072 { 14250, 13125, },
3073 { 14375, 13250, },
3074 { 14500, 13375, },
3075 { 14625, 13500, },
3076 { 14750, 13625, },
3077 { 14875, 13750, },
3078 { 15000, 13875, },
3079 { 15125, 14000, },
3080 { 15250, 14125, },
3081 { 15375, 14250, },
3082 { 15500, 14375, },
3083 { 15625, 14500, },
3084 { 15750, 14625, },
3085 { 15875, 14750, },
3086 { 16000, 14875, },
3087 { 16125, 15000, },
3088 };
3089 if (dev_priv->info->is_mobile)
3090 return v_table[pxvid].vm;
3091 else
3092 return v_table[pxvid].vd;
3093 }
3094
__i915_update_gfx_val(struct drm_i915_private * dev_priv)3095 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3096 {
3097 struct timespec now, diff1;
3098 u64 diff;
3099 unsigned long diffms;
3100 u32 count;
3101
3102 mtx_assert(&mchdev_lock, MA_OWNED);
3103
3104 nanotime(&now);
3105 timespecsub(&now, &dev_priv->ips.last_time2, &diff1);
3106
3107 /* Don't divide by 0 */
3108 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3109 if (!diffms)
3110 return;
3111
3112 count = I915_READ(GFXEC);
3113
3114 if (count < dev_priv->ips.last_count2) {
3115 diff = ~0UL - dev_priv->ips.last_count2;
3116 diff += count;
3117 } else {
3118 diff = count - dev_priv->ips.last_count2;
3119 }
3120
3121 dev_priv->ips.last_count2 = count;
3122 dev_priv->ips.last_time2 = now;
3123
3124 /* More magic constants... */
3125 diff = diff * 1181;
3126 diff = div_u64(diff, diffms * 10);
3127 dev_priv->ips.gfx_power = diff;
3128 }
3129
i915_update_gfx_val(struct drm_i915_private * dev_priv)3130 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3131 {
3132 if (dev_priv->info->gen != 5)
3133 return;
3134
3135 mtx_lock(&mchdev_lock);
3136
3137 __i915_update_gfx_val(dev_priv);
3138
3139 mtx_unlock(&mchdev_lock);
3140 }
3141
__i915_gfx_val(struct drm_i915_private * dev_priv)3142 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3143 {
3144 unsigned long t, corr, state1, corr2, state2;
3145 u32 pxvid, ext_v;
3146
3147 mtx_assert(&mchdev_lock, MA_OWNED);
3148
3149 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3150 pxvid = (pxvid >> 24) & 0x7f;
3151 ext_v = pvid_to_extvid(dev_priv, pxvid);
3152
3153 state1 = ext_v;
3154
3155 t = i915_mch_val(dev_priv);
3156
3157 /* Revel in the empirically derived constants */
3158
3159 /* Correction factor in 1/100000 units */
3160 if (t > 80)
3161 corr = ((t * 2349) + 135940);
3162 else if (t >= 50)
3163 corr = ((t * 964) + 29317);
3164 else /* < 50 */
3165 corr = ((t * 301) + 1004);
3166
3167 corr = corr * ((150142 * state1) / 10000 - 78642);
3168 corr /= 100000;
3169 corr2 = (corr * dev_priv->ips.corr);
3170
3171 state2 = (corr2 * state1) / 10000;
3172 state2 /= 100; /* convert to mW */
3173
3174 __i915_update_gfx_val(dev_priv);
3175
3176 return dev_priv->ips.gfx_power + state2;
3177 }
3178
i915_gfx_val(struct drm_i915_private * dev_priv)3179 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3180 {
3181 unsigned long val;
3182
3183 if (dev_priv->info->gen != 5)
3184 return 0;
3185
3186 mtx_lock(&mchdev_lock);
3187
3188 val = __i915_gfx_val(dev_priv);
3189
3190 mtx_unlock(&mchdev_lock);
3191
3192 return val;
3193 }
3194
3195 /**
3196 * i915_read_mch_val - return value for IPS use
3197 *
3198 * Calculate and return a value for the IPS driver to use when deciding whether
3199 * we have thermal and power headroom to increase CPU or GPU power budget.
3200 */
i915_read_mch_val(void)3201 unsigned long i915_read_mch_val(void)
3202 {
3203 struct drm_i915_private *dev_priv;
3204 unsigned long chipset_val, graphics_val, ret = 0;
3205
3206 mtx_lock(&mchdev_lock);
3207 if (!i915_mch_dev)
3208 goto out_unlock;
3209 dev_priv = i915_mch_dev;
3210
3211 chipset_val = __i915_chipset_val(dev_priv);
3212 graphics_val = __i915_gfx_val(dev_priv);
3213
3214 ret = chipset_val + graphics_val;
3215
3216 out_unlock:
3217 mtx_unlock(&mchdev_lock);
3218
3219 return ret;
3220 }
3221 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3222
3223 /**
3224 * i915_gpu_raise - raise GPU frequency limit
3225 *
3226 * Raise the limit; IPS indicates we have thermal headroom.
3227 */
i915_gpu_raise(void)3228 bool i915_gpu_raise(void)
3229 {
3230 struct drm_i915_private *dev_priv;
3231 bool ret = true;
3232
3233 mtx_lock(&mchdev_lock);
3234 if (!i915_mch_dev) {
3235 ret = false;
3236 goto out_unlock;
3237 }
3238 dev_priv = i915_mch_dev;
3239
3240 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3241 dev_priv->ips.max_delay--;
3242
3243 out_unlock:
3244 mtx_unlock(&mchdev_lock);
3245
3246 return ret;
3247 }
3248 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3249
3250 /**
3251 * i915_gpu_lower - lower GPU frequency limit
3252 *
3253 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3254 * frequency maximum.
3255 */
i915_gpu_lower(void)3256 bool i915_gpu_lower(void)
3257 {
3258 struct drm_i915_private *dev_priv;
3259 bool ret = true;
3260
3261 mtx_lock(&mchdev_lock);
3262 if (!i915_mch_dev) {
3263 ret = false;
3264 goto out_unlock;
3265 }
3266 dev_priv = i915_mch_dev;
3267
3268 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3269 dev_priv->ips.max_delay++;
3270
3271 out_unlock:
3272 mtx_unlock(&mchdev_lock);
3273
3274 return ret;
3275 }
3276 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3277
3278 /**
3279 * i915_gpu_busy - indicate GPU business to IPS
3280 *
3281 * Tell the IPS driver whether or not the GPU is busy.
3282 */
i915_gpu_busy(void)3283 bool i915_gpu_busy(void)
3284 {
3285 struct drm_i915_private *dev_priv;
3286 struct intel_ring_buffer *ring;
3287 bool ret = false;
3288 int i;
3289
3290 mtx_lock(&mchdev_lock);
3291 if (!i915_mch_dev)
3292 goto out_unlock;
3293 dev_priv = i915_mch_dev;
3294
3295 for_each_ring(ring, dev_priv, i)
3296 ret |= !list_empty(&ring->request_list);
3297
3298 out_unlock:
3299 mtx_unlock(&mchdev_lock);
3300
3301 return ret;
3302 }
3303 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3304
3305 /**
3306 * i915_gpu_turbo_disable - disable graphics turbo
3307 *
3308 * Disable graphics turbo by resetting the max frequency and setting the
3309 * current frequency to the default.
3310 */
i915_gpu_turbo_disable(void)3311 bool i915_gpu_turbo_disable(void)
3312 {
3313 struct drm_i915_private *dev_priv;
3314 bool ret = true;
3315
3316 mtx_lock(&mchdev_lock);
3317 if (!i915_mch_dev) {
3318 ret = false;
3319 goto out_unlock;
3320 }
3321 dev_priv = i915_mch_dev;
3322
3323 dev_priv->ips.max_delay = dev_priv->ips.fstart;
3324
3325 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3326 ret = false;
3327
3328 out_unlock:
3329 mtx_unlock(&mchdev_lock);
3330
3331 return ret;
3332 }
3333 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3334
3335 #ifdef FREEBSD_WIP
3336 /**
3337 * Tells the intel_ips driver that the i915 driver is now loaded, if
3338 * IPS got loaded first.
3339 *
3340 * This awkward dance is so that neither module has to depend on the
3341 * other in order for IPS to do the appropriate communication of
3342 * GPU turbo limits to i915.
3343 */
3344 static void
ips_ping_for_i915_load(void)3345 ips_ping_for_i915_load(void)
3346 {
3347 void (*link)(void);
3348
3349 link = symbol_get(ips_link_to_i915_driver);
3350 if (link) {
3351 link();
3352 symbol_put(ips_link_to_i915_driver);
3353 }
3354 }
3355 #endif /* FREEBSD_WIP */
3356
intel_gpu_ips_init(struct drm_i915_private * dev_priv)3357 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3358 {
3359 /* We only register the i915 ips part with intel-ips once everything is
3360 * set up, to avoid intel-ips sneaking in and reading bogus values. */
3361 mtx_lock(&mchdev_lock);
3362 i915_mch_dev = dev_priv;
3363 mtx_unlock(&mchdev_lock);
3364
3365 #ifdef FREEBSD_WIP
3366 ips_ping_for_i915_load();
3367 #endif /* FREEBSD_WIP */
3368 }
3369
intel_gpu_ips_teardown(void)3370 void intel_gpu_ips_teardown(void)
3371 {
3372 mtx_lock(&mchdev_lock);
3373 i915_mch_dev = NULL;
3374 mtx_unlock(&mchdev_lock);
3375 }
intel_init_emon(struct drm_device * dev)3376 static void intel_init_emon(struct drm_device *dev)
3377 {
3378 struct drm_i915_private *dev_priv = dev->dev_private;
3379 u32 lcfuse;
3380 u8 pxw[16];
3381 int i;
3382
3383 /* Disable to program */
3384 I915_WRITE(ECR, 0);
3385 POSTING_READ(ECR);
3386
3387 /* Program energy weights for various events */
3388 I915_WRITE(SDEW, 0x15040d00);
3389 I915_WRITE(CSIEW0, 0x007f0000);
3390 I915_WRITE(CSIEW1, 0x1e220004);
3391 I915_WRITE(CSIEW2, 0x04000004);
3392
3393 for (i = 0; i < 5; i++)
3394 I915_WRITE(PEW + (i * 4), 0);
3395 for (i = 0; i < 3; i++)
3396 I915_WRITE(DEW + (i * 4), 0);
3397
3398 /* Program P-state weights to account for frequency power adjustment */
3399 for (i = 0; i < 16; i++) {
3400 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3401 unsigned long freq = intel_pxfreq(pxvidfreq);
3402 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3403 PXVFREQ_PX_SHIFT;
3404 unsigned long val;
3405
3406 val = vid * vid;
3407 val *= (freq / 1000);
3408 val *= 255;
3409 val /= (127*127*900);
3410 if (val > 0xff)
3411 DRM_ERROR("bad pxval: %ld\n", val);
3412 pxw[i] = val;
3413 }
3414 /* Render standby states get 0 weight */
3415 pxw[14] = 0;
3416 pxw[15] = 0;
3417
3418 for (i = 0; i < 4; i++) {
3419 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3420 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3421 I915_WRITE(PXW + (i * 4), val);
3422 }
3423
3424 /* Adjust magic regs to magic values (more experimental results) */
3425 I915_WRITE(OGW0, 0);
3426 I915_WRITE(OGW1, 0);
3427 I915_WRITE(EG0, 0x00007f00);
3428 I915_WRITE(EG1, 0x0000000e);
3429 I915_WRITE(EG2, 0x000e0000);
3430 I915_WRITE(EG3, 0x68000300);
3431 I915_WRITE(EG4, 0x42000000);
3432 I915_WRITE(EG5, 0x00140031);
3433 I915_WRITE(EG6, 0);
3434 I915_WRITE(EG7, 0);
3435
3436 for (i = 0; i < 8; i++)
3437 I915_WRITE(PXWL + (i * 4), 0);
3438
3439 /* Enable PMON + select events */
3440 I915_WRITE(ECR, 0x80000019);
3441
3442 lcfuse = I915_READ(LCFUSE02);
3443
3444 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3445 }
3446
intel_disable_gt_powersave(struct drm_device * dev)3447 void intel_disable_gt_powersave(struct drm_device *dev)
3448 {
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450
3451 if (IS_IRONLAKE_M(dev)) {
3452 ironlake_disable_drps(dev);
3453 ironlake_disable_rc6(dev);
3454 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
3455 taskqueue_cancel_timeout(dev_priv->wq, &dev_priv->rps.delayed_resume_work, NULL);
3456 sx_xlock(&dev_priv->rps.hw_lock);
3457 gen6_disable_rps(dev);
3458 sx_xunlock(&dev_priv->rps.hw_lock);
3459 }
3460 }
3461
intel_gen6_powersave_work(void * arg,int pending)3462 static void intel_gen6_powersave_work(void *arg, int pending)
3463 {
3464 struct drm_i915_private *dev_priv = arg;
3465 struct drm_device *dev = dev_priv->dev;
3466
3467 sx_xlock(&dev_priv->rps.hw_lock);
3468 gen6_enable_rps(dev);
3469 gen6_update_ring_freq(dev);
3470 sx_xunlock(&dev_priv->rps.hw_lock);
3471 }
3472
intel_enable_gt_powersave(struct drm_device * dev)3473 void intel_enable_gt_powersave(struct drm_device *dev)
3474 {
3475 struct drm_i915_private *dev_priv = dev->dev_private;
3476
3477 if (IS_IRONLAKE_M(dev)) {
3478 ironlake_enable_drps(dev);
3479 ironlake_enable_rc6(dev);
3480 intel_init_emon(dev);
3481 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
3482 /*
3483 * PCU communication is slow and this doesn't need to be
3484 * done at any specific time, so do this out of our fast path
3485 * to make resume and init faster.
3486 */
3487 taskqueue_enqueue_timeout(dev_priv->wq, &dev_priv->rps.delayed_resume_work,
3488 round_jiffies_up_relative(HZ));
3489 }
3490 }
3491
ibx_init_clock_gating(struct drm_device * dev)3492 static void ibx_init_clock_gating(struct drm_device *dev)
3493 {
3494 struct drm_i915_private *dev_priv = dev->dev_private;
3495
3496 /*
3497 * On Ibex Peak and Cougar Point, we need to disable clock
3498 * gating for the panel power sequencer or it will fail to
3499 * start up when no ports are active.
3500 */
3501 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3502 }
3503
ironlake_init_clock_gating(struct drm_device * dev)3504 static void ironlake_init_clock_gating(struct drm_device *dev)
3505 {
3506 struct drm_i915_private *dev_priv = dev->dev_private;
3507 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3508
3509 /* Required for FBC */
3510 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3511 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3512 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3513
3514 I915_WRITE(PCH_3DCGDIS0,
3515 MARIUNIT_CLOCK_GATE_DISABLE |
3516 SVSMUNIT_CLOCK_GATE_DISABLE);
3517 I915_WRITE(PCH_3DCGDIS1,
3518 VFMUNIT_CLOCK_GATE_DISABLE);
3519
3520 /*
3521 * According to the spec the following bits should be set in
3522 * order to enable memory self-refresh
3523 * The bit 22/21 of 0x42004
3524 * The bit 5 of 0x42020
3525 * The bit 15 of 0x45000
3526 */
3527 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3528 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3529 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3530 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3531 I915_WRITE(DISP_ARB_CTL,
3532 (I915_READ(DISP_ARB_CTL) |
3533 DISP_FBC_WM_DIS));
3534 I915_WRITE(WM3_LP_ILK, 0);
3535 I915_WRITE(WM2_LP_ILK, 0);
3536 I915_WRITE(WM1_LP_ILK, 0);
3537
3538 /*
3539 * Based on the document from hardware guys the following bits
3540 * should be set unconditionally in order to enable FBC.
3541 * The bit 22 of 0x42000
3542 * The bit 22 of 0x42004
3543 * The bit 7,8,9 of 0x42020.
3544 */
3545 if (IS_IRONLAKE_M(dev)) {
3546 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3547 I915_READ(ILK_DISPLAY_CHICKEN1) |
3548 ILK_FBCQ_DIS);
3549 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3550 I915_READ(ILK_DISPLAY_CHICKEN2) |
3551 ILK_DPARB_GATE);
3552 }
3553
3554 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3555
3556 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3557 I915_READ(ILK_DISPLAY_CHICKEN2) |
3558 ILK_ELPIN_409_SELECT);
3559 I915_WRITE(_3D_CHICKEN2,
3560 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3561 _3D_CHICKEN2_WM_READ_PIPELINED);
3562
3563 /* WaDisableRenderCachePipelinedFlush */
3564 I915_WRITE(CACHE_MODE_0,
3565 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3566
3567 ibx_init_clock_gating(dev);
3568 }
3569
cpt_init_clock_gating(struct drm_device * dev)3570 static void cpt_init_clock_gating(struct drm_device *dev)
3571 {
3572 struct drm_i915_private *dev_priv = dev->dev_private;
3573 int pipe;
3574 uint32_t val;
3575
3576 /*
3577 * On Ibex Peak and Cougar Point, we need to disable clock
3578 * gating for the panel power sequencer or it will fail to
3579 * start up when no ports are active.
3580 */
3581 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3582 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3583 DPLS_EDP_PPS_FIX_DIS);
3584 /* The below fixes the weird display corruption, a few pixels shifted
3585 * downward, on (only) LVDS of some HP laptops with IVY.
3586 */
3587 for_each_pipe(pipe) {
3588 val = TRANS_CHICKEN2_TIMING_OVERRIDE;
3589 if (dev_priv->fdi_rx_polarity_inverted)
3590 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3591 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3592 }
3593 /* WADP0ClockGatingDisable */
3594 for_each_pipe(pipe) {
3595 I915_WRITE(TRANS_CHICKEN1(pipe),
3596 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3597 }
3598 }
3599
gen6_init_clock_gating(struct drm_device * dev)3600 static void gen6_init_clock_gating(struct drm_device *dev)
3601 {
3602 struct drm_i915_private *dev_priv = dev->dev_private;
3603 int pipe;
3604 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3605
3606 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3607
3608 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3609 I915_READ(ILK_DISPLAY_CHICKEN2) |
3610 ILK_ELPIN_409_SELECT);
3611
3612 /* WaDisableHiZPlanesWhenMSAAEnabled */
3613 I915_WRITE(_3D_CHICKEN,
3614 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3615
3616 /* WaSetupGtModeTdRowDispatch */
3617 if (IS_SNB_GT1(dev))
3618 I915_WRITE(GEN6_GT_MODE,
3619 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3620
3621 I915_WRITE(WM3_LP_ILK, 0);
3622 I915_WRITE(WM2_LP_ILK, 0);
3623 I915_WRITE(WM1_LP_ILK, 0);
3624
3625 I915_WRITE(CACHE_MODE_0,
3626 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3627
3628 I915_WRITE(GEN6_UCGCTL1,
3629 I915_READ(GEN6_UCGCTL1) |
3630 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3631 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3632
3633 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3634 * gating disable must be set. Failure to set it results in
3635 * flickering pixels due to Z write ordering failures after
3636 * some amount of runtime in the Mesa "fire" demo, and Unigine
3637 * Sanctuary and Tropics, and apparently anything else with
3638 * alpha test or pixel discard.
3639 *
3640 * According to the spec, bit 11 (RCCUNIT) must also be set,
3641 * but we didn't debug actual testcases to find it out.
3642 *
3643 * Also apply WaDisableVDSUnitClockGating and
3644 * WaDisableRCPBUnitClockGating.
3645 */
3646 I915_WRITE(GEN6_UCGCTL2,
3647 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3648 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3649 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3650
3651 /* Bspec says we need to always set all mask bits. */
3652 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3653 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3654
3655 /*
3656 * According to the spec the following bits should be
3657 * set in order to enable memory self-refresh and fbc:
3658 * The bit21 and bit22 of 0x42000
3659 * The bit21 and bit22 of 0x42004
3660 * The bit5 and bit7 of 0x42020
3661 * The bit14 of 0x70180
3662 * The bit14 of 0x71180
3663 */
3664 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3665 I915_READ(ILK_DISPLAY_CHICKEN1) |
3666 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3667 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3668 I915_READ(ILK_DISPLAY_CHICKEN2) |
3669 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3670 I915_WRITE(ILK_DSPCLK_GATE_D,
3671 I915_READ(ILK_DSPCLK_GATE_D) |
3672 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
3673 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
3674
3675
3676 #ifdef FREEBSD_WIP
3677 /* NOTE Linux<->FreeBSD: Disable GEN6_MBCTL write.
3678 *
3679 * This arrived in Linux 3.6 in commit
3680 * b4ae3f22d238617ca11610b29fde16cf8c0bc6e0 and causes significantly
3681 * increased power consumption after kldloading i915kms.ko on FreeBSD
3682 * on (some) Sandy Bridge laptops. A Thinkpad X220 reported about 11W
3683 * after booting while idle at the vt(4) console and about double that
3684 * after loading the driver.
3685 *
3686 * There were reports in Linux of increased consumption after a suspend
3687 * and resume cycle due to that change.
3688 *
3689 * Linux bug reports:
3690 * https://bugs.freedesktop.org/show_bug.cgi?id=54089
3691 * https://bugzilla.kernel.org/show_bug.cgi?id=58971
3692 *
3693 * This suspend and resume issue is reportedly fixed in Linux with
3694 * commits 7dcd2677ea912573d9ed4bcd629b0023b2d11505 and
3695 * 7dcd2677ea912573d9ed4bcd629b0023b2d11505 (Linux 3.11). However, I
3696 * found that those changes did not help on FreeBSD, where increased
3697 * power consumption is observed after loading i915kms.ko without
3698 * suspending and resuming.
3699 *
3700 * This workaround should be removed after updating to a future Linux
3701 * i915 version and verifying normal power consumption on Sandy Bridge.
3702 */
3703
3704 /* WaMbcDriverBootEnable */
3705 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3706 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3707 #endif /* FREEBSD_WIP */
3708
3709 for_each_pipe(pipe) {
3710 I915_WRITE(DSPCNTR(pipe),
3711 I915_READ(DSPCNTR(pipe)) |
3712 DISPPLANE_TRICKLE_FEED_DISABLE);
3713 intel_flush_display_plane(dev_priv, pipe);
3714 }
3715
3716 /* The default value should be 0x200 according to docs, but the two
3717 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3718 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3719 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3720
3721 cpt_init_clock_gating(dev);
3722 }
3723
gen7_setup_fixed_func_scheduler(struct drm_i915_private * dev_priv)3724 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3725 {
3726 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3727
3728 reg &= ~GEN7_FF_SCHED_MASK;
3729 reg |= GEN7_FF_TS_SCHED_HW;
3730 reg |= GEN7_FF_VS_SCHED_HW;
3731 reg |= GEN7_FF_DS_SCHED_HW;
3732
3733 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3734 }
3735
lpt_init_clock_gating(struct drm_device * dev)3736 static void lpt_init_clock_gating(struct drm_device *dev)
3737 {
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739
3740 /*
3741 * TODO: this bit should only be enabled when really needed, then
3742 * disabled when not needed anymore in order to save power.
3743 */
3744 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3745 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3746 I915_READ(SOUTH_DSPCLK_GATE_D) |
3747 PCH_LP_PARTITION_LEVEL_DISABLE);
3748 }
3749
haswell_init_clock_gating(struct drm_device * dev)3750 static void haswell_init_clock_gating(struct drm_device *dev)
3751 {
3752 struct drm_i915_private *dev_priv = dev->dev_private;
3753 int pipe;
3754
3755 I915_WRITE(WM3_LP_ILK, 0);
3756 I915_WRITE(WM2_LP_ILK, 0);
3757 I915_WRITE(WM1_LP_ILK, 0);
3758
3759 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3760 * This implements the WaDisableRCZUnitClockGating workaround.
3761 */
3762 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3763
3764 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3765 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3766 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3767
3768 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3769 I915_WRITE(GEN7_L3CNTLREG1,
3770 GEN7_WA_FOR_GEN7_L3_CONTROL);
3771 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3772 GEN7_WA_L3_CHICKEN_MODE);
3773
3774 /* This is required by WaCatErrorRejectionIssue */
3775 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3776 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3777 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3778
3779 for_each_pipe(pipe) {
3780 I915_WRITE(DSPCNTR(pipe),
3781 I915_READ(DSPCNTR(pipe)) |
3782 DISPPLANE_TRICKLE_FEED_DISABLE);
3783 intel_flush_display_plane(dev_priv, pipe);
3784 }
3785
3786 gen7_setup_fixed_func_scheduler(dev_priv);
3787
3788 /* WaDisable4x2SubspanOptimization */
3789 I915_WRITE(CACHE_MODE_1,
3790 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3791
3792 /* WaMbcDriverBootEnable */
3793 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3794 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3795
3796 /* XXX: This is a workaround for early silicon revisions and should be
3797 * removed later.
3798 */
3799 I915_WRITE(WM_DBG,
3800 I915_READ(WM_DBG) |
3801 WM_DBG_DISALLOW_MULTIPLE_LP |
3802 WM_DBG_DISALLOW_SPRITE |
3803 WM_DBG_DISALLOW_MAXFIFO);
3804
3805 lpt_init_clock_gating(dev);
3806 }
3807
ivybridge_init_clock_gating(struct drm_device * dev)3808 static void ivybridge_init_clock_gating(struct drm_device *dev)
3809 {
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 int pipe;
3812 uint32_t snpcr;
3813
3814 I915_WRITE(WM3_LP_ILK, 0);
3815 I915_WRITE(WM2_LP_ILK, 0);
3816 I915_WRITE(WM1_LP_ILK, 0);
3817
3818 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3819
3820 /* WaDisableEarlyCull */
3821 I915_WRITE(_3D_CHICKEN3,
3822 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3823
3824 /* WaDisableBackToBackFlipFix */
3825 I915_WRITE(IVB_CHICKEN3,
3826 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3827 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3828
3829 /* WaDisablePSDDualDispatchEnable */
3830 if (IS_IVB_GT1(dev))
3831 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3832 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3833 else
3834 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3835 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3836
3837 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3838 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3839 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3840
3841 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3842 I915_WRITE(GEN7_L3CNTLREG1,
3843 GEN7_WA_FOR_GEN7_L3_CONTROL);
3844 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3845 GEN7_WA_L3_CHICKEN_MODE);
3846 if (IS_IVB_GT1(dev))
3847 I915_WRITE(GEN7_ROW_CHICKEN2,
3848 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3849 else
3850 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3851 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3852
3853
3854 /* WaForceL3Serialization */
3855 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3856 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3857
3858 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3859 * gating disable must be set. Failure to set it results in
3860 * flickering pixels due to Z write ordering failures after
3861 * some amount of runtime in the Mesa "fire" demo, and Unigine
3862 * Sanctuary and Tropics, and apparently anything else with
3863 * alpha test or pixel discard.
3864 *
3865 * According to the spec, bit 11 (RCCUNIT) must also be set,
3866 * but we didn't debug actual testcases to find it out.
3867 *
3868 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3869 * This implements the WaDisableRCZUnitClockGating workaround.
3870 */
3871 I915_WRITE(GEN6_UCGCTL2,
3872 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3873 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3874
3875 /* This is required by WaCatErrorRejectionIssue */
3876 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3877 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3878 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3879
3880 for_each_pipe(pipe) {
3881 I915_WRITE(DSPCNTR(pipe),
3882 I915_READ(DSPCNTR(pipe)) |
3883 DISPPLANE_TRICKLE_FEED_DISABLE);
3884 intel_flush_display_plane(dev_priv, pipe);
3885 }
3886
3887 /* WaMbcDriverBootEnable */
3888 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3889 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3890
3891 gen7_setup_fixed_func_scheduler(dev_priv);
3892
3893 /* WaDisable4x2SubspanOptimization */
3894 I915_WRITE(CACHE_MODE_1,
3895 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3896
3897 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3898 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3899 snpcr |= GEN6_MBC_SNPCR_MED;
3900 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3901
3902 cpt_init_clock_gating(dev);
3903 }
3904
valleyview_init_clock_gating(struct drm_device * dev)3905 static void valleyview_init_clock_gating(struct drm_device *dev)
3906 {
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 int pipe;
3909
3910 I915_WRITE(WM3_LP_ILK, 0);
3911 I915_WRITE(WM2_LP_ILK, 0);
3912 I915_WRITE(WM1_LP_ILK, 0);
3913
3914 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
3915
3916 /* WaDisableEarlyCull */
3917 I915_WRITE(_3D_CHICKEN3,
3918 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3919
3920 /* WaDisableBackToBackFlipFix */
3921 I915_WRITE(IVB_CHICKEN3,
3922 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3923 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3924
3925 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3926 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3927
3928 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3929 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3930 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3931
3932 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3933 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
3934 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3935
3936 /* WaForceL3Serialization */
3937 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3938 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3939
3940 /* WaDisableDopClockGating */
3941 I915_WRITE(GEN7_ROW_CHICKEN2,
3942 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3943
3944 /* WaForceL3Serialization */
3945 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3946 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3947
3948 /* This is required by WaCatErrorRejectionIssue */
3949 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3950 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3951 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3952
3953 /* WaMbcDriverBootEnable */
3954 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3955 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3956
3957
3958 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3959 * gating disable must be set. Failure to set it results in
3960 * flickering pixels due to Z write ordering failures after
3961 * some amount of runtime in the Mesa "fire" demo, and Unigine
3962 * Sanctuary and Tropics, and apparently anything else with
3963 * alpha test or pixel discard.
3964 *
3965 * According to the spec, bit 11 (RCCUNIT) must also be set,
3966 * but we didn't debug actual testcases to find it out.
3967 *
3968 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3969 * This implements the WaDisableRCZUnitClockGating workaround.
3970 *
3971 * Also apply WaDisableVDSUnitClockGating and
3972 * WaDisableRCPBUnitClockGating.
3973 */
3974 I915_WRITE(GEN6_UCGCTL2,
3975 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3976 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
3977 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3978 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3979 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3980
3981 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3982
3983 for_each_pipe(pipe) {
3984 I915_WRITE(DSPCNTR(pipe),
3985 I915_READ(DSPCNTR(pipe)) |
3986 DISPPLANE_TRICKLE_FEED_DISABLE);
3987 intel_flush_display_plane(dev_priv, pipe);
3988 }
3989
3990 I915_WRITE(CACHE_MODE_1,
3991 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3992
3993 /*
3994 * On ValleyView, the GUnit needs to signal the GT
3995 * when flip and other events complete. So enable
3996 * all the GUnit->GT interrupts here
3997 */
3998 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3999 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
4000 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
4001 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
4002 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
4003 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
4004 PLANEA_FLIPDONE_INT_EN);
4005
4006 /*
4007 * WaDisableVLVClockGating_VBIIssue
4008 * Disable clock gating on th GCFG unit to prevent a delay
4009 * in the reporting of vblank events.
4010 */
4011 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
4012 }
4013
g4x_init_clock_gating(struct drm_device * dev)4014 static void g4x_init_clock_gating(struct drm_device *dev)
4015 {
4016 struct drm_i915_private *dev_priv = dev->dev_private;
4017 uint32_t dspclk_gate;
4018
4019 I915_WRITE(RENCLK_GATE_D1, 0);
4020 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4021 GS_UNIT_CLOCK_GATE_DISABLE |
4022 CL_UNIT_CLOCK_GATE_DISABLE);
4023 I915_WRITE(RAMCLK_GATE_D, 0);
4024 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4025 OVRUNIT_CLOCK_GATE_DISABLE |
4026 OVCUNIT_CLOCK_GATE_DISABLE;
4027 if (IS_GM45(dev))
4028 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4029 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4030
4031 /* WaDisableRenderCachePipelinedFlush */
4032 I915_WRITE(CACHE_MODE_0,
4033 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4034 }
4035
crestline_init_clock_gating(struct drm_device * dev)4036 static void crestline_init_clock_gating(struct drm_device *dev)
4037 {
4038 struct drm_i915_private *dev_priv = dev->dev_private;
4039
4040 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4041 I915_WRITE(RENCLK_GATE_D2, 0);
4042 I915_WRITE(DSPCLK_GATE_D, 0);
4043 I915_WRITE(RAMCLK_GATE_D, 0);
4044 I915_WRITE16(DEUC, 0);
4045 }
4046
broadwater_init_clock_gating(struct drm_device * dev)4047 static void broadwater_init_clock_gating(struct drm_device *dev)
4048 {
4049 struct drm_i915_private *dev_priv = dev->dev_private;
4050
4051 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4052 I965_RCC_CLOCK_GATE_DISABLE |
4053 I965_RCPB_CLOCK_GATE_DISABLE |
4054 I965_ISC_CLOCK_GATE_DISABLE |
4055 I965_FBC_CLOCK_GATE_DISABLE);
4056 I915_WRITE(RENCLK_GATE_D2, 0);
4057 }
4058
gen3_init_clock_gating(struct drm_device * dev)4059 static void gen3_init_clock_gating(struct drm_device *dev)
4060 {
4061 struct drm_i915_private *dev_priv = dev->dev_private;
4062 u32 dstate = I915_READ(D_STATE);
4063
4064 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4065 DSTATE_DOT_CLOCK_GATING;
4066 I915_WRITE(D_STATE, dstate);
4067
4068 if (IS_PINEVIEW(dev))
4069 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4070
4071 /* IIR "flip pending" means done if this bit is set */
4072 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4073 }
4074
i85x_init_clock_gating(struct drm_device * dev)4075 static void i85x_init_clock_gating(struct drm_device *dev)
4076 {
4077 struct drm_i915_private *dev_priv = dev->dev_private;
4078
4079 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4080 }
4081
i830_init_clock_gating(struct drm_device * dev)4082 static void i830_init_clock_gating(struct drm_device *dev)
4083 {
4084 struct drm_i915_private *dev_priv = dev->dev_private;
4085
4086 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4087 }
4088
intel_init_clock_gating(struct drm_device * dev)4089 void intel_init_clock_gating(struct drm_device *dev)
4090 {
4091 struct drm_i915_private *dev_priv = dev->dev_private;
4092
4093 dev_priv->display.init_clock_gating(dev);
4094 }
4095
4096 /* Starting with Haswell, we have different power wells for
4097 * different parts of the GPU. This attempts to enable them all.
4098 */
intel_init_power_wells(struct drm_device * dev)4099 void intel_init_power_wells(struct drm_device *dev)
4100 {
4101 struct drm_i915_private *dev_priv = dev->dev_private;
4102 unsigned long power_wells[] = {
4103 HSW_PWR_WELL_CTL1,
4104 HSW_PWR_WELL_CTL2,
4105 HSW_PWR_WELL_CTL4
4106 };
4107 int i;
4108
4109 if (!IS_HASWELL(dev))
4110 return;
4111
4112 DRM_LOCK(dev);
4113
4114 for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
4115 int well = I915_READ(power_wells[i]);
4116
4117 if ((well & HSW_PWR_WELL_STATE) == 0) {
4118 I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
4119 if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
4120 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
4121 }
4122 }
4123
4124 DRM_UNLOCK(dev);
4125 }
4126
4127 /* Set up chip specific power management-related functions */
intel_init_pm(struct drm_device * dev)4128 void intel_init_pm(struct drm_device *dev)
4129 {
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131
4132 if (I915_HAS_FBC(dev)) {
4133 if (HAS_PCH_SPLIT(dev)) {
4134 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4135 dev_priv->display.enable_fbc = ironlake_enable_fbc;
4136 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4137 } else if (IS_GM45(dev)) {
4138 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4139 dev_priv->display.enable_fbc = g4x_enable_fbc;
4140 dev_priv->display.disable_fbc = g4x_disable_fbc;
4141 } else if (IS_CRESTLINE(dev)) {
4142 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4143 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4144 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4145 }
4146 /* 855GM needs testing */
4147 }
4148
4149 /* For cxsr */
4150 if (IS_PINEVIEW(dev))
4151 i915_pineview_get_mem_freq(dev);
4152 else if (IS_GEN5(dev))
4153 i915_ironlake_get_mem_freq(dev);
4154
4155 /* For FIFO watermark updates */
4156 if (HAS_PCH_SPLIT(dev)) {
4157 if (IS_GEN5(dev)) {
4158 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4159 dev_priv->display.update_wm = ironlake_update_wm;
4160 else {
4161 DRM_DEBUG_KMS("Failed to get proper latency. "
4162 "Disable CxSR\n");
4163 dev_priv->display.update_wm = NULL;
4164 }
4165 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4166 } else if (IS_GEN6(dev)) {
4167 if (SNB_READ_WM0_LATENCY()) {
4168 dev_priv->display.update_wm = sandybridge_update_wm;
4169 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4170 } else {
4171 DRM_DEBUG_KMS("Failed to read display plane latency. "
4172 "Disable CxSR\n");
4173 dev_priv->display.update_wm = NULL;
4174 }
4175 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4176 } else if (IS_IVYBRIDGE(dev)) {
4177 /* FIXME: detect B0+ stepping and use auto training */
4178 if (SNB_READ_WM0_LATENCY()) {
4179 dev_priv->display.update_wm = ivybridge_update_wm;
4180 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4181 } else {
4182 DRM_DEBUG_KMS("Failed to read display plane latency. "
4183 "Disable CxSR\n");
4184 dev_priv->display.update_wm = NULL;
4185 }
4186 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4187 } else if (IS_HASWELL(dev)) {
4188 if (SNB_READ_WM0_LATENCY()) {
4189 dev_priv->display.update_wm = sandybridge_update_wm;
4190 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4191 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4192 } else {
4193 DRM_DEBUG_KMS("Failed to read display plane latency. "
4194 "Disable CxSR\n");
4195 dev_priv->display.update_wm = NULL;
4196 }
4197 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4198 } else
4199 dev_priv->display.update_wm = NULL;
4200 } else if (IS_VALLEYVIEW(dev)) {
4201 dev_priv->display.update_wm = valleyview_update_wm;
4202 dev_priv->display.init_clock_gating =
4203 valleyview_init_clock_gating;
4204 } else if (IS_PINEVIEW(dev)) {
4205 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4206 dev_priv->is_ddr3,
4207 dev_priv->fsb_freq,
4208 dev_priv->mem_freq)) {
4209 DRM_INFO("failed to find known CxSR latency "
4210 "(found ddr%s fsb freq %d, mem freq %d), "
4211 "disabling CxSR\n",
4212 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4213 dev_priv->fsb_freq, dev_priv->mem_freq);
4214 /* Disable CxSR and never update its watermark again */
4215 pineview_disable_cxsr(dev);
4216 dev_priv->display.update_wm = NULL;
4217 } else
4218 dev_priv->display.update_wm = pineview_update_wm;
4219 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4220 } else if (IS_G4X(dev)) {
4221 dev_priv->display.update_wm = g4x_update_wm;
4222 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4223 } else if (IS_GEN4(dev)) {
4224 dev_priv->display.update_wm = i965_update_wm;
4225 if (IS_CRESTLINE(dev))
4226 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4227 else if (IS_BROADWATER(dev))
4228 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4229 } else if (IS_GEN3(dev)) {
4230 dev_priv->display.update_wm = i9xx_update_wm;
4231 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4232 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4233 } else if (IS_I865G(dev)) {
4234 dev_priv->display.update_wm = i830_update_wm;
4235 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4236 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4237 } else if (IS_I85X(dev)) {
4238 dev_priv->display.update_wm = i9xx_update_wm;
4239 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4240 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4241 } else {
4242 dev_priv->display.update_wm = i830_update_wm;
4243 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4244 if (IS_845G(dev))
4245 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4246 else
4247 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4248 }
4249 }
4250
__gen6_gt_wait_for_thread_c0(struct drm_i915_private * dev_priv)4251 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4252 {
4253 u32 gt_thread_status_mask;
4254
4255 if (IS_HASWELL(dev_priv->dev))
4256 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4257 else
4258 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4259
4260 /* w/a for a sporadic read returning 0 by waiting for the GT
4261 * thread to wake up.
4262 */
4263 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4264 DRM_ERROR("GT thread status wait timed out\n");
4265 }
4266
__gen6_gt_force_wake_reset(struct drm_i915_private * dev_priv)4267 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4268 {
4269 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4270 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4271 }
4272
__gen6_gt_force_wake_get(struct drm_i915_private * dev_priv)4273 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4274 {
4275 u32 forcewake_ack;
4276
4277 if (IS_HASWELL(dev_priv->dev))
4278 forcewake_ack = FORCEWAKE_ACK_HSW;
4279 else
4280 forcewake_ack = FORCEWAKE_ACK;
4281
4282 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4283 FORCEWAKE_ACK_TIMEOUT_MS))
4284 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4285
4286 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
4287 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4288
4289 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4290 FORCEWAKE_ACK_TIMEOUT_MS))
4291 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4292
4293 __gen6_gt_wait_for_thread_c0(dev_priv);
4294 }
4295
__gen6_gt_force_wake_mt_reset(struct drm_i915_private * dev_priv)4296 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4297 {
4298 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4299 /* something from same cacheline, but !FORCEWAKE_MT */
4300 POSTING_READ(ECOBUS);
4301 }
4302
__gen6_gt_force_wake_mt_get(struct drm_i915_private * dev_priv)4303 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4304 {
4305 u32 forcewake_ack;
4306
4307 if (IS_HASWELL(dev_priv->dev))
4308 forcewake_ack = FORCEWAKE_ACK_HSW;
4309 else
4310 forcewake_ack = FORCEWAKE_MT_ACK;
4311
4312 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4313 FORCEWAKE_ACK_TIMEOUT_MS))
4314 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4315
4316 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4317 /* something from same cacheline, but !FORCEWAKE_MT */
4318 POSTING_READ(ECOBUS);
4319
4320 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4321 FORCEWAKE_ACK_TIMEOUT_MS))
4322 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4323
4324 __gen6_gt_wait_for_thread_c0(dev_priv);
4325 }
4326
4327 /*
4328 * Generally this is called implicitly by the register read function. However,
4329 * if some sequence requires the GT to not power down then this function should
4330 * be called at the beginning of the sequence followed by a call to
4331 * gen6_gt_force_wake_put() at the end of the sequence.
4332 */
gen6_gt_force_wake_get(struct drm_i915_private * dev_priv)4333 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4334 {
4335
4336 mtx_lock(&dev_priv->gt_lock);
4337 if (dev_priv->forcewake_count++ == 0)
4338 dev_priv->gt.force_wake_get(dev_priv);
4339 mtx_unlock(&dev_priv->gt_lock);
4340 }
4341
gen6_gt_check_fifodbg(struct drm_i915_private * dev_priv)4342 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4343 {
4344 u32 gtfifodbg;
4345 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4346 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4347 "MMIO read or write has been dropped %x\n", gtfifodbg))
4348 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4349 }
4350
__gen6_gt_force_wake_put(struct drm_i915_private * dev_priv)4351 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4352 {
4353 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4354 /* something from same cacheline, but !FORCEWAKE */
4355 POSTING_READ(ECOBUS);
4356 gen6_gt_check_fifodbg(dev_priv);
4357 }
4358
__gen6_gt_force_wake_mt_put(struct drm_i915_private * dev_priv)4359 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4360 {
4361 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4362 /* something from same cacheline, but !FORCEWAKE_MT */
4363 POSTING_READ(ECOBUS);
4364 gen6_gt_check_fifodbg(dev_priv);
4365 }
4366
4367 /*
4368 * see gen6_gt_force_wake_get()
4369 */
gen6_gt_force_wake_put(struct drm_i915_private * dev_priv)4370 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4371 {
4372
4373 mtx_lock(&dev_priv->gt_lock);
4374 if (--dev_priv->forcewake_count == 0)
4375 dev_priv->gt.force_wake_put(dev_priv);
4376 mtx_unlock(&dev_priv->gt_lock);
4377 }
4378
__gen6_gt_wait_for_fifo(struct drm_i915_private * dev_priv)4379 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4380 {
4381 int ret = 0;
4382
4383 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4384 int loop = 500;
4385 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4386 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4387 udelay(10);
4388 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4389 }
4390 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4391 ++ret;
4392 dev_priv->gt_fifo_count = fifo;
4393 }
4394 dev_priv->gt_fifo_count--;
4395
4396 return ret;
4397 }
4398
vlv_force_wake_reset(struct drm_i915_private * dev_priv)4399 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4400 {
4401 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4402 /* something from same cacheline, but !FORCEWAKE_VLV */
4403 POSTING_READ(FORCEWAKE_ACK_VLV);
4404 }
4405
vlv_force_wake_get(struct drm_i915_private * dev_priv)4406 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4407 {
4408 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4409 FORCEWAKE_ACK_TIMEOUT_MS))
4410 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4411
4412 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4413
4414 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4415 FORCEWAKE_ACK_TIMEOUT_MS))
4416 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4417
4418 __gen6_gt_wait_for_thread_c0(dev_priv);
4419 }
4420
vlv_force_wake_put(struct drm_i915_private * dev_priv)4421 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4422 {
4423 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4424 /* something from same cacheline, but !FORCEWAKE_VLV */
4425 POSTING_READ(FORCEWAKE_ACK_VLV);
4426 gen6_gt_check_fifodbg(dev_priv);
4427 }
4428
intel_gt_reset(struct drm_device * dev)4429 void intel_gt_reset(struct drm_device *dev)
4430 {
4431 struct drm_i915_private *dev_priv = dev->dev_private;
4432
4433 if (IS_VALLEYVIEW(dev)) {
4434 vlv_force_wake_reset(dev_priv);
4435 } else if (INTEL_INFO(dev)->gen >= 6) {
4436 __gen6_gt_force_wake_reset(dev_priv);
4437 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4438 __gen6_gt_force_wake_mt_reset(dev_priv);
4439 }
4440 }
4441
intel_gt_init(struct drm_device * dev)4442 void intel_gt_init(struct drm_device *dev)
4443 {
4444 struct drm_i915_private *dev_priv = dev->dev_private;
4445
4446 mtx_init(&dev_priv->gt_lock, "i915_gt_lock", NULL, MTX_DEF);
4447
4448 intel_gt_reset(dev);
4449
4450 if (IS_VALLEYVIEW(dev)) {
4451 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4452 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4453 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4454 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4455 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4456 } else if (IS_GEN6(dev)) {
4457 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4458 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4459 }
4460 TIMEOUT_TASK_INIT(dev_priv->wq, &dev_priv->rps.delayed_resume_work, 0,
4461 intel_gen6_powersave_work, dev_priv);
4462 }
4463
sandybridge_pcode_read(struct drm_i915_private * dev_priv,u8 mbox,u32 * val)4464 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4465 {
4466 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED);
4467
4468 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4469 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4470 return -EAGAIN;
4471 }
4472
4473 I915_WRITE(GEN6_PCODE_DATA, *val);
4474 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4475
4476 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4477 500)) {
4478 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4479 return -ETIMEDOUT;
4480 }
4481
4482 *val = I915_READ(GEN6_PCODE_DATA);
4483 I915_WRITE(GEN6_PCODE_DATA, 0);
4484
4485 return 0;
4486 }
4487
sandybridge_pcode_write(struct drm_i915_private * dev_priv,u8 mbox,u32 val)4488 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4489 {
4490 sx_assert(&dev_priv->rps.hw_lock, SA_XLOCKED);
4491
4492 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4493 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4494 return -EAGAIN;
4495 }
4496
4497 I915_WRITE(GEN6_PCODE_DATA, val);
4498 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4499
4500 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4501 500)) {
4502 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4503 return -ETIMEDOUT;
4504 }
4505
4506 I915_WRITE(GEN6_PCODE_DATA, 0);
4507
4508 return 0;
4509 }
4510