1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013 Ganbold Tsagaankhuu <[email protected]>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31 /* A10/A20 EMAC driver */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/bus.h>
41 #include <sys/lock.h>
42 #include <sys/mbuf.h>
43 #include <sys/mutex.h>
44 #include <sys/rman.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
48 #include <sys/gpio.h>
49
50 #include <machine/bus.h>
51 #include <machine/resource.h>
52 #include <machine/intr.h>
53
54 #include <net/if.h>
55 #include <net/if_var.h>
56 #include <net/if_arp.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
60 #include <net/if_mib.h>
61 #include <net/ethernet.h>
62 #include <net/if_vlan_var.h>
63
64 #ifdef INET
65 #include <netinet/in.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/in_var.h>
68 #include <netinet/ip.h>
69 #endif
70
71 #include <net/bpf.h>
72 #include <net/bpfdesc.h>
73
74 #include <dev/ofw/ofw_bus.h>
75 #include <dev/ofw/ofw_bus_subr.h>
76
77 #include <dev/mii/mii.h>
78 #include <dev/mii/miivar.h>
79
80 #include <arm/allwinner/if_emacreg.h>
81 #include <arm/allwinner/aw_sid.h>
82
83 #include <dev/extres/clk/clk.h>
84
85 #include "miibus_if.h"
86
87 #include "gpio_if.h"
88
89 #include "a10_sramc.h"
90
91 struct emac_softc {
92 struct ifnet *emac_ifp;
93 device_t emac_dev;
94 device_t emac_miibus;
95 bus_space_handle_t emac_handle;
96 bus_space_tag_t emac_tag;
97 struct resource *emac_res;
98 struct resource *emac_irq;
99 void *emac_intrhand;
100 clk_t emac_clk;
101 int emac_if_flags;
102 struct mtx emac_mtx;
103 struct callout emac_tick_ch;
104 int emac_watchdog_timer;
105 int emac_rx_process_limit;
106 int emac_link;
107 uint32_t emac_fifo_mask;
108 };
109
110 static int emac_probe(device_t);
111 static int emac_attach(device_t);
112 static int emac_detach(device_t);
113 static int emac_shutdown(device_t);
114 static int emac_suspend(device_t);
115 static int emac_resume(device_t);
116
117 static int emac_sys_setup(struct emac_softc *);
118 static void emac_reset(struct emac_softc *);
119
120 static void emac_init_locked(struct emac_softc *);
121 static void emac_start_locked(struct ifnet *);
122 static void emac_init(void *);
123 static void emac_stop_locked(struct emac_softc *);
124 static void emac_intr(void *);
125 static int emac_ioctl(struct ifnet *, u_long, caddr_t);
126
127 static void emac_rxeof(struct emac_softc *, int);
128 static void emac_txeof(struct emac_softc *, uint32_t);
129
130 static int emac_miibus_readreg(device_t, int, int);
131 static int emac_miibus_writereg(device_t, int, int, int);
132 static void emac_miibus_statchg(device_t);
133
134 static int emac_ifmedia_upd(struct ifnet *);
135 static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *);
136
137 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
138 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS);
139
140 #define EMAC_READ_REG(sc, reg) \
141 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg)
142 #define EMAC_WRITE_REG(sc, reg, val) \
143 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val)
144
145 static int
emac_sys_setup(struct emac_softc * sc)146 emac_sys_setup(struct emac_softc *sc)
147 {
148 int error;
149
150 /* Activate EMAC clock. */
151 error = clk_get_by_ofw_index(sc->emac_dev, 0, 0, &sc->emac_clk);
152 if (error != 0) {
153 device_printf(sc->emac_dev, "cannot get clock\n");
154 return (error);
155 }
156 error = clk_enable(sc->emac_clk);
157 if (error != 0) {
158 device_printf(sc->emac_dev, "cannot enable clock\n");
159 return (error);
160 }
161
162 /* Map sram. */
163 a10_map_to_emac();
164
165 return (0);
166 }
167
168 static void
emac_get_hwaddr(struct emac_softc * sc,uint8_t * hwaddr)169 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr)
170 {
171 uint32_t val0, val1, rnd;
172 u_char rootkey[16];
173 size_t rootkey_size;
174
175 /*
176 * Try to get MAC address from running hardware.
177 * If there is something non-zero there just use it.
178 *
179 * Otherwise set the address to a convenient locally assigned address,
180 * using the SID rootkey.
181 * This is was uboot does so we end up with the same mac as if uboot
182 * did set it.
183 * If we can't get the root key, generate a random one,
184 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
185 * assigned bit set, and the broadcast/multicast bit clear.
186 */
187 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0);
188 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1);
189 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) {
190 hwaddr[0] = (val1 >> 16) & 0xff;
191 hwaddr[1] = (val1 >> 8) & 0xff;
192 hwaddr[2] = (val1 >> 0) & 0xff;
193 hwaddr[3] = (val0 >> 16) & 0xff;
194 hwaddr[4] = (val0 >> 8) & 0xff;
195 hwaddr[5] = (val0 >> 0) & 0xff;
196 } else {
197 rootkey_size = sizeof(rootkey);
198 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey,
199 &rootkey_size) == 0) {
200 hwaddr[0] = 0x2;
201 hwaddr[1] = rootkey[3];
202 hwaddr[2] = rootkey[12];
203 hwaddr[3] = rootkey[13];
204 hwaddr[4] = rootkey[14];
205 hwaddr[5] = rootkey[15];
206 }
207 else {
208 rnd = arc4random() & 0x00ffffff;
209 hwaddr[0] = 'b';
210 hwaddr[1] = 's';
211 hwaddr[2] = 'd';
212 hwaddr[3] = (rnd >> 16) & 0xff;
213 hwaddr[4] = (rnd >> 8) & 0xff;
214 hwaddr[5] = (rnd >> 0) & 0xff;
215 }
216 }
217 if (bootverbose)
218 printf("MAC address: %s\n", ether_sprintf(hwaddr));
219 }
220
221 static void
emac_set_rx_mode(struct emac_softc * sc)222 emac_set_rx_mode(struct emac_softc *sc)
223 {
224 struct ifnet *ifp;
225 struct ifmultiaddr *ifma;
226 uint32_t h, hashes[2];
227 uint32_t rcr = 0;
228
229 EMAC_ASSERT_LOCKED(sc);
230
231 ifp = sc->emac_ifp;
232
233 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL);
234
235 /* Unicast packet and DA filtering */
236 rcr |= EMAC_RX_UCAD;
237 rcr |= EMAC_RX_DAF;
238
239 hashes[0] = 0;
240 hashes[1] = 0;
241 if (ifp->if_flags & IFF_ALLMULTI) {
242 hashes[0] = 0xffffffff;
243 hashes[1] = 0xffffffff;
244 } else {
245 if_maddr_rlock(ifp);
246 CK_STAILQ_FOREACH(ifma, &sc->emac_ifp->if_multiaddrs, ifma_link) {
247 if (ifma->ifma_addr->sa_family != AF_LINK)
248 continue;
249 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
250 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
251 hashes[h >> 5] |= 1 << (h & 0x1f);
252 }
253 if_maddr_runlock(ifp);
254 }
255 rcr |= EMAC_RX_MCO;
256 rcr |= EMAC_RX_MHF;
257 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]);
258 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]);
259
260 if (ifp->if_flags & IFF_BROADCAST) {
261 rcr |= EMAC_RX_BCO;
262 rcr |= EMAC_RX_MCO;
263 }
264
265 if (ifp->if_flags & IFF_PROMISC)
266 rcr |= EMAC_RX_PA;
267 else
268 rcr |= EMAC_RX_UCAD;
269
270 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr);
271 }
272
273 static void
emac_reset(struct emac_softc * sc)274 emac_reset(struct emac_softc *sc)
275 {
276
277 EMAC_WRITE_REG(sc, EMAC_CTL, 0);
278 DELAY(200);
279 EMAC_WRITE_REG(sc, EMAC_CTL, 1);
280 DELAY(200);
281 }
282
283 static void
emac_drain_rxfifo(struct emac_softc * sc)284 emac_drain_rxfifo(struct emac_softc *sc)
285 {
286 uint32_t data;
287
288 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0)
289 data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
290 }
291
292 static void
emac_txeof(struct emac_softc * sc,uint32_t status)293 emac_txeof(struct emac_softc *sc, uint32_t status)
294 {
295 struct ifnet *ifp;
296
297 EMAC_ASSERT_LOCKED(sc);
298
299 ifp = sc->emac_ifp;
300 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1);
301 sc->emac_fifo_mask &= ~status;
302 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
303 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2);
304 else
305 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
306 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
307
308 /* Unarm watchdog timer if no TX */
309 sc->emac_watchdog_timer = 0;
310 }
311
312 static void
emac_rxeof(struct emac_softc * sc,int count)313 emac_rxeof(struct emac_softc *sc, int count)
314 {
315 struct ifnet *ifp;
316 struct mbuf *m, *m0;
317 uint32_t reg_val, rxcount;
318 int16_t len;
319 uint16_t status;
320 int i;
321
322 ifp = sc->emac_ifp;
323 for (; count > 0 &&
324 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) {
325 /*
326 * Race warning: The first packet might arrive with
327 * the interrupts disabled, but the second will fix
328 */
329 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
330 if (!rxcount) {
331 /* Had one stuck? */
332 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
333 if (!rxcount)
334 return;
335 }
336 /* Check packet header */
337 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
338 if (reg_val != EMAC_PACKET_HEADER) {
339 /* Packet header is wrong */
340 if (bootverbose)
341 if_printf(ifp, "wrong packet header\n");
342 /* Disable RX */
343 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
344 reg_val &= ~EMAC_CTL_RX_EN;
345 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
346
347 /* Flush RX FIFO */
348 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
349 reg_val |= EMAC_RX_FLUSH_FIFO;
350 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
351 for (i = 100; i > 0; i--) {
352 DELAY(100);
353 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) &
354 EMAC_RX_FLUSH_FIFO) == 0)
355 break;
356 }
357 if (i == 0) {
358 device_printf(sc->emac_dev,
359 "flush FIFO timeout\n");
360 /* Reinitialize controller */
361 emac_init_locked(sc);
362 return;
363 }
364 /* Enable RX */
365 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
366 reg_val |= EMAC_CTL_RX_EN;
367 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
368
369 return;
370 }
371
372 /* Get packet size and status */
373 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
374 len = reg_val & 0xffff;
375 status = (reg_val >> 16) & 0xffff;
376
377 if (len < 64 || (status & EMAC_PKT_OK) == 0) {
378 if (bootverbose)
379 if_printf(ifp,
380 "bad packet: len = %i status = %i\n",
381 len, status);
382 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
383 emac_drain_rxfifo(sc);
384 continue;
385 }
386 #if 0
387 if (status & (EMAC_CRCERR | EMAC_LENERR)) {
388 good_packet = 0;
389 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
390 if (status & EMAC_CRCERR)
391 if_printf(ifp, "crc error\n");
392 if (status & EMAC_LENERR)
393 if_printf(ifp, "length error\n");
394 }
395 #endif
396 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
397 if (m == NULL) {
398 emac_drain_rxfifo(sc);
399 return;
400 }
401 m->m_len = m->m_pkthdr.len = MCLBYTES;
402
403 /* Copy entire frame to mbuf first. */
404 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle,
405 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4);
406
407 m->m_pkthdr.rcvif = ifp;
408 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN;
409
410 /*
411 * Emac controller needs strict aligment, so to avoid
412 * copying over an entire frame to align, we allocate
413 * a new mbuf and copy ethernet header + IP header to
414 * the new mbuf. The new mbuf is prepended into the
415 * existing mbuf chain.
416 */
417 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) {
418 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
419 m->m_data += ETHER_HDR_LEN;
420 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) &&
421 m->m_len > (MHLEN - ETHER_HDR_LEN)) {
422 MGETHDR(m0, M_NOWAIT, MT_DATA);
423 if (m0 != NULL) {
424 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen;
425 bcopy(m->m_data, m0->m_data, len);
426 m->m_data += len;
427 m->m_len -= len;
428 m0->m_len = len;
429 M_MOVE_PKTHDR(m0, m);
430 m0->m_next = m;
431 m = m0;
432 } else {
433 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
434 m_freem(m);
435 m = NULL;
436 continue;
437 }
438 } else if (m->m_len > EMAC_MAC_MAXF) {
439 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
440 m_freem(m);
441 m = NULL;
442 continue;
443 }
444 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
445 EMAC_UNLOCK(sc);
446 (*ifp->if_input)(ifp, m);
447 EMAC_LOCK(sc);
448 }
449 }
450
451 static void
emac_watchdog(struct emac_softc * sc)452 emac_watchdog(struct emac_softc *sc)
453 {
454 struct ifnet *ifp;
455
456 EMAC_ASSERT_LOCKED(sc);
457
458 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer)
459 return;
460
461 ifp = sc->emac_ifp;
462
463 if (sc->emac_link == 0) {
464 if (bootverbose)
465 if_printf(sc->emac_ifp, "watchdog timeout "
466 "(missed link)\n");
467 } else
468 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n");
469
470 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
471 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
472 emac_init_locked(sc);
473 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
474 emac_start_locked(ifp);
475 }
476
477 static void
emac_tick(void * arg)478 emac_tick(void *arg)
479 {
480 struct emac_softc *sc;
481 struct mii_data *mii;
482
483 sc = (struct emac_softc *)arg;
484 mii = device_get_softc(sc->emac_miibus);
485 mii_tick(mii);
486
487 emac_watchdog(sc);
488 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
489 }
490
491 static void
emac_init(void * xcs)492 emac_init(void *xcs)
493 {
494 struct emac_softc *sc;
495
496 sc = (struct emac_softc *)xcs;
497 EMAC_LOCK(sc);
498 emac_init_locked(sc);
499 EMAC_UNLOCK(sc);
500 }
501
502 static void
emac_init_locked(struct emac_softc * sc)503 emac_init_locked(struct emac_softc *sc)
504 {
505 struct ifnet *ifp;
506 struct mii_data *mii;
507 uint32_t reg_val;
508 uint8_t *eaddr;
509
510 EMAC_ASSERT_LOCKED(sc);
511
512 ifp = sc->emac_ifp;
513 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
514 return;
515
516 /* Flush RX FIFO */
517 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
518 reg_val |= EMAC_RX_FLUSH_FIFO;
519 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
520 DELAY(1);
521
522 /* Soft reset MAC */
523 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
524 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST);
525 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
526
527 /* Set MII clock */
528 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG);
529 reg_val &= (~(0xf << 2));
530 reg_val |= (0xd << 2);
531 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val);
532
533 /* Clear RX counter */
534 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0);
535
536 /* Disable all interrupt and clear interrupt status */
537 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
538 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
539 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
540 DELAY(1);
541
542 /* Set up TX */
543 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE);
544 reg_val |= EMAC_TX_AB_M;
545 reg_val &= EMAC_TX_TM;
546 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val);
547
548 /* Set up RX */
549 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
550 reg_val |= EMAC_RX_SETUP;
551 reg_val &= EMAC_RX_TM;
552 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
553
554 /* Set up MAC CTL0. */
555 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
556 reg_val |= EMAC_MAC_CTL0_SETUP;
557 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
558
559 /* Set up MAC CTL1. */
560 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1);
561 reg_val |= EMAC_MAC_CTL1_SETUP;
562 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val);
563
564 /* Set up IPGT */
565 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD);
566
567 /* Set up IPGR */
568 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 |
569 (EMAC_MAC_NBTB_IPG1 << 8));
570
571 /* Set up Collison window */
572 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8));
573
574 /* Set up Max Frame Length */
575 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL);
576
577 /* Setup ethernet address */
578 eaddr = IF_LLADDR(ifp);
579 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 |
580 eaddr[1] << 8 | eaddr[2]);
581 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 |
582 eaddr[4] << 8 | eaddr[5]);
583
584 /* Setup rx filter */
585 emac_set_rx_mode(sc);
586
587 /* Enable RX/TX0/RX Hlevel interrupt */
588 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
589 reg_val |= EMAC_INT_EN;
590 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
591
592 ifp->if_drv_flags |= IFF_DRV_RUNNING;
593 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
594
595 sc->emac_link = 0;
596
597 /* Switch to the current media. */
598 mii = device_get_softc(sc->emac_miibus);
599 mii_mediachg(mii);
600
601 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
602 }
603
604
605 static void
emac_start(struct ifnet * ifp)606 emac_start(struct ifnet *ifp)
607 {
608 struct emac_softc *sc;
609
610 sc = ifp->if_softc;
611 EMAC_LOCK(sc);
612 emac_start_locked(ifp);
613 EMAC_UNLOCK(sc);
614 }
615
616 static void
emac_start_locked(struct ifnet * ifp)617 emac_start_locked(struct ifnet *ifp)
618 {
619 struct emac_softc *sc;
620 struct mbuf *m, *m0;
621 uint32_t fifo, reg;
622
623 sc = ifp->if_softc;
624 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
625 return;
626 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
627 return;
628 if (sc->emac_link == 0)
629 return;
630 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
631 if (m == NULL)
632 return;
633
634 /* Select channel */
635 if (sc->emac_fifo_mask & EMAC_TX_FIFO0)
636 fifo = 1;
637 else
638 fifo = 0;
639 sc->emac_fifo_mask |= (1 << fifo);
640 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
641 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
642 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo);
643
644 /*
645 * Emac controller wants 4 byte aligned TX buffers.
646 * We have to copy pretty much all the time.
647 */
648 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) {
649 m0 = m_defrag(m, M_NOWAIT);
650 if (m0 == NULL) {
651 m_freem(m);
652 m = NULL;
653 return;
654 }
655 m = m0;
656 }
657 /* Write data */
658 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle,
659 EMAC_TX_IO_DATA, mtod(m, uint32_t *),
660 roundup2(m->m_len, 4) / 4);
661
662 /* Send the data lengh. */
663 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1;
664 EMAC_WRITE_REG(sc, reg, m->m_len);
665
666 /* Start translate from fifo to phy. */
667 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1;
668 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1);
669
670 /* Set timeout */
671 sc->emac_watchdog_timer = 5;
672
673 /* Data have been sent to hardware, it is okay to free the mbuf now. */
674 BPF_MTAP(ifp, m);
675 m_freem(m);
676 }
677
678 static void
emac_stop_locked(struct emac_softc * sc)679 emac_stop_locked(struct emac_softc *sc)
680 {
681 struct ifnet *ifp;
682 uint32_t reg_val;
683
684 EMAC_ASSERT_LOCKED(sc);
685
686 ifp = sc->emac_ifp;
687 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
688 sc->emac_link = 0;
689
690 /* Disable all interrupt and clear interrupt status */
691 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
692 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
693 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
694
695 /* Disable RX/TX */
696 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
697 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
698 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
699
700 callout_stop(&sc->emac_tick_ch);
701 }
702
703 static void
emac_intr(void * arg)704 emac_intr(void *arg)
705 {
706 struct emac_softc *sc;
707 struct ifnet *ifp;
708 uint32_t reg_val;
709
710 sc = (struct emac_softc *)arg;
711 EMAC_LOCK(sc);
712
713 /* Disable all interrupts */
714 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
715 /* Get EMAC interrupt status */
716 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
717 /* Clear ISR status */
718 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
719
720 /* Received incoming packet */
721 if (reg_val & EMAC_INT_STA_RX)
722 emac_rxeof(sc, sc->emac_rx_process_limit);
723
724 /* Transmit Interrupt check */
725 if (reg_val & EMAC_INT_STA_TX) {
726 emac_txeof(sc, reg_val);
727 ifp = sc->emac_ifp;
728 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
729 emac_start_locked(ifp);
730 }
731
732 /* Re-enable interrupt mask */
733 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
734 reg_val |= EMAC_INT_EN;
735 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
736 EMAC_UNLOCK(sc);
737 }
738
739 static int
emac_ioctl(struct ifnet * ifp,u_long command,caddr_t data)740 emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
741 {
742 struct emac_softc *sc;
743 struct mii_data *mii;
744 struct ifreq *ifr;
745 int error = 0;
746
747 sc = ifp->if_softc;
748 ifr = (struct ifreq *)data;
749
750 switch (command) {
751 case SIOCSIFFLAGS:
752 EMAC_LOCK(sc);
753 if (ifp->if_flags & IFF_UP) {
754 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
755 if ((ifp->if_flags ^ sc->emac_if_flags) &
756 (IFF_PROMISC | IFF_ALLMULTI))
757 emac_set_rx_mode(sc);
758 } else
759 emac_init_locked(sc);
760 } else {
761 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
762 emac_stop_locked(sc);
763 }
764 sc->emac_if_flags = ifp->if_flags;
765 EMAC_UNLOCK(sc);
766 break;
767 case SIOCADDMULTI:
768 case SIOCDELMULTI:
769 EMAC_LOCK(sc);
770 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
771 emac_set_rx_mode(sc);
772 }
773 EMAC_UNLOCK(sc);
774 break;
775 case SIOCGIFMEDIA:
776 case SIOCSIFMEDIA:
777 mii = device_get_softc(sc->emac_miibus);
778 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
779 break;
780 default:
781 error = ether_ioctl(ifp, command, data);
782 break;
783 }
784 return (error);
785 }
786
787 static int
emac_probe(device_t dev)788 emac_probe(device_t dev)
789 {
790
791 if (!ofw_bus_status_okay(dev))
792 return (ENXIO);
793
794 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac"))
795 return (ENXIO);
796
797 device_set_desc(dev, "A10/A20 EMAC ethernet controller");
798 return (BUS_PROBE_DEFAULT);
799 }
800
801 static int
emac_detach(device_t dev)802 emac_detach(device_t dev)
803 {
804 struct emac_softc *sc;
805
806 sc = device_get_softc(dev);
807 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
808 if (device_is_attached(dev)) {
809 ether_ifdetach(sc->emac_ifp);
810 EMAC_LOCK(sc);
811 emac_stop_locked(sc);
812 EMAC_UNLOCK(sc);
813 callout_drain(&sc->emac_tick_ch);
814 }
815
816 if (sc->emac_intrhand != NULL)
817 bus_teardown_intr(sc->emac_dev, sc->emac_irq,
818 sc->emac_intrhand);
819
820 if (sc->emac_miibus != NULL) {
821 device_delete_child(sc->emac_dev, sc->emac_miibus);
822 bus_generic_detach(sc->emac_dev);
823 }
824
825 if (sc->emac_clk != NULL)
826 clk_disable(sc->emac_clk);
827
828 if (sc->emac_res != NULL)
829 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res);
830
831 if (sc->emac_irq != NULL)
832 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq);
833
834 if (sc->emac_ifp != NULL)
835 if_free(sc->emac_ifp);
836
837 if (mtx_initialized(&sc->emac_mtx))
838 mtx_destroy(&sc->emac_mtx);
839
840 return (0);
841 }
842
843 static int
emac_shutdown(device_t dev)844 emac_shutdown(device_t dev)
845 {
846
847 return (emac_suspend(dev));
848 }
849
850 static int
emac_suspend(device_t dev)851 emac_suspend(device_t dev)
852 {
853 struct emac_softc *sc;
854 struct ifnet *ifp;
855
856 sc = device_get_softc(dev);
857
858 EMAC_LOCK(sc);
859 ifp = sc->emac_ifp;
860 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
861 emac_stop_locked(sc);
862 EMAC_UNLOCK(sc);
863
864 return (0);
865 }
866
867 static int
emac_resume(device_t dev)868 emac_resume(device_t dev)
869 {
870 struct emac_softc *sc;
871 struct ifnet *ifp;
872
873 sc = device_get_softc(dev);
874
875 EMAC_LOCK(sc);
876 ifp = sc->emac_ifp;
877 if ((ifp->if_flags & IFF_UP) != 0) {
878 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
879 emac_init_locked(sc);
880 }
881 EMAC_UNLOCK(sc);
882
883 return (0);
884 }
885
886 static int
emac_attach(device_t dev)887 emac_attach(device_t dev)
888 {
889 struct emac_softc *sc;
890 struct ifnet *ifp;
891 int error, rid;
892 uint8_t eaddr[ETHER_ADDR_LEN];
893
894 sc = device_get_softc(dev);
895 sc->emac_dev = dev;
896
897 error = 0;
898 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
899 MTX_DEF);
900 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0);
901
902 rid = 0;
903 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
904 RF_ACTIVE);
905 if (sc->emac_res == NULL) {
906 device_printf(dev, "unable to map memory\n");
907 error = ENXIO;
908 goto fail;
909 }
910
911 sc->emac_tag = rman_get_bustag(sc->emac_res);
912 sc->emac_handle = rman_get_bushandle(sc->emac_res);
913
914 rid = 0;
915 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
916 RF_SHAREABLE | RF_ACTIVE);
917 if (sc->emac_irq == NULL) {
918 device_printf(dev, "cannot allocate IRQ resources.\n");
919 error = ENXIO;
920 goto fail;
921 }
922 /* Create device sysctl node. */
923 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
924 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
925 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
926 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I",
927 "max number of Rx events to process");
928
929 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
930 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
931 "process_limit", &sc->emac_rx_process_limit);
932 if (error == 0) {
933 if (sc->emac_rx_process_limit < EMAC_PROC_MIN ||
934 sc->emac_rx_process_limit > EMAC_PROC_MAX) {
935 device_printf(dev, "process_limit value out of range; "
936 "using default: %d\n", EMAC_PROC_DEFAULT);
937 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
938 }
939 }
940 /* Setup EMAC */
941 error = emac_sys_setup(sc);
942 if (error != 0)
943 goto fail;
944
945 emac_reset(sc);
946
947 ifp = sc->emac_ifp = if_alloc(IFT_ETHER);
948 if (ifp == NULL) {
949 device_printf(dev, "unable to allocate ifp\n");
950 error = ENOSPC;
951 goto fail;
952 }
953 ifp->if_softc = sc;
954
955 /* Setup MII */
956 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd,
957 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
958 if (error != 0) {
959 device_printf(dev, "PHY probe failed\n");
960 goto fail;
961 }
962
963 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
964 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
965 ifp->if_start = emac_start;
966 ifp->if_ioctl = emac_ioctl;
967 ifp->if_init = emac_init;
968 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
969
970 /* Get MAC address */
971 emac_get_hwaddr(sc, eaddr);
972 ether_ifattach(ifp, eaddr);
973
974 /* VLAN capability setup. */
975 ifp->if_capabilities |= IFCAP_VLAN_MTU;
976 ifp->if_capenable = ifp->if_capabilities;
977 /* Tell the upper layer we support VLAN over-sized frames. */
978 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
979
980 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE,
981 NULL, emac_intr, sc, &sc->emac_intrhand);
982 if (error != 0) {
983 device_printf(dev, "could not set up interrupt handler.\n");
984 ether_ifdetach(ifp);
985 goto fail;
986 }
987
988 fail:
989 if (error != 0)
990 emac_detach(dev);
991 return (error);
992 }
993
994 static boolean_t
emac_miibus_iowait(struct emac_softc * sc)995 emac_miibus_iowait(struct emac_softc *sc)
996 {
997 uint32_t timeout;
998
999 for (timeout = 100; timeout != 0; --timeout) {
1000 DELAY(100);
1001 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0)
1002 return (true);
1003 }
1004
1005 return (false);
1006 }
1007
1008 /*
1009 * The MII bus interface
1010 */
1011 static int
emac_miibus_readreg(device_t dev,int phy,int reg)1012 emac_miibus_readreg(device_t dev, int phy, int reg)
1013 {
1014 struct emac_softc *sc;
1015 int rval;
1016
1017 sc = device_get_softc(dev);
1018
1019 /* Issue phy address and reg */
1020 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1021 /* Pull up the phy io line */
1022 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1023 if (!emac_miibus_iowait(sc)) {
1024 device_printf(dev, "timeout waiting for mii read\n");
1025 return (0);
1026 }
1027 /* Push down the phy io line */
1028 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1029 /* Read data */
1030 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD);
1031
1032 return (rval);
1033 }
1034
1035 static int
emac_miibus_writereg(device_t dev,int phy,int reg,int data)1036 emac_miibus_writereg(device_t dev, int phy, int reg, int data)
1037 {
1038 struct emac_softc *sc;
1039
1040 sc = device_get_softc(dev);
1041
1042 /* Issue phy address and reg */
1043 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1044 /* Write data */
1045 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data);
1046 /* Pull up the phy io line */
1047 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1048 if (!emac_miibus_iowait(sc)) {
1049 device_printf(dev, "timeout waiting for mii write\n");
1050 return (0);
1051 }
1052 /* Push down the phy io line */
1053 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1054
1055 return (0);
1056 }
1057
1058 static void
emac_miibus_statchg(device_t dev)1059 emac_miibus_statchg(device_t dev)
1060 {
1061 struct emac_softc *sc;
1062 struct mii_data *mii;
1063 struct ifnet *ifp;
1064 uint32_t reg_val;
1065
1066 sc = device_get_softc(dev);
1067
1068 mii = device_get_softc(sc->emac_miibus);
1069 ifp = sc->emac_ifp;
1070 if (mii == NULL || ifp == NULL ||
1071 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1072 return;
1073
1074 sc->emac_link = 0;
1075 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1076 (IFM_ACTIVE | IFM_AVALID)) {
1077 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1078 case IFM_10_T:
1079 case IFM_100_TX:
1080 sc->emac_link = 1;
1081 break;
1082 default:
1083 break;
1084 }
1085 }
1086 /* Program MACs with resolved speed/duplex. */
1087 if (sc->emac_link != 0) {
1088 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT);
1089 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1090 reg_val &= ~EMAC_MAC_IPGT_HD;
1091 reg_val |= EMAC_MAC_IPGT_FD;
1092 } else {
1093 reg_val &= ~EMAC_MAC_IPGT_FD;
1094 reg_val |= EMAC_MAC_IPGT_HD;
1095 }
1096 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val);
1097 /* Enable RX/TX */
1098 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1099 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN;
1100 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1101 } else {
1102 /* Disable RX/TX */
1103 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1104 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
1105 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1106 }
1107 }
1108
1109 static int
emac_ifmedia_upd(struct ifnet * ifp)1110 emac_ifmedia_upd(struct ifnet *ifp)
1111 {
1112 struct emac_softc *sc;
1113 struct mii_data *mii;
1114 struct mii_softc *miisc;
1115 int error;
1116
1117 sc = ifp->if_softc;
1118 mii = device_get_softc(sc->emac_miibus);
1119 EMAC_LOCK(sc);
1120 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1121 PHY_RESET(miisc);
1122 error = mii_mediachg(mii);
1123 EMAC_UNLOCK(sc);
1124
1125 return (error);
1126 }
1127
1128 static void
emac_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1129 emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1130 {
1131 struct emac_softc *sc;
1132 struct mii_data *mii;
1133
1134 sc = ifp->if_softc;
1135 mii = device_get_softc(sc->emac_miibus);
1136
1137 EMAC_LOCK(sc);
1138 mii_pollstat(mii);
1139 ifmr->ifm_active = mii->mii_media_active;
1140 ifmr->ifm_status = mii->mii_media_status;
1141 EMAC_UNLOCK(sc);
1142 }
1143
1144 static device_method_t emac_methods[] = {
1145 /* Device interface */
1146 DEVMETHOD(device_probe, emac_probe),
1147 DEVMETHOD(device_attach, emac_attach),
1148 DEVMETHOD(device_detach, emac_detach),
1149 DEVMETHOD(device_shutdown, emac_shutdown),
1150 DEVMETHOD(device_suspend, emac_suspend),
1151 DEVMETHOD(device_resume, emac_resume),
1152
1153 /* bus interface, for miibus */
1154 DEVMETHOD(bus_print_child, bus_generic_print_child),
1155 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1156
1157 /* MII interface */
1158 DEVMETHOD(miibus_readreg, emac_miibus_readreg),
1159 DEVMETHOD(miibus_writereg, emac_miibus_writereg),
1160 DEVMETHOD(miibus_statchg, emac_miibus_statchg),
1161
1162 DEVMETHOD_END
1163 };
1164
1165 static driver_t emac_driver = {
1166 "emac",
1167 emac_methods,
1168 sizeof(struct emac_softc)
1169 };
1170
1171 static devclass_t emac_devclass;
1172
1173 DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0);
1174 DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0);
1175 MODULE_DEPEND(emac, miibus, 1, 1, 1);
1176 MODULE_DEPEND(emac, ether, 1, 1, 1);
1177
1178 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)1179 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
1180 {
1181 int error, value;
1182
1183 if (arg1 == NULL)
1184 return (EINVAL);
1185 value = *(int *)arg1;
1186 error = sysctl_handle_int(oidp, &value, 0, req);
1187 if (error || req->newptr == NULL)
1188 return (error);
1189 if (value < low || value > high)
1190 return (EINVAL);
1191 *(int *)arg1 = value;
1192
1193 return (0);
1194 }
1195
1196 static int
sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS)1197 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS)
1198 {
1199
1200 return (sysctl_int_range(oidp, arg1, arg2, req,
1201 EMAC_PROC_MIN, EMAC_PROC_MAX));
1202 }
1203