1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Zhixiang Yu <[email protected]>
5 * Copyright (c) 2015-2016 Alexander Motin <[email protected]>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include <sys/param.h>
32 #include <sys/linker_set.h>
33 #include <sys/stat.h>
34 #include <sys/uio.h>
35 #include <sys/ioctl.h>
36 #include <sys/disk.h>
37 #include <sys/ata.h>
38 #include <sys/endian.h>
39
40 #include <errno.h>
41 #include <fcntl.h>
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <stdint.h>
45 #include <string.h>
46 #include <strings.h>
47 #include <unistd.h>
48 #include <assert.h>
49 #include <pthread.h>
50 #include <pthread_np.h>
51 #include <inttypes.h>
52 #include <md5.h>
53
54 #include "bhyverun.h"
55 #include "config.h"
56 #include "debug.h"
57 #include "pci_emul.h"
58 #ifdef BHYVE_SNAPSHOT
59 #include "snapshot.h"
60 #endif
61 #include "ahci.h"
62 #include "block_if.h"
63
64 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
65 #define MAX_PORTS 32 /* AHCI supports 32 ports */
66
67 #define PxSIG_ATA 0x00000101 /* ATA drive */
68 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
69
70 enum sata_fis_type {
71 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
72 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
73 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
74 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
75 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
76 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
77 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
78 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
79 };
80
81 /*
82 * SCSI opcodes
83 */
84 #define TEST_UNIT_READY 0x00
85 #define REQUEST_SENSE 0x03
86 #define INQUIRY 0x12
87 #define START_STOP_UNIT 0x1B
88 #define PREVENT_ALLOW 0x1E
89 #define READ_CAPACITY 0x25
90 #define READ_10 0x28
91 #define POSITION_TO_ELEMENT 0x2B
92 #define READ_TOC 0x43
93 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
94 #define MODE_SENSE_10 0x5A
95 #define REPORT_LUNS 0xA0
96 #define READ_12 0xA8
97 #define READ_CD 0xBE
98
99 /*
100 * SCSI mode page codes
101 */
102 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
103 #define MODEPAGE_CD_CAPABILITIES 0x2A
104
105 /*
106 * ATA commands
107 */
108 #define ATA_SF_ENAB_SATA_SF 0x10
109 #define ATA_SATA_SF_AN 0x05
110 #define ATA_SF_DIS_SATA_SF 0x90
111
112 /*
113 * Debug printf
114 */
115 #ifdef AHCI_DEBUG
116 static FILE *dbg;
117 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
118 #else
119 #define DPRINTF(format, arg...)
120 #endif
121
122 #define AHCI_PORT_IDENT 20 + 1
123
124 struct ahci_ioreq {
125 struct blockif_req io_req;
126 struct ahci_port *io_pr;
127 STAILQ_ENTRY(ahci_ioreq) io_flist;
128 TAILQ_ENTRY(ahci_ioreq) io_blist;
129 uint8_t *cfis;
130 uint8_t *dsm;
131 uint32_t len;
132 uint32_t done;
133 int slot;
134 int more;
135 int readop;
136 };
137
138 struct ahci_port {
139 struct blockif_ctxt *bctx;
140 struct pci_ahci_softc *pr_sc;
141 struct ata_params ata_ident;
142 uint8_t *cmd_lst;
143 uint8_t *rfis;
144 int port;
145 int atapi;
146 int reset;
147 int waitforclear;
148 int mult_sectors;
149 uint8_t xfermode;
150 uint8_t err_cfis[20];
151 uint8_t sense_key;
152 uint8_t asc;
153 u_int ccs;
154 uint32_t pending;
155
156 uint32_t clb;
157 uint32_t clbu;
158 uint32_t fb;
159 uint32_t fbu;
160 uint32_t is;
161 uint32_t ie;
162 uint32_t cmd;
163 uint32_t unused0;
164 uint32_t tfd;
165 uint32_t sig;
166 uint32_t ssts;
167 uint32_t sctl;
168 uint32_t serr;
169 uint32_t sact;
170 uint32_t ci;
171 uint32_t sntf;
172 uint32_t fbs;
173
174 /*
175 * i/o request info
176 */
177 struct ahci_ioreq *ioreq;
178 int ioqsz;
179 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
180 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
181 };
182
183 struct ahci_cmd_hdr {
184 uint16_t flags;
185 uint16_t prdtl;
186 uint32_t prdbc;
187 uint64_t ctba;
188 uint32_t reserved[4];
189 };
190
191 struct ahci_prdt_entry {
192 uint64_t dba;
193 uint32_t reserved;
194 #define DBCMASK 0x3fffff
195 uint32_t dbc;
196 };
197
198 struct pci_ahci_softc {
199 struct pci_devinst *asc_pi;
200 pthread_mutex_t mtx;
201 int ports;
202 uint32_t cap;
203 uint32_t ghc;
204 uint32_t is;
205 uint32_t pi;
206 uint32_t vs;
207 uint32_t ccc_ctl;
208 uint32_t ccc_pts;
209 uint32_t em_loc;
210 uint32_t em_ctl;
211 uint32_t cap2;
212 uint32_t bohc;
213 uint32_t lintr;
214 struct ahci_port port[MAX_PORTS];
215 };
216 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
217
218 static void ahci_handle_next_trim(struct ahci_port *p, int slot, uint8_t *cfis,
219 uint8_t *buf, uint32_t len, uint32_t done);
220 static void ahci_handle_port(struct ahci_port *p);
221
lba_to_msf(uint8_t * buf,int lba)222 static inline void lba_to_msf(uint8_t *buf, int lba)
223 {
224 lba += 150;
225 buf[0] = (lba / 75) / 60;
226 buf[1] = (lba / 75) % 60;
227 buf[2] = lba % 75;
228 }
229
230 /*
231 * Generate HBA interrupts on global IS register write.
232 */
233 static void
ahci_generate_intr(struct pci_ahci_softc * sc,uint32_t mask)234 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask)
235 {
236 struct pci_devinst *pi = sc->asc_pi;
237 struct ahci_port *p;
238 int i, nmsg;
239 uint32_t mmask;
240
241 /* Update global IS from PxIS/PxIE. */
242 for (i = 0; i < sc->ports; i++) {
243 p = &sc->port[i];
244 if (p->is & p->ie)
245 sc->is |= (1 << i);
246 }
247 DPRINTF("%s(%08x) %08x", __func__, mask, sc->is);
248
249 /* If there is nothing enabled -- clear legacy interrupt and exit. */
250 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) {
251 if (sc->lintr) {
252 pci_lintr_deassert(pi);
253 sc->lintr = 0;
254 }
255 return;
256 }
257
258 /* If there is anything and no MSI -- assert legacy interrupt. */
259 nmsg = pci_msi_maxmsgnum(pi);
260 if (nmsg == 0) {
261 if (!sc->lintr) {
262 sc->lintr = 1;
263 pci_lintr_assert(pi);
264 }
265 return;
266 }
267
268 /* Assert respective MSIs for ports that were touched. */
269 for (i = 0; i < nmsg; i++) {
270 if (sc->ports <= nmsg || i < nmsg - 1)
271 mmask = 1 << i;
272 else
273 mmask = 0xffffffff << i;
274 if (sc->is & mask && mmask & mask)
275 pci_generate_msi(pi, i);
276 }
277 }
278
279 /*
280 * Generate HBA interrupt on specific port event.
281 */
282 static void
ahci_port_intr(struct ahci_port * p)283 ahci_port_intr(struct ahci_port *p)
284 {
285 struct pci_ahci_softc *sc = p->pr_sc;
286 struct pci_devinst *pi = sc->asc_pi;
287 int nmsg;
288
289 DPRINTF("%s(%d) %08x/%08x %08x", __func__,
290 p->port, p->is, p->ie, sc->is);
291
292 /* If there is nothing enabled -- we are done. */
293 if ((p->is & p->ie) == 0)
294 return;
295
296 /* In case of non-shared MSI always generate interrupt. */
297 nmsg = pci_msi_maxmsgnum(pi);
298 if (sc->ports <= nmsg || p->port < nmsg - 1) {
299 sc->is |= (1 << p->port);
300 if ((sc->ghc & AHCI_GHC_IE) == 0)
301 return;
302 pci_generate_msi(pi, p->port);
303 return;
304 }
305
306 /* If IS for this port is already set -- do nothing. */
307 if (sc->is & (1 << p->port))
308 return;
309
310 sc->is |= (1 << p->port);
311
312 /* If interrupts are enabled -- generate one. */
313 if ((sc->ghc & AHCI_GHC_IE) == 0)
314 return;
315 if (nmsg > 0) {
316 pci_generate_msi(pi, nmsg - 1);
317 } else if (!sc->lintr) {
318 sc->lintr = 1;
319 pci_lintr_assert(pi);
320 }
321 }
322
323 static void
ahci_write_fis(struct ahci_port * p,enum sata_fis_type ft,uint8_t * fis)324 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
325 {
326 int offset, len, irq;
327
328 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
329 return;
330
331 switch (ft) {
332 case FIS_TYPE_REGD2H:
333 offset = 0x40;
334 len = 20;
335 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0;
336 break;
337 case FIS_TYPE_SETDEVBITS:
338 offset = 0x58;
339 len = 8;
340 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0;
341 break;
342 case FIS_TYPE_PIOSETUP:
343 offset = 0x20;
344 len = 20;
345 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
346 break;
347 default:
348 EPRINTLN("unsupported fis type %d", ft);
349 return;
350 }
351 if (fis[2] & ATA_S_ERROR) {
352 p->waitforclear = 1;
353 irq |= AHCI_P_IX_TFE;
354 }
355 memcpy(p->rfis + offset, fis, len);
356 if (irq) {
357 if (~p->is & irq) {
358 p->is |= irq;
359 ahci_port_intr(p);
360 }
361 }
362 }
363
364 static void
ahci_write_fis_piosetup(struct ahci_port * p)365 ahci_write_fis_piosetup(struct ahci_port *p)
366 {
367 uint8_t fis[20];
368
369 memset(fis, 0, sizeof(fis));
370 fis[0] = FIS_TYPE_PIOSETUP;
371 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
372 }
373
374 static void
ahci_write_fis_sdb(struct ahci_port * p,int slot,uint8_t * cfis,uint32_t tfd)375 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
376 {
377 uint8_t fis[8];
378 uint8_t error;
379
380 error = (tfd >> 8) & 0xff;
381 tfd &= 0x77;
382 memset(fis, 0, sizeof(fis));
383 fis[0] = FIS_TYPE_SETDEVBITS;
384 fis[1] = (1 << 6);
385 fis[2] = tfd;
386 fis[3] = error;
387 if (fis[2] & ATA_S_ERROR) {
388 p->err_cfis[0] = slot;
389 p->err_cfis[2] = tfd;
390 p->err_cfis[3] = error;
391 memcpy(&p->err_cfis[4], cfis + 4, 16);
392 } else {
393 *(uint32_t *)(fis + 4) = (1 << slot);
394 p->sact &= ~(1 << slot);
395 }
396 p->tfd &= ~0x77;
397 p->tfd |= tfd;
398 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
399 }
400
401 static void
ahci_write_fis_d2h(struct ahci_port * p,int slot,uint8_t * cfis,uint32_t tfd)402 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
403 {
404 uint8_t fis[20];
405 uint8_t error;
406
407 error = (tfd >> 8) & 0xff;
408 memset(fis, 0, sizeof(fis));
409 fis[0] = FIS_TYPE_REGD2H;
410 fis[1] = (1 << 6);
411 fis[2] = tfd & 0xff;
412 fis[3] = error;
413 fis[4] = cfis[4];
414 fis[5] = cfis[5];
415 fis[6] = cfis[6];
416 fis[7] = cfis[7];
417 fis[8] = cfis[8];
418 fis[9] = cfis[9];
419 fis[10] = cfis[10];
420 fis[11] = cfis[11];
421 fis[12] = cfis[12];
422 fis[13] = cfis[13];
423 if (fis[2] & ATA_S_ERROR) {
424 p->err_cfis[0] = 0x80;
425 p->err_cfis[2] = tfd & 0xff;
426 p->err_cfis[3] = error;
427 memcpy(&p->err_cfis[4], cfis + 4, 16);
428 } else
429 p->ci &= ~(1 << slot);
430 p->tfd = tfd;
431 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
432 }
433
434 static void
ahci_write_fis_d2h_ncq(struct ahci_port * p,int slot)435 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot)
436 {
437 uint8_t fis[20];
438
439 p->tfd = ATA_S_READY | ATA_S_DSC;
440 memset(fis, 0, sizeof(fis));
441 fis[0] = FIS_TYPE_REGD2H;
442 fis[1] = 0; /* No interrupt */
443 fis[2] = p->tfd; /* Status */
444 fis[3] = 0; /* No error */
445 p->ci &= ~(1 << slot);
446 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
447 }
448
449 static void
ahci_write_reset_fis_d2h(struct ahci_port * p)450 ahci_write_reset_fis_d2h(struct ahci_port *p)
451 {
452 uint8_t fis[20];
453
454 memset(fis, 0, sizeof(fis));
455 fis[0] = FIS_TYPE_REGD2H;
456 fis[3] = 1;
457 fis[4] = 1;
458 if (p->atapi) {
459 fis[5] = 0x14;
460 fis[6] = 0xeb;
461 }
462 fis[12] = 1;
463 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
464 }
465
466 static void
ahci_check_stopped(struct ahci_port * p)467 ahci_check_stopped(struct ahci_port *p)
468 {
469 /*
470 * If we are no longer processing the command list and nothing
471 * is in-flight, clear the running bit, the current command
472 * slot, the command issue and active bits.
473 */
474 if (!(p->cmd & AHCI_P_CMD_ST)) {
475 if (p->pending == 0) {
476 p->ccs = 0;
477 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
478 p->ci = 0;
479 p->sact = 0;
480 p->waitforclear = 0;
481 }
482 }
483 }
484
485 static void
ahci_port_stop(struct ahci_port * p)486 ahci_port_stop(struct ahci_port *p)
487 {
488 struct ahci_ioreq *aior;
489 uint8_t *cfis;
490 int slot;
491 int error;
492
493 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
494
495 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
496 /*
497 * Try to cancel the outstanding blockif request.
498 */
499 error = blockif_cancel(p->bctx, &aior->io_req);
500 if (error != 0)
501 continue;
502
503 slot = aior->slot;
504 cfis = aior->cfis;
505 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
506 cfis[2] == ATA_READ_FPDMA_QUEUED ||
507 cfis[2] == ATA_SEND_FPDMA_QUEUED)
508 p->sact &= ~(1 << slot); /* NCQ */
509 else
510 p->ci &= ~(1 << slot);
511
512 /*
513 * This command is now done.
514 */
515 p->pending &= ~(1 << slot);
516
517 /*
518 * Delete the blockif request from the busy list
519 */
520 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
521
522 /*
523 * Move the blockif request back to the free list
524 */
525 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
526 }
527
528 ahci_check_stopped(p);
529 }
530
531 static void
ahci_port_reset(struct ahci_port * pr)532 ahci_port_reset(struct ahci_port *pr)
533 {
534 pr->serr = 0;
535 pr->sact = 0;
536 pr->xfermode = ATA_UDMA6;
537 pr->mult_sectors = 128;
538
539 if (!pr->bctx) {
540 pr->ssts = ATA_SS_DET_NO_DEVICE;
541 pr->sig = 0xFFFFFFFF;
542 pr->tfd = 0x7F;
543 return;
544 }
545 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
546 if (pr->sctl & ATA_SC_SPD_MASK)
547 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
548 else
549 pr->ssts |= ATA_SS_SPD_GEN3;
550 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
551 if (!pr->atapi) {
552 pr->sig = PxSIG_ATA;
553 pr->tfd |= ATA_S_READY;
554 } else
555 pr->sig = PxSIG_ATAPI;
556 ahci_write_reset_fis_d2h(pr);
557 }
558
559 static void
ahci_reset(struct pci_ahci_softc * sc)560 ahci_reset(struct pci_ahci_softc *sc)
561 {
562 int i;
563
564 sc->ghc = AHCI_GHC_AE;
565 sc->is = 0;
566
567 if (sc->lintr) {
568 pci_lintr_deassert(sc->asc_pi);
569 sc->lintr = 0;
570 }
571
572 for (i = 0; i < sc->ports; i++) {
573 sc->port[i].ie = 0;
574 sc->port[i].is = 0;
575 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD);
576 if (sc->port[i].bctx)
577 sc->port[i].cmd |= AHCI_P_CMD_CPS;
578 sc->port[i].sctl = 0;
579 ahci_port_reset(&sc->port[i]);
580 }
581 }
582
583 static void
ata_string(uint8_t * dest,const char * src,int len)584 ata_string(uint8_t *dest, const char *src, int len)
585 {
586 int i;
587
588 for (i = 0; i < len; i++) {
589 if (*src)
590 dest[i ^ 1] = *src++;
591 else
592 dest[i ^ 1] = ' ';
593 }
594 }
595
596 static void
atapi_string(uint8_t * dest,const char * src,int len)597 atapi_string(uint8_t *dest, const char *src, int len)
598 {
599 int i;
600
601 for (i = 0; i < len; i++) {
602 if (*src)
603 dest[i] = *src++;
604 else
605 dest[i] = ' ';
606 }
607 }
608
609 /*
610 * Build up the iovec based on the PRDT, 'done' and 'len'.
611 */
612 static void
ahci_build_iov(struct ahci_port * p,struct ahci_ioreq * aior,struct ahci_prdt_entry * prdt,uint16_t prdtl)613 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior,
614 struct ahci_prdt_entry *prdt, uint16_t prdtl)
615 {
616 struct blockif_req *breq = &aior->io_req;
617 uint32_t dbcsz, extra, left, skip, todo;
618 int i, j;
619
620 assert(aior->len >= aior->done);
621
622 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */
623 skip = aior->done;
624 left = aior->len - aior->done;
625 todo = 0;
626 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0;
627 i++, prdt++) {
628 dbcsz = (prdt->dbc & DBCMASK) + 1;
629 /* Skip already done part of the PRDT */
630 if (dbcsz <= skip) {
631 skip -= dbcsz;
632 continue;
633 }
634 dbcsz -= skip;
635 if (dbcsz > left)
636 dbcsz = left;
637 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc),
638 prdt->dba + skip, dbcsz);
639 breq->br_iov[j].iov_len = dbcsz;
640 todo += dbcsz;
641 left -= dbcsz;
642 skip = 0;
643 j++;
644 }
645
646 /* If we got limited by IOV length, round I/O down to sector size. */
647 if (j == BLOCKIF_IOV_MAX) {
648 extra = todo % blockif_sectsz(p->bctx);
649 todo -= extra;
650 assert(todo > 0);
651 while (extra > 0) {
652 if (breq->br_iov[j - 1].iov_len > extra) {
653 breq->br_iov[j - 1].iov_len -= extra;
654 break;
655 }
656 extra -= breq->br_iov[j - 1].iov_len;
657 j--;
658 }
659 }
660
661 breq->br_iovcnt = j;
662 breq->br_resid = todo;
663 aior->done += todo;
664 aior->more = (aior->done < aior->len && i < prdtl);
665 }
666
667 static void
ahci_handle_rw(struct ahci_port * p,int slot,uint8_t * cfis,uint32_t done)668 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
669 {
670 struct ahci_ioreq *aior;
671 struct blockif_req *breq;
672 struct ahci_prdt_entry *prdt;
673 struct ahci_cmd_hdr *hdr;
674 uint64_t lba;
675 uint32_t len;
676 int err, first, ncq, readop;
677
678 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
679 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
680 ncq = 0;
681 readop = 1;
682 first = (done == 0);
683
684 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
685 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
686 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
687 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
688 readop = 0;
689
690 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
691 cfis[2] == ATA_READ_FPDMA_QUEUED) {
692 lba = ((uint64_t)cfis[10] << 40) |
693 ((uint64_t)cfis[9] << 32) |
694 ((uint64_t)cfis[8] << 24) |
695 ((uint64_t)cfis[6] << 16) |
696 ((uint64_t)cfis[5] << 8) |
697 cfis[4];
698 len = cfis[11] << 8 | cfis[3];
699 if (!len)
700 len = 65536;
701 ncq = 1;
702 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
703 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
704 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
705 lba = ((uint64_t)cfis[10] << 40) |
706 ((uint64_t)cfis[9] << 32) |
707 ((uint64_t)cfis[8] << 24) |
708 ((uint64_t)cfis[6] << 16) |
709 ((uint64_t)cfis[5] << 8) |
710 cfis[4];
711 len = cfis[13] << 8 | cfis[12];
712 if (!len)
713 len = 65536;
714 } else {
715 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
716 (cfis[5] << 8) | cfis[4];
717 len = cfis[12];
718 if (!len)
719 len = 256;
720 }
721 lba *= blockif_sectsz(p->bctx);
722 len *= blockif_sectsz(p->bctx);
723
724 /* Pull request off free list */
725 aior = STAILQ_FIRST(&p->iofhd);
726 assert(aior != NULL);
727 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
728
729 aior->cfis = cfis;
730 aior->slot = slot;
731 aior->len = len;
732 aior->done = done;
733 aior->readop = readop;
734 breq = &aior->io_req;
735 breq->br_offset = lba + done;
736 ahci_build_iov(p, aior, prdt, hdr->prdtl);
737
738 /* Mark this command in-flight. */
739 p->pending |= 1 << slot;
740
741 /* Stuff request onto busy list. */
742 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
743
744 if (ncq && first)
745 ahci_write_fis_d2h_ncq(p, slot);
746
747 if (readop)
748 err = blockif_read(p->bctx, breq);
749 else
750 err = blockif_write(p->bctx, breq);
751 assert(err == 0);
752 }
753
754 static void
ahci_handle_flush(struct ahci_port * p,int slot,uint8_t * cfis)755 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
756 {
757 struct ahci_ioreq *aior;
758 struct blockif_req *breq;
759 int err;
760
761 /*
762 * Pull request off free list
763 */
764 aior = STAILQ_FIRST(&p->iofhd);
765 assert(aior != NULL);
766 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
767 aior->cfis = cfis;
768 aior->slot = slot;
769 aior->len = 0;
770 aior->done = 0;
771 aior->more = 0;
772 breq = &aior->io_req;
773
774 /*
775 * Mark this command in-flight.
776 */
777 p->pending |= 1 << slot;
778
779 /*
780 * Stuff request onto busy list
781 */
782 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
783
784 err = blockif_flush(p->bctx, breq);
785 assert(err == 0);
786 }
787
788 static inline unsigned int
read_prdt(struct ahci_port * p,int slot,uint8_t * cfis,void * buf,unsigned int size)789 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf,
790 unsigned int size)
791 {
792 struct ahci_cmd_hdr *hdr;
793 struct ahci_prdt_entry *prdt;
794 uint8_t *to;
795 unsigned int len;
796 int i;
797
798 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
799 len = size;
800 to = buf;
801 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
802 for (i = 0; i < hdr->prdtl && len; i++) {
803 uint8_t *ptr;
804 uint32_t dbcsz;
805 unsigned int sublen;
806
807 dbcsz = (prdt->dbc & DBCMASK) + 1;
808 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
809 sublen = MIN(len, dbcsz);
810 memcpy(to, ptr, sublen);
811 len -= sublen;
812 to += sublen;
813 prdt++;
814 }
815 return (size - len);
816 }
817
818 static void
ahci_handle_dsm_trim(struct ahci_port * p,int slot,uint8_t * cfis)819 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis)
820 {
821 uint32_t len;
822 int ncq;
823 uint8_t *buf;
824 unsigned int nread;
825
826 buf = NULL;
827 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
828 len = (uint16_t)cfis[13] << 8 | cfis[12];
829 len *= 512;
830 ncq = 0;
831 } else { /* ATA_SEND_FPDMA_QUEUED */
832 len = (uint16_t)cfis[11] << 8 | cfis[3];
833 len *= 512;
834 ncq = 1;
835 }
836
837 /* Support for only a single block is advertised via IDENTIFY. */
838 if (len > 512) {
839 goto invalid_command;
840 }
841
842 buf = malloc(len);
843 nread = read_prdt(p, slot, cfis, buf, len);
844 if (nread != len) {
845 goto invalid_command;
846 }
847 ahci_handle_next_trim(p, slot, cfis, buf, len, 0);
848 return;
849
850 invalid_command:
851 free(buf);
852 if (ncq) {
853 ahci_write_fis_d2h_ncq(p, slot);
854 ahci_write_fis_sdb(p, slot, cfis,
855 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
856 } else {
857 ahci_write_fis_d2h(p, slot, cfis,
858 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
859 }
860 }
861
862 static void
ahci_handle_next_trim(struct ahci_port * p,int slot,uint8_t * cfis,uint8_t * buf,uint32_t len,uint32_t done)863 ahci_handle_next_trim(struct ahci_port *p, int slot, uint8_t *cfis,
864 uint8_t *buf, uint32_t len, uint32_t done)
865 {
866 struct ahci_ioreq *aior;
867 struct blockif_req *breq;
868 uint8_t *entry;
869 uint64_t elba;
870 uint32_t elen;
871 int err;
872 bool first, ncq;
873
874 first = (done == 0);
875 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
876 ncq = false;
877 } else { /* ATA_SEND_FPDMA_QUEUED */
878 ncq = true;
879 }
880
881 /* Find the next range to TRIM. */
882 while (done < len) {
883 entry = &buf[done];
884 elba = ((uint64_t)entry[5] << 40) |
885 ((uint64_t)entry[4] << 32) |
886 ((uint64_t)entry[3] << 24) |
887 ((uint64_t)entry[2] << 16) |
888 ((uint64_t)entry[1] << 8) |
889 entry[0];
890 elen = (uint16_t)entry[7] << 8 | entry[6];
891 done += 8;
892 if (elen != 0)
893 break;
894 }
895
896 /* All remaining ranges were empty. */
897 if (done == len) {
898 free(buf);
899 if (ncq) {
900 if (first)
901 ahci_write_fis_d2h_ncq(p, slot);
902 ahci_write_fis_sdb(p, slot, cfis,
903 ATA_S_READY | ATA_S_DSC);
904 } else {
905 ahci_write_fis_d2h(p, slot, cfis,
906 ATA_S_READY | ATA_S_DSC);
907 }
908 if (!first) {
909 p->pending &= ~(1 << slot);
910 ahci_check_stopped(p);
911 ahci_handle_port(p);
912 }
913 return;
914 }
915
916 /*
917 * Pull request off free list
918 */
919 aior = STAILQ_FIRST(&p->iofhd);
920 assert(aior != NULL);
921 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
922 aior->cfis = cfis;
923 aior->slot = slot;
924 aior->len = len;
925 aior->done = done;
926 aior->dsm = buf;
927 aior->more = (len != done);
928
929 breq = &aior->io_req;
930 breq->br_offset = elba * blockif_sectsz(p->bctx);
931 breq->br_resid = elen * blockif_sectsz(p->bctx);
932
933 /*
934 * Mark this command in-flight.
935 */
936 p->pending |= 1 << slot;
937
938 /*
939 * Stuff request onto busy list
940 */
941 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
942
943 if (ncq && first)
944 ahci_write_fis_d2h_ncq(p, slot);
945
946 err = blockif_delete(p->bctx, breq);
947 assert(err == 0);
948 }
949
950 static inline void
write_prdt(struct ahci_port * p,int slot,uint8_t * cfis,void * buf,unsigned int size)951 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf,
952 unsigned int size)
953 {
954 struct ahci_cmd_hdr *hdr;
955 struct ahci_prdt_entry *prdt;
956 uint8_t *from;
957 unsigned int len;
958 int i;
959
960 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
961 len = size;
962 from = buf;
963 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
964 for (i = 0; i < hdr->prdtl && len; i++) {
965 uint8_t *ptr;
966 uint32_t dbcsz;
967 int sublen;
968
969 dbcsz = (prdt->dbc & DBCMASK) + 1;
970 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
971 sublen = MIN(len, dbcsz);
972 memcpy(ptr, from, sublen);
973 len -= sublen;
974 from += sublen;
975 prdt++;
976 }
977 hdr->prdbc = size - len;
978 }
979
980 static void
ahci_checksum(uint8_t * buf,int size)981 ahci_checksum(uint8_t *buf, int size)
982 {
983 int i;
984 uint8_t sum = 0;
985
986 for (i = 0; i < size - 1; i++)
987 sum += buf[i];
988 buf[size - 1] = 0x100 - sum;
989 }
990
991 static void
ahci_handle_read_log(struct ahci_port * p,int slot,uint8_t * cfis)992 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
993 {
994 struct ahci_cmd_hdr *hdr;
995 uint32_t buf[128];
996 uint8_t *buf8 = (uint8_t *)buf;
997 uint16_t *buf16 = (uint16_t *)buf;
998
999 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1000 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 ||
1001 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
1002 ahci_write_fis_d2h(p, slot, cfis,
1003 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1004 return;
1005 }
1006
1007 memset(buf, 0, sizeof(buf));
1008 if (cfis[4] == 0x00) { /* Log directory */
1009 buf16[0x00] = 1; /* Version -- 1 */
1010 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */
1011 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */
1012 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */
1013 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis));
1014 ahci_checksum(buf8, sizeof(buf));
1015 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */
1016 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) {
1017 buf[0x00] = 1; /* SFQ DSM supported */
1018 buf[0x01] = 1; /* SFQ DSM TRIM supported */
1019 }
1020 } else {
1021 ahci_write_fis_d2h(p, slot, cfis,
1022 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1023 return;
1024 }
1025
1026 if (cfis[2] == ATA_READ_LOG_EXT)
1027 ahci_write_fis_piosetup(p);
1028 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
1029 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1030 }
1031
1032 static void
handle_identify(struct ahci_port * p,int slot,uint8_t * cfis)1033 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1034 {
1035 struct ahci_cmd_hdr *hdr;
1036
1037 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1038 if (p->atapi || hdr->prdtl == 0) {
1039 ahci_write_fis_d2h(p, slot, cfis,
1040 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1041 } else {
1042 ahci_write_fis_piosetup(p);
1043 write_prdt(p, slot, cfis, (void*)&p->ata_ident, sizeof(struct ata_params));
1044 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1045 }
1046 }
1047
1048 static void
ata_identify_init(struct ahci_port * p,int atapi)1049 ata_identify_init(struct ahci_port* p, int atapi)
1050 {
1051 struct ata_params* ata_ident = &p->ata_ident;
1052
1053 if (atapi) {
1054 ata_ident->config = ATA_PROTO_ATAPI | ATA_ATAPI_TYPE_CDROM |
1055 ATA_ATAPI_REMOVABLE | ATA_DRQ_FAST;
1056 ata_ident->capabilities1 = ATA_SUPPORT_LBA |
1057 ATA_SUPPORT_DMA;
1058 ata_ident->capabilities2 = (1 << 14 | 1);
1059 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1060 ata_ident->obsolete62 = 0x3f;
1061 ata_ident->mwdmamodes = 7;
1062 if (p->xfermode & ATA_WDMA0)
1063 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1064 ata_ident->apiomodes = 3;
1065 ata_ident->mwdmamin = 0x0078;
1066 ata_ident->mwdmarec = 0x0078;
1067 ata_ident->pioblind = 0x0078;
1068 ata_ident->pioiordy = 0x0078;
1069 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
1070 ata_ident->satacapabilities2 = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
1071 ata_ident->satasupport = ATA_SUPPORT_NCQ_STREAM;
1072 ata_ident->version_major = 0x3f0;
1073 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1074 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1075 ata_ident->support.command2 = (1 << 14);
1076 ata_ident->support.extension = (1 << 14);
1077 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1078 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1079 ata_ident->enabled.extension = (1 << 14);
1080 ata_ident->udmamodes = 0x7f;
1081 if (p->xfermode & ATA_UDMA0)
1082 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1083 ata_ident->transport_major = 0x1020;
1084 ata_ident->integrity = 0x00a5;
1085 } else {
1086 uint64_t sectors;
1087 int sectsz, psectsz, psectoff, candelete, ro;
1088 uint16_t cyl;
1089 uint8_t sech, heads;
1090
1091 ro = blockif_is_ro(p->bctx);
1092 candelete = blockif_candelete(p->bctx);
1093 sectsz = blockif_sectsz(p->bctx);
1094 sectors = blockif_size(p->bctx) / sectsz;
1095 blockif_chs(p->bctx, &cyl, &heads, &sech);
1096 blockif_psectsz(p->bctx, &psectsz, &psectoff);
1097 ata_ident->config = ATA_DRQ_FAST;
1098 ata_ident->cylinders = cyl;
1099 ata_ident->heads = heads;
1100 ata_ident->sectors = sech;
1101
1102 ata_ident->sectors_intr = (0x8000 | 128);
1103 ata_ident->tcg = 0;
1104
1105 ata_ident->capabilities1 = ATA_SUPPORT_DMA |
1106 ATA_SUPPORT_LBA | ATA_SUPPORT_IORDY;
1107 ata_ident->capabilities2 = (1 << 14);
1108 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1109 if (p->mult_sectors)
1110 ata_ident->multi = (ATA_MULTI_VALID | p->mult_sectors);
1111 if (sectors <= 0x0fffffff) {
1112 ata_ident->lba_size_1 = sectors;
1113 ata_ident->lba_size_2 = (sectors >> 16);
1114 } else {
1115 ata_ident->lba_size_1 = 0xffff;
1116 ata_ident->lba_size_2 = 0x0fff;
1117 }
1118 ata_ident->mwdmamodes = 0x7;
1119 if (p->xfermode & ATA_WDMA0)
1120 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1121 ata_ident->apiomodes = 0x3;
1122 ata_ident->mwdmamin = 0x0078;
1123 ata_ident->mwdmarec = 0x0078;
1124 ata_ident->pioblind = 0x0078;
1125 ata_ident->pioiordy = 0x0078;
1126 ata_ident->support3 = 0;
1127 ata_ident->queue = 31;
1128 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
1129 ATA_SUPPORT_NCQ);
1130 ata_ident->satacapabilities2 = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
1131 (p->ssts & ATA_SS_SPD_MASK) >> 3);
1132 ata_ident->version_major = 0x3f0;
1133 ata_ident->version_minor = 0x28;
1134 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1135 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1136 ata_ident->support.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1137 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
1138 ata_ident->support.extension = (1 << 14);
1139 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1140 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1141 ata_ident->enabled.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1142 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
1143 ata_ident->enabled.extension = (1 << 14);
1144 ata_ident->udmamodes = 0x7f;
1145 if (p->xfermode & ATA_UDMA0)
1146 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1147 ata_ident->lba_size48_1 = sectors;
1148 ata_ident->lba_size48_2 = (sectors >> 16);
1149 ata_ident->lba_size48_3 = (sectors >> 32);
1150 ata_ident->lba_size48_4 = (sectors >> 48);
1151
1152 if (candelete && !ro) {
1153 ata_ident->support3 |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
1154 ata_ident->max_dsm_blocks = 1;
1155 ata_ident->support_dsm = ATA_SUPPORT_DSM_TRIM;
1156 }
1157 ata_ident->pss = ATA_PSS_VALID_VALUE;
1158 ata_ident->lsalign = 0x4000;
1159 if (psectsz > sectsz) {
1160 ata_ident->pss |= ATA_PSS_MULTLS;
1161 ata_ident->pss |= ffsl(psectsz / sectsz) - 1;
1162 ata_ident->lsalign |= (psectoff / sectsz);
1163 }
1164 if (sectsz > 512) {
1165 ata_ident->pss |= ATA_PSS_LSSABOVE512;
1166 ata_ident->lss_1 = sectsz / 2;
1167 ata_ident->lss_2 = ((sectsz / 2) >> 16);
1168 }
1169 ata_ident->support2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1170 ata_ident->enabled2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1171 ata_ident->transport_major = 0x1020;
1172 ata_ident->integrity = 0x00a5;
1173 }
1174 ahci_checksum((uint8_t*)ata_ident, sizeof(struct ata_params));
1175 }
1176
1177 static void
handle_atapi_identify(struct ahci_port * p,int slot,uint8_t * cfis)1178 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1179 {
1180 if (!p->atapi) {
1181 ahci_write_fis_d2h(p, slot, cfis,
1182 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1183 } else {
1184 ahci_write_fis_piosetup(p);
1185 write_prdt(p, slot, cfis, (void *)&p->ata_ident, sizeof(struct ata_params));
1186 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1187 }
1188 }
1189
1190 static void
atapi_inquiry(struct ahci_port * p,int slot,uint8_t * cfis)1191 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
1192 {
1193 uint8_t buf[36];
1194 uint8_t *acmd;
1195 unsigned int len;
1196 uint32_t tfd;
1197
1198 acmd = cfis + 0x40;
1199
1200 if (acmd[1] & 1) { /* VPD */
1201 if (acmd[2] == 0) { /* Supported VPD pages */
1202 buf[0] = 0x05;
1203 buf[1] = 0;
1204 buf[2] = 0;
1205 buf[3] = 1;
1206 buf[4] = 0;
1207 len = 4 + buf[3];
1208 } else {
1209 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1210 p->asc = 0x24;
1211 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1212 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1213 ahci_write_fis_d2h(p, slot, cfis, tfd);
1214 return;
1215 }
1216 } else {
1217 buf[0] = 0x05;
1218 buf[1] = 0x80;
1219 buf[2] = 0x00;
1220 buf[3] = 0x21;
1221 buf[4] = 31;
1222 buf[5] = 0;
1223 buf[6] = 0;
1224 buf[7] = 0;
1225 atapi_string(buf + 8, "BHYVE", 8);
1226 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1227 atapi_string(buf + 32, "001", 4);
1228 len = sizeof(buf);
1229 }
1230
1231 if (len > acmd[4])
1232 len = acmd[4];
1233 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1234 write_prdt(p, slot, cfis, buf, len);
1235 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1236 }
1237
1238 static void
atapi_read_capacity(struct ahci_port * p,int slot,uint8_t * cfis)1239 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1240 {
1241 uint8_t buf[8];
1242 uint64_t sectors;
1243
1244 sectors = blockif_size(p->bctx) / 2048;
1245 be32enc(buf, sectors - 1);
1246 be32enc(buf + 4, 2048);
1247 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1248 write_prdt(p, slot, cfis, buf, sizeof(buf));
1249 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1250 }
1251
1252 static void
atapi_read_toc(struct ahci_port * p,int slot,uint8_t * cfis)1253 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1254 {
1255 uint8_t *acmd;
1256 uint8_t format;
1257 unsigned int len;
1258
1259 acmd = cfis + 0x40;
1260
1261 len = be16dec(acmd + 7);
1262 format = acmd[9] >> 6;
1263 switch (format) {
1264 case 0:
1265 {
1266 size_t size;
1267 int msf;
1268 uint64_t sectors;
1269 uint8_t start_track, buf[20], *bp;
1270
1271 msf = (acmd[1] >> 1) & 1;
1272 start_track = acmd[6];
1273 if (start_track > 1 && start_track != 0xaa) {
1274 uint32_t tfd;
1275 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1276 p->asc = 0x24;
1277 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1278 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1279 ahci_write_fis_d2h(p, slot, cfis, tfd);
1280 return;
1281 }
1282 bp = buf + 2;
1283 *bp++ = 1;
1284 *bp++ = 1;
1285 if (start_track <= 1) {
1286 *bp++ = 0;
1287 *bp++ = 0x14;
1288 *bp++ = 1;
1289 *bp++ = 0;
1290 if (msf) {
1291 *bp++ = 0;
1292 lba_to_msf(bp, 0);
1293 bp += 3;
1294 } else {
1295 *bp++ = 0;
1296 *bp++ = 0;
1297 *bp++ = 0;
1298 *bp++ = 0;
1299 }
1300 }
1301 *bp++ = 0;
1302 *bp++ = 0x14;
1303 *bp++ = 0xaa;
1304 *bp++ = 0;
1305 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1306 sectors >>= 2;
1307 if (msf) {
1308 *bp++ = 0;
1309 lba_to_msf(bp, sectors);
1310 bp += 3;
1311 } else {
1312 be32enc(bp, sectors);
1313 bp += 4;
1314 }
1315 size = bp - buf;
1316 be16enc(buf, size - 2);
1317 if (len > size)
1318 len = size;
1319 write_prdt(p, slot, cfis, buf, len);
1320 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1321 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1322 break;
1323 }
1324 case 1:
1325 {
1326 uint8_t buf[12];
1327
1328 memset(buf, 0, sizeof(buf));
1329 buf[1] = 0xa;
1330 buf[2] = 0x1;
1331 buf[3] = 0x1;
1332 if (len > sizeof(buf))
1333 len = sizeof(buf);
1334 write_prdt(p, slot, cfis, buf, len);
1335 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1336 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1337 break;
1338 }
1339 case 2:
1340 {
1341 size_t size;
1342 int msf;
1343 uint64_t sectors;
1344 uint8_t *bp, buf[50];
1345
1346 msf = (acmd[1] >> 1) & 1;
1347 bp = buf + 2;
1348 *bp++ = 1;
1349 *bp++ = 1;
1350
1351 *bp++ = 1;
1352 *bp++ = 0x14;
1353 *bp++ = 0;
1354 *bp++ = 0xa0;
1355 *bp++ = 0;
1356 *bp++ = 0;
1357 *bp++ = 0;
1358 *bp++ = 0;
1359 *bp++ = 1;
1360 *bp++ = 0;
1361 *bp++ = 0;
1362
1363 *bp++ = 1;
1364 *bp++ = 0x14;
1365 *bp++ = 0;
1366 *bp++ = 0xa1;
1367 *bp++ = 0;
1368 *bp++ = 0;
1369 *bp++ = 0;
1370 *bp++ = 0;
1371 *bp++ = 1;
1372 *bp++ = 0;
1373 *bp++ = 0;
1374
1375 *bp++ = 1;
1376 *bp++ = 0x14;
1377 *bp++ = 0;
1378 *bp++ = 0xa2;
1379 *bp++ = 0;
1380 *bp++ = 0;
1381 *bp++ = 0;
1382 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1383 sectors >>= 2;
1384 if (msf) {
1385 *bp++ = 0;
1386 lba_to_msf(bp, sectors);
1387 bp += 3;
1388 } else {
1389 be32enc(bp, sectors);
1390 bp += 4;
1391 }
1392
1393 *bp++ = 1;
1394 *bp++ = 0x14;
1395 *bp++ = 0;
1396 *bp++ = 1;
1397 *bp++ = 0;
1398 *bp++ = 0;
1399 *bp++ = 0;
1400 if (msf) {
1401 *bp++ = 0;
1402 lba_to_msf(bp, 0);
1403 bp += 3;
1404 } else {
1405 *bp++ = 0;
1406 *bp++ = 0;
1407 *bp++ = 0;
1408 *bp++ = 0;
1409 }
1410
1411 size = bp - buf;
1412 be16enc(buf, size - 2);
1413 if (len > size)
1414 len = size;
1415 write_prdt(p, slot, cfis, buf, len);
1416 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1417 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1418 break;
1419 }
1420 default:
1421 {
1422 uint32_t tfd;
1423
1424 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1425 p->asc = 0x24;
1426 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1427 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1428 ahci_write_fis_d2h(p, slot, cfis, tfd);
1429 break;
1430 }
1431 }
1432 }
1433
1434 static void
atapi_report_luns(struct ahci_port * p,int slot,uint8_t * cfis)1435 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1436 {
1437 uint8_t buf[16];
1438
1439 memset(buf, 0, sizeof(buf));
1440 buf[3] = 8;
1441
1442 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1443 write_prdt(p, slot, cfis, buf, sizeof(buf));
1444 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1445 }
1446
1447 static void
atapi_read(struct ahci_port * p,int slot,uint8_t * cfis,uint32_t done)1448 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
1449 {
1450 struct ahci_ioreq *aior;
1451 struct ahci_cmd_hdr *hdr;
1452 struct ahci_prdt_entry *prdt;
1453 struct blockif_req *breq;
1454 uint8_t *acmd;
1455 uint64_t lba;
1456 uint32_t len;
1457 int err;
1458
1459 acmd = cfis + 0x40;
1460 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1461 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1462
1463 lba = be32dec(acmd + 2);
1464 if (acmd[0] == READ_10)
1465 len = be16dec(acmd + 7);
1466 else
1467 len = be32dec(acmd + 6);
1468 if (len == 0) {
1469 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1470 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1471 }
1472 lba *= 2048;
1473 len *= 2048;
1474
1475 /*
1476 * Pull request off free list
1477 */
1478 aior = STAILQ_FIRST(&p->iofhd);
1479 assert(aior != NULL);
1480 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1481 aior->cfis = cfis;
1482 aior->slot = slot;
1483 aior->len = len;
1484 aior->done = done;
1485 aior->readop = 1;
1486 breq = &aior->io_req;
1487 breq->br_offset = lba + done;
1488 ahci_build_iov(p, aior, prdt, hdr->prdtl);
1489
1490 /* Mark this command in-flight. */
1491 p->pending |= 1 << slot;
1492
1493 /* Stuff request onto busy list. */
1494 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1495
1496 err = blockif_read(p->bctx, breq);
1497 assert(err == 0);
1498 }
1499
1500 static void
atapi_request_sense(struct ahci_port * p,int slot,uint8_t * cfis)1501 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1502 {
1503 uint8_t buf[64];
1504 uint8_t *acmd;
1505 unsigned int len;
1506
1507 acmd = cfis + 0x40;
1508 len = acmd[4];
1509 if (len > sizeof(buf))
1510 len = sizeof(buf);
1511 memset(buf, 0, len);
1512 buf[0] = 0x70 | (1 << 7);
1513 buf[2] = p->sense_key;
1514 buf[7] = 10;
1515 buf[12] = p->asc;
1516 write_prdt(p, slot, cfis, buf, len);
1517 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1518 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1519 }
1520
1521 static void
atapi_start_stop_unit(struct ahci_port * p,int slot,uint8_t * cfis)1522 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1523 {
1524 uint8_t *acmd = cfis + 0x40;
1525 uint32_t tfd;
1526
1527 switch (acmd[4] & 3) {
1528 case 0:
1529 case 1:
1530 case 3:
1531 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1532 tfd = ATA_S_READY | ATA_S_DSC;
1533 break;
1534 case 2:
1535 /* TODO eject media */
1536 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1537 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1538 p->asc = 0x53;
1539 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1540 break;
1541 }
1542 ahci_write_fis_d2h(p, slot, cfis, tfd);
1543 }
1544
1545 static void
atapi_mode_sense(struct ahci_port * p,int slot,uint8_t * cfis)1546 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1547 {
1548 uint8_t *acmd;
1549 uint32_t tfd;
1550 uint8_t pc, code;
1551 unsigned int len;
1552
1553 acmd = cfis + 0x40;
1554 len = be16dec(acmd + 7);
1555 pc = acmd[2] >> 6;
1556 code = acmd[2] & 0x3f;
1557
1558 switch (pc) {
1559 case 0:
1560 switch (code) {
1561 case MODEPAGE_RW_ERROR_RECOVERY:
1562 {
1563 uint8_t buf[16];
1564
1565 if (len > sizeof(buf))
1566 len = sizeof(buf);
1567
1568 memset(buf, 0, sizeof(buf));
1569 be16enc(buf, 16 - 2);
1570 buf[2] = 0x70;
1571 buf[8] = 0x01;
1572 buf[9] = 16 - 10;
1573 buf[11] = 0x05;
1574 write_prdt(p, slot, cfis, buf, len);
1575 tfd = ATA_S_READY | ATA_S_DSC;
1576 break;
1577 }
1578 case MODEPAGE_CD_CAPABILITIES:
1579 {
1580 uint8_t buf[30];
1581
1582 if (len > sizeof(buf))
1583 len = sizeof(buf);
1584
1585 memset(buf, 0, sizeof(buf));
1586 be16enc(buf, 30 - 2);
1587 buf[2] = 0x70;
1588 buf[8] = 0x2A;
1589 buf[9] = 30 - 10;
1590 buf[10] = 0x08;
1591 buf[12] = 0x71;
1592 be16enc(&buf[18], 2);
1593 be16enc(&buf[20], 512);
1594 write_prdt(p, slot, cfis, buf, len);
1595 tfd = ATA_S_READY | ATA_S_DSC;
1596 break;
1597 }
1598 default:
1599 goto error;
1600 break;
1601 }
1602 break;
1603 case 3:
1604 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1605 p->asc = 0x39;
1606 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1607 break;
1608 error:
1609 case 1:
1610 case 2:
1611 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1612 p->asc = 0x24;
1613 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1614 break;
1615 }
1616 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1617 ahci_write_fis_d2h(p, slot, cfis, tfd);
1618 }
1619
1620 static void
atapi_get_event_status_notification(struct ahci_port * p,int slot,uint8_t * cfis)1621 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1622 uint8_t *cfis)
1623 {
1624 uint8_t *acmd;
1625 uint32_t tfd;
1626
1627 acmd = cfis + 0x40;
1628
1629 /* we don't support asynchronous operation */
1630 if (!(acmd[1] & 1)) {
1631 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1632 p->asc = 0x24;
1633 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1634 } else {
1635 uint8_t buf[8];
1636 unsigned int len;
1637
1638 len = be16dec(acmd + 7);
1639 if (len > sizeof(buf))
1640 len = sizeof(buf);
1641
1642 memset(buf, 0, sizeof(buf));
1643 be16enc(buf, 8 - 2);
1644 buf[2] = 0x04;
1645 buf[3] = 0x10;
1646 buf[5] = 0x02;
1647 write_prdt(p, slot, cfis, buf, len);
1648 tfd = ATA_S_READY | ATA_S_DSC;
1649 }
1650 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1651 ahci_write_fis_d2h(p, slot, cfis, tfd);
1652 }
1653
1654 static void
handle_packet_cmd(struct ahci_port * p,int slot,uint8_t * cfis)1655 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1656 {
1657 uint8_t *acmd;
1658
1659 acmd = cfis + 0x40;
1660
1661 #ifdef AHCI_DEBUG
1662 {
1663 int i;
1664 DPRINTF("ACMD:");
1665 for (i = 0; i < 16; i++)
1666 DPRINTF("%02x ", acmd[i]);
1667 DPRINTF("");
1668 }
1669 #endif
1670
1671 switch (acmd[0]) {
1672 case TEST_UNIT_READY:
1673 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1674 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1675 break;
1676 case INQUIRY:
1677 atapi_inquiry(p, slot, cfis);
1678 break;
1679 case READ_CAPACITY:
1680 atapi_read_capacity(p, slot, cfis);
1681 break;
1682 case PREVENT_ALLOW:
1683 /* TODO */
1684 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1685 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1686 break;
1687 case READ_TOC:
1688 atapi_read_toc(p, slot, cfis);
1689 break;
1690 case REPORT_LUNS:
1691 atapi_report_luns(p, slot, cfis);
1692 break;
1693 case READ_10:
1694 case READ_12:
1695 atapi_read(p, slot, cfis, 0);
1696 break;
1697 case REQUEST_SENSE:
1698 atapi_request_sense(p, slot, cfis);
1699 break;
1700 case START_STOP_UNIT:
1701 atapi_start_stop_unit(p, slot, cfis);
1702 break;
1703 case MODE_SENSE_10:
1704 atapi_mode_sense(p, slot, cfis);
1705 break;
1706 case GET_EVENT_STATUS_NOTIFICATION:
1707 atapi_get_event_status_notification(p, slot, cfis);
1708 break;
1709 default:
1710 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1711 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1712 p->asc = 0x20;
1713 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1714 ATA_S_READY | ATA_S_ERROR);
1715 break;
1716 }
1717 }
1718
1719 static void
ahci_handle_cmd(struct ahci_port * p,int slot,uint8_t * cfis)1720 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1721 {
1722
1723 p->tfd |= ATA_S_BUSY;
1724 switch (cfis[2]) {
1725 case ATA_ATA_IDENTIFY:
1726 handle_identify(p, slot, cfis);
1727 break;
1728 case ATA_SETFEATURES:
1729 {
1730 switch (cfis[3]) {
1731 case ATA_SF_ENAB_SATA_SF:
1732 switch (cfis[12]) {
1733 case ATA_SATA_SF_AN:
1734 p->tfd = ATA_S_DSC | ATA_S_READY;
1735 break;
1736 default:
1737 p->tfd = ATA_S_ERROR | ATA_S_READY;
1738 p->tfd |= (ATA_ERROR_ABORT << 8);
1739 break;
1740 }
1741 break;
1742 case ATA_SF_ENAB_WCACHE:
1743 case ATA_SF_DIS_WCACHE:
1744 case ATA_SF_ENAB_RCACHE:
1745 case ATA_SF_DIS_RCACHE:
1746 p->tfd = ATA_S_DSC | ATA_S_READY;
1747 break;
1748 case ATA_SF_SETXFER:
1749 {
1750 switch (cfis[12] & 0xf8) {
1751 case ATA_PIO:
1752 case ATA_PIO0:
1753 break;
1754 case ATA_WDMA0:
1755 case ATA_UDMA0:
1756 p->xfermode = (cfis[12] & 0x7);
1757 break;
1758 }
1759 p->tfd = ATA_S_DSC | ATA_S_READY;
1760 break;
1761 }
1762 default:
1763 p->tfd = ATA_S_ERROR | ATA_S_READY;
1764 p->tfd |= (ATA_ERROR_ABORT << 8);
1765 break;
1766 }
1767 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1768 break;
1769 }
1770 case ATA_SET_MULTI:
1771 if (cfis[12] != 0 &&
1772 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1773 p->tfd = ATA_S_ERROR | ATA_S_READY;
1774 p->tfd |= (ATA_ERROR_ABORT << 8);
1775 } else {
1776 p->mult_sectors = cfis[12];
1777 p->tfd = ATA_S_DSC | ATA_S_READY;
1778 }
1779 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1780 break;
1781 case ATA_READ:
1782 case ATA_WRITE:
1783 case ATA_READ48:
1784 case ATA_WRITE48:
1785 case ATA_READ_MUL:
1786 case ATA_WRITE_MUL:
1787 case ATA_READ_MUL48:
1788 case ATA_WRITE_MUL48:
1789 case ATA_READ_DMA:
1790 case ATA_WRITE_DMA:
1791 case ATA_READ_DMA48:
1792 case ATA_WRITE_DMA48:
1793 case ATA_READ_FPDMA_QUEUED:
1794 case ATA_WRITE_FPDMA_QUEUED:
1795 ahci_handle_rw(p, slot, cfis, 0);
1796 break;
1797 case ATA_FLUSHCACHE:
1798 case ATA_FLUSHCACHE48:
1799 ahci_handle_flush(p, slot, cfis);
1800 break;
1801 case ATA_DATA_SET_MANAGEMENT:
1802 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1803 cfis[13] == 0 && cfis[12] == 1) {
1804 ahci_handle_dsm_trim(p, slot, cfis);
1805 break;
1806 }
1807 ahci_write_fis_d2h(p, slot, cfis,
1808 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1809 break;
1810 case ATA_SEND_FPDMA_QUEUED:
1811 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1812 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1813 cfis[11] == 0 && cfis[3] == 1) {
1814 ahci_handle_dsm_trim(p, slot, cfis);
1815 break;
1816 }
1817 ahci_write_fis_d2h(p, slot, cfis,
1818 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1819 break;
1820 case ATA_READ_LOG_EXT:
1821 case ATA_READ_LOG_DMA_EXT:
1822 ahci_handle_read_log(p, slot, cfis);
1823 break;
1824 case ATA_SECURITY_FREEZE_LOCK:
1825 case ATA_SMART_CMD:
1826 case ATA_NOP:
1827 ahci_write_fis_d2h(p, slot, cfis,
1828 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1829 break;
1830 case ATA_CHECK_POWER_MODE:
1831 cfis[12] = 0xff; /* always on */
1832 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1833 break;
1834 case ATA_STANDBY_CMD:
1835 case ATA_STANDBY_IMMEDIATE:
1836 case ATA_IDLE_CMD:
1837 case ATA_IDLE_IMMEDIATE:
1838 case ATA_SLEEP:
1839 case ATA_READ_VERIFY:
1840 case ATA_READ_VERIFY48:
1841 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1842 break;
1843 case ATA_ATAPI_IDENTIFY:
1844 handle_atapi_identify(p, slot, cfis);
1845 break;
1846 case ATA_PACKET_CMD:
1847 if (!p->atapi) {
1848 ahci_write_fis_d2h(p, slot, cfis,
1849 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1850 } else
1851 handle_packet_cmd(p, slot, cfis);
1852 break;
1853 default:
1854 EPRINTLN("Unsupported cmd:%02x", cfis[2]);
1855 ahci_write_fis_d2h(p, slot, cfis,
1856 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1857 break;
1858 }
1859 }
1860
1861 static void
ahci_handle_slot(struct ahci_port * p,int slot)1862 ahci_handle_slot(struct ahci_port *p, int slot)
1863 {
1864 struct ahci_cmd_hdr *hdr;
1865 #ifdef AHCI_DEBUG
1866 struct ahci_prdt_entry *prdt;
1867 #endif
1868 struct pci_ahci_softc *sc;
1869 uint8_t *cfis;
1870 #ifdef AHCI_DEBUG
1871 int cfl, i;
1872 #endif
1873
1874 sc = p->pr_sc;
1875 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1876 #ifdef AHCI_DEBUG
1877 cfl = (hdr->flags & 0x1f) * 4;
1878 #endif
1879 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1880 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1881 #ifdef AHCI_DEBUG
1882 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1883
1884 DPRINTF("cfis:");
1885 for (i = 0; i < cfl; i++) {
1886 if (i % 10 == 0)
1887 DPRINTF("");
1888 DPRINTF("%02x ", cfis[i]);
1889 }
1890 DPRINTF("");
1891
1892 for (i = 0; i < hdr->prdtl; i++) {
1893 DPRINTF("%d@%08"PRIx64"", prdt->dbc & 0x3fffff, prdt->dba);
1894 prdt++;
1895 }
1896 #endif
1897
1898 if (cfis[0] != FIS_TYPE_REGH2D) {
1899 EPRINTLN("Not a H2D FIS:%02x", cfis[0]);
1900 return;
1901 }
1902
1903 if (cfis[1] & 0x80) {
1904 ahci_handle_cmd(p, slot, cfis);
1905 } else {
1906 if (cfis[15] & (1 << 2))
1907 p->reset = 1;
1908 else if (p->reset) {
1909 p->reset = 0;
1910 ahci_port_reset(p);
1911 }
1912 p->ci &= ~(1 << slot);
1913 }
1914 }
1915
1916 static void
ahci_handle_port(struct ahci_port * p)1917 ahci_handle_port(struct ahci_port *p)
1918 {
1919
1920 if (!(p->cmd & AHCI_P_CMD_ST))
1921 return;
1922
1923 /*
1924 * Search for any new commands to issue ignoring those that
1925 * are already in-flight. Stop if device is busy or in error.
1926 */
1927 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) {
1928 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0)
1929 break;
1930 if (p->waitforclear)
1931 break;
1932 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) {
1933 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1934 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT;
1935 ahci_handle_slot(p, p->ccs);
1936 }
1937 }
1938 }
1939
1940 /*
1941 * blockif callback routine - this runs in the context of the blockif
1942 * i/o thread, so the mutex needs to be acquired.
1943 */
1944 static void
ata_ioreq_cb(struct blockif_req * br,int err)1945 ata_ioreq_cb(struct blockif_req *br, int err)
1946 {
1947 struct ahci_cmd_hdr *hdr;
1948 struct ahci_ioreq *aior;
1949 struct ahci_port *p;
1950 struct pci_ahci_softc *sc;
1951 uint32_t tfd;
1952 uint8_t *cfis, *dsm;
1953 int slot, ncq;
1954
1955 DPRINTF("%s %d", __func__, err);
1956
1957 ncq = 0;
1958 aior = br->br_param;
1959 p = aior->io_pr;
1960 cfis = aior->cfis;
1961 slot = aior->slot;
1962 sc = p->pr_sc;
1963 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1964
1965 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1966 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1967 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1968 ncq = 1;
1969 dsm = aior->dsm;
1970 aior->dsm = NULL;
1971
1972 pthread_mutex_lock(&sc->mtx);
1973
1974 /*
1975 * Delete the blockif request from the busy list
1976 */
1977 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1978
1979 /*
1980 * Move the blockif request back to the free list
1981 */
1982 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1983
1984 if (!err)
1985 hdr->prdbc = aior->done;
1986
1987 if (!err && aior->more) {
1988 if (dsm != NULL)
1989 ahci_handle_next_trim(p, slot, cfis, dsm,
1990 aior->len, aior->done);
1991 else
1992 ahci_handle_rw(p, slot, cfis, aior->done);
1993 goto out;
1994 }
1995
1996 if (!err)
1997 tfd = ATA_S_READY | ATA_S_DSC;
1998 else
1999 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
2000 if (ncq)
2001 ahci_write_fis_sdb(p, slot, cfis, tfd);
2002 else
2003 ahci_write_fis_d2h(p, slot, cfis, tfd);
2004
2005 /*
2006 * This command is now complete.
2007 */
2008 p->pending &= ~(1 << slot);
2009
2010 ahci_check_stopped(p);
2011 ahci_handle_port(p);
2012 free(dsm);
2013 out:
2014 pthread_mutex_unlock(&sc->mtx);
2015 DPRINTF("%s exit", __func__);
2016 }
2017
2018 static void
atapi_ioreq_cb(struct blockif_req * br,int err)2019 atapi_ioreq_cb(struct blockif_req *br, int err)
2020 {
2021 struct ahci_cmd_hdr *hdr;
2022 struct ahci_ioreq *aior;
2023 struct ahci_port *p;
2024 struct pci_ahci_softc *sc;
2025 uint8_t *cfis;
2026 uint32_t tfd;
2027 int slot;
2028
2029 DPRINTF("%s %d", __func__, err);
2030
2031 aior = br->br_param;
2032 p = aior->io_pr;
2033 cfis = aior->cfis;
2034 slot = aior->slot;
2035 sc = p->pr_sc;
2036 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
2037
2038 pthread_mutex_lock(&sc->mtx);
2039
2040 /*
2041 * Delete the blockif request from the busy list
2042 */
2043 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
2044
2045 /*
2046 * Move the blockif request back to the free list
2047 */
2048 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
2049
2050 if (!err)
2051 hdr->prdbc = aior->done;
2052
2053 if (!err && aior->more) {
2054 atapi_read(p, slot, cfis, aior->done);
2055 goto out;
2056 }
2057
2058 if (!err) {
2059 tfd = ATA_S_READY | ATA_S_DSC;
2060 } else {
2061 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
2062 p->asc = 0x21;
2063 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
2064 }
2065 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
2066 ahci_write_fis_d2h(p, slot, cfis, tfd);
2067
2068 /*
2069 * This command is now complete.
2070 */
2071 p->pending &= ~(1 << slot);
2072
2073 ahci_check_stopped(p);
2074 ahci_handle_port(p);
2075 out:
2076 pthread_mutex_unlock(&sc->mtx);
2077 DPRINTF("%s exit", __func__);
2078 }
2079
2080 static void
pci_ahci_ioreq_init(struct ahci_port * pr)2081 pci_ahci_ioreq_init(struct ahci_port *pr)
2082 {
2083 struct ahci_ioreq *vr;
2084 int i;
2085
2086 pr->ioqsz = blockif_queuesz(pr->bctx);
2087 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
2088 STAILQ_INIT(&pr->iofhd);
2089
2090 /*
2091 * Add all i/o request entries to the free queue
2092 */
2093 for (i = 0; i < pr->ioqsz; i++) {
2094 vr = &pr->ioreq[i];
2095 vr->io_pr = pr;
2096 if (!pr->atapi)
2097 vr->io_req.br_callback = ata_ioreq_cb;
2098 else
2099 vr->io_req.br_callback = atapi_ioreq_cb;
2100 vr->io_req.br_param = vr;
2101 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
2102 }
2103
2104 TAILQ_INIT(&pr->iobhd);
2105 }
2106
2107 static void
pci_ahci_port_write(struct pci_ahci_softc * sc,uint64_t offset,uint64_t value)2108 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2109 {
2110 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2111 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2112 struct ahci_port *p = &sc->port[port];
2113
2114 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2115 port, offset, value);
2116
2117 switch (offset) {
2118 case AHCI_P_CLB:
2119 p->clb = value;
2120 break;
2121 case AHCI_P_CLBU:
2122 p->clbu = value;
2123 break;
2124 case AHCI_P_FB:
2125 p->fb = value;
2126 break;
2127 case AHCI_P_FBU:
2128 p->fbu = value;
2129 break;
2130 case AHCI_P_IS:
2131 p->is &= ~value;
2132 ahci_port_intr(p);
2133 break;
2134 case AHCI_P_IE:
2135 p->ie = value & 0xFDC000FF;
2136 ahci_port_intr(p);
2137 break;
2138 case AHCI_P_CMD:
2139 {
2140 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2141 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2142 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2143 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK);
2144 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2145 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2146 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2147 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value;
2148
2149 if (!(value & AHCI_P_CMD_ST)) {
2150 ahci_port_stop(p);
2151 } else {
2152 uint64_t clb;
2153
2154 p->cmd |= AHCI_P_CMD_CR;
2155 clb = (uint64_t)p->clbu << 32 | p->clb;
2156 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
2157 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
2158 }
2159
2160 if (value & AHCI_P_CMD_FRE) {
2161 uint64_t fb;
2162
2163 p->cmd |= AHCI_P_CMD_FR;
2164 fb = (uint64_t)p->fbu << 32 | p->fb;
2165 /* we don't support FBSCP, so rfis size is 256Bytes */
2166 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
2167 } else {
2168 p->cmd &= ~AHCI_P_CMD_FR;
2169 }
2170
2171 if (value & AHCI_P_CMD_CLO) {
2172 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ);
2173 p->cmd &= ~AHCI_P_CMD_CLO;
2174 }
2175
2176 if (value & AHCI_P_CMD_ICC_MASK) {
2177 p->cmd &= ~AHCI_P_CMD_ICC_MASK;
2178 }
2179
2180 ahci_handle_port(p);
2181 break;
2182 }
2183 case AHCI_P_TFD:
2184 case AHCI_P_SIG:
2185 case AHCI_P_SSTS:
2186 EPRINTLN("pci_ahci_port: read only registers 0x%"PRIx64"", offset);
2187 break;
2188 case AHCI_P_SCTL:
2189 p->sctl = value;
2190 if (!(p->cmd & AHCI_P_CMD_ST)) {
2191 if (value & ATA_SC_DET_RESET)
2192 ahci_port_reset(p);
2193 }
2194 break;
2195 case AHCI_P_SERR:
2196 p->serr &= ~value;
2197 break;
2198 case AHCI_P_SACT:
2199 p->sact |= value;
2200 break;
2201 case AHCI_P_CI:
2202 p->ci |= value;
2203 ahci_handle_port(p);
2204 break;
2205 case AHCI_P_SNTF:
2206 case AHCI_P_FBS:
2207 default:
2208 break;
2209 }
2210 }
2211
2212 static void
pci_ahci_host_write(struct pci_ahci_softc * sc,uint64_t offset,uint64_t value)2213 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2214 {
2215 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2216 offset, value);
2217
2218 switch (offset) {
2219 case AHCI_CAP:
2220 case AHCI_PI:
2221 case AHCI_VS:
2222 case AHCI_CAP2:
2223 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"", offset);
2224 break;
2225 case AHCI_GHC:
2226 if (value & AHCI_GHC_HR) {
2227 ahci_reset(sc);
2228 break;
2229 }
2230 if (value & AHCI_GHC_IE)
2231 sc->ghc |= AHCI_GHC_IE;
2232 else
2233 sc->ghc &= ~AHCI_GHC_IE;
2234 ahci_generate_intr(sc, 0xffffffff);
2235 break;
2236 case AHCI_IS:
2237 sc->is &= ~value;
2238 ahci_generate_intr(sc, value);
2239 break;
2240 default:
2241 break;
2242 }
2243 }
2244
2245 static void
pci_ahci_write(struct pci_devinst * pi,int baridx,uint64_t offset,int size,uint64_t value)2246 pci_ahci_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
2247 uint64_t value)
2248 {
2249 struct pci_ahci_softc *sc = pi->pi_arg;
2250
2251 assert(baridx == 5);
2252 assert((offset % 4) == 0 && size == 4);
2253
2254 pthread_mutex_lock(&sc->mtx);
2255
2256 if (offset < AHCI_OFFSET)
2257 pci_ahci_host_write(sc, offset, value);
2258 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP)
2259 pci_ahci_port_write(sc, offset, value);
2260 else
2261 EPRINTLN("pci_ahci: unknown i/o write offset 0x%"PRIx64"", offset);
2262
2263 pthread_mutex_unlock(&sc->mtx);
2264 }
2265
2266 static uint64_t
pci_ahci_host_read(struct pci_ahci_softc * sc,uint64_t offset)2267 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2268 {
2269 uint32_t value;
2270
2271 switch (offset) {
2272 case AHCI_CAP:
2273 case AHCI_GHC:
2274 case AHCI_IS:
2275 case AHCI_PI:
2276 case AHCI_VS:
2277 case AHCI_CCCC:
2278 case AHCI_CCCP:
2279 case AHCI_EM_LOC:
2280 case AHCI_EM_CTL:
2281 case AHCI_CAP2:
2282 {
2283 uint32_t *p = &sc->cap;
2284 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2285 value = *p;
2286 break;
2287 }
2288 default:
2289 value = 0;
2290 break;
2291 }
2292 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x",
2293 offset, value);
2294
2295 return (value);
2296 }
2297
2298 static uint64_t
pci_ahci_port_read(struct pci_ahci_softc * sc,uint64_t offset)2299 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2300 {
2301 uint32_t value;
2302 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2303 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2304
2305 switch (offset) {
2306 case AHCI_P_CLB:
2307 case AHCI_P_CLBU:
2308 case AHCI_P_FB:
2309 case AHCI_P_FBU:
2310 case AHCI_P_IS:
2311 case AHCI_P_IE:
2312 case AHCI_P_CMD:
2313 case AHCI_P_TFD:
2314 case AHCI_P_SIG:
2315 case AHCI_P_SSTS:
2316 case AHCI_P_SCTL:
2317 case AHCI_P_SERR:
2318 case AHCI_P_SACT:
2319 case AHCI_P_CI:
2320 case AHCI_P_SNTF:
2321 case AHCI_P_FBS:
2322 {
2323 uint32_t *p= &sc->port[port].clb;
2324 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2325 value = *p;
2326 break;
2327 }
2328 default:
2329 value = 0;
2330 break;
2331 }
2332
2333 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x",
2334 port, offset, value);
2335
2336 return value;
2337 }
2338
2339 static uint64_t
pci_ahci_read(struct pci_devinst * pi,int baridx,uint64_t regoff,int size)2340 pci_ahci_read(struct pci_devinst *pi, int baridx, uint64_t regoff, int size)
2341 {
2342 struct pci_ahci_softc *sc = pi->pi_arg;
2343 uint64_t offset;
2344 uint32_t value;
2345
2346 assert(baridx == 5);
2347 assert(size == 1 || size == 2 || size == 4);
2348 assert((regoff & (size - 1)) == 0);
2349
2350 pthread_mutex_lock(&sc->mtx);
2351
2352 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */
2353 if (offset < AHCI_OFFSET)
2354 value = pci_ahci_host_read(sc, offset);
2355 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP)
2356 value = pci_ahci_port_read(sc, offset);
2357 else {
2358 value = 0;
2359 EPRINTLN("pci_ahci: unknown i/o read offset 0x%"PRIx64"",
2360 regoff);
2361 }
2362 value >>= 8 * (regoff & 0x3);
2363
2364 pthread_mutex_unlock(&sc->mtx);
2365
2366 return (value);
2367 }
2368
2369 /*
2370 * Each AHCI controller has a "port" node which contains nodes for
2371 * each port named after the decimal number of the port (no leading
2372 * zeroes). Port nodes contain a "type" ("hd" or "cd"), as well as
2373 * options for blockif. For example:
2374 *
2375 * pci.0.1.0
2376 * .device="ahci"
2377 * .port
2378 * .0
2379 * .type="hd"
2380 * .path="/path/to/image"
2381 */
2382 static int
pci_ahci_legacy_config_port(nvlist_t * nvl,int port,const char * type,const char * opts)2383 pci_ahci_legacy_config_port(nvlist_t *nvl, int port, const char *type,
2384 const char *opts)
2385 {
2386 char node_name[sizeof("XX")];
2387 nvlist_t *port_nvl;
2388
2389 snprintf(node_name, sizeof(node_name), "%d", port);
2390 port_nvl = create_relative_config_node(nvl, node_name);
2391 set_config_value_node(port_nvl, "type", type);
2392 return (blockif_legacy_config(port_nvl, opts));
2393 }
2394
2395 static int
pci_ahci_legacy_config(nvlist_t * nvl,const char * opts)2396 pci_ahci_legacy_config(nvlist_t *nvl, const char *opts)
2397 {
2398 nvlist_t *ports_nvl;
2399 const char *type;
2400 char *next, *next2, *str, *tofree;
2401 int p, ret;
2402
2403 if (opts == NULL)
2404 return (0);
2405
2406 ports_nvl = create_relative_config_node(nvl, "port");
2407 ret = 1;
2408 tofree = str = strdup(opts);
2409 for (p = 0; p < MAX_PORTS && str != NULL; p++, str = next) {
2410 /* Identify and cut off type of present port. */
2411 if (strncmp(str, "hd:", 3) == 0) {
2412 type = "hd";
2413 str += 3;
2414 } else if (strncmp(str, "cd:", 3) == 0) {
2415 type = "cd";
2416 str += 3;
2417 } else
2418 type = NULL;
2419
2420 /* Find and cut off the next port options. */
2421 next = strstr(str, ",hd:");
2422 next2 = strstr(str, ",cd:");
2423 if (next == NULL || (next2 != NULL && next2 < next))
2424 next = next2;
2425 if (next != NULL) {
2426 next[0] = 0;
2427 next++;
2428 }
2429
2430 if (str[0] == 0)
2431 continue;
2432
2433 if (type == NULL) {
2434 EPRINTLN("Missing or invalid type for port %d: \"%s\"",
2435 p, str);
2436 goto out;
2437 }
2438
2439 if (pci_ahci_legacy_config_port(ports_nvl, p, type, str) != 0)
2440 goto out;
2441 }
2442 ret = 0;
2443 out:
2444 free(tofree);
2445 return (ret);
2446 }
2447
2448 static int
pci_ahci_cd_legacy_config(nvlist_t * nvl,const char * opts)2449 pci_ahci_cd_legacy_config(nvlist_t *nvl, const char *opts)
2450 {
2451 nvlist_t *ports_nvl;
2452
2453 ports_nvl = create_relative_config_node(nvl, "port");
2454 return (pci_ahci_legacy_config_port(ports_nvl, 0, "cd", opts));
2455 }
2456
2457 static int
pci_ahci_hd_legacy_config(nvlist_t * nvl,const char * opts)2458 pci_ahci_hd_legacy_config(nvlist_t *nvl, const char *opts)
2459 {
2460 nvlist_t *ports_nvl;
2461
2462 ports_nvl = create_relative_config_node(nvl, "port");
2463 return (pci_ahci_legacy_config_port(ports_nvl, 0, "hd", opts));
2464 }
2465
2466 static int
pci_ahci_init(struct pci_devinst * pi,nvlist_t * nvl)2467 pci_ahci_init(struct pci_devinst *pi, nvlist_t *nvl)
2468 {
2469 char bident[sizeof("XXX:XXX:XXX")];
2470 char node_name[sizeof("XX")];
2471 struct blockif_ctxt *bctxt;
2472 struct pci_ahci_softc *sc;
2473 int atapi, ret, slots, p;
2474 MD5_CTX mdctx;
2475 u_char digest[16];
2476 const char *path, *type, *value;
2477 nvlist_t *ports_nvl, *port_nvl;
2478
2479 ret = 0;
2480
2481 #ifdef AHCI_DEBUG
2482 dbg = fopen("/tmp/log", "w+");
2483 #endif
2484
2485 sc = calloc(1, sizeof(struct pci_ahci_softc));
2486 pi->pi_arg = sc;
2487 sc->asc_pi = pi;
2488 pthread_mutex_init(&sc->mtx, NULL);
2489 sc->ports = 0;
2490 sc->pi = 0;
2491 slots = 32;
2492
2493 ports_nvl = find_relative_config_node(nvl, "port");
2494 for (p = 0; ports_nvl != NULL && p < MAX_PORTS; p++) {
2495 struct ata_params *ata_ident = &sc->port[p].ata_ident;
2496 char ident[AHCI_PORT_IDENT];
2497
2498 snprintf(node_name, sizeof(node_name), "%d", p);
2499 port_nvl = find_relative_config_node(ports_nvl, node_name);
2500 if (port_nvl == NULL)
2501 continue;
2502
2503 type = get_config_value_node(port_nvl, "type");
2504 if (type == NULL)
2505 continue;
2506
2507 if (strcmp(type, "hd") == 0)
2508 atapi = 0;
2509 else
2510 atapi = 1;
2511
2512 /*
2513 * Attempt to open the backing image. Use the PCI slot/func
2514 * and the port number for the identifier string.
2515 */
2516 snprintf(bident, sizeof(bident), "%u:%u:%u", pi->pi_slot,
2517 pi->pi_func, p);
2518
2519 bctxt = blockif_open(port_nvl, bident);
2520 if (bctxt == NULL) {
2521 sc->ports = p;
2522 ret = 1;
2523 goto open_fail;
2524 }
2525
2526 ret = blockif_add_boot_device(pi, bctxt);
2527 if (ret) {
2528 sc->ports = p;
2529 goto open_fail;
2530 }
2531
2532 sc->port[p].bctx = bctxt;
2533 sc->port[p].pr_sc = sc;
2534 sc->port[p].port = p;
2535 sc->port[p].atapi = atapi;
2536
2537 /*
2538 * Create an identifier for the backing file.
2539 * Use parts of the md5 sum of the filename
2540 */
2541 path = get_config_value_node(port_nvl, "path");
2542 MD5Init(&mdctx);
2543 MD5Update(&mdctx, path, strlen(path));
2544 MD5Final(digest, &mdctx);
2545 snprintf(ident, AHCI_PORT_IDENT,
2546 "BHYVE-%02X%02X-%02X%02X-%02X%02X",
2547 digest[0], digest[1], digest[2], digest[3], digest[4],
2548 digest[5]);
2549
2550 memset(ata_ident, 0, sizeof(struct ata_params));
2551 ata_string((uint8_t*)&ata_ident->serial, ident, 20);
2552 ata_string((uint8_t*)&ata_ident->revision, "001", 8);
2553 if (atapi)
2554 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DVD ROM", 40);
2555 else
2556 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DISK", 40);
2557 value = get_config_value_node(port_nvl, "nmrr");
2558 if (value != NULL)
2559 ata_ident->media_rotation_rate = atoi(value);
2560 value = get_config_value_node(port_nvl, "ser");
2561 if (value != NULL)
2562 ata_string((uint8_t*)(&ata_ident->serial), value, 20);
2563 value = get_config_value_node(port_nvl, "rev");
2564 if (value != NULL)
2565 ata_string((uint8_t*)(&ata_ident->revision), value, 8);
2566 value = get_config_value_node(port_nvl, "model");
2567 if (value != NULL)
2568 ata_string((uint8_t*)(&ata_ident->model), value, 40);
2569 ata_identify_init(&sc->port[p], atapi);
2570
2571 /*
2572 * Allocate blockif request structures and add them
2573 * to the free list
2574 */
2575 pci_ahci_ioreq_init(&sc->port[p]);
2576
2577 sc->pi |= (1 << p);
2578 if (sc->port[p].ioqsz < slots)
2579 slots = sc->port[p].ioqsz;
2580 }
2581 sc->ports = p;
2582
2583 /* Intel ICH8 AHCI */
2584 --slots;
2585 if (sc->ports < DEF_PORTS)
2586 sc->ports = DEF_PORTS;
2587 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2588 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2589 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2590 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2591 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2592
2593 sc->vs = 0x10300;
2594 sc->cap2 = AHCI_CAP2_APST;
2595 ahci_reset(sc);
2596
2597 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2598 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2599 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2600 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2601 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2602 p = MIN(sc->ports, 16);
2603 p = flsl(p) - ((p & (p - 1)) ? 0 : 1);
2604 pci_emul_add_msicap(pi, 1 << p);
2605 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2606 AHCI_OFFSET + sc->ports * AHCI_STEP);
2607
2608 pci_lintr_request(pi);
2609
2610 open_fail:
2611 if (ret) {
2612 for (p = 0; p < sc->ports; p++) {
2613 if (sc->port[p].bctx != NULL)
2614 blockif_close(sc->port[p].bctx);
2615 }
2616 free(sc);
2617 }
2618
2619 return (ret);
2620 }
2621
2622 #ifdef BHYVE_SNAPSHOT
2623 static int
pci_ahci_snapshot(struct vm_snapshot_meta * meta)2624 pci_ahci_snapshot(struct vm_snapshot_meta *meta)
2625 {
2626 int i, ret;
2627 void *bctx;
2628 struct pci_devinst *pi;
2629 struct pci_ahci_softc *sc;
2630 struct ahci_port *port;
2631
2632 pi = meta->dev_data;
2633 sc = pi->pi_arg;
2634
2635 /* TODO: add mtx lock/unlock */
2636
2637 SNAPSHOT_VAR_OR_LEAVE(sc->ports, meta, ret, done);
2638 SNAPSHOT_VAR_OR_LEAVE(sc->cap, meta, ret, done);
2639 SNAPSHOT_VAR_OR_LEAVE(sc->ghc, meta, ret, done);
2640 SNAPSHOT_VAR_OR_LEAVE(sc->is, meta, ret, done);
2641 SNAPSHOT_VAR_OR_LEAVE(sc->pi, meta, ret, done);
2642 SNAPSHOT_VAR_OR_LEAVE(sc->vs, meta, ret, done);
2643 SNAPSHOT_VAR_OR_LEAVE(sc->ccc_ctl, meta, ret, done);
2644 SNAPSHOT_VAR_OR_LEAVE(sc->ccc_pts, meta, ret, done);
2645 SNAPSHOT_VAR_OR_LEAVE(sc->em_loc, meta, ret, done);
2646 SNAPSHOT_VAR_OR_LEAVE(sc->em_ctl, meta, ret, done);
2647 SNAPSHOT_VAR_OR_LEAVE(sc->cap2, meta, ret, done);
2648 SNAPSHOT_VAR_OR_LEAVE(sc->bohc, meta, ret, done);
2649 SNAPSHOT_VAR_OR_LEAVE(sc->lintr, meta, ret, done);
2650
2651 for (i = 0; i < MAX_PORTS; i++) {
2652 port = &sc->port[i];
2653
2654 if (meta->op == VM_SNAPSHOT_SAVE)
2655 bctx = port->bctx;
2656
2657 SNAPSHOT_VAR_OR_LEAVE(bctx, meta, ret, done);
2658 SNAPSHOT_VAR_OR_LEAVE(port->port, meta, ret, done);
2659
2660 /* Mostly for restore; save is ensured by the lines above. */
2661 if (((bctx == NULL) && (port->bctx != NULL)) ||
2662 ((bctx != NULL) && (port->bctx == NULL))) {
2663 EPRINTLN("%s: ports not matching", __func__);
2664 ret = EINVAL;
2665 goto done;
2666 }
2667
2668 if (port->bctx == NULL)
2669 continue;
2670
2671 if (port->port != i) {
2672 EPRINTLN("%s: ports not matching: "
2673 "actual: %d expected: %d", __func__, port->port, i);
2674 ret = EINVAL;
2675 goto done;
2676 }
2677
2678 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, port->cmd_lst,
2679 AHCI_CL_SIZE * AHCI_MAX_SLOTS, false, meta, ret, done);
2680 SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(pi->pi_vmctx, port->rfis, 256,
2681 false, meta, ret, done);
2682
2683 SNAPSHOT_VAR_OR_LEAVE(port->ata_ident, meta, ret, done);
2684 SNAPSHOT_VAR_OR_LEAVE(port->atapi, meta, ret, done);
2685 SNAPSHOT_VAR_OR_LEAVE(port->reset, meta, ret, done);
2686 SNAPSHOT_VAR_OR_LEAVE(port->waitforclear, meta, ret, done);
2687 SNAPSHOT_VAR_OR_LEAVE(port->mult_sectors, meta, ret, done);
2688 SNAPSHOT_VAR_OR_LEAVE(port->xfermode, meta, ret, done);
2689 SNAPSHOT_VAR_OR_LEAVE(port->err_cfis, meta, ret, done);
2690 SNAPSHOT_VAR_OR_LEAVE(port->sense_key, meta, ret, done);
2691 SNAPSHOT_VAR_OR_LEAVE(port->asc, meta, ret, done);
2692 SNAPSHOT_VAR_OR_LEAVE(port->ccs, meta, ret, done);
2693 SNAPSHOT_VAR_OR_LEAVE(port->pending, meta, ret, done);
2694
2695 SNAPSHOT_VAR_OR_LEAVE(port->clb, meta, ret, done);
2696 SNAPSHOT_VAR_OR_LEAVE(port->clbu, meta, ret, done);
2697 SNAPSHOT_VAR_OR_LEAVE(port->fb, meta, ret, done);
2698 SNAPSHOT_VAR_OR_LEAVE(port->fbu, meta, ret, done);
2699 SNAPSHOT_VAR_OR_LEAVE(port->ie, meta, ret, done);
2700 SNAPSHOT_VAR_OR_LEAVE(port->cmd, meta, ret, done);
2701 SNAPSHOT_VAR_OR_LEAVE(port->unused0, meta, ret, done);
2702 SNAPSHOT_VAR_OR_LEAVE(port->tfd, meta, ret, done);
2703 SNAPSHOT_VAR_OR_LEAVE(port->sig, meta, ret, done);
2704 SNAPSHOT_VAR_OR_LEAVE(port->ssts, meta, ret, done);
2705 SNAPSHOT_VAR_OR_LEAVE(port->sctl, meta, ret, done);
2706 SNAPSHOT_VAR_OR_LEAVE(port->serr, meta, ret, done);
2707 SNAPSHOT_VAR_OR_LEAVE(port->sact, meta, ret, done);
2708 SNAPSHOT_VAR_OR_LEAVE(port->ci, meta, ret, done);
2709 SNAPSHOT_VAR_OR_LEAVE(port->sntf, meta, ret, done);
2710 SNAPSHOT_VAR_OR_LEAVE(port->fbs, meta, ret, done);
2711 SNAPSHOT_VAR_OR_LEAVE(port->ioqsz, meta, ret, done);
2712
2713 assert(TAILQ_EMPTY(&port->iobhd));
2714 }
2715
2716 done:
2717 return (ret);
2718 }
2719
2720 static int
pci_ahci_pause(struct pci_devinst * pi)2721 pci_ahci_pause(struct pci_devinst *pi)
2722 {
2723 struct pci_ahci_softc *sc;
2724 struct blockif_ctxt *bctxt;
2725 int i;
2726
2727 sc = pi->pi_arg;
2728
2729 for (i = 0; i < MAX_PORTS; i++) {
2730 bctxt = sc->port[i].bctx;
2731 if (bctxt == NULL)
2732 continue;
2733
2734 blockif_pause(bctxt);
2735 }
2736
2737 return (0);
2738 }
2739
2740 static int
pci_ahci_resume(struct pci_devinst * pi)2741 pci_ahci_resume(struct pci_devinst *pi)
2742 {
2743 struct pci_ahci_softc *sc;
2744 struct blockif_ctxt *bctxt;
2745 int i;
2746
2747 sc = pi->pi_arg;
2748
2749 for (i = 0; i < MAX_PORTS; i++) {
2750 bctxt = sc->port[i].bctx;
2751 if (bctxt == NULL)
2752 continue;
2753
2754 blockif_resume(bctxt);
2755 }
2756
2757 return (0);
2758 }
2759 #endif /* BHYVE_SNAPSHOT */
2760
2761 /*
2762 * Use separate emulation names to distinguish drive and atapi devices
2763 */
2764 static const struct pci_devemu pci_de_ahci = {
2765 .pe_emu = "ahci",
2766 .pe_init = pci_ahci_init,
2767 .pe_legacy_config = pci_ahci_legacy_config,
2768 .pe_barwrite = pci_ahci_write,
2769 .pe_barread = pci_ahci_read,
2770 #ifdef BHYVE_SNAPSHOT
2771 .pe_snapshot = pci_ahci_snapshot,
2772 .pe_pause = pci_ahci_pause,
2773 .pe_resume = pci_ahci_resume,
2774 #endif
2775 };
2776 PCI_EMUL_SET(pci_de_ahci);
2777
2778 static const struct pci_devemu pci_de_ahci_hd = {
2779 .pe_emu = "ahci-hd",
2780 .pe_legacy_config = pci_ahci_hd_legacy_config,
2781 .pe_alias = "ahci",
2782 };
2783 PCI_EMUL_SET(pci_de_ahci_hd);
2784
2785 static const struct pci_devemu pci_de_ahci_cd = {
2786 .pe_emu = "ahci-cd",
2787 .pe_legacy_config = pci_ahci_cd_legacy_config,
2788 .pe_alias = "ahci",
2789 };
2790 PCI_EMUL_SET(pci_de_ahci_cd);
2791