1 /*-
2 * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 #include "opt_rss.h"
29 #include "opt_ratelimit.h"
30
31 #include <linux/module.h>
32 #include <linux/errno.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/slab.h>
36 #if defined(CONFIG_X86)
37 #include <asm/pat.h>
38 #endif
39 #include <linux/sched.h>
40 #include <linux/delay.h>
41 #include <linux/fs.h>
42 #undef inode
43 #include <rdma/ib_user_verbs.h>
44 #include <rdma/ib_addr.h>
45 #include <rdma/ib_cache.h>
46 #include <dev/mlx5/port.h>
47 #include <dev/mlx5/vport.h>
48 #include <linux/list.h>
49 #include <rdma/ib_smi.h>
50 #include <rdma/ib_umem.h>
51 #include <linux/in.h>
52 #include <linux/etherdevice.h>
53 #include <dev/mlx5/fs.h>
54 #include <dev/mlx5/mlx5_ib/mlx5_ib.h>
55
56 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
57 MODULE_LICENSE("Dual BSD/GPL");
58 MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1);
59 MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1);
60 MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1);
61 MODULE_VERSION(mlx5ib, 1);
62
63 enum {
64 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
65 };
66
67 static enum rdma_link_layer
mlx5_port_type_cap_to_rdma_ll(int port_type_cap)68 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
69 {
70 switch (port_type_cap) {
71 case MLX5_CAP_PORT_TYPE_IB:
72 return IB_LINK_LAYER_INFINIBAND;
73 case MLX5_CAP_PORT_TYPE_ETH:
74 return IB_LINK_LAYER_ETHERNET;
75 default:
76 return IB_LINK_LAYER_UNSPECIFIED;
77 }
78 }
79
80 static enum rdma_link_layer
mlx5_ib_port_link_layer(struct ib_device * device,u8 port_num)81 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
82 {
83 struct mlx5_ib_dev *dev = to_mdev(device);
84 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
85
86 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
87 }
88
mlx5_netdev_match(struct ifnet * ndev,struct mlx5_core_dev * mdev,const char * dname)89 static bool mlx5_netdev_match(struct ifnet *ndev,
90 struct mlx5_core_dev *mdev,
91 const char *dname)
92 {
93 return ndev->if_type == IFT_ETHER &&
94 ndev->if_dname != NULL &&
95 strcmp(ndev->if_dname, dname) == 0 &&
96 ndev->if_softc != NULL &&
97 *(struct mlx5_core_dev **)ndev->if_softc == mdev;
98 }
99
mlx5_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)100 static int mlx5_netdev_event(struct notifier_block *this,
101 unsigned long event, void *ptr)
102 {
103 struct ifnet *ndev = netdev_notifier_info_to_ifp(ptr);
104 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
105 roce.nb);
106
107 switch (event) {
108 case NETDEV_REGISTER:
109 case NETDEV_UNREGISTER:
110 write_lock(&ibdev->roce.netdev_lock);
111 /* check if network interface belongs to mlx5en */
112 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce"))
113 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
114 NULL : ndev;
115 write_unlock(&ibdev->roce.netdev_lock);
116 break;
117
118 case NETDEV_UP:
119 case NETDEV_DOWN: {
120 struct ifnet *upper = NULL;
121
122 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
123 && ibdev->ib_active) {
124 struct ib_event ibev = {0};
125
126 ibev.device = &ibdev->ib_dev;
127 ibev.event = (event == NETDEV_UP) ?
128 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
129 ibev.element.port_num = 1;
130 ib_dispatch_event(&ibev);
131 }
132 break;
133 }
134
135 default:
136 break;
137 }
138
139 return NOTIFY_DONE;
140 }
141
mlx5_ib_get_netdev(struct ib_device * device,u8 port_num)142 static struct ifnet *mlx5_ib_get_netdev(struct ib_device *device,
143 u8 port_num)
144 {
145 struct mlx5_ib_dev *ibdev = to_mdev(device);
146 struct ifnet *ndev;
147
148 /* Ensure ndev does not disappear before we invoke if_ref()
149 */
150 read_lock(&ibdev->roce.netdev_lock);
151 ndev = ibdev->roce.netdev;
152 if (ndev)
153 if_ref(ndev);
154 read_unlock(&ibdev->roce.netdev_lock);
155
156 return ndev;
157 }
158
translate_eth_proto_oper(u32 eth_proto_oper,u8 * active_speed,u8 * active_width)159 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
160 u8 *active_width)
161 {
162 switch (eth_proto_oper) {
163 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
164 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
165 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
166 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
167 *active_width = IB_WIDTH_1X;
168 *active_speed = IB_SPEED_SDR;
169 break;
170 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
171 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
172 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
173 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
174 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
175 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
176 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER_LR):
177 *active_width = IB_WIDTH_1X;
178 *active_speed = IB_SPEED_QDR;
179 break;
180 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
181 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
182 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
183 *active_width = IB_WIDTH_1X;
184 *active_speed = IB_SPEED_EDR;
185 break;
186 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
187 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
188 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
189 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4_ER4):
190 *active_width = IB_WIDTH_4X;
191 *active_speed = IB_SPEED_QDR;
192 break;
193 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
194 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
195 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR4):
196 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
197 *active_width = IB_WIDTH_1X;
198 *active_speed = IB_SPEED_HDR;
199 break;
200 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
201 *active_width = IB_WIDTH_4X;
202 *active_speed = IB_SPEED_FDR;
203 break;
204 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
205 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
206 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
207 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
208 *active_width = IB_WIDTH_4X;
209 *active_speed = IB_SPEED_EDR;
210 break;
211 default:
212 *active_width = IB_WIDTH_4X;
213 *active_speed = IB_SPEED_QDR;
214 return -EINVAL;
215 }
216
217 return 0;
218 }
219
translate_eth_ext_proto_oper(u32 eth_proto_oper,u8 * active_speed,u8 * active_width)220 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
221 u8 *active_width)
222 {
223 switch (eth_proto_oper) {
224 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
225 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
226 *active_width = IB_WIDTH_1X;
227 *active_speed = IB_SPEED_SDR;
228 break;
229 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
230 *active_width = IB_WIDTH_1X;
231 *active_speed = IB_SPEED_DDR;
232 break;
233 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
234 *active_width = IB_WIDTH_1X;
235 *active_speed = IB_SPEED_QDR;
236 break;
237 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
238 *active_width = IB_WIDTH_4X;
239 *active_speed = IB_SPEED_QDR;
240 break;
241 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
242 *active_width = IB_WIDTH_1X;
243 *active_speed = IB_SPEED_EDR;
244 break;
245 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
246 *active_width = IB_WIDTH_2X;
247 *active_speed = IB_SPEED_EDR;
248 break;
249 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
250 *active_width = IB_WIDTH_1X;
251 *active_speed = IB_SPEED_HDR;
252 break;
253 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
254 *active_width = IB_WIDTH_4X;
255 *active_speed = IB_SPEED_EDR;
256 break;
257 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
258 *active_width = IB_WIDTH_2X;
259 *active_speed = IB_SPEED_HDR;
260 break;
261 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
262 *active_width = IB_WIDTH_1X;
263 *active_speed = IB_SPEED_NDR;
264 break;
265 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
266 *active_width = IB_WIDTH_4X;
267 *active_speed = IB_SPEED_HDR;
268 break;
269 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
270 *active_width = IB_WIDTH_2X;
271 *active_speed = IB_SPEED_NDR;
272 break;
273 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
274 *active_width = IB_WIDTH_4X;
275 *active_speed = IB_SPEED_NDR;
276 break;
277 default:
278 *active_width = IB_WIDTH_4X;
279 *active_speed = IB_SPEED_QDR;
280 return -EINVAL;
281 }
282
283 return 0;
284 }
285
mlx5_query_port_roce(struct ib_device * device,u8 port_num,struct ib_port_attr * props)286 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
287 struct ib_port_attr *props)
288 {
289 struct mlx5_ib_dev *dev = to_mdev(device);
290 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
291 struct ifnet *ndev;
292 enum ib_mtu ndev_ib_mtu;
293 u16 qkey_viol_cntr;
294 u32 eth_prot_oper;
295 bool ext;
296 int err;
297
298 memset(props, 0, sizeof(*props));
299
300 /* Possible bad flows are checked before filling out props so in case
301 * of an error it will still be zeroed out.
302 */
303 err = mlx5_query_port_ptys(dev->mdev, out, sizeof(out), MLX5_PTYS_EN,
304 port_num);
305 if (err)
306 return err;
307
308 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
309 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
310
311 if (ext)
312 translate_eth_ext_proto_oper(eth_prot_oper, &props->active_speed,
313 &props->active_width);
314 else
315 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
316 &props->active_width);
317
318 props->port_cap_flags |= IB_PORT_CM_SUP;
319 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
320
321 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
322 roce_address_table_size);
323 props->max_mtu = IB_MTU_4096;
324 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
325 props->pkey_tbl_len = 1;
326 props->state = IB_PORT_DOWN;
327 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
328
329 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
330 props->qkey_viol_cntr = qkey_viol_cntr;
331
332 ndev = mlx5_ib_get_netdev(device, port_num);
333 if (!ndev)
334 return 0;
335
336 if (ndev->if_drv_flags & IFF_DRV_RUNNING &&
337 ndev->if_link_state == LINK_STATE_UP) {
338 props->state = IB_PORT_ACTIVE;
339 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
340 }
341
342 ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu);
343
344 if_rele(ndev);
345
346 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
347 return 0;
348 }
349
ib_gid_to_mlx5_roce_addr(const union ib_gid * gid,const struct ib_gid_attr * attr,void * mlx5_addr)350 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
351 const struct ib_gid_attr *attr,
352 void *mlx5_addr)
353 {
354 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
355 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
356 source_l3_address);
357 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
358 source_mac_47_32);
359 u16 vlan_id;
360
361 if (!gid)
362 return;
363 ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev));
364
365 vlan_id = rdma_vlan_dev_vlan_id(attr->ndev);
366 if (vlan_id != 0xffff) {
367 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
368 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_id);
369 }
370
371 switch (attr->gid_type) {
372 case IB_GID_TYPE_IB:
373 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
374 break;
375 case IB_GID_TYPE_ROCE_UDP_ENCAP:
376 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
377 break;
378
379 default:
380 WARN_ON(true);
381 }
382
383 if (attr->gid_type != IB_GID_TYPE_IB) {
384 if (ipv6_addr_v4mapped((void *)gid))
385 MLX5_SET_RA(mlx5_addr, roce_l3_type,
386 MLX5_ROCE_L3_TYPE_IPV4);
387 else
388 MLX5_SET_RA(mlx5_addr, roce_l3_type,
389 MLX5_ROCE_L3_TYPE_IPV6);
390 }
391
392 if ((attr->gid_type == IB_GID_TYPE_IB) ||
393 !ipv6_addr_v4mapped((void *)gid))
394 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
395 else
396 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
397 }
398
set_roce_addr(struct ib_device * device,u8 port_num,unsigned int index,const union ib_gid * gid,const struct ib_gid_attr * attr)399 static int set_roce_addr(struct ib_device *device, u8 port_num,
400 unsigned int index,
401 const union ib_gid *gid,
402 const struct ib_gid_attr *attr)
403 {
404 struct mlx5_ib_dev *dev = to_mdev(device);
405 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
406 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
407 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
408 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
409
410 if (ll != IB_LINK_LAYER_ETHERNET)
411 return -EINVAL;
412
413 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
414
415 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
416 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
417 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
418 }
419
mlx5_ib_add_gid(struct ib_device * device,u8 port_num,unsigned int index,const union ib_gid * gid,const struct ib_gid_attr * attr,__always_unused void ** context)420 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
421 unsigned int index, const union ib_gid *gid,
422 const struct ib_gid_attr *attr,
423 __always_unused void **context)
424 {
425 return set_roce_addr(device, port_num, index, gid, attr);
426 }
427
mlx5_ib_del_gid(struct ib_device * device,u8 port_num,unsigned int index,__always_unused void ** context)428 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
429 unsigned int index, __always_unused void **context)
430 {
431 return set_roce_addr(device, port_num, index, NULL, NULL);
432 }
433
mlx5_get_roce_udp_sport(struct mlx5_ib_dev * dev,u8 port_num,int index)434 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
435 int index)
436 {
437 struct ib_gid_attr attr;
438 union ib_gid gid;
439
440 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
441 return 0;
442
443 if (!attr.ndev)
444 return 0;
445
446 if_rele(attr.ndev);
447
448 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
449 return 0;
450
451 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
452 }
453
mlx5_get_roce_gid_type(struct mlx5_ib_dev * dev,u8 port_num,int index,enum ib_gid_type * gid_type)454 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
455 int index, enum ib_gid_type *gid_type)
456 {
457 struct ib_gid_attr attr;
458 union ib_gid gid;
459 int ret;
460
461 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
462 if (ret)
463 return ret;
464
465 if (!attr.ndev)
466 return -ENODEV;
467
468 if_rele(attr.ndev);
469
470 *gid_type = attr.gid_type;
471
472 return 0;
473 }
474
mlx5_use_mad_ifc(struct mlx5_ib_dev * dev)475 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
476 {
477 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
478 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
479 return 0;
480 }
481
482 enum {
483 MLX5_VPORT_ACCESS_METHOD_MAD,
484 MLX5_VPORT_ACCESS_METHOD_HCA,
485 MLX5_VPORT_ACCESS_METHOD_NIC,
486 };
487
mlx5_get_vport_access_method(struct ib_device * ibdev)488 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
489 {
490 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
491 return MLX5_VPORT_ACCESS_METHOD_MAD;
492
493 if (mlx5_ib_port_link_layer(ibdev, 1) ==
494 IB_LINK_LAYER_ETHERNET)
495 return MLX5_VPORT_ACCESS_METHOD_NIC;
496
497 return MLX5_VPORT_ACCESS_METHOD_HCA;
498 }
499
get_atomic_caps(struct mlx5_ib_dev * dev,struct ib_device_attr * props)500 static void get_atomic_caps(struct mlx5_ib_dev *dev,
501 struct ib_device_attr *props)
502 {
503 u8 tmp;
504 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
505 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
506 u8 atomic_req_8B_endianness_mode =
507 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
508
509 /* Check if HW supports 8 bytes standard atomic operations and capable
510 * of host endianness respond
511 */
512 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
513 if (((atomic_operations & tmp) == tmp) &&
514 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
515 (atomic_req_8B_endianness_mode)) {
516 props->atomic_cap = IB_ATOMIC_HCA;
517 } else {
518 props->atomic_cap = IB_ATOMIC_NONE;
519 }
520 }
521
mlx5_query_system_image_guid(struct ib_device * ibdev,__be64 * sys_image_guid)522 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
523 __be64 *sys_image_guid)
524 {
525 struct mlx5_ib_dev *dev = to_mdev(ibdev);
526 struct mlx5_core_dev *mdev = dev->mdev;
527 u64 tmp;
528 int err;
529
530 switch (mlx5_get_vport_access_method(ibdev)) {
531 case MLX5_VPORT_ACCESS_METHOD_MAD:
532 return mlx5_query_mad_ifc_system_image_guid(ibdev,
533 sys_image_guid);
534
535 case MLX5_VPORT_ACCESS_METHOD_HCA:
536 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
537 break;
538
539 case MLX5_VPORT_ACCESS_METHOD_NIC:
540 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
541 break;
542
543 default:
544 return -EINVAL;
545 }
546
547 if (!err)
548 *sys_image_guid = cpu_to_be64(tmp);
549
550 return err;
551
552 }
553
mlx5_query_max_pkeys(struct ib_device * ibdev,u16 * max_pkeys)554 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
555 u16 *max_pkeys)
556 {
557 struct mlx5_ib_dev *dev = to_mdev(ibdev);
558 struct mlx5_core_dev *mdev = dev->mdev;
559
560 switch (mlx5_get_vport_access_method(ibdev)) {
561 case MLX5_VPORT_ACCESS_METHOD_MAD:
562 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
563
564 case MLX5_VPORT_ACCESS_METHOD_HCA:
565 case MLX5_VPORT_ACCESS_METHOD_NIC:
566 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
567 pkey_table_size));
568 return 0;
569
570 default:
571 return -EINVAL;
572 }
573 }
574
mlx5_query_vendor_id(struct ib_device * ibdev,u32 * vendor_id)575 static int mlx5_query_vendor_id(struct ib_device *ibdev,
576 u32 *vendor_id)
577 {
578 struct mlx5_ib_dev *dev = to_mdev(ibdev);
579
580 switch (mlx5_get_vport_access_method(ibdev)) {
581 case MLX5_VPORT_ACCESS_METHOD_MAD:
582 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
583
584 case MLX5_VPORT_ACCESS_METHOD_HCA:
585 case MLX5_VPORT_ACCESS_METHOD_NIC:
586 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
587
588 default:
589 return -EINVAL;
590 }
591 }
592
mlx5_query_node_guid(struct mlx5_ib_dev * dev,__be64 * node_guid)593 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
594 __be64 *node_guid)
595 {
596 u64 tmp;
597 int err;
598
599 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
600 case MLX5_VPORT_ACCESS_METHOD_MAD:
601 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
602
603 case MLX5_VPORT_ACCESS_METHOD_HCA:
604 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
605 break;
606
607 case MLX5_VPORT_ACCESS_METHOD_NIC:
608 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
609 break;
610
611 default:
612 return -EINVAL;
613 }
614
615 if (!err)
616 *node_guid = cpu_to_be64(tmp);
617
618 return err;
619 }
620
621 struct mlx5_reg_node_desc {
622 u8 desc[IB_DEVICE_NODE_DESC_MAX];
623 };
624
mlx5_query_node_desc(struct mlx5_ib_dev * dev,char * node_desc)625 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
626 {
627 struct mlx5_reg_node_desc in;
628
629 if (mlx5_use_mad_ifc(dev))
630 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
631
632 memset(&in, 0, sizeof(in));
633
634 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
635 sizeof(struct mlx5_reg_node_desc),
636 MLX5_REG_NODE_DESC, 0, 0);
637 }
638
mlx5_ib_query_device(struct ib_device * ibdev,struct ib_device_attr * props,struct ib_udata * uhw)639 static int mlx5_ib_query_device(struct ib_device *ibdev,
640 struct ib_device_attr *props,
641 struct ib_udata *uhw)
642 {
643 struct mlx5_ib_dev *dev = to_mdev(ibdev);
644 struct mlx5_core_dev *mdev = dev->mdev;
645 int err = -ENOMEM;
646 int max_sq_desc;
647 int max_rq_sg;
648 int max_sq_sg;
649 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
650 struct mlx5_ib_query_device_resp resp = {};
651 size_t resp_len;
652 u64 max_tso;
653
654 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
655 if (uhw->outlen && uhw->outlen < resp_len)
656 return -EINVAL;
657 else
658 resp.response_length = resp_len;
659
660 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
661 return -EINVAL;
662
663 memset(props, 0, sizeof(*props));
664 err = mlx5_query_system_image_guid(ibdev,
665 &props->sys_image_guid);
666 if (err)
667 return err;
668
669 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
670 if (err)
671 return err;
672
673 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
674 if (err)
675 return err;
676
677 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
678 ((u32)fw_rev_min(dev->mdev) << 16) |
679 fw_rev_sub(dev->mdev);
680 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
681 IB_DEVICE_PORT_ACTIVE_EVENT |
682 IB_DEVICE_SYS_IMAGE_GUID |
683 IB_DEVICE_RC_RNR_NAK_GEN;
684
685 if (MLX5_CAP_GEN(mdev, pkv))
686 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
687 if (MLX5_CAP_GEN(mdev, qkv))
688 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
689 if (MLX5_CAP_GEN(mdev, apm))
690 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
691 if (MLX5_CAP_GEN(mdev, xrc))
692 props->device_cap_flags |= IB_DEVICE_XRC;
693 if (MLX5_CAP_GEN(mdev, imaicl)) {
694 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
695 IB_DEVICE_MEM_WINDOW_TYPE_2B;
696 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
697 /* We support 'Gappy' memory registration too */
698 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
699 }
700 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
701 if (MLX5_CAP_GEN(mdev, sho)) {
702 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
703 /* At this stage no support for signature handover */
704 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
705 IB_PROT_T10DIF_TYPE_2 |
706 IB_PROT_T10DIF_TYPE_3;
707 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
708 IB_GUARD_T10DIF_CSUM;
709 }
710 if (MLX5_CAP_GEN(mdev, block_lb_mc))
711 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
712
713 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
714 if (MLX5_CAP_ETH(mdev, csum_cap))
715 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
716
717 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
718 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
719 if (max_tso) {
720 resp.tso_caps.max_tso = 1 << max_tso;
721 resp.tso_caps.supported_qpts |=
722 1 << IB_QPT_RAW_PACKET;
723 resp.response_length += sizeof(resp.tso_caps);
724 }
725 }
726
727 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
728 resp.rss_caps.rx_hash_function =
729 MLX5_RX_HASH_FUNC_TOEPLITZ;
730 resp.rss_caps.rx_hash_fields_mask =
731 MLX5_RX_HASH_SRC_IPV4 |
732 MLX5_RX_HASH_DST_IPV4 |
733 MLX5_RX_HASH_SRC_IPV6 |
734 MLX5_RX_HASH_DST_IPV6 |
735 MLX5_RX_HASH_SRC_PORT_TCP |
736 MLX5_RX_HASH_DST_PORT_TCP |
737 MLX5_RX_HASH_SRC_PORT_UDP |
738 MLX5_RX_HASH_DST_PORT_UDP;
739 resp.response_length += sizeof(resp.rss_caps);
740 }
741 } else {
742 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
743 resp.response_length += sizeof(resp.tso_caps);
744 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
745 resp.response_length += sizeof(resp.rss_caps);
746 }
747
748 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) {
749 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
750 props->device_cap_flags |= IB_DEVICE_UD_TSO;
751 }
752
753 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
754 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
755 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
756
757 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
758 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
759
760 props->vendor_part_id = mdev->pdev->device;
761 props->hw_ver = mdev->pdev->revision;
762
763 props->max_mr_size = ~0ull;
764 props->page_size_cap = ~(min_page_size - 1);
765 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
766 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
767 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
768 sizeof(struct mlx5_wqe_data_seg);
769 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
770 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
771 sizeof(struct mlx5_wqe_raddr_seg)) /
772 sizeof(struct mlx5_wqe_data_seg);
773 props->max_sge = min(max_rq_sg, max_sq_sg);
774 props->max_sge_rd = MLX5_MAX_SGE_RD;
775 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
776 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
777 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
778 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
779 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
780 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
781 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
782 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
783 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
784 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
785 props->max_srq_sge = max_rq_sg - 1;
786 props->max_fast_reg_page_list_len =
787 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
788 get_atomic_caps(dev, props);
789 props->masked_atomic_cap = IB_ATOMIC_NONE;
790 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
791 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
792 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
793 props->max_mcast_grp;
794 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
795 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
796 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
797
798 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
799 if (MLX5_CAP_GEN(mdev, pg))
800 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
801 props->odp_caps = dev->odp_caps;
802 #endif
803
804 if (MLX5_CAP_GEN(mdev, cd))
805 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
806
807 if (!mlx5_core_is_pf(mdev))
808 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
809
810 if (mlx5_ib_port_link_layer(ibdev, 1) ==
811 IB_LINK_LAYER_ETHERNET) {
812 props->rss_caps.max_rwq_indirection_tables =
813 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
814 props->rss_caps.max_rwq_indirection_table_size =
815 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
816 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
817 props->max_wq_type_rq =
818 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
819 }
820
821 if (uhw->outlen) {
822 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
823
824 if (err)
825 return err;
826 }
827
828 return 0;
829 }
830
831 enum mlx5_ib_width {
832 MLX5_IB_WIDTH_1X = 1 << 0,
833 MLX5_IB_WIDTH_2X = 1 << 1,
834 MLX5_IB_WIDTH_4X = 1 << 2,
835 MLX5_IB_WIDTH_8X = 1 << 3,
836 MLX5_IB_WIDTH_12X = 1 << 4
837 };
838
translate_active_width(struct ib_device * ibdev,u8 active_width,u8 * ib_width)839 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
840 u8 *ib_width)
841 {
842 struct mlx5_ib_dev *dev = to_mdev(ibdev);
843 int err = 0;
844
845 if (active_width & MLX5_IB_WIDTH_1X) {
846 *ib_width = IB_WIDTH_1X;
847 } else if (active_width & MLX5_IB_WIDTH_2X) {
848 *ib_width = IB_WIDTH_2X;
849 } else if (active_width & MLX5_IB_WIDTH_4X) {
850 *ib_width = IB_WIDTH_4X;
851 } else if (active_width & MLX5_IB_WIDTH_8X) {
852 *ib_width = IB_WIDTH_8X;
853 } else if (active_width & MLX5_IB_WIDTH_12X) {
854 *ib_width = IB_WIDTH_12X;
855 } else {
856 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
857 (int)active_width);
858 err = -EINVAL;
859 }
860
861 return err;
862 }
863
864 enum ib_max_vl_num {
865 __IB_MAX_VL_0 = 1,
866 __IB_MAX_VL_0_1 = 2,
867 __IB_MAX_VL_0_3 = 3,
868 __IB_MAX_VL_0_7 = 4,
869 __IB_MAX_VL_0_14 = 5,
870 };
871
872 enum mlx5_vl_hw_cap {
873 MLX5_VL_HW_0 = 1,
874 MLX5_VL_HW_0_1 = 2,
875 MLX5_VL_HW_0_2 = 3,
876 MLX5_VL_HW_0_3 = 4,
877 MLX5_VL_HW_0_4 = 5,
878 MLX5_VL_HW_0_5 = 6,
879 MLX5_VL_HW_0_6 = 7,
880 MLX5_VL_HW_0_7 = 8,
881 MLX5_VL_HW_0_14 = 15
882 };
883
translate_max_vl_num(struct ib_device * ibdev,u8 vl_hw_cap,u8 * max_vl_num)884 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
885 u8 *max_vl_num)
886 {
887 switch (vl_hw_cap) {
888 case MLX5_VL_HW_0:
889 *max_vl_num = __IB_MAX_VL_0;
890 break;
891 case MLX5_VL_HW_0_1:
892 *max_vl_num = __IB_MAX_VL_0_1;
893 break;
894 case MLX5_VL_HW_0_3:
895 *max_vl_num = __IB_MAX_VL_0_3;
896 break;
897 case MLX5_VL_HW_0_7:
898 *max_vl_num = __IB_MAX_VL_0_7;
899 break;
900 case MLX5_VL_HW_0_14:
901 *max_vl_num = __IB_MAX_VL_0_14;
902 break;
903
904 default:
905 return -EINVAL;
906 }
907
908 return 0;
909 }
910
mlx5_query_hca_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)911 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
912 struct ib_port_attr *props)
913 {
914 struct mlx5_ib_dev *dev = to_mdev(ibdev);
915 struct mlx5_core_dev *mdev = dev->mdev;
916 u32 *rep;
917 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out);
918 struct mlx5_ptys_reg *ptys;
919 struct mlx5_pmtu_reg *pmtu;
920 struct mlx5_pvlc_reg pvlc;
921 void *ctx;
922 int err;
923
924 rep = mlx5_vzalloc(replen);
925 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL);
926 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL);
927 if (!rep || !ptys || !pmtu) {
928 err = -ENOMEM;
929 goto out;
930 }
931
932 memset(props, 0, sizeof(*props));
933
934 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen);
935 if (err)
936 goto out;
937
938 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context);
939
940 props->lid = MLX5_GET(hca_vport_context, ctx, lid);
941 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc);
942 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid);
943 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl);
944 props->state = MLX5_GET(hca_vport_context, ctx, vport_state);
945 props->phys_state = MLX5_GET(hca_vport_context, ctx,
946 port_physical_state);
947 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1);
948 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
949 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
950 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
951 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx,
952 pkey_violation_counter);
953 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx,
954 qkey_violation_counter);
955 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx,
956 subnet_timeout);
957 props->init_type_reply = MLX5_GET(hca_vport_context, ctx,
958 init_type_reply);
959 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required);
960
961 ptys->proto_mask |= MLX5_PTYS_IB;
962 ptys->local_port = port;
963 err = mlx5_core_access_ptys(mdev, ptys, 0);
964 if (err)
965 goto out;
966
967 err = translate_active_width(ibdev, ptys->ib_link_width_oper,
968 &props->active_width);
969 if (err)
970 goto out;
971
972 props->active_speed = (u8)ptys->ib_proto_oper;
973
974 pmtu->local_port = port;
975 err = mlx5_core_access_pmtu(mdev, pmtu, 0);
976 if (err)
977 goto out;
978
979 props->max_mtu = pmtu->max_mtu;
980 props->active_mtu = pmtu->oper_mtu;
981
982 memset(&pvlc, 0, sizeof(pvlc));
983 pvlc.local_port = port;
984 err = mlx5_core_access_pvlc(mdev, &pvlc, 0);
985 if (err)
986 goto out;
987
988 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap,
989 &props->max_vl_num);
990 out:
991 kvfree(rep);
992 kfree(ptys);
993 kfree(pmtu);
994 return err;
995 }
996
mlx5_ib_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)997 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
998 struct ib_port_attr *props)
999 {
1000 switch (mlx5_get_vport_access_method(ibdev)) {
1001 case MLX5_VPORT_ACCESS_METHOD_MAD:
1002 return mlx5_query_mad_ifc_port(ibdev, port, props);
1003
1004 case MLX5_VPORT_ACCESS_METHOD_HCA:
1005 return mlx5_query_hca_port(ibdev, port, props);
1006
1007 case MLX5_VPORT_ACCESS_METHOD_NIC:
1008 return mlx5_query_port_roce(ibdev, port, props);
1009
1010 default:
1011 return -EINVAL;
1012 }
1013 }
1014
mlx5_ib_query_gid(struct ib_device * ibdev,u8 port,int index,union ib_gid * gid)1015 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1016 union ib_gid *gid)
1017 {
1018 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1019 struct mlx5_core_dev *mdev = dev->mdev;
1020
1021 switch (mlx5_get_vport_access_method(ibdev)) {
1022 case MLX5_VPORT_ACCESS_METHOD_MAD:
1023 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1024
1025 case MLX5_VPORT_ACCESS_METHOD_HCA:
1026 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid);
1027
1028 default:
1029 return -EINVAL;
1030 }
1031
1032 }
1033
mlx5_ib_query_pkey(struct ib_device * ibdev,u8 port,u16 index,u16 * pkey)1034 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1035 u16 *pkey)
1036 {
1037 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1038 struct mlx5_core_dev *mdev = dev->mdev;
1039
1040 switch (mlx5_get_vport_access_method(ibdev)) {
1041 case MLX5_VPORT_ACCESS_METHOD_MAD:
1042 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1043
1044 case MLX5_VPORT_ACCESS_METHOD_HCA:
1045 case MLX5_VPORT_ACCESS_METHOD_NIC:
1046 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1047 pkey);
1048 default:
1049 return -EINVAL;
1050 }
1051 }
1052
mlx5_ib_modify_device(struct ib_device * ibdev,int mask,struct ib_device_modify * props)1053 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1054 struct ib_device_modify *props)
1055 {
1056 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1057 struct mlx5_reg_node_desc in;
1058 struct mlx5_reg_node_desc out;
1059 int err;
1060
1061 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1062 return -EOPNOTSUPP;
1063
1064 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1065 return 0;
1066
1067 /*
1068 * If possible, pass node desc to FW, so it can generate
1069 * a 144 trap. If cmd fails, just ignore.
1070 */
1071 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1072 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1073 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1074 if (err)
1075 return err;
1076
1077 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1078
1079 return err;
1080 }
1081
mlx5_ib_modify_port(struct ib_device * ibdev,u8 port,int mask,struct ib_port_modify * props)1082 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1083 struct ib_port_modify *props)
1084 {
1085 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1086 struct ib_port_attr attr;
1087 u32 tmp;
1088 int err;
1089
1090 /*
1091 * CM layer calls ib_modify_port() regardless of the link
1092 * layer. For Ethernet ports, qkey violation and Port
1093 * capabilities are meaningless.
1094 */
1095 if (mlx5_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_ETHERNET)
1096 return 0;
1097
1098 mutex_lock(&dev->cap_mask_mutex);
1099
1100 err = mlx5_ib_query_port(ibdev, port, &attr);
1101 if (err)
1102 goto out;
1103
1104 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1105 ~props->clr_port_cap_mask;
1106
1107 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1108
1109 out:
1110 mutex_unlock(&dev->cap_mask_mutex);
1111 return err;
1112 }
1113
calc_dynamic_bfregs(int uars_per_sys_page)1114 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1115 {
1116 /* Large page with non 4k uar support might limit the dynamic size */
1117 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1118 return MLX5_MIN_DYN_BFREGS;
1119
1120 return MLX5_MAX_DYN_BFREGS;
1121 }
1122
calc_total_bfregs(struct mlx5_ib_dev * dev,bool lib_uar_4k,struct mlx5_ib_alloc_ucontext_req_v2 * req,struct mlx5_bfreg_info * bfregi)1123 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1124 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1125 struct mlx5_bfreg_info *bfregi)
1126 {
1127 int uars_per_sys_page;
1128 int bfregs_per_sys_page;
1129 int ref_bfregs = req->total_num_bfregs;
1130
1131 if (req->total_num_bfregs == 0)
1132 return -EINVAL;
1133
1134 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1135 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1136
1137 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1138 return -ENOMEM;
1139
1140 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1141 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1142 /* This holds the required static allocation asked by the user */
1143 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1144 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1145 return -EINVAL;
1146
1147 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1148 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1149 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1150 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1151
1152 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1153 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1154 lib_uar_4k ? "yes" : "no", ref_bfregs,
1155 req->total_num_bfregs, bfregi->total_num_bfregs,
1156 bfregi->num_sys_pages);
1157
1158 return 0;
1159 }
1160
allocate_uars(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1161 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1162 {
1163 struct mlx5_bfreg_info *bfregi;
1164 int err;
1165 int i;
1166
1167 bfregi = &context->bfregi;
1168 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1169 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1170 if (err)
1171 goto error;
1172
1173 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1174 }
1175
1176 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1177 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1178
1179 return 0;
1180
1181 error:
1182 for (--i; i >= 0; i--)
1183 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1184 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1185
1186 return err;
1187 }
1188
deallocate_uars(struct mlx5_ib_dev * dev,struct mlx5_ib_ucontext * context)1189 static void deallocate_uars(struct mlx5_ib_dev *dev,
1190 struct mlx5_ib_ucontext *context)
1191 {
1192 struct mlx5_bfreg_info *bfregi;
1193 int i;
1194
1195 bfregi = &context->bfregi;
1196 for (i = 0; i < bfregi->num_sys_pages; i++)
1197 if (i < bfregi->num_static_sys_pages ||
1198 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1199 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1200 }
1201
mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev * dev,u32 * tdn)1202 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1203 {
1204 int err;
1205
1206 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1207 return 0;
1208
1209 err = mlx5_alloc_transport_domain(dev->mdev, tdn);
1210 if (err)
1211 return err;
1212
1213 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1214 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1215 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1216 return 0;
1217
1218 mutex_lock(&dev->lb_mutex);
1219 dev->user_td++;
1220
1221 if (dev->user_td == 2)
1222 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1223
1224 mutex_unlock(&dev->lb_mutex);
1225
1226 if (err != 0)
1227 mlx5_dealloc_transport_domain(dev->mdev, *tdn);
1228 return err;
1229 }
1230
mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev * dev,u32 tdn)1231 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1232 {
1233 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1234 return;
1235
1236 mlx5_dealloc_transport_domain(dev->mdev, tdn);
1237
1238 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1239 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1240 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1241 return;
1242
1243 mutex_lock(&dev->lb_mutex);
1244 dev->user_td--;
1245
1246 if (dev->user_td < 2)
1247 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1248
1249 mutex_unlock(&dev->lb_mutex);
1250 }
1251
mlx5_ib_alloc_ucontext(struct ib_device * ibdev,struct ib_udata * udata)1252 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1253 struct ib_udata *udata)
1254 {
1255 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1256 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1257 struct mlx5_ib_alloc_ucontext_resp resp = {};
1258 struct mlx5_ib_ucontext *context;
1259 struct mlx5_bfreg_info *bfregi;
1260 int ver;
1261 int err;
1262 size_t reqlen;
1263 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1264 max_cqe_version);
1265 bool lib_uar_4k;
1266 bool lib_uar_dyn;
1267
1268 if (!dev->ib_active)
1269 return ERR_PTR(-EAGAIN);
1270
1271 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1272 return ERR_PTR(-EINVAL);
1273
1274 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1275 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1276 ver = 0;
1277 else if (reqlen >= min_req_v2)
1278 ver = 2;
1279 else
1280 return ERR_PTR(-EINVAL);
1281
1282 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1283 if (err)
1284 return ERR_PTR(err);
1285
1286 if (req.flags)
1287 return ERR_PTR(-EINVAL);
1288
1289 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1290 return ERR_PTR(-EOPNOTSUPP);
1291
1292 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1293 MLX5_NON_FP_BFREGS_PER_UAR);
1294 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1295 return ERR_PTR(-EINVAL);
1296
1297 if (reqlen > sizeof(req) &&
1298 !ib_is_udata_cleared(udata, sizeof(req),
1299 reqlen - sizeof(req)))
1300 return ERR_PTR(-EOPNOTSUPP);
1301
1302 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1303 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1304 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1305 resp.cache_line_size = cache_line_size();
1306 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1307 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1308 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1309 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1310 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1311 resp.cqe_version = min_t(__u8,
1312 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1313 req.max_cqe_version);
1314 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1315 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1316 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1317 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1318 resp.response_length = min(offsetof(typeof(resp), response_length) +
1319 sizeof(resp.response_length), udata->outlen);
1320
1321 context = kzalloc(sizeof(*context), GFP_KERNEL);
1322 if (!context)
1323 return ERR_PTR(-ENOMEM);
1324
1325 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1326 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1327 bfregi = &context->bfregi;
1328
1329 if (lib_uar_dyn) {
1330 bfregi->lib_uar_dyn = lib_uar_dyn;
1331 goto uar_done;
1332 }
1333
1334 /* updates req->total_num_bfregs */
1335 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1336 if (err)
1337 goto out_ctx;
1338
1339 mutex_init(&bfregi->lock);
1340 bfregi->lib_uar_4k = lib_uar_4k;
1341 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1342 GFP_KERNEL);
1343 if (!bfregi->count) {
1344 err = -ENOMEM;
1345 goto out_ctx;
1346 }
1347
1348 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1349 sizeof(*bfregi->sys_pages),
1350 GFP_KERNEL);
1351 if (!bfregi->sys_pages) {
1352 err = -ENOMEM;
1353 goto out_count;
1354 }
1355
1356 err = allocate_uars(dev, context);
1357 if (err)
1358 goto out_sys_pages;
1359
1360 uar_done:
1361
1362 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1363 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1364 #endif
1365
1366 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1367 if (err)
1368 goto out_uars;
1369
1370 INIT_LIST_HEAD(&context->vma_private_list);
1371 INIT_LIST_HEAD(&context->db_page_list);
1372 mutex_init(&context->db_page_mutex);
1373
1374 resp.tot_bfregs = lib_uar_dyn ? 0 : req.total_num_bfregs;
1375 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1376
1377 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1378 resp.response_length += sizeof(resp.cqe_version);
1379
1380 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1381 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1382 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1383 resp.response_length += sizeof(resp.cmds_supp_uhw);
1384 }
1385
1386 /*
1387 * We don't want to expose information from the PCI bar that is located
1388 * after 4096 bytes, so if the arch only supports larger pages, let's
1389 * pretend we don't support reading the HCA's core clock. This is also
1390 * forced by mmap function.
1391 */
1392 if (offsetofend(typeof(resp), hca_core_clock_offset) <= udata->outlen) {
1393 if (PAGE_SIZE <= 4096) {
1394 resp.comp_mask |=
1395 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1396 resp.hca_core_clock_offset =
1397 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1398 }
1399 resp.response_length += sizeof(resp.hca_core_clock_offset);
1400 }
1401
1402 if (offsetofend(typeof(resp), log_uar_size) <= udata->outlen)
1403 resp.response_length += sizeof(resp.log_uar_size);
1404
1405 if (offsetofend(typeof(resp), num_uars_per_page) <= udata->outlen)
1406 resp.response_length += sizeof(resp.num_uars_per_page);
1407
1408 if (offsetofend(typeof(resp), num_dyn_bfregs) <= udata->outlen) {
1409 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1410 resp.response_length += sizeof(resp.num_dyn_bfregs);
1411 }
1412
1413 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1414 if (err)
1415 goto out_td;
1416
1417 bfregi->ver = ver;
1418 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1419 context->cqe_version = resp.cqe_version;
1420
1421 return &context->ibucontext;
1422
1423 out_td:
1424 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1425
1426 out_uars:
1427 deallocate_uars(dev, context);
1428
1429 out_sys_pages:
1430 kfree(bfregi->sys_pages);
1431
1432 out_count:
1433 kfree(bfregi->count);
1434
1435 out_ctx:
1436 kfree(context);
1437 return ERR_PTR(err);
1438 }
1439
mlx5_ib_dealloc_ucontext(struct ib_ucontext * ibcontext)1440 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1441 {
1442 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1443 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1444 struct mlx5_bfreg_info *bfregi;
1445
1446 bfregi = &context->bfregi;
1447 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1448
1449 deallocate_uars(dev, context);
1450 kfree(bfregi->sys_pages);
1451 kfree(bfregi->count);
1452 kfree(context);
1453
1454 return 0;
1455 }
1456
uar_index2pfn(struct mlx5_ib_dev * dev,int uar_idx)1457 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1458 int uar_idx)
1459 {
1460 int fw_uars_per_page;
1461
1462 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1463
1464 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1465 }
1466
get_command(unsigned long offset)1467 static int get_command(unsigned long offset)
1468 {
1469 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1470 }
1471
get_arg(unsigned long offset)1472 static int get_arg(unsigned long offset)
1473 {
1474 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1475 }
1476
get_index(unsigned long offset)1477 static int get_index(unsigned long offset)
1478 {
1479 return get_arg(offset);
1480 }
1481
1482 /* Index resides in an extra byte to enable larger values than 255 */
get_extended_index(unsigned long offset)1483 static int get_extended_index(unsigned long offset)
1484 {
1485 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1486 }
1487
mlx5_ib_vma_open(struct vm_area_struct * area)1488 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1489 {
1490 /* vma_open is called when a new VMA is created on top of our VMA. This
1491 * is done through either mremap flow or split_vma (usually due to
1492 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1493 * as this VMA is strongly hardware related. Therefore we set the
1494 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1495 * calling us again and trying to do incorrect actions. We assume that
1496 * the original VMA size is exactly a single page, and therefore all
1497 * "splitting" operation will not happen to it.
1498 */
1499 area->vm_ops = NULL;
1500 }
1501
mlx5_ib_vma_close(struct vm_area_struct * area)1502 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1503 {
1504 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1505
1506 /* It's guaranteed that all VMAs opened on a FD are closed before the
1507 * file itself is closed, therefore no sync is needed with the regular
1508 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1509 * However need a sync with accessing the vma as part of
1510 * mlx5_ib_disassociate_ucontext.
1511 * The close operation is usually called under mm->mmap_sem except when
1512 * process is exiting.
1513 * The exiting case is handled explicitly as part of
1514 * mlx5_ib_disassociate_ucontext.
1515 */
1516 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1517
1518 /* setting the vma context pointer to null in the mlx5_ib driver's
1519 * private data, to protect a race condition in
1520 * mlx5_ib_disassociate_ucontext().
1521 */
1522 mlx5_ib_vma_priv_data->vma = NULL;
1523 list_del(&mlx5_ib_vma_priv_data->list);
1524 kfree(mlx5_ib_vma_priv_data);
1525 }
1526
1527 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1528 .open = mlx5_ib_vma_open,
1529 .close = mlx5_ib_vma_close
1530 };
1531
mlx5_ib_set_vma_data(struct vm_area_struct * vma,struct mlx5_ib_ucontext * ctx)1532 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1533 struct mlx5_ib_ucontext *ctx)
1534 {
1535 struct mlx5_ib_vma_private_data *vma_prv;
1536 struct list_head *vma_head = &ctx->vma_private_list;
1537
1538 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1539 if (!vma_prv)
1540 return -ENOMEM;
1541
1542 vma_prv->vma = vma;
1543 vma->vm_private_data = vma_prv;
1544 vma->vm_ops = &mlx5_ib_vm_ops;
1545
1546 list_add(&vma_prv->list, vma_head);
1547
1548 return 0;
1549 }
1550
mlx5_ib_disassociate_ucontext(struct ib_ucontext * ibcontext)1551 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1552 {
1553 int ret;
1554 struct vm_area_struct *vma;
1555 struct mlx5_ib_vma_private_data *vma_private, *n;
1556 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1557 struct task_struct *owning_process = NULL;
1558 struct mm_struct *owning_mm = NULL;
1559
1560 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1561 if (!owning_process)
1562 return;
1563
1564 owning_mm = get_task_mm(owning_process);
1565 if (!owning_mm) {
1566 pr_info("no mm, disassociate ucontext is pending task termination\n");
1567 while (1) {
1568 put_task_struct(owning_process);
1569 usleep_range(1000, 2000);
1570 owning_process = get_pid_task(ibcontext->tgid,
1571 PIDTYPE_PID);
1572 if (!owning_process || owning_process->task_thread->
1573 td_proc->p_state == PRS_ZOMBIE) {
1574 pr_info("disassociate ucontext done, task was terminated\n");
1575 /* in case task was dead need to release the
1576 * task struct.
1577 */
1578 if (owning_process)
1579 put_task_struct(owning_process);
1580 return;
1581 }
1582 }
1583 }
1584
1585 /* need to protect from a race on closing the vma as part of
1586 * mlx5_ib_vma_close.
1587 */
1588 down_write(&owning_mm->mmap_sem);
1589 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1590 list) {
1591 vma = vma_private->vma;
1592 ret = zap_vma_ptes(vma, vma->vm_start,
1593 PAGE_SIZE);
1594 if (ret == -ENOTSUP) {
1595 if (bootverbose)
1596 WARN_ONCE(
1597 "%s: zap_vma_ptes not implemented for unmanaged mappings", __func__);
1598 } else {
1599 WARN(ret, "%s: zap_vma_ptes failed, error %d",
1600 __func__, -ret);
1601 }
1602 /* context going to be destroyed, should
1603 * not access ops any more.
1604 */
1605 /* XXXKIB vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); */
1606 vma->vm_ops = NULL;
1607 list_del(&vma_private->list);
1608 kfree(vma_private);
1609 }
1610 up_write(&owning_mm->mmap_sem);
1611 mmput(owning_mm);
1612 put_task_struct(owning_process);
1613 }
1614
mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)1615 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1616 {
1617 switch (cmd) {
1618 case MLX5_IB_MMAP_WC_PAGE:
1619 return "WC";
1620 case MLX5_IB_MMAP_REGULAR_PAGE:
1621 return "best effort WC";
1622 case MLX5_IB_MMAP_NC_PAGE:
1623 return "NC";
1624 default:
1625 return NULL;
1626 }
1627 }
1628
uar_mmap(struct mlx5_ib_dev * dev,enum mlx5_ib_mmap_cmd cmd,struct vm_area_struct * vma,struct mlx5_ib_ucontext * context)1629 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1630 struct vm_area_struct *vma,
1631 struct mlx5_ib_ucontext *context)
1632 {
1633 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1634 int err;
1635 unsigned long idx;
1636 phys_addr_t pfn;
1637 pgprot_t prot;
1638 u32 bfreg_dyn_idx = 0;
1639 u32 uar_index;
1640 int dyn_uar = (cmd == MLX5_IB_MMAP_WC_PAGE);
1641 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
1642 bfregi->num_static_sys_pages;
1643
1644 if (bfregi->lib_uar_dyn)
1645 return -EINVAL;
1646
1647 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1648 return -EINVAL;
1649
1650 if (dyn_uar)
1651 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
1652 else
1653 idx = get_index(vma->vm_pgoff);
1654
1655 if (idx >= max_valid_idx) {
1656 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
1657 idx, max_valid_idx);
1658 return -EINVAL;
1659 }
1660
1661 switch (cmd) {
1662 case MLX5_IB_MMAP_WC_PAGE:
1663 case MLX5_IB_MMAP_REGULAR_PAGE:
1664 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1665 prot = pgprot_writecombine(vma->vm_page_prot);
1666 break;
1667 case MLX5_IB_MMAP_NC_PAGE:
1668 prot = pgprot_noncached(vma->vm_page_prot);
1669 break;
1670 default:
1671 return -EINVAL;
1672 }
1673
1674 if (dyn_uar) {
1675 int uars_per_page;
1676
1677 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1678 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
1679 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
1680 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
1681 bfreg_dyn_idx, bfregi->total_num_bfregs);
1682 return -EINVAL;
1683 }
1684
1685 mutex_lock(&bfregi->lock);
1686 /* Fail if uar already allocated, first bfreg index of each
1687 * page holds its count.
1688 */
1689 if (bfregi->count[bfreg_dyn_idx]) {
1690 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
1691 mutex_unlock(&bfregi->lock);
1692 return -EINVAL;
1693 }
1694
1695 bfregi->count[bfreg_dyn_idx]++;
1696 mutex_unlock(&bfregi->lock);
1697
1698 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
1699 if (err) {
1700 mlx5_ib_warn(dev, "UAR alloc failed\n");
1701 goto free_bfreg;
1702 }
1703 } else {
1704 uar_index = bfregi->sys_pages[idx];
1705 }
1706
1707 pfn = uar_index2pfn(dev, uar_index);
1708 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1709
1710 vma->vm_page_prot = prot;
1711 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1712 PAGE_SIZE, vma->vm_page_prot);
1713 if (err) {
1714 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%llx, pfn=%pa, mmap_cmd=%s\n",
1715 err, (unsigned long long)vma->vm_start, &pfn, mmap_cmd2str(cmd));
1716 goto err;
1717 }
1718
1719 if (dyn_uar)
1720 bfregi->sys_pages[idx] = uar_index;
1721 return mlx5_ib_set_vma_data(vma, context);
1722
1723 err:
1724 if (!dyn_uar)
1725 return err;
1726
1727 mlx5_cmd_free_uar(dev->mdev, idx);
1728
1729 free_bfreg:
1730 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
1731
1732 return err;
1733 }
1734
mlx5_ib_mmap(struct ib_ucontext * ibcontext,struct vm_area_struct * vma)1735 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1736 {
1737 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1738 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1739 unsigned long command;
1740 phys_addr_t pfn;
1741
1742 command = get_command(vma->vm_pgoff);
1743 switch (command) {
1744 case MLX5_IB_MMAP_WC_PAGE:
1745 case MLX5_IB_MMAP_NC_PAGE:
1746 case MLX5_IB_MMAP_REGULAR_PAGE:
1747 return uar_mmap(dev, command, vma, context);
1748
1749 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1750 return -ENOSYS;
1751
1752 case MLX5_IB_MMAP_CORE_CLOCK:
1753 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1754 return -EINVAL;
1755
1756 if (vma->vm_flags & VM_WRITE)
1757 return -EPERM;
1758
1759 /* Don't expose to user-space information it shouldn't have */
1760 if (PAGE_SIZE > 4096)
1761 return -EOPNOTSUPP;
1762
1763 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1764 pfn = (dev->mdev->iseg_base +
1765 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1766 PAGE_SHIFT;
1767 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1768 PAGE_SIZE, vma->vm_page_prot))
1769 return -EAGAIN;
1770
1771 mlx5_ib_dbg(dev, "mapped internal timer at 0x%llx, PA 0x%llx\n",
1772 (unsigned long long)vma->vm_start,
1773 (unsigned long long)pfn << PAGE_SHIFT);
1774 break;
1775
1776 default:
1777 return -EINVAL;
1778 }
1779
1780 return 0;
1781 }
1782
mlx5_ib_alloc_pd(struct ib_device * ibdev,struct ib_ucontext * context,struct ib_udata * udata)1783 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1784 struct ib_ucontext *context,
1785 struct ib_udata *udata)
1786 {
1787 struct mlx5_ib_alloc_pd_resp resp;
1788 struct mlx5_ib_pd *pd;
1789 int err;
1790
1791 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1792 if (!pd)
1793 return ERR_PTR(-ENOMEM);
1794
1795 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1796 if (err) {
1797 kfree(pd);
1798 return ERR_PTR(err);
1799 }
1800
1801 if (context) {
1802 resp.pdn = pd->pdn;
1803 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1804 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1805 kfree(pd);
1806 return ERR_PTR(-EFAULT);
1807 }
1808 }
1809
1810 return &pd->ibpd;
1811 }
1812
mlx5_ib_dealloc_pd(struct ib_pd * pd)1813 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1814 {
1815 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1816 struct mlx5_ib_pd *mpd = to_mpd(pd);
1817
1818 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1819 kfree(mpd);
1820
1821 return 0;
1822 }
1823
1824 enum {
1825 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1826 MATCH_CRITERIA_ENABLE_MISC_BIT,
1827 MATCH_CRITERIA_ENABLE_INNER_BIT
1828 };
1829
1830 #define HEADER_IS_ZERO(match_criteria, headers) \
1831 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1832 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1833
get_match_criteria_enable(u32 * match_criteria)1834 static u8 get_match_criteria_enable(u32 *match_criteria)
1835 {
1836 u8 match_criteria_enable;
1837
1838 match_criteria_enable =
1839 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1840 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1841 match_criteria_enable |=
1842 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1843 MATCH_CRITERIA_ENABLE_MISC_BIT;
1844 match_criteria_enable |=
1845 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1846 MATCH_CRITERIA_ENABLE_INNER_BIT;
1847
1848 return match_criteria_enable;
1849 }
1850
set_proto(void * outer_c,void * outer_v,u8 mask,u8 val)1851 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1852 {
1853 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1854 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1855 }
1856
set_tos(void * outer_c,void * outer_v,u8 mask,u8 val)1857 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1858 {
1859 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1860 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1861 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1862 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1863 }
1864
1865 #define LAST_ETH_FIELD vlan_tag
1866 #define LAST_IB_FIELD sl
1867 #define LAST_IPV4_FIELD tos
1868 #define LAST_IPV6_FIELD traffic_class
1869 #define LAST_TCP_UDP_FIELD src_port
1870
1871 /* Field is the last supported field */
1872 #define FIELDS_NOT_SUPPORTED(filter, field)\
1873 memchr_inv((void *)&filter.field +\
1874 sizeof(filter.field), 0,\
1875 sizeof(filter) -\
1876 offsetof(typeof(filter), field) -\
1877 sizeof(filter.field))
1878
parse_flow_attr(u32 * match_c,u32 * match_v,const union ib_flow_spec * ib_spec)1879 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1880 const union ib_flow_spec *ib_spec)
1881 {
1882 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1883 outer_headers);
1884 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1885 outer_headers);
1886 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1887 misc_parameters);
1888 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1889 misc_parameters);
1890
1891 switch (ib_spec->type) {
1892 case IB_FLOW_SPEC_ETH:
1893 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1894 return -ENOTSUPP;
1895
1896 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1897 dmac_47_16),
1898 ib_spec->eth.mask.dst_mac);
1899 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1900 dmac_47_16),
1901 ib_spec->eth.val.dst_mac);
1902
1903 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1904 smac_47_16),
1905 ib_spec->eth.mask.src_mac);
1906 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1907 smac_47_16),
1908 ib_spec->eth.val.src_mac);
1909
1910 if (ib_spec->eth.mask.vlan_tag) {
1911 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1912 cvlan_tag, 1);
1913 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1914 cvlan_tag, 1);
1915
1916 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1917 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1918 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1919 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1920
1921 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1922 first_cfi,
1923 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1924 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1925 first_cfi,
1926 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1927
1928 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1929 first_prio,
1930 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1931 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1932 first_prio,
1933 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1934 }
1935 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1936 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1937 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1938 ethertype, ntohs(ib_spec->eth.val.ether_type));
1939 break;
1940 case IB_FLOW_SPEC_IPV4:
1941 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1942 return -ENOTSUPP;
1943
1944 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1945 ethertype, 0xffff);
1946 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1947 ethertype, ETH_P_IP);
1948
1949 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1950 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1951 &ib_spec->ipv4.mask.src_ip,
1952 sizeof(ib_spec->ipv4.mask.src_ip));
1953 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1954 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1955 &ib_spec->ipv4.val.src_ip,
1956 sizeof(ib_spec->ipv4.val.src_ip));
1957 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1958 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1959 &ib_spec->ipv4.mask.dst_ip,
1960 sizeof(ib_spec->ipv4.mask.dst_ip));
1961 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1962 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1963 &ib_spec->ipv4.val.dst_ip,
1964 sizeof(ib_spec->ipv4.val.dst_ip));
1965
1966 set_tos(outer_headers_c, outer_headers_v,
1967 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1968
1969 set_proto(outer_headers_c, outer_headers_v,
1970 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1971 break;
1972 case IB_FLOW_SPEC_IPV6:
1973 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1974 return -ENOTSUPP;
1975
1976 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1977 ethertype, 0xffff);
1978 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1979 ethertype, IPPROTO_IPV6);
1980
1981 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1982 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1983 &ib_spec->ipv6.mask.src_ip,
1984 sizeof(ib_spec->ipv6.mask.src_ip));
1985 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1986 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1987 &ib_spec->ipv6.val.src_ip,
1988 sizeof(ib_spec->ipv6.val.src_ip));
1989 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1990 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1991 &ib_spec->ipv6.mask.dst_ip,
1992 sizeof(ib_spec->ipv6.mask.dst_ip));
1993 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1994 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1995 &ib_spec->ipv6.val.dst_ip,
1996 sizeof(ib_spec->ipv6.val.dst_ip));
1997
1998 set_tos(outer_headers_c, outer_headers_v,
1999 ib_spec->ipv6.mask.traffic_class,
2000 ib_spec->ipv6.val.traffic_class);
2001
2002 set_proto(outer_headers_c, outer_headers_v,
2003 ib_spec->ipv6.mask.next_hdr,
2004 ib_spec->ipv6.val.next_hdr);
2005
2006 MLX5_SET(fte_match_set_misc, misc_params_c,
2007 outer_ipv6_flow_label,
2008 ntohl(ib_spec->ipv6.mask.flow_label));
2009 MLX5_SET(fte_match_set_misc, misc_params_v,
2010 outer_ipv6_flow_label,
2011 ntohl(ib_spec->ipv6.val.flow_label));
2012 break;
2013 case IB_FLOW_SPEC_TCP:
2014 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2015 LAST_TCP_UDP_FIELD))
2016 return -ENOTSUPP;
2017
2018 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
2019 0xff);
2020 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
2021 IPPROTO_TCP);
2022
2023 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
2024 ntohs(ib_spec->tcp_udp.mask.src_port));
2025 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
2026 ntohs(ib_spec->tcp_udp.val.src_port));
2027
2028 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
2029 ntohs(ib_spec->tcp_udp.mask.dst_port));
2030 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
2031 ntohs(ib_spec->tcp_udp.val.dst_port));
2032 break;
2033 case IB_FLOW_SPEC_UDP:
2034 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2035 LAST_TCP_UDP_FIELD))
2036 return -ENOTSUPP;
2037
2038 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
2039 0xff);
2040 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
2041 IPPROTO_UDP);
2042
2043 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
2044 ntohs(ib_spec->tcp_udp.mask.src_port));
2045 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
2046 ntohs(ib_spec->tcp_udp.val.src_port));
2047
2048 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
2049 ntohs(ib_spec->tcp_udp.mask.dst_port));
2050 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
2051 ntohs(ib_spec->tcp_udp.val.dst_port));
2052 break;
2053 default:
2054 return -EINVAL;
2055 }
2056
2057 return 0;
2058 }
2059
2060 /* If a flow could catch both multicast and unicast packets,
2061 * it won't fall into the multicast flow steering table and this rule
2062 * could steal other multicast packets.
2063 */
flow_is_multicast_only(struct ib_flow_attr * ib_attr)2064 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
2065 {
2066 struct ib_flow_spec_eth *eth_spec;
2067
2068 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2069 ib_attr->size < sizeof(struct ib_flow_attr) +
2070 sizeof(struct ib_flow_spec_eth) ||
2071 ib_attr->num_of_specs < 1)
2072 return false;
2073
2074 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
2075 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
2076 eth_spec->size != sizeof(*eth_spec))
2077 return false;
2078
2079 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2080 is_multicast_ether_addr(eth_spec->val.dst_mac);
2081 }
2082
is_valid_attr(const struct ib_flow_attr * flow_attr)2083 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
2084 {
2085 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2086 bool has_ipv4_spec = false;
2087 bool eth_type_ipv4 = true;
2088 unsigned int spec_index;
2089
2090 /* Validate that ethertype is correct */
2091 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2092 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
2093 ib_spec->eth.mask.ether_type) {
2094 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
2095 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
2096 eth_type_ipv4 = false;
2097 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
2098 has_ipv4_spec = true;
2099 }
2100 ib_spec = (void *)ib_spec + ib_spec->size;
2101 }
2102 return !has_ipv4_spec || eth_type_ipv4;
2103 }
2104
put_flow_table(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * prio,bool ft_added)2105 static void put_flow_table(struct mlx5_ib_dev *dev,
2106 struct mlx5_ib_flow_prio *prio, bool ft_added)
2107 {
2108 prio->refcount -= !!ft_added;
2109 if (!prio->refcount) {
2110 mlx5_destroy_flow_table(prio->flow_table);
2111 prio->flow_table = NULL;
2112 }
2113 }
2114
mlx5_ib_destroy_flow(struct ib_flow * flow_id)2115 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2116 {
2117 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2118 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2119 struct mlx5_ib_flow_handler,
2120 ibflow);
2121 struct mlx5_ib_flow_handler *iter, *tmp;
2122
2123 mutex_lock(&dev->flow_db.lock);
2124
2125 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2126 mlx5_del_flow_rule(iter->rule);
2127 put_flow_table(dev, iter->prio, true);
2128 list_del(&iter->list);
2129 kfree(iter);
2130 }
2131
2132 mlx5_del_flow_rule(handler->rule);
2133 put_flow_table(dev, handler->prio, true);
2134 mutex_unlock(&dev->flow_db.lock);
2135
2136 kfree(handler);
2137
2138 return 0;
2139 }
2140
ib_prio_to_core_prio(unsigned int priority,bool dont_trap)2141 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2142 {
2143 priority *= 2;
2144 if (!dont_trap)
2145 priority++;
2146 return priority;
2147 }
2148
2149 enum flow_table_type {
2150 MLX5_IB_FT_RX,
2151 MLX5_IB_FT_TX
2152 };
2153
2154 #define MLX5_FS_MAX_TYPES 10
2155 #define MLX5_FS_MAX_ENTRIES 32000UL
get_flow_table(struct mlx5_ib_dev * dev,struct ib_flow_attr * flow_attr,enum flow_table_type ft_type)2156 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2157 struct ib_flow_attr *flow_attr,
2158 enum flow_table_type ft_type)
2159 {
2160 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2161 struct mlx5_flow_namespace *ns = NULL;
2162 struct mlx5_ib_flow_prio *prio;
2163 struct mlx5_flow_table *ft;
2164 int num_entries;
2165 int num_groups;
2166 int priority;
2167 int err = 0;
2168
2169 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2170 if (flow_is_multicast_only(flow_attr) &&
2171 !dont_trap)
2172 priority = MLX5_IB_FLOW_MCAST_PRIO;
2173 else
2174 priority = ib_prio_to_core_prio(flow_attr->priority,
2175 dont_trap);
2176 ns = mlx5_get_flow_namespace(dev->mdev,
2177 MLX5_FLOW_NAMESPACE_BYPASS);
2178 num_entries = MLX5_FS_MAX_ENTRIES;
2179 num_groups = MLX5_FS_MAX_TYPES;
2180 prio = &dev->flow_db.prios[priority];
2181 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2182 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2183 ns = mlx5_get_flow_namespace(dev->mdev,
2184 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2185 build_leftovers_ft_param("bypass", &priority,
2186 &num_entries,
2187 &num_groups);
2188 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2189 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2190 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2191 allow_sniffer_and_nic_rx_shared_tir))
2192 return ERR_PTR(-ENOTSUPP);
2193
2194 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2195 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2196 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2197
2198 prio = &dev->flow_db.sniffer[ft_type];
2199 priority = 0;
2200 num_entries = 1;
2201 num_groups = 1;
2202 }
2203
2204 if (!ns)
2205 return ERR_PTR(-ENOTSUPP);
2206
2207 ft = prio->flow_table;
2208 if (!ft) {
2209 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass",
2210 num_entries,
2211 num_groups);
2212
2213 if (!IS_ERR(ft)) {
2214 prio->refcount = 0;
2215 prio->flow_table = ft;
2216 } else {
2217 err = PTR_ERR(ft);
2218 }
2219 }
2220
2221 return err ? ERR_PTR(err) : prio;
2222 }
2223
create_flow_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,const struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)2224 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2225 struct mlx5_ib_flow_prio *ft_prio,
2226 const struct ib_flow_attr *flow_attr,
2227 struct mlx5_flow_destination *dst)
2228 {
2229 struct mlx5_flow_table *ft = ft_prio->flow_table;
2230 struct mlx5_ib_flow_handler *handler;
2231 struct mlx5_flow_spec *spec;
2232 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2233 unsigned int spec_index;
2234 u32 action;
2235 int err = 0;
2236
2237 if (!is_valid_attr(flow_attr))
2238 return ERR_PTR(-EINVAL);
2239
2240 spec = mlx5_vzalloc(sizeof(*spec));
2241 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2242 if (!handler || !spec) {
2243 err = -ENOMEM;
2244 goto free;
2245 }
2246
2247 INIT_LIST_HEAD(&handler->list);
2248
2249 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2250 err = parse_flow_attr(spec->match_criteria,
2251 spec->match_value, ib_flow);
2252 if (err < 0)
2253 goto free;
2254
2255 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2256 }
2257
2258 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2259 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2260 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2261 handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable,
2262 spec->match_criteria,
2263 spec->match_value,
2264 action,
2265 MLX5_FS_DEFAULT_FLOW_TAG,
2266 dst);
2267
2268 if (IS_ERR(handler->rule)) {
2269 err = PTR_ERR(handler->rule);
2270 goto free;
2271 }
2272
2273 ft_prio->refcount++;
2274 handler->prio = ft_prio;
2275
2276 ft_prio->flow_table = ft;
2277 free:
2278 if (err)
2279 kfree(handler);
2280 kvfree(spec);
2281 return err ? ERR_PTR(err) : handler;
2282 }
2283
create_dont_trap_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)2284 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2285 struct mlx5_ib_flow_prio *ft_prio,
2286 struct ib_flow_attr *flow_attr,
2287 struct mlx5_flow_destination *dst)
2288 {
2289 struct mlx5_ib_flow_handler *handler_dst = NULL;
2290 struct mlx5_ib_flow_handler *handler = NULL;
2291
2292 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2293 if (!IS_ERR(handler)) {
2294 handler_dst = create_flow_rule(dev, ft_prio,
2295 flow_attr, dst);
2296 if (IS_ERR(handler_dst)) {
2297 mlx5_del_flow_rule(handler->rule);
2298 ft_prio->refcount--;
2299 kfree(handler);
2300 handler = handler_dst;
2301 } else {
2302 list_add(&handler_dst->list, &handler->list);
2303 }
2304 }
2305
2306 return handler;
2307 }
2308 enum {
2309 LEFTOVERS_MC,
2310 LEFTOVERS_UC,
2311 };
2312
create_leftovers_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)2313 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2314 struct mlx5_ib_flow_prio *ft_prio,
2315 struct ib_flow_attr *flow_attr,
2316 struct mlx5_flow_destination *dst)
2317 {
2318 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2319 struct mlx5_ib_flow_handler *handler = NULL;
2320
2321 static struct {
2322 struct ib_flow_attr flow_attr;
2323 struct ib_flow_spec_eth eth_flow;
2324 } leftovers_specs[] = {
2325 [LEFTOVERS_MC] = {
2326 .flow_attr = {
2327 .num_of_specs = 1,
2328 .size = sizeof(leftovers_specs[0])
2329 },
2330 .eth_flow = {
2331 .type = IB_FLOW_SPEC_ETH,
2332 .size = sizeof(struct ib_flow_spec_eth),
2333 .mask = {.dst_mac = {0x1} },
2334 .val = {.dst_mac = {0x1} }
2335 }
2336 },
2337 [LEFTOVERS_UC] = {
2338 .flow_attr = {
2339 .num_of_specs = 1,
2340 .size = sizeof(leftovers_specs[0])
2341 },
2342 .eth_flow = {
2343 .type = IB_FLOW_SPEC_ETH,
2344 .size = sizeof(struct ib_flow_spec_eth),
2345 .mask = {.dst_mac = {0x1} },
2346 .val = {.dst_mac = {} }
2347 }
2348 }
2349 };
2350
2351 handler = create_flow_rule(dev, ft_prio,
2352 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2353 dst);
2354 if (!IS_ERR(handler) &&
2355 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2356 handler_ucast = create_flow_rule(dev, ft_prio,
2357 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2358 dst);
2359 if (IS_ERR(handler_ucast)) {
2360 mlx5_del_flow_rule(handler->rule);
2361 ft_prio->refcount--;
2362 kfree(handler);
2363 handler = handler_ucast;
2364 } else {
2365 list_add(&handler_ucast->list, &handler->list);
2366 }
2367 }
2368
2369 return handler;
2370 }
2371
create_sniffer_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_rx,struct mlx5_ib_flow_prio * ft_tx,struct mlx5_flow_destination * dst)2372 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2373 struct mlx5_ib_flow_prio *ft_rx,
2374 struct mlx5_ib_flow_prio *ft_tx,
2375 struct mlx5_flow_destination *dst)
2376 {
2377 struct mlx5_ib_flow_handler *handler_rx;
2378 struct mlx5_ib_flow_handler *handler_tx;
2379 int err;
2380 static const struct ib_flow_attr flow_attr = {
2381 .num_of_specs = 0,
2382 .size = sizeof(flow_attr)
2383 };
2384
2385 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2386 if (IS_ERR(handler_rx)) {
2387 err = PTR_ERR(handler_rx);
2388 goto err;
2389 }
2390
2391 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2392 if (IS_ERR(handler_tx)) {
2393 err = PTR_ERR(handler_tx);
2394 goto err_tx;
2395 }
2396
2397 list_add(&handler_tx->list, &handler_rx->list);
2398
2399 return handler_rx;
2400
2401 err_tx:
2402 mlx5_del_flow_rule(handler_rx->rule);
2403 ft_rx->refcount--;
2404 kfree(handler_rx);
2405 err:
2406 return ERR_PTR(err);
2407 }
2408
mlx5_ib_create_flow(struct ib_qp * qp,struct ib_flow_attr * flow_attr,int domain)2409 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2410 struct ib_flow_attr *flow_attr,
2411 int domain)
2412 {
2413 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2414 struct mlx5_ib_qp *mqp = to_mqp(qp);
2415 struct mlx5_ib_flow_handler *handler = NULL;
2416 struct mlx5_flow_destination *dst = NULL;
2417 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2418 struct mlx5_ib_flow_prio *ft_prio;
2419 int err;
2420
2421 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2422 return ERR_PTR(-ENOSPC);
2423
2424 if (domain != IB_FLOW_DOMAIN_USER ||
2425 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2426 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2427 return ERR_PTR(-EINVAL);
2428
2429 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2430 if (!dst)
2431 return ERR_PTR(-ENOMEM);
2432
2433 mutex_lock(&dev->flow_db.lock);
2434
2435 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2436 if (IS_ERR(ft_prio)) {
2437 err = PTR_ERR(ft_prio);
2438 goto unlock;
2439 }
2440 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2441 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2442 if (IS_ERR(ft_prio_tx)) {
2443 err = PTR_ERR(ft_prio_tx);
2444 ft_prio_tx = NULL;
2445 goto destroy_ft;
2446 }
2447 }
2448
2449 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2450 if (mqp->flags & MLX5_IB_QP_RSS)
2451 dst->tir_num = mqp->rss_qp.tirn;
2452 else
2453 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2454
2455 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2456 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2457 handler = create_dont_trap_rule(dev, ft_prio,
2458 flow_attr, dst);
2459 } else {
2460 handler = create_flow_rule(dev, ft_prio, flow_attr,
2461 dst);
2462 }
2463 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2464 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2465 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2466 dst);
2467 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2468 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2469 } else {
2470 err = -EINVAL;
2471 goto destroy_ft;
2472 }
2473
2474 if (IS_ERR(handler)) {
2475 err = PTR_ERR(handler);
2476 handler = NULL;
2477 goto destroy_ft;
2478 }
2479
2480 mutex_unlock(&dev->flow_db.lock);
2481 kfree(dst);
2482
2483 return &handler->ibflow;
2484
2485 destroy_ft:
2486 put_flow_table(dev, ft_prio, false);
2487 if (ft_prio_tx)
2488 put_flow_table(dev, ft_prio_tx, false);
2489 unlock:
2490 mutex_unlock(&dev->flow_db.lock);
2491 kfree(dst);
2492 kfree(handler);
2493 return ERR_PTR(err);
2494 }
2495
mlx5_ib_mcg_attach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2496 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2497 {
2498 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2499 int err;
2500
2501 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2502 if (err)
2503 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2504 ibqp->qp_num, gid->raw);
2505
2506 return err;
2507 }
2508
mlx5_ib_mcg_detach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2509 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2510 {
2511 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2512 int err;
2513
2514 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2515 if (err)
2516 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2517 ibqp->qp_num, gid->raw);
2518
2519 return err;
2520 }
2521
init_node_data(struct mlx5_ib_dev * dev)2522 static int init_node_data(struct mlx5_ib_dev *dev)
2523 {
2524 int err;
2525
2526 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2527 if (err)
2528 return err;
2529
2530 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2531 }
2532
show_fw_pages(struct device * device,struct device_attribute * attr,char * buf)2533 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2534 char *buf)
2535 {
2536 struct mlx5_ib_dev *dev =
2537 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2538
2539 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages);
2540 }
2541
show_reg_pages(struct device * device,struct device_attribute * attr,char * buf)2542 static ssize_t show_reg_pages(struct device *device,
2543 struct device_attribute *attr, char *buf)
2544 {
2545 struct mlx5_ib_dev *dev =
2546 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2547
2548 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2549 }
2550
show_hca(struct device * device,struct device_attribute * attr,char * buf)2551 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2552 char *buf)
2553 {
2554 struct mlx5_ib_dev *dev =
2555 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2556 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2557 }
2558
show_rev(struct device * device,struct device_attribute * attr,char * buf)2559 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2560 char *buf)
2561 {
2562 struct mlx5_ib_dev *dev =
2563 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2564 return sprintf(buf, "%x\n", dev->mdev->pdev->revision);
2565 }
2566
show_board(struct device * device,struct device_attribute * attr,char * buf)2567 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2568 char *buf)
2569 {
2570 struct mlx5_ib_dev *dev =
2571 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2572 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2573 dev->mdev->board_id);
2574 }
2575
2576 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2577 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2578 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2579 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2580 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2581
2582 static struct device_attribute *mlx5_class_attributes[] = {
2583 &dev_attr_hw_rev,
2584 &dev_attr_hca_type,
2585 &dev_attr_board_id,
2586 &dev_attr_fw_pages,
2587 &dev_attr_reg_pages,
2588 };
2589
pkey_change_handler(struct work_struct * work)2590 static void pkey_change_handler(struct work_struct *work)
2591 {
2592 struct mlx5_ib_port_resources *ports =
2593 container_of(work, struct mlx5_ib_port_resources,
2594 pkey_change_work);
2595
2596 mutex_lock(&ports->devr->mutex);
2597 mlx5_ib_gsi_pkey_change(ports->gsi);
2598 mutex_unlock(&ports->devr->mutex);
2599 }
2600
mlx5_ib_handle_internal_error(struct mlx5_ib_dev * ibdev)2601 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2602 {
2603 struct mlx5_ib_qp *mqp;
2604 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2605 struct mlx5_core_cq *mcq;
2606 struct list_head cq_armed_list;
2607 unsigned long flags_qp;
2608 unsigned long flags_cq;
2609 unsigned long flags;
2610
2611 INIT_LIST_HEAD(&cq_armed_list);
2612
2613 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2614 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2615 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2616 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2617 if (mqp->sq.tail != mqp->sq.head) {
2618 send_mcq = to_mcq(mqp->ibqp.send_cq);
2619 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2620 if (send_mcq->mcq.comp &&
2621 mqp->ibqp.send_cq->comp_handler) {
2622 if (!send_mcq->mcq.reset_notify_added) {
2623 send_mcq->mcq.reset_notify_added = 1;
2624 list_add_tail(&send_mcq->mcq.reset_notify,
2625 &cq_armed_list);
2626 }
2627 }
2628 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2629 }
2630 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2631 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2632 /* no handling is needed for SRQ */
2633 if (!mqp->ibqp.srq) {
2634 if (mqp->rq.tail != mqp->rq.head) {
2635 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2636 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2637 if (recv_mcq->mcq.comp &&
2638 mqp->ibqp.recv_cq->comp_handler) {
2639 if (!recv_mcq->mcq.reset_notify_added) {
2640 recv_mcq->mcq.reset_notify_added = 1;
2641 list_add_tail(&recv_mcq->mcq.reset_notify,
2642 &cq_armed_list);
2643 }
2644 }
2645 spin_unlock_irqrestore(&recv_mcq->lock,
2646 flags_cq);
2647 }
2648 }
2649 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2650 }
2651 /*At that point all inflight post send were put to be executed as of we
2652 * lock/unlock above locks Now need to arm all involved CQs.
2653 */
2654 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2655 mcq->comp(mcq, NULL);
2656 }
2657 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2658 }
2659
mlx5_ib_event(struct mlx5_core_dev * dev,void * context,enum mlx5_dev_event event,unsigned long param)2660 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2661 enum mlx5_dev_event event, unsigned long param)
2662 {
2663 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2664 struct ib_event ibev;
2665 bool fatal = false;
2666 u8 port = (u8)param;
2667
2668 switch (event) {
2669 case MLX5_DEV_EVENT_SYS_ERROR:
2670 ibev.event = IB_EVENT_DEVICE_FATAL;
2671 mlx5_ib_handle_internal_error(ibdev);
2672 fatal = true;
2673 break;
2674
2675 case MLX5_DEV_EVENT_PORT_UP:
2676 case MLX5_DEV_EVENT_PORT_DOWN:
2677 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2678 /* In RoCE, port up/down events are handled in
2679 * mlx5_netdev_event().
2680 */
2681 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2682 IB_LINK_LAYER_ETHERNET)
2683 return;
2684
2685 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2686 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2687 break;
2688
2689 case MLX5_DEV_EVENT_LID_CHANGE:
2690 ibev.event = IB_EVENT_LID_CHANGE;
2691 break;
2692
2693 case MLX5_DEV_EVENT_PKEY_CHANGE:
2694 ibev.event = IB_EVENT_PKEY_CHANGE;
2695
2696 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2697 break;
2698
2699 case MLX5_DEV_EVENT_GUID_CHANGE:
2700 ibev.event = IB_EVENT_GID_CHANGE;
2701 break;
2702
2703 case MLX5_DEV_EVENT_CLIENT_REREG:
2704 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2705 break;
2706
2707 default:
2708 /* unsupported event */
2709 return;
2710 }
2711
2712 ibev.device = &ibdev->ib_dev;
2713 ibev.element.port_num = port;
2714
2715 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
2716 mlx5_ib_warn(ibdev, "warning: event(%d) on port %d\n", event, port);
2717 return;
2718 }
2719
2720 if (ibdev->ib_active)
2721 ib_dispatch_event(&ibev);
2722
2723 if (fatal)
2724 ibdev->ib_active = false;
2725 }
2726
get_ext_port_caps(struct mlx5_ib_dev * dev)2727 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2728 {
2729 int port;
2730
2731 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2732 mlx5_query_ext_port_caps(dev, port);
2733 }
2734
get_port_caps(struct mlx5_ib_dev * dev)2735 static int get_port_caps(struct mlx5_ib_dev *dev)
2736 {
2737 struct ib_device_attr *dprops = NULL;
2738 struct ib_port_attr *pprops = NULL;
2739 int err = -ENOMEM;
2740 int port;
2741 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2742
2743 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2744 if (!pprops)
2745 goto out;
2746
2747 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2748 if (!dprops)
2749 goto out;
2750
2751 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2752 if (err) {
2753 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2754 goto out;
2755 }
2756
2757 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2758 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2759 if (err) {
2760 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2761 port, err);
2762 break;
2763 }
2764 dev->mdev->port_caps[port - 1].pkey_table_len =
2765 dprops->max_pkeys;
2766 dev->mdev->port_caps[port - 1].gid_table_len =
2767 pprops->gid_tbl_len;
2768 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2769 dprops->max_pkeys, pprops->gid_tbl_len);
2770 }
2771
2772 out:
2773 kfree(pprops);
2774 kfree(dprops);
2775
2776 return err;
2777 }
2778
destroy_umrc_res(struct mlx5_ib_dev * dev)2779 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2780 {
2781 int err;
2782
2783 err = mlx5_mr_cache_cleanup(dev);
2784 if (err)
2785 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2786
2787 mlx5_ib_destroy_qp(dev->umrc.qp);
2788 ib_free_cq(dev->umrc.cq);
2789 ib_dealloc_pd(dev->umrc.pd);
2790 }
2791
2792 enum {
2793 MAX_UMR_WR = 128,
2794 };
2795
create_umr_res(struct mlx5_ib_dev * dev)2796 static int create_umr_res(struct mlx5_ib_dev *dev)
2797 {
2798 struct ib_qp_init_attr *init_attr = NULL;
2799 struct ib_qp_attr *attr = NULL;
2800 struct ib_pd *pd;
2801 struct ib_cq *cq;
2802 struct ib_qp *qp;
2803 int ret;
2804
2805 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2806 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2807 if (!attr || !init_attr) {
2808 ret = -ENOMEM;
2809 goto error_0;
2810 }
2811
2812 pd = ib_alloc_pd(&dev->ib_dev, 0);
2813 if (IS_ERR(pd)) {
2814 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2815 ret = PTR_ERR(pd);
2816 goto error_0;
2817 }
2818
2819 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2820 if (IS_ERR(cq)) {
2821 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2822 ret = PTR_ERR(cq);
2823 goto error_2;
2824 }
2825
2826 init_attr->send_cq = cq;
2827 init_attr->recv_cq = cq;
2828 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2829 init_attr->cap.max_send_wr = MAX_UMR_WR;
2830 init_attr->cap.max_send_sge = 1;
2831 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2832 init_attr->port_num = 1;
2833 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2834 if (IS_ERR(qp)) {
2835 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2836 ret = PTR_ERR(qp);
2837 goto error_3;
2838 }
2839 qp->device = &dev->ib_dev;
2840 qp->real_qp = qp;
2841 qp->uobject = NULL;
2842 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2843
2844 attr->qp_state = IB_QPS_INIT;
2845 attr->port_num = 1;
2846 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2847 IB_QP_PORT, NULL);
2848 if (ret) {
2849 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2850 goto error_4;
2851 }
2852
2853 memset(attr, 0, sizeof(*attr));
2854 attr->qp_state = IB_QPS_RTR;
2855 attr->path_mtu = IB_MTU_256;
2856
2857 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2858 if (ret) {
2859 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2860 goto error_4;
2861 }
2862
2863 memset(attr, 0, sizeof(*attr));
2864 attr->qp_state = IB_QPS_RTS;
2865 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2866 if (ret) {
2867 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2868 goto error_4;
2869 }
2870
2871 dev->umrc.qp = qp;
2872 dev->umrc.cq = cq;
2873 dev->umrc.pd = pd;
2874
2875 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2876 ret = mlx5_mr_cache_init(dev);
2877 if (ret) {
2878 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2879 goto error_4;
2880 }
2881
2882 kfree(attr);
2883 kfree(init_attr);
2884
2885 return 0;
2886
2887 error_4:
2888 mlx5_ib_destroy_qp(qp);
2889
2890 error_3:
2891 ib_free_cq(cq);
2892
2893 error_2:
2894 ib_dealloc_pd(pd);
2895
2896 error_0:
2897 kfree(attr);
2898 kfree(init_attr);
2899 return ret;
2900 }
2901
create_dev_resources(struct mlx5_ib_resources * devr)2902 static int create_dev_resources(struct mlx5_ib_resources *devr)
2903 {
2904 struct ib_srq_init_attr attr;
2905 struct mlx5_ib_dev *dev;
2906 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2907 int port;
2908 int ret = 0;
2909
2910 dev = container_of(devr, struct mlx5_ib_dev, devr);
2911
2912 mutex_init(&devr->mutex);
2913
2914 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2915 if (IS_ERR(devr->p0)) {
2916 ret = PTR_ERR(devr->p0);
2917 goto error0;
2918 }
2919 devr->p0->device = &dev->ib_dev;
2920 devr->p0->uobject = NULL;
2921 atomic_set(&devr->p0->usecnt, 0);
2922
2923 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2924 if (IS_ERR(devr->c0)) {
2925 ret = PTR_ERR(devr->c0);
2926 goto error1;
2927 }
2928 devr->c0->device = &dev->ib_dev;
2929 devr->c0->uobject = NULL;
2930 devr->c0->comp_handler = NULL;
2931 devr->c0->event_handler = NULL;
2932 devr->c0->cq_context = NULL;
2933 atomic_set(&devr->c0->usecnt, 0);
2934
2935 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2936 if (IS_ERR(devr->x0)) {
2937 ret = PTR_ERR(devr->x0);
2938 goto error2;
2939 }
2940 devr->x0->device = &dev->ib_dev;
2941 devr->x0->inode = NULL;
2942 atomic_set(&devr->x0->usecnt, 0);
2943 mutex_init(&devr->x0->tgt_qp_mutex);
2944 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2945
2946 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2947 if (IS_ERR(devr->x1)) {
2948 ret = PTR_ERR(devr->x1);
2949 goto error3;
2950 }
2951 devr->x1->device = &dev->ib_dev;
2952 devr->x1->inode = NULL;
2953 atomic_set(&devr->x1->usecnt, 0);
2954 mutex_init(&devr->x1->tgt_qp_mutex);
2955 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2956
2957 memset(&attr, 0, sizeof(attr));
2958 attr.attr.max_sge = 1;
2959 attr.attr.max_wr = 1;
2960 attr.srq_type = IB_SRQT_XRC;
2961 attr.ext.xrc.cq = devr->c0;
2962 attr.ext.xrc.xrcd = devr->x0;
2963
2964 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2965 if (IS_ERR(devr->s0)) {
2966 ret = PTR_ERR(devr->s0);
2967 goto error4;
2968 }
2969 devr->s0->device = &dev->ib_dev;
2970 devr->s0->pd = devr->p0;
2971 devr->s0->uobject = NULL;
2972 devr->s0->event_handler = NULL;
2973 devr->s0->srq_context = NULL;
2974 devr->s0->srq_type = IB_SRQT_XRC;
2975 devr->s0->ext.xrc.xrcd = devr->x0;
2976 devr->s0->ext.xrc.cq = devr->c0;
2977 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2978 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2979 atomic_inc(&devr->p0->usecnt);
2980 atomic_set(&devr->s0->usecnt, 0);
2981
2982 memset(&attr, 0, sizeof(attr));
2983 attr.attr.max_sge = 1;
2984 attr.attr.max_wr = 1;
2985 attr.srq_type = IB_SRQT_BASIC;
2986 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2987 if (IS_ERR(devr->s1)) {
2988 ret = PTR_ERR(devr->s1);
2989 goto error5;
2990 }
2991 devr->s1->device = &dev->ib_dev;
2992 devr->s1->pd = devr->p0;
2993 devr->s1->uobject = NULL;
2994 devr->s1->event_handler = NULL;
2995 devr->s1->srq_context = NULL;
2996 devr->s1->srq_type = IB_SRQT_BASIC;
2997 devr->s1->ext.xrc.cq = devr->c0;
2998 atomic_inc(&devr->p0->usecnt);
2999 atomic_set(&devr->s0->usecnt, 0);
3000
3001 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3002 INIT_WORK(&devr->ports[port].pkey_change_work,
3003 pkey_change_handler);
3004 devr->ports[port].devr = devr;
3005 }
3006
3007 return 0;
3008
3009 error5:
3010 mlx5_ib_destroy_srq(devr->s0);
3011 error4:
3012 mlx5_ib_dealloc_xrcd(devr->x1);
3013 error3:
3014 mlx5_ib_dealloc_xrcd(devr->x0);
3015 error2:
3016 mlx5_ib_destroy_cq(devr->c0);
3017 error1:
3018 mlx5_ib_dealloc_pd(devr->p0);
3019 error0:
3020 return ret;
3021 }
3022
destroy_dev_resources(struct mlx5_ib_resources * devr)3023 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3024 {
3025 struct mlx5_ib_dev *dev =
3026 container_of(devr, struct mlx5_ib_dev, devr);
3027 int port;
3028
3029 mlx5_ib_destroy_srq(devr->s1);
3030 mlx5_ib_destroy_srq(devr->s0);
3031 mlx5_ib_dealloc_xrcd(devr->x0);
3032 mlx5_ib_dealloc_xrcd(devr->x1);
3033 mlx5_ib_destroy_cq(devr->c0);
3034 mlx5_ib_dealloc_pd(devr->p0);
3035
3036 /* Make sure no change P_Key work items are still executing */
3037 for (port = 0; port < dev->num_ports; ++port)
3038 cancel_work_sync(&devr->ports[port].pkey_change_work);
3039 }
3040
get_core_cap_flags(struct ib_device * ibdev)3041 static u32 get_core_cap_flags(struct ib_device *ibdev)
3042 {
3043 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3044 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3045 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3046 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3047 u32 ret = 0;
3048
3049 if (ll == IB_LINK_LAYER_INFINIBAND)
3050 return RDMA_CORE_PORT_IBA_IB;
3051
3052 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3053 return 0;
3054
3055 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3056 return 0;
3057
3058 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3059 ret |= RDMA_CORE_PORT_IBA_ROCE;
3060
3061 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3062 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3063
3064 return ret;
3065 }
3066
mlx5_port_immutable(struct ib_device * ibdev,u8 port_num,struct ib_port_immutable * immutable)3067 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3068 struct ib_port_immutable *immutable)
3069 {
3070 struct ib_port_attr attr;
3071 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3072 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3073 int err;
3074
3075 err = mlx5_ib_query_port(ibdev, port_num, &attr);
3076 if (err)
3077 return err;
3078
3079 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3080 immutable->gid_tbl_len = attr.gid_tbl_len;
3081 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3082 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3083 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3084
3085 return 0;
3086 }
3087
get_dev_fw_str(struct ib_device * ibdev,char * str,size_t str_len)3088 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
3089 size_t str_len)
3090 {
3091 struct mlx5_ib_dev *dev =
3092 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3093 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
3094 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
3095 }
3096
mlx5_roce_lag_init(struct mlx5_ib_dev * dev)3097 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
3098 {
3099 return 0;
3100 }
3101
mlx5_roce_lag_cleanup(struct mlx5_ib_dev * dev)3102 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
3103 {
3104 }
3105
mlx5_remove_roce_notifier(struct mlx5_ib_dev * dev)3106 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
3107 {
3108 if (dev->roce.nb.notifier_call) {
3109 unregister_netdevice_notifier(&dev->roce.nb);
3110 dev->roce.nb.notifier_call = NULL;
3111 }
3112 }
3113
mlx5_enable_roce(struct mlx5_ib_dev * dev)3114 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
3115 {
3116 VNET_ITERATOR_DECL(vnet_iter);
3117 struct ifnet *idev;
3118 int err;
3119
3120 /* Check if mlx5en net device already exists */
3121 VNET_LIST_RLOCK();
3122 VNET_FOREACH(vnet_iter) {
3123 IFNET_RLOCK();
3124 CURVNET_SET_QUIET(vnet_iter);
3125 CK_STAILQ_FOREACH(idev, &V_ifnet, if_link) {
3126 /* check if network interface belongs to mlx5en */
3127 if (!mlx5_netdev_match(idev, dev->mdev, "mce"))
3128 continue;
3129 write_lock(&dev->roce.netdev_lock);
3130 dev->roce.netdev = idev;
3131 write_unlock(&dev->roce.netdev_lock);
3132 }
3133 CURVNET_RESTORE();
3134 IFNET_RUNLOCK();
3135 }
3136 VNET_LIST_RUNLOCK();
3137
3138 dev->roce.nb.notifier_call = mlx5_netdev_event;
3139 err = register_netdevice_notifier(&dev->roce.nb);
3140 if (err) {
3141 dev->roce.nb.notifier_call = NULL;
3142 return err;
3143 }
3144
3145 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3146 err = mlx5_nic_vport_enable_roce(dev->mdev);
3147 if (err)
3148 goto err_unregister_netdevice_notifier;
3149 }
3150
3151 err = mlx5_roce_lag_init(dev);
3152 if (err)
3153 goto err_disable_roce;
3154
3155 return 0;
3156
3157 err_disable_roce:
3158 if (MLX5_CAP_GEN(dev->mdev, roce))
3159 mlx5_nic_vport_disable_roce(dev->mdev);
3160
3161 err_unregister_netdevice_notifier:
3162 mlx5_remove_roce_notifier(dev);
3163 return err;
3164 }
3165
mlx5_disable_roce(struct mlx5_ib_dev * dev)3166 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
3167 {
3168 mlx5_roce_lag_cleanup(dev);
3169 if (MLX5_CAP_GEN(dev->mdev, roce))
3170 mlx5_nic_vport_disable_roce(dev->mdev);
3171 }
3172
mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev * dev,u8 port_num)3173 static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num)
3174 {
3175 mlx5_vport_dealloc_q_counter(dev->mdev,
3176 MLX5_INTERFACE_PROTOCOL_IB,
3177 dev->port[port_num].q_cnt_id);
3178 dev->port[port_num].q_cnt_id = 0;
3179 }
3180
mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev * dev)3181 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
3182 {
3183 unsigned int i;
3184
3185 for (i = 0; i < dev->num_ports; i++)
3186 mlx5_ib_dealloc_q_port_counter(dev, i);
3187 }
3188
mlx5_ib_alloc_q_counters(struct mlx5_ib_dev * dev)3189 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
3190 {
3191 int i;
3192 int ret;
3193
3194 for (i = 0; i < dev->num_ports; i++) {
3195 ret = mlx5_vport_alloc_q_counter(dev->mdev,
3196 MLX5_INTERFACE_PROTOCOL_IB,
3197 &dev->port[i].q_cnt_id);
3198 if (ret) {
3199 mlx5_ib_warn(dev,
3200 "couldn't allocate queue counter for port %d, err %d\n",
3201 i + 1, ret);
3202 goto dealloc_counters;
3203 }
3204 }
3205
3206 return 0;
3207
3208 dealloc_counters:
3209 while (--i >= 0)
3210 mlx5_ib_dealloc_q_port_counter(dev, i);
3211
3212 return ret;
3213 }
3214
3215 static const char * const names[] = {
3216 "rx_write_requests",
3217 "rx_read_requests",
3218 "rx_atomic_requests",
3219 "out_of_buffer",
3220 "out_of_sequence",
3221 "duplicate_request",
3222 "rnr_nak_retry_err",
3223 "packet_seq_err",
3224 "implied_nak_seq_err",
3225 "local_ack_timeout_err",
3226 };
3227
3228 static const size_t stats_offsets[] = {
3229 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
3230 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
3231 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
3232 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
3233 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
3234 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
3235 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
3236 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
3237 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
3238 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
3239 };
3240
mlx5_ib_alloc_hw_stats(struct ib_device * ibdev,u8 port_num)3241 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3242 u8 port_num)
3243 {
3244 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
3245
3246 /* We support only per port stats */
3247 if (port_num == 0)
3248 return NULL;
3249
3250 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
3251 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3252 }
3253
mlx5_ib_get_hw_stats(struct ib_device * ibdev,struct rdma_hw_stats * stats,u8 port,int index)3254 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3255 struct rdma_hw_stats *stats,
3256 u8 port, int index)
3257 {
3258 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3259 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3260 void *out;
3261 __be32 val;
3262 int ret;
3263 int i;
3264
3265 if (!port || !stats)
3266 return -ENOSYS;
3267
3268 out = mlx5_vzalloc(outlen);
3269 if (!out)
3270 return -ENOMEM;
3271
3272 ret = mlx5_vport_query_q_counter(dev->mdev,
3273 dev->port[port - 1].q_cnt_id, 0,
3274 out, outlen);
3275 if (ret)
3276 goto free;
3277
3278 for (i = 0; i < ARRAY_SIZE(names); i++) {
3279 val = *(__be32 *)(out + stats_offsets[i]);
3280 stats->value[i] = (u64)be32_to_cpu(val);
3281 }
3282 free:
3283 kvfree(out);
3284 return ARRAY_SIZE(names);
3285 }
3286
mlx5_ib_stage_bfreg_init(struct mlx5_ib_dev * dev)3287 static int mlx5_ib_stage_bfreg_init(struct mlx5_ib_dev *dev)
3288 {
3289 int err;
3290
3291 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3292 if (err)
3293 return err;
3294
3295 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3296 if (err) {
3297 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3298 return err;
3299 }
3300
3301 err = mlx5_alloc_bfreg(dev->mdev, &dev->wc_bfreg, true, false);
3302 if (err) {
3303 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3304 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3305 }
3306
3307 return err;
3308 }
3309
mlx5_ib_stage_bfreg_cleanup(struct mlx5_ib_dev * dev)3310 static void mlx5_ib_stage_bfreg_cleanup(struct mlx5_ib_dev *dev)
3311 {
3312 mlx5_free_bfreg(dev->mdev, &dev->wc_bfreg);
3313 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3314 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3315 }
3316
mlx5_ib_add(struct mlx5_core_dev * mdev)3317 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3318 {
3319 struct mlx5_ib_dev *dev;
3320 enum rdma_link_layer ll;
3321 int port_type_cap;
3322 int err;
3323 int i;
3324
3325 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3326 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3327
3328 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3329 if (!dev)
3330 return NULL;
3331
3332 dev->mdev = mdev;
3333
3334 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3335 GFP_KERNEL);
3336 if (!dev->port)
3337 goto err_dealloc;
3338
3339 rwlock_init(&dev->roce.netdev_lock);
3340 err = get_port_caps(dev);
3341 if (err)
3342 goto err_free_port;
3343
3344 if (mlx5_use_mad_ifc(dev))
3345 get_ext_port_caps(dev);
3346
3347 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
3348
3349 mutex_init(&dev->lb_mutex);
3350
3351 snprintf(dev->ib_dev.name, IB_DEVICE_NAME_MAX, "mlx5_%d", device_get_unit(mdev->pdev->dev.bsddev));
3352 dev->ib_dev.owner = THIS_MODULE;
3353 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3354 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3355 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
3356 dev->ib_dev.phys_port_cnt = dev->num_ports;
3357 dev->ib_dev.num_comp_vectors =
3358 dev->mdev->priv.eq_table.num_comp_vectors;
3359 dev->ib_dev.dma_device = &mdev->pdev->dev;
3360
3361 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3362 dev->ib_dev.uverbs_cmd_mask =
3363 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3364 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3365 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3366 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3367 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
3368 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3369 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
3370 (1ull << IB_USER_VERBS_CMD_REG_MR) |
3371 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
3372 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3373 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3374 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3375 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3376 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3377 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3378 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3379 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3380 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3381 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3382 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3383 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3384 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3385 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3386 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3387 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3388 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3389 dev->ib_dev.uverbs_ex_cmd_mask =
3390 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3391 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3392 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3393
3394 dev->ib_dev.query_device = mlx5_ib_query_device;
3395 dev->ib_dev.query_port = mlx5_ib_query_port;
3396 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3397 if (ll == IB_LINK_LAYER_ETHERNET)
3398 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
3399 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3400 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3401 dev->ib_dev.del_gid = mlx5_ib_del_gid;
3402 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3403 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3404 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3405 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3406 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3407 dev->ib_dev.mmap = mlx5_ib_mmap;
3408 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3409 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3410 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3411 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3412 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3413 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3414 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3415 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3416 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3417 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3418 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3419 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3420 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3421 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3422 dev->ib_dev.post_send = mlx5_ib_post_send;
3423 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3424 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3425 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3426 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3427 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3428 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3429 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3430 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3431 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
3432 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
3433 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3434 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3435 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3436 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3437 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3438 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3439 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3440 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3441 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3442 if (mlx5_core_is_pf(mdev)) {
3443 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3444 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3445 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3446 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3447 }
3448
3449 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3450
3451 mlx5_ib_internal_fill_odp_caps(dev);
3452
3453 if (MLX5_CAP_GEN(mdev, imaicl)) {
3454 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3455 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3456 dev->ib_dev.uverbs_cmd_mask |=
3457 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3458 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3459 }
3460
3461 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3462 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3463 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3464 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3465 }
3466
3467 if (MLX5_CAP_GEN(mdev, xrc)) {
3468 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3469 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3470 dev->ib_dev.uverbs_cmd_mask |=
3471 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3472 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3473 }
3474
3475 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3476 IB_LINK_LAYER_ETHERNET) {
3477 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3478 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3479 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3480 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3481 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
3482 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3483 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3484 dev->ib_dev.uverbs_ex_cmd_mask |=
3485 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3486 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3487 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3488 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3489 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3490 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3491 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3492 }
3493 err = init_node_data(dev);
3494 if (err)
3495 goto err_free_port;
3496
3497 mutex_init(&dev->flow_db.lock);
3498 mutex_init(&dev->cap_mask_mutex);
3499 INIT_LIST_HEAD(&dev->qp_list);
3500 spin_lock_init(&dev->reset_flow_resource_lock);
3501
3502 if (ll == IB_LINK_LAYER_ETHERNET) {
3503 err = mlx5_enable_roce(dev);
3504 if (err)
3505 goto err_free_port;
3506 }
3507
3508 err = create_dev_resources(&dev->devr);
3509 if (err)
3510 goto err_disable_roce;
3511
3512 err = mlx5_ib_odp_init_one(dev);
3513 if (err)
3514 goto err_rsrc;
3515
3516 err = mlx5_ib_alloc_q_counters(dev);
3517 if (err)
3518 goto err_odp;
3519
3520 err = mlx5_ib_stage_bfreg_init(dev);
3521 if (err)
3522 goto err_q_cnt;
3523
3524 err = ib_register_device(&dev->ib_dev, NULL);
3525 if (err)
3526 goto err_bfreg;
3527
3528 err = create_umr_res(dev);
3529 if (err)
3530 goto err_dev;
3531
3532 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3533 err = device_create_file(&dev->ib_dev.dev,
3534 mlx5_class_attributes[i]);
3535 if (err)
3536 goto err_umrc;
3537 }
3538
3539 err = mlx5_ib_init_congestion(dev);
3540 if (err)
3541 goto err_umrc;
3542
3543 dev->ib_active = true;
3544
3545 return dev;
3546
3547 err_umrc:
3548 destroy_umrc_res(dev);
3549
3550 err_dev:
3551 ib_unregister_device(&dev->ib_dev);
3552
3553 err_bfreg:
3554 mlx5_ib_stage_bfreg_cleanup(dev);
3555
3556 err_q_cnt:
3557 mlx5_ib_dealloc_q_counters(dev);
3558
3559 err_odp:
3560 mlx5_ib_odp_remove_one(dev);
3561
3562 err_rsrc:
3563 destroy_dev_resources(&dev->devr);
3564
3565 err_disable_roce:
3566 if (ll == IB_LINK_LAYER_ETHERNET) {
3567 mlx5_disable_roce(dev);
3568 mlx5_remove_roce_notifier(dev);
3569 }
3570
3571 err_free_port:
3572 kfree(dev->port);
3573
3574 err_dealloc:
3575 ib_dealloc_device((struct ib_device *)dev);
3576
3577 return NULL;
3578 }
3579
mlx5_ib_remove(struct mlx5_core_dev * mdev,void * context)3580 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3581 {
3582 struct mlx5_ib_dev *dev = context;
3583 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3584
3585 mlx5_ib_cleanup_congestion(dev);
3586 mlx5_remove_roce_notifier(dev);
3587 ib_unregister_device(&dev->ib_dev);
3588 mlx5_ib_stage_bfreg_cleanup(dev);
3589 mlx5_ib_dealloc_q_counters(dev);
3590 destroy_umrc_res(dev);
3591 mlx5_ib_odp_remove_one(dev);
3592 destroy_dev_resources(&dev->devr);
3593 if (ll == IB_LINK_LAYER_ETHERNET)
3594 mlx5_disable_roce(dev);
3595 kfree(dev->port);
3596 ib_dealloc_device(&dev->ib_dev);
3597 }
3598
3599 static struct mlx5_interface mlx5_ib_interface = {
3600 .add = mlx5_ib_add,
3601 .remove = mlx5_ib_remove,
3602 .event = mlx5_ib_event,
3603 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
3604 };
3605
mlx5_ib_init(void)3606 static int __init mlx5_ib_init(void)
3607 {
3608 int err;
3609
3610 err = mlx5_ib_odp_init();
3611 if (err)
3612 return err;
3613
3614 err = mlx5_register_interface(&mlx5_ib_interface);
3615 if (err)
3616 goto clean_odp;
3617
3618 return err;
3619
3620 clean_odp:
3621 mlx5_ib_odp_cleanup();
3622 return err;
3623 }
3624
mlx5_ib_cleanup(void)3625 static void __exit mlx5_ib_cleanup(void)
3626 {
3627 mlx5_unregister_interface(&mlx5_ib_interface);
3628 mlx5_ib_odp_cleanup();
3629 }
3630
3631 module_init_order(mlx5_ib_init, SI_ORDER_SEVENTH);
3632 module_exit_order(mlx5_ib_cleanup, SI_ORDER_SEVENTH);
3633