1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013-2015 The FreeBSD Foundation
5 * All rights reserved.
6 *
7 * This software was developed by Konstantin Belousov <[email protected]>
8 * under sponsorship from the FreeBSD Foundation.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD$
32 */
33
34 #ifndef __X86_IOMMU_INTEL_DMAR_H
35 #define __X86_IOMMU_INTEL_DMAR_H
36
37 /* Host or physical memory address, after translation. */
38 typedef uint64_t dmar_haddr_t;
39 /* Guest or bus address, before translation. */
40 typedef uint64_t dmar_gaddr_t;
41
42 struct dmar_qi_genseq {
43 u_int gen;
44 uint32_t seq;
45 };
46
47 struct dmar_map_entry {
48 dmar_gaddr_t start;
49 dmar_gaddr_t end;
50 dmar_gaddr_t free_after; /* Free space after the entry */
51 dmar_gaddr_t free_down; /* Max free space below the
52 current R/B tree node */
53 u_int flags;
54 TAILQ_ENTRY(dmar_map_entry) dmamap_link; /* Link for dmamap entries */
55 RB_ENTRY(dmar_map_entry) rb_entry; /* Links for domain entries */
56 TAILQ_ENTRY(dmar_map_entry) unroll_link; /* Link for unroll after
57 dmamap_load failure */
58 struct dmar_domain *domain;
59 struct dmar_qi_genseq gseq;
60 };
61
62 RB_HEAD(dmar_gas_entries_tree, dmar_map_entry);
63 RB_PROTOTYPE(dmar_gas_entries_tree, dmar_map_entry, rb_entry,
64 dmar_gas_cmp_entries);
65
66 #define DMAR_MAP_ENTRY_PLACE 0x0001 /* Fake entry */
67 #define DMAR_MAP_ENTRY_RMRR 0x0002 /* Permanent, not linked by
68 dmamap_link */
69 #define DMAR_MAP_ENTRY_MAP 0x0004 /* Busdma created, linked by
70 dmamap_link */
71 #define DMAR_MAP_ENTRY_UNMAPPED 0x0010 /* No backing pages */
72 #define DMAR_MAP_ENTRY_QI_NF 0x0020 /* qi task, do not free entry */
73 #define DMAR_MAP_ENTRY_READ 0x1000 /* Read permitted */
74 #define DMAR_MAP_ENTRY_WRITE 0x2000 /* Write permitted */
75 #define DMAR_MAP_ENTRY_SNOOP 0x4000 /* Snoop */
76 #define DMAR_MAP_ENTRY_TM 0x8000 /* Transient */
77
78 /*
79 * Locking annotations:
80 * (u) - Protected by dmar unit lock
81 * (d) - Protected by domain lock
82 * (c) - Immutable after initialization
83 */
84
85 /*
86 * The domain abstraction. Most non-constant members of the domain
87 * are protected by owning dmar unit lock, not by the domain lock.
88 * Most important, the dmar lock protects the contexts list.
89 *
90 * The domain lock protects the address map for the domain, and list
91 * of unload entries delayed.
92 *
93 * Page tables pages and pages content is protected by the vm object
94 * lock pgtbl_obj, which contains the page tables pages.
95 */
96 struct dmar_domain {
97 int domain; /* (c) DID, written in context entry */
98 int mgaw; /* (c) Real max address width */
99 int agaw; /* (c) Adjusted guest address width */
100 int pglvl; /* (c) The pagelevel */
101 int awlvl; /* (c) The pagelevel as the bitmask,
102 to set in context entry */
103 dmar_gaddr_t end; /* (c) Highest address + 1 in
104 the guest AS */
105 u_int ctx_cnt; /* (u) Number of contexts owned */
106 u_int refs; /* (u) Refs, including ctx */
107 struct dmar_unit *dmar; /* (c) */
108 struct mtx lock; /* (c) */
109 LIST_ENTRY(dmar_domain) link; /* (u) Member in the dmar list */
110 LIST_HEAD(, dmar_ctx) contexts; /* (u) */
111 vm_object_t pgtbl_obj; /* (c) Page table pages */
112 u_int flags; /* (u) */
113 u_int entries_cnt; /* (d) */
114 struct dmar_gas_entries_tree rb_root; /* (d) */
115 struct dmar_map_entries_tailq unload_entries; /* (d) Entries to
116 unload */
117 struct dmar_map_entry *first_place, *last_place; /* (d) */
118 struct task unload_task; /* (c) */
119 u_int batch_no;
120 };
121
122 struct dmar_ctx {
123 struct bus_dma_tag_dmar ctx_tag; /* (c) Root tag */
124 uint16_t rid; /* (c) pci RID */
125 uint64_t last_fault_rec[2]; /* Last fault reported */
126 struct dmar_domain *domain; /* (c) */
127 LIST_ENTRY(dmar_ctx) link; /* (u) Member in the domain list */
128 u_int refs; /* (u) References from tags */
129 u_int flags; /* (u) */
130 u_long loads; /* atomic updates, for stat only */
131 u_long unloads; /* same */
132 };
133
134 #define DMAR_DOMAIN_GAS_INITED 0x0001
135 #define DMAR_DOMAIN_PGTBL_INITED 0x0002
136 #define DMAR_DOMAIN_IDMAP 0x0010 /* Domain uses identity
137 page table */
138 #define DMAR_DOMAIN_RMRR 0x0020 /* Domain contains RMRR entry,
139 cannot be turned off */
140
141 /* struct dmar_ctx flags */
142 #define DMAR_CTX_FAULTED 0x0001 /* Fault was reported,
143 last_fault_rec is valid */
144 #define DMAR_CTX_DISABLED 0x0002 /* Device is disabled, the
145 ephemeral reference is kept
146 to prevent context destruction */
147
148 #define DMAR_DOMAIN_PGLOCK(dom) VM_OBJECT_WLOCK((dom)->pgtbl_obj)
149 #define DMAR_DOMAIN_PGTRYLOCK(dom) VM_OBJECT_TRYWLOCK((dom)->pgtbl_obj)
150 #define DMAR_DOMAIN_PGUNLOCK(dom) VM_OBJECT_WUNLOCK((dom)->pgtbl_obj)
151 #define DMAR_DOMAIN_ASSERT_PGLOCKED(dom) \
152 VM_OBJECT_ASSERT_WLOCKED((dom)->pgtbl_obj)
153
154 #define DMAR_DOMAIN_LOCK(dom) mtx_lock(&(dom)->lock)
155 #define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->lock)
156 #define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->lock, MA_OWNED)
157
158 struct dmar_msi_data {
159 int irq;
160 int irq_rid;
161 struct resource *irq_res;
162 void *intr_handle;
163 int (*handler)(void *);
164 int msi_data_reg;
165 int msi_addr_reg;
166 int msi_uaddr_reg;
167 void (*enable_intr)(struct dmar_unit *);
168 void (*disable_intr)(struct dmar_unit *);
169 const char *name;
170 };
171
172 #define DMAR_INTR_FAULT 0
173 #define DMAR_INTR_QI 1
174 #define DMAR_INTR_TOTAL 2
175
176 struct dmar_unit {
177 device_t dev;
178 int unit;
179 uint16_t segment;
180 uint64_t base;
181
182 /* Resources */
183 int reg_rid;
184 struct resource *regs;
185
186 struct dmar_msi_data intrs[DMAR_INTR_TOTAL];
187
188 /* Hardware registers cache */
189 uint32_t hw_ver;
190 uint64_t hw_cap;
191 uint64_t hw_ecap;
192 uint32_t hw_gcmd;
193
194 /* Data for being a dmar */
195 struct mtx lock;
196 LIST_HEAD(, dmar_domain) domains;
197 struct unrhdr *domids;
198 vm_object_t ctx_obj;
199 u_int barrier_flags;
200
201 /* Fault handler data */
202 struct mtx fault_lock;
203 uint64_t *fault_log;
204 int fault_log_head;
205 int fault_log_tail;
206 int fault_log_size;
207 struct task fault_task;
208 struct taskqueue *fault_taskqueue;
209
210 /* QI */
211 int qi_enabled;
212 vm_offset_t inv_queue;
213 vm_size_t inv_queue_size;
214 uint32_t inv_queue_avail;
215 uint32_t inv_queue_tail;
216 volatile uint32_t inv_waitd_seq_hw; /* hw writes there on wait
217 descr completion */
218 uint64_t inv_waitd_seq_hw_phys;
219 uint32_t inv_waitd_seq; /* next sequence number to use for wait descr */
220 u_int inv_waitd_gen; /* seq number generation AKA seq overflows */
221 u_int inv_seq_waiters; /* count of waiters for seq */
222 u_int inv_queue_full; /* informational counter */
223
224 /* IR */
225 int ir_enabled;
226 vm_paddr_t irt_phys;
227 dmar_irte_t *irt;
228 u_int irte_cnt;
229 vmem_t *irtids;
230
231 /* Delayed freeing of map entries queue processing */
232 struct dmar_map_entries_tailq tlb_flush_entries;
233 struct task qi_task;
234 struct taskqueue *qi_taskqueue;
235
236 /* Busdma delayed map load */
237 struct task dmamap_load_task;
238 TAILQ_HEAD(, bus_dmamap_dmar) delayed_maps;
239 struct taskqueue *delayed_taskqueue;
240
241 int dma_enabled;
242 };
243
244 #define DMAR_LOCK(dmar) mtx_lock(&(dmar)->lock)
245 #define DMAR_UNLOCK(dmar) mtx_unlock(&(dmar)->lock)
246 #define DMAR_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->lock, MA_OWNED)
247
248 #define DMAR_FAULT_LOCK(dmar) mtx_lock_spin(&(dmar)->fault_lock)
249 #define DMAR_FAULT_UNLOCK(dmar) mtx_unlock_spin(&(dmar)->fault_lock)
250 #define DMAR_FAULT_ASSERT_LOCKED(dmar) mtx_assert(&(dmar)->fault_lock, MA_OWNED)
251
252 #define DMAR_IS_COHERENT(dmar) (((dmar)->hw_ecap & DMAR_ECAP_C) != 0)
253 #define DMAR_HAS_QI(dmar) (((dmar)->hw_ecap & DMAR_ECAP_QI) != 0)
254 #define DMAR_X2APIC(dmar) \
255 (x2apic_mode && ((dmar)->hw_ecap & DMAR_ECAP_EIM) != 0)
256
257 /* Barrier ids */
258 #define DMAR_BARRIER_RMRR 0
259 #define DMAR_BARRIER_USEQ 1
260
261 struct dmar_unit *dmar_find(device_t dev, bool verbose);
262 struct dmar_unit *dmar_find_hpet(device_t dev, uint16_t *rid);
263 struct dmar_unit *dmar_find_ioapic(u_int apic_id, uint16_t *rid);
264
265 u_int dmar_nd2mask(u_int nd);
266 bool dmar_pglvl_supported(struct dmar_unit *unit, int pglvl);
267 int domain_set_agaw(struct dmar_domain *domain, int mgaw);
268 int dmar_maxaddr2mgaw(struct dmar_unit *unit, dmar_gaddr_t maxaddr,
269 bool allow_less);
270 vm_pindex_t pglvl_max_pages(int pglvl);
271 int domain_is_sp_lvl(struct dmar_domain *domain, int lvl);
272 dmar_gaddr_t pglvl_page_size(int total_pglvl, int lvl);
273 dmar_gaddr_t domain_page_size(struct dmar_domain *domain, int lvl);
274 int calc_am(struct dmar_unit *unit, dmar_gaddr_t base, dmar_gaddr_t size,
275 dmar_gaddr_t *isizep);
276 struct vm_page *dmar_pgalloc(vm_object_t obj, vm_pindex_t idx, int flags);
277 void dmar_pgfree(vm_object_t obj, vm_pindex_t idx, int flags);
278 void *dmar_map_pgtbl(vm_object_t obj, vm_pindex_t idx, int flags,
279 struct sf_buf **sf);
280 void dmar_unmap_pgtbl(struct sf_buf *sf);
281 int dmar_load_root_entry_ptr(struct dmar_unit *unit);
282 int dmar_inv_ctx_glob(struct dmar_unit *unit);
283 int dmar_inv_iotlb_glob(struct dmar_unit *unit);
284 int dmar_flush_write_bufs(struct dmar_unit *unit);
285 void dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst);
286 void dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst);
287 void dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst);
288 int dmar_enable_translation(struct dmar_unit *unit);
289 int dmar_disable_translation(struct dmar_unit *unit);
290 int dmar_load_irt_ptr(struct dmar_unit *unit);
291 int dmar_enable_ir(struct dmar_unit *unit);
292 int dmar_disable_ir(struct dmar_unit *unit);
293 bool dmar_barrier_enter(struct dmar_unit *dmar, u_int barrier_id);
294 void dmar_barrier_exit(struct dmar_unit *dmar, u_int barrier_id);
295 uint64_t dmar_get_timeout(void);
296 void dmar_update_timeout(uint64_t newval);
297
298 int dmar_fault_intr(void *arg);
299 void dmar_enable_fault_intr(struct dmar_unit *unit);
300 void dmar_disable_fault_intr(struct dmar_unit *unit);
301 int dmar_init_fault_log(struct dmar_unit *unit);
302 void dmar_fini_fault_log(struct dmar_unit *unit);
303
304 int dmar_qi_intr(void *arg);
305 void dmar_enable_qi_intr(struct dmar_unit *unit);
306 void dmar_disable_qi_intr(struct dmar_unit *unit);
307 int dmar_init_qi(struct dmar_unit *unit);
308 void dmar_fini_qi(struct dmar_unit *unit);
309 void dmar_qi_invalidate_locked(struct dmar_domain *domain, dmar_gaddr_t start,
310 dmar_gaddr_t size, struct dmar_qi_genseq *psec, bool emit_wait);
311 void dmar_qi_invalidate_ctx_glob_locked(struct dmar_unit *unit);
312 void dmar_qi_invalidate_iotlb_glob_locked(struct dmar_unit *unit);
313 void dmar_qi_invalidate_iec_glob(struct dmar_unit *unit);
314 void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt);
315
316 vm_object_t domain_get_idmap_pgtbl(struct dmar_domain *domain,
317 dmar_gaddr_t maxaddr);
318 void put_idmap_pgtbl(vm_object_t obj);
319 int domain_map_buf(struct dmar_domain *domain, dmar_gaddr_t base,
320 dmar_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags);
321 int domain_unmap_buf(struct dmar_domain *domain, dmar_gaddr_t base,
322 dmar_gaddr_t size, int flags);
323 void domain_flush_iotlb_sync(struct dmar_domain *domain, dmar_gaddr_t base,
324 dmar_gaddr_t size);
325 int domain_alloc_pgtbl(struct dmar_domain *domain);
326 void domain_free_pgtbl(struct dmar_domain *domain);
327
328 int dmar_dev_depth(device_t child);
329 void dmar_dev_path(device_t child, int *busno, void *path1, int depth);
330
331 struct dmar_ctx *dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev,
332 bool rmrr);
333 struct dmar_ctx *dmar_get_ctx_for_dev(struct dmar_unit *dmar, device_t dev,
334 uint16_t rid, bool id_mapped, bool rmrr_init);
335 struct dmar_ctx *dmar_get_ctx_for_devpath(struct dmar_unit *dmar, uint16_t rid,
336 int dev_domain, int dev_busno, const void *dev_path, int dev_path_len,
337 bool id_mapped, bool rmrr_init);
338 int dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx);
339 void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx);
340 void dmar_free_ctx(struct dmar_ctx *ctx);
341 struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid);
342 void dmar_domain_unload_entry(struct dmar_map_entry *entry, bool free);
343 void dmar_domain_unload(struct dmar_domain *domain,
344 struct dmar_map_entries_tailq *entries, bool cansleep);
345 void dmar_domain_free_entry(struct dmar_map_entry *entry, bool free);
346
347 int dmar_init_busdma(struct dmar_unit *unit);
348 void dmar_fini_busdma(struct dmar_unit *unit);
349 device_t dmar_get_requester(device_t dev, uint16_t *rid);
350
351 void dmar_gas_init_domain(struct dmar_domain *domain);
352 void dmar_gas_fini_domain(struct dmar_domain *domain);
353 struct dmar_map_entry *dmar_gas_alloc_entry(struct dmar_domain *domain,
354 u_int flags);
355 void dmar_gas_free_entry(struct dmar_domain *domain,
356 struct dmar_map_entry *entry);
357 void dmar_gas_free_space(struct dmar_domain *domain,
358 struct dmar_map_entry *entry);
359 int dmar_gas_map(struct dmar_domain *domain,
360 const struct bus_dma_tag_common *common, dmar_gaddr_t size, int offset,
361 u_int eflags, u_int flags, vm_page_t *ma, struct dmar_map_entry **res);
362 void dmar_gas_free_region(struct dmar_domain *domain,
363 struct dmar_map_entry *entry);
364 int dmar_gas_map_region(struct dmar_domain *domain,
365 struct dmar_map_entry *entry, u_int eflags, u_int flags, vm_page_t *ma);
366 int dmar_gas_reserve_region(struct dmar_domain *domain, dmar_gaddr_t start,
367 dmar_gaddr_t end);
368
369 void dmar_dev_parse_rmrr(struct dmar_domain *domain, int dev_domain,
370 int dev_busno, const void *dev_path, int dev_path_len,
371 struct dmar_map_entries_tailq *rmrr_entries);
372 int dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar);
373
374 void dmar_quirks_post_ident(struct dmar_unit *dmar);
375 void dmar_quirks_pre_use(struct dmar_unit *dmar);
376
377 int dmar_init_irt(struct dmar_unit *unit);
378 void dmar_fini_irt(struct dmar_unit *unit);
379
380 #define DMAR_GM_CANWAIT 0x0001
381 #define DMAR_GM_CANSPLIT 0x0002
382
383 #define DMAR_PGF_WAITOK 0x0001
384 #define DMAR_PGF_ZERO 0x0002
385 #define DMAR_PGF_ALLOC 0x0004
386 #define DMAR_PGF_NOALLOC 0x0008
387 #define DMAR_PGF_OBJL 0x0010
388
389 extern dmar_haddr_t dmar_high;
390 extern int haw;
391 extern int dmar_tbl_pagecnt;
392 extern int dmar_batch_coalesce;
393 extern int dmar_check_free;
394
395 static inline uint32_t
dmar_read4(const struct dmar_unit * unit,int reg)396 dmar_read4(const struct dmar_unit *unit, int reg)
397 {
398
399 return (bus_read_4(unit->regs, reg));
400 }
401
402 static inline uint64_t
dmar_read8(const struct dmar_unit * unit,int reg)403 dmar_read8(const struct dmar_unit *unit, int reg)
404 {
405 #ifdef __i386__
406 uint32_t high, low;
407
408 low = bus_read_4(unit->regs, reg);
409 high = bus_read_4(unit->regs, reg + 4);
410 return (low | ((uint64_t)high << 32));
411 #else
412 return (bus_read_8(unit->regs, reg));
413 #endif
414 }
415
416 static inline void
dmar_write4(const struct dmar_unit * unit,int reg,uint32_t val)417 dmar_write4(const struct dmar_unit *unit, int reg, uint32_t val)
418 {
419
420 KASSERT(reg != DMAR_GCMD_REG || (val & DMAR_GCMD_TE) ==
421 (unit->hw_gcmd & DMAR_GCMD_TE),
422 ("dmar%d clearing TE 0x%08x 0x%08x", unit->unit,
423 unit->hw_gcmd, val));
424 bus_write_4(unit->regs, reg, val);
425 }
426
427 static inline void
dmar_write8(const struct dmar_unit * unit,int reg,uint64_t val)428 dmar_write8(const struct dmar_unit *unit, int reg, uint64_t val)
429 {
430
431 KASSERT(reg != DMAR_GCMD_REG, ("8byte GCMD write"));
432 #ifdef __i386__
433 uint32_t high, low;
434
435 low = val;
436 high = val >> 32;
437 bus_write_4(unit->regs, reg, low);
438 bus_write_4(unit->regs, reg + 4, high);
439 #else
440 bus_write_8(unit->regs, reg, val);
441 #endif
442 }
443
444 /*
445 * dmar_pte_store and dmar_pte_clear ensure that on i386, 32bit writes
446 * are issued in the correct order. For store, the lower word,
447 * containing the P or R and W bits, is set only after the high word
448 * is written. For clear, the P bit is cleared first, then the high
449 * word is cleared.
450 *
451 * dmar_pte_update updates the pte. For amd64, the update is atomic.
452 * For i386, it first disables the entry by clearing the word
453 * containing the P bit, and then defer to dmar_pte_store. The locked
454 * cmpxchg8b is probably available on any machine having DMAR support,
455 * but interrupt translation table may be mapped uncached.
456 */
457 static inline void
dmar_pte_store1(volatile uint64_t * dst,uint64_t val)458 dmar_pte_store1(volatile uint64_t *dst, uint64_t val)
459 {
460 #ifdef __i386__
461 volatile uint32_t *p;
462 uint32_t hi, lo;
463
464 hi = val >> 32;
465 lo = val;
466 p = (volatile uint32_t *)dst;
467 *(p + 1) = hi;
468 *p = lo;
469 #else
470 *dst = val;
471 #endif
472 }
473
474 static inline void
dmar_pte_store(volatile uint64_t * dst,uint64_t val)475 dmar_pte_store(volatile uint64_t *dst, uint64_t val)
476 {
477
478 KASSERT(*dst == 0, ("used pte %p oldval %jx newval %jx",
479 dst, (uintmax_t)*dst, (uintmax_t)val));
480 dmar_pte_store1(dst, val);
481 }
482
483 static inline void
dmar_pte_update(volatile uint64_t * dst,uint64_t val)484 dmar_pte_update(volatile uint64_t *dst, uint64_t val)
485 {
486
487 #ifdef __i386__
488 volatile uint32_t *p;
489
490 p = (volatile uint32_t *)dst;
491 *p = 0;
492 #endif
493 dmar_pte_store1(dst, val);
494 }
495
496 static inline void
dmar_pte_clear(volatile uint64_t * dst)497 dmar_pte_clear(volatile uint64_t *dst)
498 {
499 #ifdef __i386__
500 volatile uint32_t *p;
501
502 p = (volatile uint32_t *)dst;
503 *p = 0;
504 *(p + 1) = 0;
505 #else
506 *dst = 0;
507 #endif
508 }
509
510 static inline bool
dmar_test_boundary(dmar_gaddr_t start,dmar_gaddr_t size,dmar_gaddr_t boundary)511 dmar_test_boundary(dmar_gaddr_t start, dmar_gaddr_t size,
512 dmar_gaddr_t boundary)
513 {
514
515 if (boundary == 0)
516 return (true);
517 return (start + size <= ((start + boundary) & ~(boundary - 1)));
518 }
519
520 extern struct timespec dmar_hw_timeout;
521
522 #define DMAR_WAIT_UNTIL(cond) \
523 { \
524 struct timespec last, curr; \
525 bool forever; \
526 \
527 if (dmar_hw_timeout.tv_sec == 0 && \
528 dmar_hw_timeout.tv_nsec == 0) { \
529 forever = true; \
530 } else { \
531 forever = false; \
532 nanouptime(&curr); \
533 timespecadd(&curr, &dmar_hw_timeout, &last); \
534 } \
535 for (;;) { \
536 if (cond) { \
537 error = 0; \
538 break; \
539 } \
540 nanouptime(&curr); \
541 if (!forever && timespeccmp(&last, &curr, <)) { \
542 error = ETIMEDOUT; \
543 break; \
544 } \
545 cpu_spinwait(); \
546 } \
547 }
548
549 #ifdef INVARIANTS
550 #define TD_PREP_PINNED_ASSERT \
551 int old_td_pinned; \
552 old_td_pinned = curthread->td_pinned
553 #define TD_PINNED_ASSERT \
554 KASSERT(curthread->td_pinned == old_td_pinned, \
555 ("pin count leak: %d %d %s:%d", curthread->td_pinned, \
556 old_td_pinned, __FILE__, __LINE__))
557 #else
558 #define TD_PREP_PINNED_ASSERT
559 #define TD_PINNED_ASSERT
560 #endif
561
562 #endif
563