1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/rman.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <machine/bus.h>
40
41 #include <dev/fdt/simplebus.h>
42
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45
46 #ifdef __aarch64__
47 #include "opt_soc.h"
48 #endif
49
50 #include <dev/extres/clk/clk_div.h>
51 #include <dev/extres/clk/clk_fixed.h>
52 #include <dev/extres/clk/clk_mux.h>
53
54 #include <dev/extres/hwreset/hwreset.h>
55
56 #include <arm/allwinner/clkng/aw_ccung.h>
57
58 #include <dt-bindings/clock/sun8i-de2.h>
59 #include <dt-bindings/reset/sun8i-de2.h>
60
61 enum CCU_DE2 {
62 H3_CCU = 1,
63 A64_CCU,
64 };
65
66 /* Non exported clocks */
67 #define CLK_MIXER0_DIV 3
68 #define CLK_MIXER1_DIV 4
69 #define CLK_WB_DIV 5
70
71 static struct aw_ccung_reset h3_de2_ccu_resets[] = {
72 CCU_RESET(RST_MIXER0, 0x08, 0)
73 CCU_RESET(RST_WB, 0x08, 2)
74 };
75
76 static struct aw_ccung_reset a64_de2_ccu_resets[] = {
77 CCU_RESET(RST_MIXER0, 0x08, 0)
78 CCU_RESET(RST_MIXER1, 0x08, 1)
79 CCU_RESET(RST_WB, 0x08, 2)
80 };
81
82 static struct aw_ccung_gate h3_de2_ccu_gates[] = {
83 CCU_GATE(CLK_BUS_MIXER0, "mixer0", "mixer0-div", 0x00, 0)
84 CCU_GATE(CLK_BUS_WB, "wb", "wb-div", 0x00, 2)
85
86 CCU_GATE(CLK_MIXER0, "bus-mixer0", "bus-de", 0x04, 0)
87 CCU_GATE(CLK_WB, "bus-wb", "bus-de", 0x04, 2)
88 };
89
90 static struct aw_ccung_gate a64_de2_ccu_gates[] = {
91 CCU_GATE(CLK_BUS_MIXER0, "mixer0", "mixer0-div", 0x00, 0)
92 CCU_GATE(CLK_BUS_MIXER1, "mixer1", "mixer1-div", 0x00, 1)
93 CCU_GATE(CLK_BUS_WB, "wb", "wb-div", 0x00, 2)
94
95 CCU_GATE(CLK_MIXER0, "bus-mixer0", "bus-de", 0x04, 0)
96 CCU_GATE(CLK_MIXER1, "bus-mixer1", "bus-de", 0x04, 1)
97 CCU_GATE(CLK_WB, "bus-wb", "bus-de", 0x04, 2)
98 };
99
100 static const char *div_parents[] = {"de"};
101
102 NM_CLK(mixer0_div_clk,
103 CLK_MIXER0_DIV, /* id */
104 "mixer0-div", div_parents, /* names, parents */
105 0x0C, /* offset */
106 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/
107 0, 4, 0, 0, /* M flags */
108 0, 0, /* mux */
109 0, /* gate */
110 AW_CLK_SCALE_CHANGE); /* flags */
111
112 NM_CLK(mixer1_div_clk,
113 CLK_MIXER1_DIV, /* id */
114 "mixer1-div", div_parents, /* names, parents */
115 0x0C, /* offset */
116 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/
117 4, 4, 0, 0, /* M flags */
118 0, 0, /* mux */
119 0, /* gate */
120 AW_CLK_SCALE_CHANGE); /* flags */
121
122 NM_CLK(wb_div_clk,
123 CLK_WB_DIV, /* id */
124 "wb-div", div_parents, /* names, parents */
125 0x0C, /* offset */
126 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/
127 8, 4, 0, 0, /* M flags */
128 0, 0, /* mux */
129 0, /* gate */
130 AW_CLK_SCALE_CHANGE); /* flags */
131
132 static struct aw_ccung_clk h3_de2_ccu_clks[] = {
133 { .type = AW_CLK_NM, .clk.nm = &mixer0_div_clk},
134 { .type = AW_CLK_NM, .clk.nm = &wb_div_clk},
135 };
136
137 static struct aw_ccung_clk a64_de2_ccu_clks[] = {
138 { .type = AW_CLK_NM, .clk.nm = &mixer0_div_clk},
139 { .type = AW_CLK_NM, .clk.nm = &mixer1_div_clk},
140 { .type = AW_CLK_NM, .clk.nm = &wb_div_clk},
141 };
142
143 static struct ofw_compat_data compat_data[] = {
144 {"allwinner,sun8i-h3-de2-clk", H3_CCU},
145 {"allwinner,sun50i-a64-de2-clk", A64_CCU},
146 {NULL, 0}
147 };
148
149 static int
ccu_de2_probe(device_t dev)150 ccu_de2_probe(device_t dev)
151 {
152
153 if (!ofw_bus_status_okay(dev))
154 return (ENXIO);
155
156 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
157 return (ENXIO);
158
159 device_set_desc(dev, "Allwinner DE2 Clock Control Unit");
160 return (BUS_PROBE_DEFAULT);
161 }
162
163 static int
ccu_de2_attach(device_t dev)164 ccu_de2_attach(device_t dev)
165 {
166 struct aw_ccung_softc *sc;
167 phandle_t node;
168 clk_t mod, bus;
169 hwreset_t rst_de;
170 enum CCU_DE2 type;
171
172 sc = device_get_softc(dev);
173 node = ofw_bus_get_node(dev);
174
175 type = (enum CCU_DE2)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
176
177 switch (type) {
178 case H3_CCU:
179 sc->resets = h3_de2_ccu_resets;
180 sc->nresets = nitems(h3_de2_ccu_resets);
181 sc->gates = h3_de2_ccu_gates;
182 sc->ngates = nitems(h3_de2_ccu_gates);
183 sc->clks = h3_de2_ccu_clks;
184 sc->nclks = nitems(h3_de2_ccu_clks);
185 break;
186 case A64_CCU:
187 sc->resets = a64_de2_ccu_resets;
188 sc->nresets = nitems(a64_de2_ccu_resets);
189 sc->gates = a64_de2_ccu_gates;
190 sc->ngates = nitems(a64_de2_ccu_gates);
191 sc->clks = a64_de2_ccu_clks;
192 sc->nclks = nitems(a64_de2_ccu_clks);
193 break;
194 }
195
196 if (hwreset_get_by_ofw_idx(dev, node, 0, &rst_de) != 0) {
197 device_printf(dev, "Cannot get de reset\n");
198 return (ENXIO);
199 }
200 if (hwreset_deassert(rst_de) != 0) {
201 device_printf(dev, "Cannot de-assert de reset\n");
202 return (ENXIO);
203 }
204
205 if (clk_get_by_ofw_name(dev, node, "mod", &mod) != 0) {
206 device_printf(dev, "Cannot get mod clock\n");
207 return (ENXIO);
208 }
209 if (clk_enable(mod) != 0) {
210 device_printf(dev, "Cannot enable mod clock\n");
211 return (ENXIO);
212 }
213
214 if (clk_get_by_ofw_name(dev, node, "bus", &bus) != 0) {
215 device_printf(dev, "Cannot get bus clock\n");
216 return (ENXIO);
217 }
218 if (clk_enable(bus) != 0) {
219 device_printf(dev, "Cannot enable bus clock\n");
220 return (ENXIO);
221 }
222
223 return (aw_ccung_attach(dev));
224 }
225
226 static device_method_t ccu_de2_methods[] = {
227 /* Device interface */
228 DEVMETHOD(device_probe, ccu_de2_probe),
229 DEVMETHOD(device_attach, ccu_de2_attach),
230
231 DEVMETHOD_END
232 };
233
234 static devclass_t ccu_de2ng_devclass;
235
236 DEFINE_CLASS_1(ccu_de2, ccu_de2_driver, ccu_de2_methods,
237 sizeof(struct aw_ccung_softc), aw_ccung_driver);
238
239 EARLY_DRIVER_MODULE(ccu_de2, simplebus, ccu_de2_driver,
240 ccu_de2ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LAST);
241