1 /*- 2 * Copyright 2015 Alexander Kabaev <[email protected]> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _MIPS_INGENIC_JZ4780_CLK_H 30 #define _MIPS_INGENIC_JZ4780_CLK_H 31 32 #include <dev/extres/clk/clk.h> 33 #include <dev/extres/clk/clk_gate.h> 34 35 /* Convenience bitfiled manipulation macros */ 36 #define REG_MSK(field) (((1u << field ## _WIDTH) - 1) << field ##_SHIFT) 37 #define REG_VAL(field, val) ((val) << field ##_SHIFT) 38 #define REG_CLR(reg, field) ((reg) & ~REG_MSK(field)) 39 #define REG_GET(reg, field) (((reg) & REG_MSK(field)) >> field ##_SHIFT) 40 #define REG_SET(reg, field, val) (REG_CLR(reg, field) | REG_VAL(field, val)) 41 42 /* Common clock macros */ 43 #define CLK_LOCK(_sc) mtx_lock((_sc)->clk_mtx) 44 #define CLK_UNLOCK(_sc) mtx_unlock((_sc)->clk_mtx) 45 46 #define CLK_WR_4(_sc, off, val) bus_write_4((_sc)->clk_res, (off), (val)) 47 #define CLK_RD_4(_sc, off) bus_read_4((_sc)->clk_res, (off)) 48 49 struct jz4780_clk_mux_descr { 50 uint16_t mux_reg; 51 uint16_t mux_shift: 5; 52 uint16_t mux_bits: 5; 53 uint16_t mux_map: 4; /* Map into mux space */ 54 }; 55 56 struct jz4780_clk_div_descr { 57 uint16_t div_reg; 58 uint16_t div_shift: 5; 59 uint16_t div_bits: 5; 60 uint16_t div_lg: 5; 61 int div_ce_bit: 6; /* -1, if CE bit is not present */ 62 int div_st_bit: 6; /* Can be negative */ 63 int div_busy_bit: 6; /* Can be negative */ 64 }; 65 66 struct jz4780_clk_descr { 67 uint16_t clk_id: 6; 68 uint16_t clk_type: 3; 69 int clk_gate_bit: 7; /* Can be negative */ 70 struct jz4780_clk_mux_descr clk_mux; 71 struct jz4780_clk_div_descr clk_div; 72 const char *clk_name; 73 const char *clk_pnames[4]; 74 }; 75 76 /* clk_type bits */ 77 #define CLK_MASK_GATE 0x01 78 #define CLK_MASK_DIV 0x02 79 #define CLK_MASK_MUX 0x04 80 81 extern int jz4780_clk_gen_register(struct clkdom *clkdom, 82 const struct jz4780_clk_descr *descr, struct mtx *dev_mtx, 83 struct resource *mem_res); 84 85 extern int jz4780_clk_pll_register(struct clkdom *clkdom, 86 struct clknode_init_def *clkdef, struct mtx *dev_mtx, 87 struct resource *mem_res, uint32_t mem_reg); 88 89 extern int jz4780_clk_otg_register(struct clkdom *clkdom, 90 struct clknode_init_def *clkdef, struct mtx *dev_mtx, 91 struct resource *mem_res); 92 93 #endif /* _MIPS_INGENIC_JZ4780_CLK_PLL_H */ 94