1 /*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 * Copyright (c) 2016, Hiroki Mori
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30
31 #include "opt_ddb.h"
32
33 #include <sys/param.h>
34 #include <sys/conf.h>
35 #include <sys/kernel.h>
36 #include <sys/socket.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/cons.h>
40 #include <sys/kdb.h>
41 #include <sys/reboot.h>
42
43 #include <vm/vm.h>
44 #include <vm/vm_page.h>
45
46 #include <net/ethernet.h>
47
48 #include <machine/clock.h>
49 #include <machine/cpu.h>
50 #include <machine/cpuregs.h>
51 #include <machine/hwfunc.h>
52 #include <machine/md_var.h>
53 #include <machine/trap.h>
54 #include <machine/vmparam.h>
55
56 #include <mips/atheros/ar531x/ar5315reg.h>
57 #include <mips/atheros/ar531x/ar5315_chip.h>
58 #include <mips/atheros/ar531x/ar5315_cpudef.h>
59
60 /* XXX these shouldn't be in here - this file is a per-chip file */
61 /* XXX these should be in the top-level ar5315 type, not ar5315 -chip */
62 uint32_t u_ar531x_cpu_freq;
63 uint32_t u_ar531x_ahb_freq;
64 uint32_t u_ar531x_ddr_freq;
65
66 uint32_t u_ar531x_uart_addr;
67
68 uint32_t u_ar531x_gpio_di;
69 uint32_t u_ar531x_gpio_do;
70 uint32_t u_ar531x_gpio_cr;
71 uint32_t u_ar531x_gpio_pins;
72
73 uint32_t u_ar531x_wdog_ctl;
74 uint32_t u_ar531x_wdog_timer;
75
76 static void
ar5315_chip_detect_mem_size(void)77 ar5315_chip_detect_mem_size(void)
78 {
79 uint32_t memsize = 0;
80 uint32_t memcfg, cw, rw, dw;
81
82 /*
83 * Determine the memory size. We query the board info.
84 */
85 memcfg = ATH_READ_REG(AR5315_SDRAMCTL_BASE + AR5315_SDRAMCTL_MEM_CFG);
86 cw = __SHIFTOUT(memcfg, AR5315_MEM_CFG_COL_WIDTH);
87 cw += 1;
88 rw = __SHIFTOUT(memcfg, AR5315_MEM_CFG_ROW_WIDTH);
89 rw += 1;
90
91 /* XXX: according to redboot, this could be wrong if DDR SDRAM */
92 dw = __SHIFTOUT(memcfg, AR5315_MEM_CFG_DATA_WIDTH);
93 dw += 1;
94 dw *= 8; /* bits */
95
96 /* not too sure about this math, but it _seems_ to add up */
97 memsize = (1 << cw) * (1 << rw) * dw;
98 #if 0
99 printf("SDRAM_MEM_CFG =%x, cw=%d rw=%d dw=%d xmemsize=%d\n", memcfg,
100 cw, rw, dw, memsize);
101 #endif
102 realmem = memsize;
103 }
104
105 static void
ar5315_chip_detect_sys_frequency(void)106 ar5315_chip_detect_sys_frequency(void)
107 {
108 uint32_t freq_ref, freq_pll;
109 static const uint8_t pll_divide_table[] = {
110 2, 3, 4, 6, 3,
111 /*
112 * these entries are bogus, but it avoids a possible
113 * bad table dereference
114 */
115 1, 1, 1
116 };
117 static const uint8_t pre_divide_table[] = {
118 1, 2, 4, 5
119 };
120
121 const uint32_t pllc = ATH_READ_REG(AR5315_SYSREG_BASE +
122 AR5315_SYSREG_PLLC_CTL);
123
124 const uint32_t refdiv = pre_divide_table[AR5315_PLLC_REF_DIV(pllc)];
125 const uint32_t fbdiv = AR5315_PLLC_FB_DIV(pllc);
126 const uint32_t div2 = (AR5315_PLLC_DIV_2(pllc) + 1) * 2; /* results in 2 or 4 */
127
128 freq_ref = 40000000;
129
130 /* 40MHz reference clk, reference and feedback dividers */
131 freq_pll = (freq_ref / refdiv) * div2 * fbdiv;
132
133 const uint32_t pllout[4] = {
134 /* CLKM select */
135 [0] = freq_pll / pll_divide_table[AR5315_PLLC_CLKM(pllc)],
136 [1] = freq_pll / pll_divide_table[AR5315_PLLC_CLKM(pllc)],
137
138 /* CLKC select */
139 [2] = freq_pll / pll_divide_table[AR5315_PLLC_CLKC(pllc)],
140
141 /* ref_clk select */
142 [3] = freq_ref, /* use original reference clock */
143 };
144
145 const uint32_t amba_clkctl = ATH_READ_REG(AR5315_SYSREG_BASE +
146 AR5315_SYSREG_AMBACLK);
147 uint32_t ambadiv = AR5315_CLOCKCTL_DIV(amba_clkctl);
148 ambadiv = ambadiv ? (ambadiv * 2) : 1;
149 u_ar531x_ahb_freq = pllout[AR5315_CLOCKCTL_SELECT(amba_clkctl)] / ambadiv;
150
151 const uint32_t cpu_clkctl = ATH_READ_REG(AR5315_SYSREG_BASE +
152 AR5315_SYSREG_CPUCLK);
153 uint32_t cpudiv = AR5315_CLOCKCTL_DIV(cpu_clkctl);
154 cpudiv = cpudiv ? (cpudiv * 2) : 1;
155 u_ar531x_cpu_freq = pllout[AR5315_CLOCKCTL_SELECT(cpu_clkctl)] / cpudiv;
156
157 u_ar531x_ddr_freq = 0;
158 }
159
160 /*
161 * This does not lock the CPU whilst doing the work!
162 */
163 static void
ar5315_chip_device_reset(void)164 ar5315_chip_device_reset(void)
165 {
166 ATH_WRITE_REG(AR5315_SYSREG_BASE + AR5315_SYSREG_COLDRESET,
167 AR5315_COLD_AHB | AR5315_COLD_APB | AR5315_COLD_CPU);
168 }
169
170 static void
ar5315_chip_device_start(void)171 ar5315_chip_device_start(void)
172 {
173 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ERR0,
174 AR5315_AHB_ERROR_DET);
175 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ERR1);
176 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_WDOG_CTL,
177 AR5315_WDOG_CTL_IGNORE);
178
179 // set Ethernet AHB master arbitration control
180 // Maybe RedBoot was enabled. But to make sure.
181 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL,
182 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL) |
183 AR5315_ARB_ENET);
184
185 // set Ethernet controller byteswap control
186 /*
187 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_ENDIAN,
188 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_ENDIAN) |
189 AR5315_ENDIAN_ENET);
190 */
191 /* Disable interrupts for all gpio pins. */
192 ATH_WRITE_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_GPIO_INT, 0);
193
194 printf("AHB Master Arbitration Control %08x\n",
195 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL));
196 printf("Byteswap Control %08x\n",
197 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_ENDIAN));
198 }
199
200 static int
ar5315_chip_device_stopped(uint32_t mask)201 ar5315_chip_device_stopped(uint32_t mask)
202 {
203 uint32_t reg;
204
205 reg = ATH_READ_REG(AR5315_SYSREG_BASE + AR5315_SYSREG_COLDRESET);
206 return ((reg & mask) == mask);
207 }
208
209 static void
ar5315_chip_set_mii_speed(uint32_t unit,uint32_t speed)210 ar5315_chip_set_mii_speed(uint32_t unit, uint32_t speed)
211 {
212 }
213
214 /* Speed is either 10, 100 or 1000 */
215 static void
ar5315_chip_set_pll_ge(int unit,int speed)216 ar5315_chip_set_pll_ge(int unit, int speed)
217 {
218 }
219
220 static void
ar5315_chip_ddr_flush_ge(int unit)221 ar5315_chip_ddr_flush_ge(int unit)
222 {
223 }
224
225 static void
ar5315_chip_soc_init(void)226 ar5315_chip_soc_init(void)
227 {
228 u_ar531x_uart_addr = MIPS_PHYS_TO_KSEG1(AR5315_UART_BASE);
229
230 u_ar531x_gpio_di = AR5315_SYSREG_GPIO_DI;
231 u_ar531x_gpio_do = AR5315_SYSREG_GPIO_DO;
232 u_ar531x_gpio_cr = AR5315_SYSREG_GPIO_CR;
233 u_ar531x_gpio_pins = AR5315_GPIO_PINS;
234
235 u_ar531x_wdog_ctl = AR5315_SYSREG_WDOG_CTL;
236 u_ar531x_wdog_timer = AR5315_SYSREG_WDOG_TIMER;
237 }
238
239 static uint32_t
ar5315_chip_get_eth_pll(unsigned int mac,int speed)240 ar5315_chip_get_eth_pll(unsigned int mac, int speed)
241 {
242 return 0;
243 }
244
245 struct ar5315_cpu_def ar5315_chip_def = {
246 &ar5315_chip_detect_mem_size,
247 &ar5315_chip_detect_sys_frequency,
248 &ar5315_chip_device_reset,
249 &ar5315_chip_device_start,
250 &ar5315_chip_device_stopped,
251 &ar5315_chip_set_pll_ge,
252 &ar5315_chip_set_mii_speed,
253 &ar5315_chip_ddr_flush_ge,
254 &ar5315_chip_get_eth_pll,
255 &ar5315_chip_soc_init,
256 };
257