1 /*-
2 * Core routines and tables shareable across OS platforms.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 * Copyright (c) 1994-2002 Justin T. Gibbs.
7 * Copyright (c) 2000-2002 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
43 */
44
45 #ifdef __linux__
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
49 #else
50 #include <sys/cdefs.h>
51 #include <dev/aic7xxx/aic7xxx_osm.h>
52 #include <dev/aic7xxx/aic7xxx_inline.h>
53 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
54 #endif
55
56 /****************************** Softc Data ************************************/
57 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
58
59 /***************************** Lookup Tables **********************************/
60 char *ahc_chip_names[] =
61 {
62 "NONE",
63 "aic7770",
64 "aic7850",
65 "aic7855",
66 "aic7859",
67 "aic7860",
68 "aic7870",
69 "aic7880",
70 "aic7895",
71 "aic7895C",
72 "aic7890/91",
73 "aic7896/97",
74 "aic7892",
75 "aic7899"
76 };
77
78 /*
79 * Hardware error codes.
80 */
81 struct ahc_hard_error_entry {
82 uint8_t errno;
83 char *errmesg;
84 };
85
86 static struct ahc_hard_error_entry ahc_hard_errors[] = {
87 { ILLHADDR, "Illegal Host Access" },
88 { ILLSADDR, "Illegal Sequencer Address referrenced" },
89 { ILLOPCODE, "Illegal Opcode in sequencer program" },
90 { SQPARERR, "Sequencer Parity Error" },
91 { DPARERR, "Data-path Parity Error" },
92 { MPARERR, "Scratch or SCB Memory Parity Error" },
93 { PCIERRSTAT, "PCI Error detected" },
94 { CIOPARERR, "CIOBUS Parity Error" },
95 };
96 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
97
98 static struct ahc_phase_table_entry ahc_phase_table[] =
99 {
100 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
101 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
102 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
103 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
104 { P_COMMAND, MSG_NOOP, "in Command phase" },
105 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
106 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
107 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
108 { P_BUSFREE, MSG_NOOP, "while idle" },
109 { 0, MSG_NOOP, "in unknown phase" }
110 };
111
112 /*
113 * In most cases we only wish to itterate over real phases, so
114 * exclude the last element from the count.
115 */
116 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
117
118 /*
119 * Valid SCSIRATE values. (p. 3-17)
120 * Provides a mapping of transfer periods in ns to the proper value to
121 * stick in the scsixfer reg.
122 */
123 static struct ahc_syncrate ahc_syncrates[] =
124 {
125 /* ultra2 fast/ultra period rate */
126 { 0x42, 0x000, 9, "80.0" },
127 { 0x03, 0x000, 10, "40.0" },
128 { 0x04, 0x000, 11, "33.0" },
129 { 0x05, 0x100, 12, "20.0" },
130 { 0x06, 0x110, 15, "16.0" },
131 { 0x07, 0x120, 18, "13.4" },
132 { 0x08, 0x000, 25, "10.0" },
133 { 0x19, 0x010, 31, "8.0" },
134 { 0x1a, 0x020, 37, "6.67" },
135 { 0x1b, 0x030, 43, "5.7" },
136 { 0x1c, 0x040, 50, "5.0" },
137 { 0x00, 0x050, 56, "4.4" },
138 { 0x00, 0x060, 62, "4.0" },
139 { 0x00, 0x070, 68, "3.6" },
140 { 0x00, 0x000, 0, NULL }
141 };
142
143 /* Our Sequencer Program */
144 #include "aic7xxx_seq.h"
145
146 /**************************** Function Declarations ***************************/
147 static void ahc_force_renegotiation(struct ahc_softc *ahc,
148 struct ahc_devinfo *devinfo);
149 static struct ahc_tmode_tstate*
150 ahc_alloc_tstate(struct ahc_softc *ahc,
151 u_int scsi_id, char channel);
152 #ifdef AHC_TARGET_MODE
153 static void ahc_free_tstate(struct ahc_softc *ahc,
154 u_int scsi_id, char channel, int force);
155 #endif
156 static struct ahc_syncrate*
157 ahc_devlimited_syncrate(struct ahc_softc *ahc,
158 struct ahc_initiator_tinfo *,
159 u_int *period,
160 u_int *ppr_options,
161 role_t role);
162 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
163 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
164 struct ahc_devinfo *devinfo);
165 static void ahc_scb_devinfo(struct ahc_softc *ahc,
166 struct ahc_devinfo *devinfo,
167 struct scb *scb);
168 static void ahc_assert_atn(struct ahc_softc *ahc);
169 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
170 struct ahc_devinfo *devinfo,
171 struct scb *scb);
172 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
173 struct ahc_devinfo *devinfo);
174 static void ahc_construct_sdtr(struct ahc_softc *ahc,
175 struct ahc_devinfo *devinfo,
176 u_int period, u_int offset);
177 static void ahc_construct_wdtr(struct ahc_softc *ahc,
178 struct ahc_devinfo *devinfo,
179 u_int bus_width);
180 static void ahc_construct_ppr(struct ahc_softc *ahc,
181 struct ahc_devinfo *devinfo,
182 u_int period, u_int offset,
183 u_int bus_width, u_int ppr_options);
184 static void ahc_clear_msg_state(struct ahc_softc *ahc);
185 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
186 static void ahc_handle_message_phase(struct ahc_softc *ahc);
187 typedef enum {
188 AHCMSG_1B,
189 AHCMSG_2B,
190 AHCMSG_EXT
191 } ahc_msgtype;
192 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
193 u_int msgval, int full);
194 static int ahc_parse_msg(struct ahc_softc *ahc,
195 struct ahc_devinfo *devinfo);
196 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
197 struct ahc_devinfo *devinfo);
198 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
199 struct ahc_devinfo *devinfo);
200 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
201 static void ahc_handle_devreset(struct ahc_softc *ahc,
202 struct ahc_devinfo *devinfo,
203 cam_status status, char *message,
204 int verbose_level);
205 #ifdef AHC_TARGET_MODE
206 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
207 struct ahc_devinfo *devinfo,
208 struct scb *scb);
209 #endif
210
211 static bus_dmamap_callback_t ahc_dmamap_cb;
212 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
213 static int ahc_init_scbdata(struct ahc_softc *ahc);
214 static void ahc_fini_scbdata(struct ahc_softc *ahc);
215 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
216 struct scb *prev_scb,
217 struct scb *scb);
218 static int ahc_qinfifo_count(struct ahc_softc *ahc);
219 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
220 u_int prev, u_int scbptr);
221 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
222 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
223 u_int scbpos, u_int prev);
224 static void ahc_reset_current_bus(struct ahc_softc *ahc);
225 #ifdef AHC_DUMP_SEQ
226 static void ahc_dumpseq(struct ahc_softc *ahc);
227 #endif
228 static int ahc_loadseq(struct ahc_softc *ahc);
229 static int ahc_check_patch(struct ahc_softc *ahc,
230 struct patch **start_patch,
231 u_int start_instr, u_int *skip_addr);
232 static void ahc_download_instr(struct ahc_softc *ahc,
233 u_int instrptr, uint8_t *dconsts);
234 static int ahc_other_scb_timeout(struct ahc_softc *ahc,
235 struct scb *scb,
236 struct scb *other_scb);
237 #ifdef AHC_TARGET_MODE
238 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
239 struct ahc_tmode_lstate *lstate,
240 u_int initiator_id,
241 u_int event_type,
242 u_int event_arg);
243 static void ahc_update_scsiid(struct ahc_softc *ahc,
244 u_int targid_mask);
245 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
246 struct target_cmd *cmd);
247 #endif
248 /************************* Sequencer Execution Control ************************/
249 /*
250 * Restart the sequencer program from address zero
251 */
252 void
ahc_restart(struct ahc_softc * ahc)253 ahc_restart(struct ahc_softc *ahc)
254 {
255
256 ahc_pause(ahc);
257
258 /* No more pending messages. */
259 ahc_clear_msg_state(ahc);
260
261 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
262 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
263 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
264 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
265 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
266 ahc_outb(ahc, SAVED_LUN, 0xFF);
267
268 /*
269 * Ensure that the sequencer's idea of TQINPOS
270 * matches our own. The sequencer increments TQINPOS
271 * only after it sees a DMA complete and a reset could
272 * occur before the increment leaving the kernel to believe
273 * the command arrived but the sequencer to not.
274 */
275 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
276
277 /* Always allow reselection */
278 ahc_outb(ahc, SCSISEQ,
279 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
280 if ((ahc->features & AHC_CMD_CHAN) != 0) {
281 /* Ensure that no DMA operations are in progress */
282 ahc_outb(ahc, CCSCBCNT, 0);
283 ahc_outb(ahc, CCSGCTL, 0);
284 ahc_outb(ahc, CCSCBCTL, 0);
285 }
286 /*
287 * If we were in the process of DMA'ing SCB data into
288 * an SCB, replace that SCB on the free list. This prevents
289 * an SCB leak.
290 */
291 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
292 ahc_add_curscb_to_free_list(ahc);
293 ahc_outb(ahc, SEQ_FLAGS2,
294 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
295 }
296
297 /*
298 * Clear any pending sequencer interrupt. It is no
299 * longer relevant since we're resetting the Program
300 * Counter.
301 */
302 ahc_outb(ahc, CLRINT, CLRSEQINT);
303
304 ahc_outb(ahc, MWI_RESIDUAL, 0);
305 ahc_outb(ahc, SEQCTL, ahc->seqctl);
306 ahc_outb(ahc, SEQADDR0, 0);
307 ahc_outb(ahc, SEQADDR1, 0);
308
309 ahc_unpause(ahc);
310 }
311
312 /************************* Input/Output Queues ********************************/
313 void
ahc_run_qoutfifo(struct ahc_softc * ahc)314 ahc_run_qoutfifo(struct ahc_softc *ahc)
315 {
316 struct scb *scb;
317 u_int scb_index;
318
319 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
320 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
321 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
322 if ((ahc->qoutfifonext & 0x03) == 0x03) {
323 u_int modnext;
324
325 /*
326 * Clear 32bits of QOUTFIFO at a time
327 * so that we don't clobber an incoming
328 * byte DMA to the array on architectures
329 * that only support 32bit load and store
330 * operations.
331 */
332 modnext = ahc->qoutfifonext & ~0x3;
333 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
334 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
335 ahc->shared_data_dmamap,
336 /*offset*/modnext, /*len*/4,
337 BUS_DMASYNC_PREREAD);
338 }
339 ahc->qoutfifonext++;
340
341 scb = ahc_lookup_scb(ahc, scb_index);
342 if (scb == NULL) {
343 printf("%s: WARNING no command for scb %d "
344 "(cmdcmplt)\nQOUTPOS = %d\n",
345 ahc_name(ahc), scb_index,
346 (ahc->qoutfifonext - 1) & 0xFF);
347 continue;
348 }
349
350 /*
351 * Save off the residual
352 * if there is one.
353 */
354 ahc_update_residual(ahc, scb);
355 ahc_done(ahc, scb);
356 }
357 }
358
359 void
ahc_run_untagged_queues(struct ahc_softc * ahc)360 ahc_run_untagged_queues(struct ahc_softc *ahc)
361 {
362 int i;
363
364 for (i = 0; i < 16; i++)
365 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
366 }
367
368 void
ahc_run_untagged_queue(struct ahc_softc * ahc,struct scb_tailq * queue)369 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
370 {
371 struct scb *scb;
372
373 if (ahc->untagged_queue_lock != 0)
374 return;
375
376 if ((scb = TAILQ_FIRST(queue)) != NULL
377 && (scb->flags & SCB_ACTIVE) == 0) {
378 scb->flags |= SCB_ACTIVE;
379 /*
380 * Timers are disabled while recovery is in progress.
381 */
382 aic_scb_timer_start(scb);
383 ahc_queue_scb(ahc, scb);
384 }
385 }
386
387 /************************* Interrupt Handling *********************************/
388 void
ahc_handle_brkadrint(struct ahc_softc * ahc)389 ahc_handle_brkadrint(struct ahc_softc *ahc)
390 {
391 /*
392 * We upset the sequencer :-(
393 * Lookup the error message
394 */
395 int i;
396 int error;
397
398 error = ahc_inb(ahc, ERROR);
399 for (i = 0; error != 1 && i < num_errors; i++)
400 error >>= 1;
401 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
402 ahc_name(ahc), ahc_hard_errors[i].errmesg,
403 ahc_inb(ahc, SEQADDR0) |
404 (ahc_inb(ahc, SEQADDR1) << 8));
405
406 ahc_dump_card_state(ahc);
407
408 /* Tell everyone that this HBA is no longer available */
409 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
410 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
411 CAM_NO_HBA);
412
413 /* Disable all interrupt sources by resetting the controller */
414 ahc_shutdown(ahc);
415 }
416
417 void
ahc_handle_seqint(struct ahc_softc * ahc,u_int intstat)418 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
419 {
420 struct scb *scb;
421 struct ahc_devinfo devinfo;
422
423 ahc_fetch_devinfo(ahc, &devinfo);
424
425 /*
426 * Clear the upper byte that holds SEQINT status
427 * codes and clear the SEQINT bit. We will unpause
428 * the sequencer, if appropriate, after servicing
429 * the request.
430 */
431 ahc_outb(ahc, CLRINT, CLRSEQINT);
432 switch (intstat & SEQINT_MASK) {
433 case BAD_STATUS:
434 {
435 u_int scb_index;
436 struct hardware_scb *hscb;
437
438 /*
439 * Set the default return value to 0 (don't
440 * send sense). The sense code will change
441 * this if needed.
442 */
443 ahc_outb(ahc, RETURN_1, 0);
444
445 /*
446 * The sequencer will notify us when a command
447 * has an error that would be of interest to
448 * the kernel. This allows us to leave the sequencer
449 * running in the common case of command completes
450 * without error. The sequencer will already have
451 * dma'd the SCB back up to us, so we can reference
452 * the in kernel copy directly.
453 */
454 scb_index = ahc_inb(ahc, SCB_TAG);
455 scb = ahc_lookup_scb(ahc, scb_index);
456 if (scb == NULL) {
457 ahc_print_devinfo(ahc, &devinfo);
458 printf("ahc_intr - referenced scb "
459 "not valid during seqint 0x%x scb(%d)\n",
460 intstat, scb_index);
461 ahc_dump_card_state(ahc);
462 panic("for safety");
463 goto unpause;
464 }
465
466 hscb = scb->hscb;
467
468 /* Don't want to clobber the original sense code */
469 if ((scb->flags & SCB_SENSE) != 0) {
470 /*
471 * Clear the SCB_SENSE Flag and have
472 * the sequencer do a normal command
473 * complete.
474 */
475 scb->flags &= ~SCB_SENSE;
476 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
477 break;
478 }
479 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
480 /* Freeze the queue until the client sees the error. */
481 ahc_freeze_devq(ahc, scb);
482 aic_freeze_scb(scb);
483 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
484 switch (hscb->shared_data.status.scsi_status) {
485 case SCSI_STATUS_OK:
486 printf("%s: Interrupted for staus of 0???\n",
487 ahc_name(ahc));
488 break;
489 case SCSI_STATUS_CMD_TERMINATED:
490 case SCSI_STATUS_CHECK_COND:
491 {
492 struct ahc_dma_seg *sg;
493 struct scsi_sense *sc;
494 struct ahc_initiator_tinfo *targ_info;
495 struct ahc_tmode_tstate *tstate;
496 struct ahc_transinfo *tinfo;
497 #ifdef AHC_DEBUG
498 if (ahc_debug & AHC_SHOW_SENSE) {
499 ahc_print_path(ahc, scb);
500 printf("SCB %d: requests Check Status\n",
501 scb->hscb->tag);
502 }
503 #endif
504
505 if (aic_perform_autosense(scb) == 0)
506 break;
507
508 targ_info = ahc_fetch_transinfo(ahc,
509 devinfo.channel,
510 devinfo.our_scsiid,
511 devinfo.target,
512 &tstate);
513 tinfo = &targ_info->curr;
514 sg = scb->sg_list;
515 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
516 /*
517 * Save off the residual if there is one.
518 */
519 ahc_update_residual(ahc, scb);
520 #ifdef AHC_DEBUG
521 if (ahc_debug & AHC_SHOW_SENSE) {
522 ahc_print_path(ahc, scb);
523 printf("Sending Sense\n");
524 }
525 #endif
526 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
527 sg->len = aic_get_sense_bufsize(ahc, scb);
528 sg->len |= AHC_DMA_LAST_SEG;
529
530 /* Fixup byte order */
531 sg->addr = aic_htole32(sg->addr);
532 sg->len = aic_htole32(sg->len);
533
534 sc->opcode = REQUEST_SENSE;
535 sc->byte2 = 0;
536 if (tinfo->protocol_version <= SCSI_REV_2
537 && SCB_GET_LUN(scb) < 8)
538 sc->byte2 = SCB_GET_LUN(scb) << 5;
539 sc->unused[0] = 0;
540 sc->unused[1] = 0;
541 sc->length = sg->len;
542 sc->control = 0;
543
544 /*
545 * We can't allow the target to disconnect.
546 * This will be an untagged transaction and
547 * having the target disconnect will make this
548 * transaction indestinguishable from outstanding
549 * tagged transactions.
550 */
551 hscb->control = 0;
552
553 /*
554 * This request sense could be because the
555 * the device lost power or in some other
556 * way has lost our transfer negotiations.
557 * Renegotiate if appropriate. Unit attention
558 * errors will be reported before any data
559 * phases occur.
560 */
561 if (aic_get_residual(scb)
562 == aic_get_transfer_length(scb)) {
563 ahc_update_neg_request(ahc, &devinfo,
564 tstate, targ_info,
565 AHC_NEG_IF_NON_ASYNC);
566 }
567 if (tstate->auto_negotiate & devinfo.target_mask) {
568 hscb->control |= MK_MESSAGE;
569 scb->flags &= ~SCB_NEGOTIATE;
570 scb->flags |= SCB_AUTO_NEGOTIATE;
571 }
572 hscb->cdb_len = sizeof(*sc);
573 hscb->dataptr = sg->addr;
574 hscb->datacnt = sg->len;
575 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
576 hscb->sgptr = aic_htole32(hscb->sgptr);
577 scb->sg_count = 1;
578 scb->flags |= SCB_SENSE;
579 ahc_qinfifo_requeue_tail(ahc, scb);
580 ahc_outb(ahc, RETURN_1, SEND_SENSE);
581 /*
582 * Ensure we have enough time to actually
583 * retrieve the sense, but only schedule
584 * the timer if we are not in recovery or
585 * this is a recovery SCB that is allowed
586 * to have an active timer.
587 */
588 if (ahc->scb_data->recovery_scbs == 0
589 || (scb->flags & SCB_RECOVERY_SCB) != 0)
590 aic_scb_timer_reset(scb, 5 * 1000);
591 break;
592 }
593 default:
594 break;
595 }
596 break;
597 }
598 case NO_MATCH:
599 {
600 /* Ensure we don't leave the selection hardware on */
601 ahc_outb(ahc, SCSISEQ,
602 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
603
604 printf("%s:%c:%d: no active SCB for reconnecting "
605 "target - issuing BUS DEVICE RESET\n",
606 ahc_name(ahc), devinfo.channel, devinfo.target);
607 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
608 "ARG_1 == 0x%x ACCUM = 0x%x\n",
609 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
610 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
611 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
612 "SINDEX == 0x%x\n",
613 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
614 ahc_index_busy_tcl(ahc,
615 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
616 ahc_inb(ahc, SAVED_LUN))),
617 ahc_inb(ahc, SINDEX));
618 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
619 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
620 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
621 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
622 ahc_inb(ahc, SCB_CONTROL));
623 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
624 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
625 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
626 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
627 ahc_dump_card_state(ahc);
628 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
629 ahc->msgout_len = 1;
630 ahc->msgout_index = 0;
631 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
632 ahc_outb(ahc, MSG_OUT, HOST_MSG);
633 ahc_assert_atn(ahc);
634 break;
635 }
636 case SEND_REJECT:
637 {
638 u_int rejbyte = ahc_inb(ahc, ACCUM);
639 printf("%s:%c:%d: Warning - unknown message received from "
640 "target (0x%x). Rejecting\n",
641 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
642 break;
643 }
644 case PROTO_VIOLATION:
645 {
646 ahc_handle_proto_violation(ahc);
647 break;
648 }
649 case IGN_WIDE_RES:
650 ahc_handle_ign_wide_residue(ahc, &devinfo);
651 break;
652 case PDATA_REINIT:
653 ahc_reinitialize_dataptrs(ahc);
654 break;
655 case BAD_PHASE:
656 {
657 u_int lastphase;
658
659 lastphase = ahc_inb(ahc, LASTPHASE);
660 printf("%s:%c:%d: unknown scsi bus phase %x, "
661 "lastphase = 0x%x. Attempting to continue\n",
662 ahc_name(ahc), devinfo.channel, devinfo.target,
663 lastphase, ahc_inb(ahc, SCSISIGI));
664 break;
665 }
666 case MISSED_BUSFREE:
667 {
668 u_int lastphase;
669
670 lastphase = ahc_inb(ahc, LASTPHASE);
671 printf("%s:%c:%d: Missed busfree. "
672 "Lastphase = 0x%x, Curphase = 0x%x\n",
673 ahc_name(ahc), devinfo.channel, devinfo.target,
674 lastphase, ahc_inb(ahc, SCSISIGI));
675 ahc_restart(ahc);
676 return;
677 }
678 case HOST_MSG_LOOP:
679 {
680 /*
681 * The sequencer has encountered a message phase
682 * that requires host assistance for completion.
683 * While handling the message phase(s), we will be
684 * notified by the sequencer after each byte is
685 * transferred so we can track bus phase changes.
686 *
687 * If this is the first time we've seen a HOST_MSG_LOOP
688 * interrupt, initialize the state of the host message
689 * loop.
690 */
691 if (ahc->msg_type == MSG_TYPE_NONE) {
692 struct scb *scb;
693 u_int scb_index;
694 u_int bus_phase;
695
696 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
697 if (bus_phase != P_MESGIN
698 && bus_phase != P_MESGOUT) {
699 printf("ahc_intr: HOST_MSG_LOOP bad "
700 "phase 0x%x\n",
701 bus_phase);
702 /*
703 * Probably transitioned to bus free before
704 * we got here. Just punt the message.
705 */
706 ahc_clear_intstat(ahc);
707 ahc_restart(ahc);
708 return;
709 }
710
711 scb_index = ahc_inb(ahc, SCB_TAG);
712 scb = ahc_lookup_scb(ahc, scb_index);
713 if (devinfo.role == ROLE_INITIATOR) {
714 if (scb == NULL)
715 panic("HOST_MSG_LOOP with "
716 "invalid SCB %x\n", scb_index);
717
718 if (bus_phase == P_MESGOUT)
719 ahc_setup_initiator_msgout(ahc,
720 &devinfo,
721 scb);
722 else {
723 ahc->msg_type =
724 MSG_TYPE_INITIATOR_MSGIN;
725 ahc->msgin_index = 0;
726 }
727 }
728 #ifdef AHC_TARGET_MODE
729 else {
730 if (bus_phase == P_MESGOUT) {
731 ahc->msg_type =
732 MSG_TYPE_TARGET_MSGOUT;
733 ahc->msgin_index = 0;
734 }
735 else
736 ahc_setup_target_msgin(ahc,
737 &devinfo,
738 scb);
739 }
740 #endif
741 }
742
743 ahc_handle_message_phase(ahc);
744 break;
745 }
746 case PERR_DETECTED:
747 {
748 /*
749 * If we've cleared the parity error interrupt
750 * but the sequencer still believes that SCSIPERR
751 * is true, it must be that the parity error is
752 * for the currently presented byte on the bus,
753 * and we are not in a phase (data-in) where we will
754 * eventually ack this byte. Ack the byte and
755 * throw it away in the hope that the target will
756 * take us to message out to deliver the appropriate
757 * error message.
758 */
759 if ((intstat & SCSIINT) == 0
760 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
761 if ((ahc->features & AHC_DT) == 0) {
762 u_int curphase;
763
764 /*
765 * The hardware will only let you ack bytes
766 * if the expected phase in SCSISIGO matches
767 * the current phase. Make sure this is
768 * currently the case.
769 */
770 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
771 ahc_outb(ahc, LASTPHASE, curphase);
772 ahc_outb(ahc, SCSISIGO, curphase);
773 }
774 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
775 int wait;
776
777 /*
778 * In a data phase. Faster to bitbucket
779 * the data than to individually ack each
780 * byte. This is also the only strategy
781 * that will work with AUTOACK enabled.
782 */
783 ahc_outb(ahc, SXFRCTL1,
784 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
785 wait = 5000;
786 while (--wait != 0) {
787 if ((ahc_inb(ahc, SCSISIGI)
788 & (CDI|MSGI)) != 0)
789 break;
790 aic_delay(100);
791 }
792 ahc_outb(ahc, SXFRCTL1,
793 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
794 if (wait == 0) {
795 struct scb *scb;
796 u_int scb_index;
797
798 ahc_print_devinfo(ahc, &devinfo);
799 printf("Unable to clear parity error. "
800 "Resetting bus.\n");
801 scb_index = ahc_inb(ahc, SCB_TAG);
802 scb = ahc_lookup_scb(ahc, scb_index);
803 if (scb != NULL)
804 aic_set_transaction_status(scb,
805 CAM_UNCOR_PARITY);
806 ahc_reset_channel(ahc, devinfo.channel,
807 /*init reset*/TRUE);
808 }
809 } else {
810 ahc_inb(ahc, SCSIDATL);
811 }
812 }
813 break;
814 }
815 case DATA_OVERRUN:
816 {
817 /*
818 * When the sequencer detects an overrun, it
819 * places the controller in "BITBUCKET" mode
820 * and allows the target to complete its transfer.
821 * Unfortunately, none of the counters get updated
822 * when the controller is in this mode, so we have
823 * no way of knowing how large the overrun was.
824 */
825 u_int scbindex = ahc_inb(ahc, SCB_TAG);
826 u_int lastphase = ahc_inb(ahc, LASTPHASE);
827 u_int i;
828
829 scb = ahc_lookup_scb(ahc, scbindex);
830 for (i = 0; i < num_phases; i++) {
831 if (lastphase == ahc_phase_table[i].phase)
832 break;
833 }
834 ahc_print_path(ahc, scb);
835 printf("data overrun detected %s."
836 " Tag == 0x%x.\n",
837 ahc_phase_table[i].phasemsg,
838 scb->hscb->tag);
839 ahc_print_path(ahc, scb);
840 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
841 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
842 aic_get_transfer_length(scb), scb->sg_count);
843 if (scb->sg_count > 0) {
844 for (i = 0; i < scb->sg_count; i++) {
845 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
846 i,
847 (aic_le32toh(scb->sg_list[i].len) >> 24
848 & SG_HIGH_ADDR_BITS),
849 aic_le32toh(scb->sg_list[i].addr),
850 aic_le32toh(scb->sg_list[i].len)
851 & AHC_SG_LEN_MASK);
852 }
853 }
854 /*
855 * Set this and it will take effect when the
856 * target does a command complete.
857 */
858 ahc_freeze_devq(ahc, scb);
859 if ((scb->flags & SCB_SENSE) == 0) {
860 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
861 } else {
862 scb->flags &= ~SCB_SENSE;
863 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
864 }
865 aic_freeze_scb(scb);
866
867 if ((ahc->features & AHC_ULTRA2) != 0) {
868 /*
869 * Clear the channel in case we return
870 * to data phase later.
871 */
872 ahc_outb(ahc, SXFRCTL0,
873 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
874 ahc_outb(ahc, SXFRCTL0,
875 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
876 }
877 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
878 u_int dscommand1;
879
880 /* Ensure HHADDR is 0 for future DMA operations. */
881 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
882 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
883 ahc_outb(ahc, HADDR, 0);
884 ahc_outb(ahc, DSCOMMAND1, dscommand1);
885 }
886 break;
887 }
888 case MKMSG_FAILED:
889 {
890 u_int scbindex;
891
892 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
893 ahc_name(ahc), devinfo.channel, devinfo.target,
894 devinfo.lun);
895 scbindex = ahc_inb(ahc, SCB_TAG);
896 scb = ahc_lookup_scb(ahc, scbindex);
897 if (scb != NULL
898 && (scb->flags & SCB_RECOVERY_SCB) != 0)
899 /*
900 * Ensure that we didn't put a second instance of this
901 * SCB into the QINFIFO.
902 */
903 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
904 SCB_GET_CHANNEL(ahc, scb),
905 SCB_GET_LUN(scb), scb->hscb->tag,
906 ROLE_INITIATOR, /*status*/0,
907 SEARCH_REMOVE);
908 break;
909 }
910 case NO_FREE_SCB:
911 {
912 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
913 ahc_dump_card_state(ahc);
914 panic("for safety");
915 break;
916 }
917 case SCB_MISMATCH:
918 {
919 u_int scbptr;
920
921 scbptr = ahc_inb(ahc, SCBPTR);
922 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
923 scbptr, ahc_inb(ahc, ARG_1),
924 ahc->scb_data->hscbs[scbptr].tag);
925 ahc_dump_card_state(ahc);
926 panic("for safety");
927 break;
928 }
929 case OUT_OF_RANGE:
930 {
931 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
932 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
933 "ARG_1 == 0x%x ACCUM = 0x%x\n",
934 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
935 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
936 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
937 "SINDEX == 0x%x\n, A == 0x%x\n",
938 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
939 ahc_index_busy_tcl(ahc,
940 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
941 ahc_inb(ahc, SAVED_LUN))),
942 ahc_inb(ahc, SINDEX),
943 ahc_inb(ahc, ACCUM));
944 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
945 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
946 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
947 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
948 ahc_inb(ahc, SCB_CONTROL));
949 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
950 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
951 ahc_dump_card_state(ahc);
952 panic("for safety");
953 break;
954 }
955 default:
956 printf("ahc_intr: seqint, "
957 "intstat == 0x%x, scsisigi = 0x%x\n",
958 intstat, ahc_inb(ahc, SCSISIGI));
959 break;
960 }
961 unpause:
962 /*
963 * The sequencer is paused immediately on
964 * a SEQINT, so we should restart it when
965 * we're done.
966 */
967 ahc_unpause(ahc);
968 }
969
970 void
ahc_handle_scsiint(struct ahc_softc * ahc,u_int intstat)971 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
972 {
973 u_int scb_index;
974 u_int status0;
975 u_int status;
976 struct scb *scb;
977 char cur_channel;
978 char intr_channel;
979
980 if ((ahc->features & AHC_TWIN) != 0
981 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
982 cur_channel = 'B';
983 else
984 cur_channel = 'A';
985 intr_channel = cur_channel;
986
987 if ((ahc->features & AHC_ULTRA2) != 0)
988 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
989 else
990 status0 = 0;
991 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
992 if (status == 0 && status0 == 0) {
993 if ((ahc->features & AHC_TWIN) != 0) {
994 /* Try the other channel */
995 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
996 status = ahc_inb(ahc, SSTAT1)
997 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
998 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
999 }
1000 if (status == 0) {
1001 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1002 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1003 ahc_unpause(ahc);
1004 return;
1005 }
1006 }
1007
1008 /* Make sure the sequencer is in a safe location. */
1009 ahc_clear_critical_section(ahc);
1010
1011 scb_index = ahc_inb(ahc, SCB_TAG);
1012 scb = ahc_lookup_scb(ahc, scb_index);
1013 if (scb != NULL
1014 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1015 scb = NULL;
1016
1017 if ((ahc->features & AHC_ULTRA2) != 0
1018 && (status0 & IOERR) != 0) {
1019 int now_lvd;
1020
1021 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1022 printf("%s: Transceiver State Has Changed to %s mode\n",
1023 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1024 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1025 /*
1026 * When transitioning to SE mode, the reset line
1027 * glitches, triggering an arbitration bug in some
1028 * Ultra2 controllers. This bug is cleared when we
1029 * assert the reset line. Since a reset glitch has
1030 * already occurred with this transition and a
1031 * transceiver state change is handled just like
1032 * a bus reset anyway, asserting the reset line
1033 * ourselves is safe.
1034 */
1035 ahc_reset_channel(ahc, intr_channel,
1036 /*Initiate Reset*/now_lvd == 0);
1037 } else if ((status & SCSIRSTI) != 0) {
1038 printf("%s: Someone reset channel %c\n",
1039 ahc_name(ahc), intr_channel);
1040 if (intr_channel != cur_channel)
1041 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1042 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1043 } else if ((status & SCSIPERR) != 0) {
1044 /*
1045 * Determine the bus phase and queue an appropriate message.
1046 * SCSIPERR is latched true as soon as a parity error
1047 * occurs. If the sequencer acked the transfer that
1048 * caused the parity error and the currently presented
1049 * transfer on the bus has correct parity, SCSIPERR will
1050 * be cleared by CLRSCSIPERR. Use this to determine if
1051 * we should look at the last phase the sequencer recorded,
1052 * or the current phase presented on the bus.
1053 */
1054 struct ahc_devinfo devinfo;
1055 u_int mesg_out;
1056 u_int curphase;
1057 u_int errorphase;
1058 u_int lastphase;
1059 u_int scsirate;
1060 u_int i;
1061 u_int sstat2;
1062 int silent;
1063
1064 lastphase = ahc_inb(ahc, LASTPHASE);
1065 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1066 sstat2 = ahc_inb(ahc, SSTAT2);
1067 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1068 /*
1069 * For all phases save DATA, the sequencer won't
1070 * automatically ack a byte that has a parity error
1071 * in it. So the only way that the current phase
1072 * could be 'data-in' is if the parity error is for
1073 * an already acked byte in the data phase. During
1074 * synchronous data-in transfers, we may actually
1075 * ack bytes before latching the current phase in
1076 * LASTPHASE, leading to the discrepancy between
1077 * curphase and lastphase.
1078 */
1079 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1080 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1081 errorphase = curphase;
1082 else
1083 errorphase = lastphase;
1084
1085 for (i = 0; i < num_phases; i++) {
1086 if (errorphase == ahc_phase_table[i].phase)
1087 break;
1088 }
1089 mesg_out = ahc_phase_table[i].mesg_out;
1090 silent = FALSE;
1091 if (scb != NULL) {
1092 if (SCB_IS_SILENT(scb))
1093 silent = TRUE;
1094 else
1095 ahc_print_path(ahc, scb);
1096 scb->flags |= SCB_TRANSMISSION_ERROR;
1097 } else
1098 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1099 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1100 scsirate = ahc_inb(ahc, SCSIRATE);
1101 if (silent == FALSE) {
1102 printf("parity error detected %s. "
1103 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1104 ahc_phase_table[i].phasemsg,
1105 ahc_inw(ahc, SEQADDR0),
1106 scsirate);
1107 if ((ahc->features & AHC_DT) != 0) {
1108 if ((sstat2 & CRCVALERR) != 0)
1109 printf("\tCRC Value Mismatch\n");
1110 if ((sstat2 & CRCENDERR) != 0)
1111 printf("\tNo terminal CRC packet "
1112 "received\n");
1113 if ((sstat2 & CRCREQERR) != 0)
1114 printf("\tIllegal CRC packet "
1115 "request\n");
1116 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1117 printf("\tUnexpected %sDT Data Phase\n",
1118 (scsirate & SINGLE_EDGE)
1119 ? "" : "non-");
1120 }
1121 }
1122
1123 if ((ahc->features & AHC_DT) != 0
1124 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1125 /*
1126 * This error applies regardless of
1127 * data direction, so ignore the value
1128 * in the phase table.
1129 */
1130 mesg_out = MSG_INITIATOR_DET_ERR;
1131 }
1132
1133 /*
1134 * We've set the hardware to assert ATN if we
1135 * get a parity error on "in" phases, so all we
1136 * need to do is stuff the message buffer with
1137 * the appropriate message. "In" phases have set
1138 * mesg_out to something other than MSG_NOP.
1139 */
1140 if (mesg_out != MSG_NOOP) {
1141 if (ahc->msg_type != MSG_TYPE_NONE)
1142 ahc->send_msg_perror = TRUE;
1143 else
1144 ahc_outb(ahc, MSG_OUT, mesg_out);
1145 }
1146 /*
1147 * Force a renegotiation with this target just in
1148 * case we are out of sync for some external reason
1149 * unknown (or unreported) by the target.
1150 */
1151 ahc_fetch_devinfo(ahc, &devinfo);
1152 ahc_force_renegotiation(ahc, &devinfo);
1153
1154 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1155 ahc_unpause(ahc);
1156 } else if ((status & SELTO) != 0) {
1157 u_int scbptr;
1158
1159 /* Stop the selection */
1160 ahc_outb(ahc, SCSISEQ, 0);
1161
1162 /* No more pending messages */
1163 ahc_clear_msg_state(ahc);
1164
1165 /* Clear interrupt state */
1166 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1167 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1168
1169 /*
1170 * Although the driver does not care about the
1171 * 'Selection in Progress' status bit, the busy
1172 * LED does. SELINGO is only cleared by a successful
1173 * selection, so we must manually clear it to insure
1174 * the LED turns off just incase no future successful
1175 * selections occur (e.g. no devices on the bus).
1176 */
1177 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1178
1179 scbptr = ahc_inb(ahc, WAITING_SCBH);
1180 ahc_outb(ahc, SCBPTR, scbptr);
1181 scb_index = ahc_inb(ahc, SCB_TAG);
1182
1183 scb = ahc_lookup_scb(ahc, scb_index);
1184 if (scb == NULL) {
1185 printf("%s: ahc_intr - referenced scb not "
1186 "valid during SELTO scb(%d, %d)\n",
1187 ahc_name(ahc), scbptr, scb_index);
1188 ahc_dump_card_state(ahc);
1189 } else {
1190 struct ahc_devinfo devinfo;
1191 #ifdef AHC_DEBUG
1192 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1193 ahc_print_path(ahc, scb);
1194 printf("Saw Selection Timeout for SCB 0x%x\n",
1195 scb_index);
1196 }
1197 #endif
1198 ahc_scb_devinfo(ahc, &devinfo, scb);
1199 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1200 ahc_freeze_devq(ahc, scb);
1201
1202 /*
1203 * Cancel any pending transactions on the device
1204 * now that it seems to be missing. This will
1205 * also revert us to async/narrow transfers until
1206 * we can renegotiate with the device.
1207 */
1208 ahc_handle_devreset(ahc, &devinfo,
1209 CAM_SEL_TIMEOUT,
1210 "Selection Timeout",
1211 /*verbose_level*/1);
1212 }
1213 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1214 ahc_restart(ahc);
1215 } else if ((status & BUSFREE) != 0
1216 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1217 struct ahc_devinfo devinfo;
1218 u_int lastphase;
1219 u_int saved_scsiid;
1220 u_int saved_lun;
1221 u_int target;
1222 u_int initiator_role_id;
1223 char channel;
1224 int printerror;
1225
1226 /*
1227 * Clear our selection hardware as soon as possible.
1228 * We may have an entry in the waiting Q for this target,
1229 * that is affected by this busfree and we don't want to
1230 * go about selecting the target while we handle the event.
1231 */
1232 ahc_outb(ahc, SCSISEQ,
1233 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1234
1235 /*
1236 * Disable busfree interrupts and clear the busfree
1237 * interrupt status. We do this here so that several
1238 * bus transactions occur prior to clearing the SCSIINT
1239 * latch. It can take a bit for the clearing to take effect.
1240 */
1241 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1242 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1243
1244 /*
1245 * Look at what phase we were last in.
1246 * If its message out, chances are pretty good
1247 * that the busfree was in response to one of
1248 * our abort requests.
1249 */
1250 lastphase = ahc_inb(ahc, LASTPHASE);
1251 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1252 saved_lun = ahc_inb(ahc, SAVED_LUN);
1253 target = SCSIID_TARGET(ahc, saved_scsiid);
1254 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1255 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1256 ahc_compile_devinfo(&devinfo, initiator_role_id,
1257 target, saved_lun, channel, ROLE_INITIATOR);
1258 printerror = 1;
1259
1260 if (lastphase == P_MESGOUT) {
1261 u_int tag;
1262
1263 tag = SCB_LIST_NULL;
1264 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1265 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1266 if (ahc->msgout_buf[ahc->msgout_index - 1]
1267 == MSG_ABORT_TAG)
1268 tag = scb->hscb->tag;
1269 ahc_print_path(ahc, scb);
1270 printf("SCB %d - Abort%s Completed.\n",
1271 scb->hscb->tag, tag == SCB_LIST_NULL ?
1272 "" : " Tag");
1273 ahc_abort_scbs(ahc, target, channel,
1274 saved_lun, tag,
1275 ROLE_INITIATOR,
1276 CAM_REQ_ABORTED);
1277 printerror = 0;
1278 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1279 MSG_BUS_DEV_RESET, TRUE)) {
1280 #ifdef __FreeBSD__
1281 /*
1282 * Don't mark the user's request for this BDR
1283 * as completing with CAM_BDR_SENT. CAM3
1284 * specifies CAM_REQ_CMP.
1285 */
1286 if (scb != NULL
1287 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1288 && ahc_match_scb(ahc, scb, target, channel,
1289 CAM_LUN_WILDCARD,
1290 SCB_LIST_NULL,
1291 ROLE_INITIATOR)) {
1292 aic_set_transaction_status(scb, CAM_REQ_CMP);
1293 }
1294 #endif
1295 ahc_compile_devinfo(&devinfo,
1296 initiator_role_id,
1297 target,
1298 CAM_LUN_WILDCARD,
1299 channel,
1300 ROLE_INITIATOR);
1301 ahc_handle_devreset(ahc, &devinfo,
1302 CAM_BDR_SENT,
1303 "Bus Device Reset",
1304 /*verbose_level*/0);
1305 printerror = 0;
1306 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1307 MSG_EXT_PPR, FALSE)) {
1308 struct ahc_initiator_tinfo *tinfo;
1309 struct ahc_tmode_tstate *tstate;
1310
1311 /*
1312 * PPR Rejected. Try non-ppr negotiation
1313 * and retry command.
1314 */
1315 tinfo = ahc_fetch_transinfo(ahc,
1316 devinfo.channel,
1317 devinfo.our_scsiid,
1318 devinfo.target,
1319 &tstate);
1320 tinfo->curr.transport_version = 2;
1321 tinfo->goal.transport_version = 2;
1322 tinfo->goal.ppr_options = 0;
1323 ahc_qinfifo_requeue_tail(ahc, scb);
1324 printerror = 0;
1325 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1326 MSG_EXT_WDTR, FALSE)) {
1327 /*
1328 * Negotiation Rejected. Go-narrow and
1329 * retry command.
1330 */
1331 ahc_set_width(ahc, &devinfo,
1332 MSG_EXT_WDTR_BUS_8_BIT,
1333 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1334 /*paused*/TRUE);
1335 ahc_qinfifo_requeue_tail(ahc, scb);
1336 printerror = 0;
1337 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1338 MSG_EXT_SDTR, FALSE)) {
1339 /*
1340 * Negotiation Rejected. Go-async and
1341 * retry command.
1342 */
1343 ahc_set_syncrate(ahc, &devinfo,
1344 /*syncrate*/NULL,
1345 /*period*/0, /*offset*/0,
1346 /*ppr_options*/0,
1347 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1348 /*paused*/TRUE);
1349 ahc_qinfifo_requeue_tail(ahc, scb);
1350 printerror = 0;
1351 }
1352 }
1353 if (printerror != 0) {
1354 u_int i;
1355
1356 if (scb != NULL) {
1357 u_int tag;
1358
1359 if ((scb->hscb->control & TAG_ENB) != 0)
1360 tag = scb->hscb->tag;
1361 else
1362 tag = SCB_LIST_NULL;
1363 ahc_print_path(ahc, scb);
1364 ahc_abort_scbs(ahc, target, channel,
1365 SCB_GET_LUN(scb), tag,
1366 ROLE_INITIATOR,
1367 CAM_UNEXP_BUSFREE);
1368 } else {
1369 /*
1370 * We had not fully identified this connection,
1371 * so we cannot abort anything.
1372 */
1373 printf("%s: ", ahc_name(ahc));
1374 }
1375 for (i = 0; i < num_phases; i++) {
1376 if (lastphase == ahc_phase_table[i].phase)
1377 break;
1378 }
1379 if (lastphase != P_BUSFREE) {
1380 /*
1381 * Renegotiate with this device at the
1382 * next opportunity just in case this busfree
1383 * is due to a negotiation mismatch with the
1384 * device.
1385 */
1386 ahc_force_renegotiation(ahc, &devinfo);
1387 }
1388 printf("Unexpected busfree %s\n"
1389 "SEQADDR == 0x%x\n",
1390 ahc_phase_table[i].phasemsg,
1391 ahc_inb(ahc, SEQADDR0)
1392 | (ahc_inb(ahc, SEQADDR1) << 8));
1393 }
1394 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1395 ahc_restart(ahc);
1396 } else {
1397 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1398 ahc_name(ahc), status);
1399 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1400 }
1401 }
1402
1403 /*
1404 * Force renegotiation to occur the next time we initiate
1405 * a command to the current device.
1406 */
1407 static void
ahc_force_renegotiation(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)1408 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1409 {
1410 struct ahc_initiator_tinfo *targ_info;
1411 struct ahc_tmode_tstate *tstate;
1412
1413 targ_info = ahc_fetch_transinfo(ahc,
1414 devinfo->channel,
1415 devinfo->our_scsiid,
1416 devinfo->target,
1417 &tstate);
1418 ahc_update_neg_request(ahc, devinfo, tstate,
1419 targ_info, AHC_NEG_IF_NON_ASYNC);
1420 }
1421
1422 #define AHC_MAX_STEPS 2000
1423 void
ahc_clear_critical_section(struct ahc_softc * ahc)1424 ahc_clear_critical_section(struct ahc_softc *ahc)
1425 {
1426 int stepping;
1427 int steps;
1428 u_int simode0;
1429 u_int simode1;
1430
1431 if (ahc->num_critical_sections == 0)
1432 return;
1433
1434 stepping = FALSE;
1435 steps = 0;
1436 simode0 = 0;
1437 simode1 = 0;
1438 for (;;) {
1439 struct cs *cs;
1440 u_int seqaddr;
1441 u_int i;
1442
1443 seqaddr = ahc_inb(ahc, SEQADDR0)
1444 | (ahc_inb(ahc, SEQADDR1) << 8);
1445
1446 /*
1447 * Seqaddr represents the next instruction to execute,
1448 * so we are really executing the instruction just
1449 * before it.
1450 */
1451 cs = ahc->critical_sections;
1452 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1453
1454 if (cs->begin < seqaddr && cs->end >= seqaddr)
1455 break;
1456 }
1457
1458 if (i == ahc->num_critical_sections)
1459 break;
1460
1461 if (steps > AHC_MAX_STEPS) {
1462 printf("%s: Infinite loop in critical section\n",
1463 ahc_name(ahc));
1464 ahc_dump_card_state(ahc);
1465 panic("critical section loop");
1466 }
1467
1468 steps++;
1469 if (stepping == FALSE) {
1470 /*
1471 * Disable all interrupt sources so that the
1472 * sequencer will not be stuck by a pausing
1473 * interrupt condition while we attempt to
1474 * leave a critical section.
1475 */
1476 simode0 = ahc_inb(ahc, SIMODE0);
1477 ahc_outb(ahc, SIMODE0, 0);
1478 simode1 = ahc_inb(ahc, SIMODE1);
1479 if ((ahc->features & AHC_DT) != 0)
1480 /*
1481 * On DT class controllers, we
1482 * use the enhanced busfree logic.
1483 * Unfortunately we cannot re-enable
1484 * busfree detection within the
1485 * current connection, so we must
1486 * leave it on while single stepping.
1487 */
1488 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1489 else
1490 ahc_outb(ahc, SIMODE1, 0);
1491 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1492 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1493 stepping = TRUE;
1494 }
1495 if ((ahc->features & AHC_DT) != 0) {
1496 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1497 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1498 }
1499 ahc_outb(ahc, HCNTRL, ahc->unpause);
1500 while (!ahc_is_paused(ahc))
1501 aic_delay(200);
1502 }
1503 if (stepping) {
1504 ahc_outb(ahc, SIMODE0, simode0);
1505 ahc_outb(ahc, SIMODE1, simode1);
1506 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1507 }
1508 }
1509
1510 /*
1511 * Clear any pending interrupt status.
1512 */
1513 void
ahc_clear_intstat(struct ahc_softc * ahc)1514 ahc_clear_intstat(struct ahc_softc *ahc)
1515 {
1516 /* Clear any interrupt conditions this may have caused */
1517 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1518 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1519 CLRREQINIT);
1520 ahc_flush_device_writes(ahc);
1521 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1522 ahc_flush_device_writes(ahc);
1523 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1524 ahc_flush_device_writes(ahc);
1525 }
1526
1527 /**************************** Debugging Routines ******************************/
1528 #ifdef AHC_DEBUG
1529 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1530 #endif
1531
1532 void
ahc_print_scb(struct scb * scb)1533 ahc_print_scb(struct scb *scb)
1534 {
1535 int i;
1536
1537 struct hardware_scb *hscb = scb->hscb;
1538
1539 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1540 (void *)scb,
1541 hscb->control,
1542 hscb->scsiid,
1543 hscb->lun,
1544 hscb->cdb_len);
1545 printf("Shared Data: ");
1546 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1547 printf("%#02x", hscb->shared_data.cdb[i]);
1548 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1549 aic_le32toh(hscb->dataptr),
1550 aic_le32toh(hscb->datacnt),
1551 aic_le32toh(hscb->sgptr),
1552 hscb->tag);
1553 if (scb->sg_count > 0) {
1554 for (i = 0; i < scb->sg_count; i++) {
1555 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1556 i,
1557 (aic_le32toh(scb->sg_list[i].len) >> 24
1558 & SG_HIGH_ADDR_BITS),
1559 aic_le32toh(scb->sg_list[i].addr),
1560 aic_le32toh(scb->sg_list[i].len));
1561 }
1562 }
1563 }
1564
1565 /************************* Transfer Negotiation *******************************/
1566 /*
1567 * Allocate per target mode instance (ID we respond to as a target)
1568 * transfer negotiation data structures.
1569 */
1570 static struct ahc_tmode_tstate *
ahc_alloc_tstate(struct ahc_softc * ahc,u_int scsi_id,char channel)1571 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1572 {
1573 struct ahc_tmode_tstate *master_tstate;
1574 struct ahc_tmode_tstate *tstate;
1575 int i;
1576
1577 master_tstate = ahc->enabled_targets[ahc->our_id];
1578 if (channel == 'B') {
1579 scsi_id += 8;
1580 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1581 }
1582 if (ahc->enabled_targets[scsi_id] != NULL
1583 && ahc->enabled_targets[scsi_id] != master_tstate)
1584 panic("%s: ahc_alloc_tstate - Target already allocated",
1585 ahc_name(ahc));
1586 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1587 M_DEVBUF, M_NOWAIT);
1588 if (tstate == NULL)
1589 return (NULL);
1590
1591 /*
1592 * If we have allocated a master tstate, copy user settings from
1593 * the master tstate (taken from SRAM or the EEPROM) for this
1594 * channel, but reset our current and goal settings to async/narrow
1595 * until an initiator talks to us.
1596 */
1597 if (master_tstate != NULL) {
1598 memcpy(tstate, master_tstate, sizeof(*tstate));
1599 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1600 tstate->ultraenb = 0;
1601 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1602 memset(&tstate->transinfo[i].curr, 0,
1603 sizeof(tstate->transinfo[i].curr));
1604 memset(&tstate->transinfo[i].goal, 0,
1605 sizeof(tstate->transinfo[i].goal));
1606 }
1607 } else
1608 memset(tstate, 0, sizeof(*tstate));
1609 ahc->enabled_targets[scsi_id] = tstate;
1610 return (tstate);
1611 }
1612
1613 #ifdef AHC_TARGET_MODE
1614 /*
1615 * Free per target mode instance (ID we respond to as a target)
1616 * transfer negotiation data structures.
1617 */
1618 static void
ahc_free_tstate(struct ahc_softc * ahc,u_int scsi_id,char channel,int force)1619 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1620 {
1621 struct ahc_tmode_tstate *tstate;
1622
1623 /*
1624 * Don't clean up our "master" tstate.
1625 * It has our default user settings.
1626 */
1627 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1628 || (channel == 'A' && scsi_id == ahc->our_id))
1629 && force == FALSE)
1630 return;
1631
1632 if (channel == 'B')
1633 scsi_id += 8;
1634 tstate = ahc->enabled_targets[scsi_id];
1635 if (tstate != NULL)
1636 free(tstate, M_DEVBUF);
1637 ahc->enabled_targets[scsi_id] = NULL;
1638 }
1639 #endif
1640
1641 /*
1642 * Called when we have an active connection to a target on the bus,
1643 * this function finds the nearest syncrate to the input period limited
1644 * by the capabilities of the bus connectivity of and sync settings for
1645 * the target.
1646 */
1647 struct ahc_syncrate *
ahc_devlimited_syncrate(struct ahc_softc * ahc,struct ahc_initiator_tinfo * tinfo,u_int * period,u_int * ppr_options,role_t role)1648 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1649 struct ahc_initiator_tinfo *tinfo,
1650 u_int *period, u_int *ppr_options, role_t role)
1651 {
1652 struct ahc_transinfo *transinfo;
1653 u_int maxsync;
1654
1655 if ((ahc->features & AHC_ULTRA2) != 0) {
1656 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1657 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1658 maxsync = AHC_SYNCRATE_DT;
1659 } else {
1660 maxsync = AHC_SYNCRATE_ULTRA;
1661 /* Can't do DT on an SE bus */
1662 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1663 }
1664 } else if ((ahc->features & AHC_ULTRA) != 0) {
1665 maxsync = AHC_SYNCRATE_ULTRA;
1666 } else {
1667 maxsync = AHC_SYNCRATE_FAST;
1668 }
1669 /*
1670 * Never allow a value higher than our current goal
1671 * period otherwise we may allow a target initiated
1672 * negotiation to go above the limit as set by the
1673 * user. In the case of an initiator initiated
1674 * sync negotiation, we limit based on the user
1675 * setting. This allows the system to still accept
1676 * incoming negotiations even if target initiated
1677 * negotiation is not performed.
1678 */
1679 if (role == ROLE_TARGET)
1680 transinfo = &tinfo->user;
1681 else
1682 transinfo = &tinfo->goal;
1683 *ppr_options &= transinfo->ppr_options;
1684 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1685 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1686 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1687 }
1688 if (transinfo->period == 0) {
1689 *period = 0;
1690 *ppr_options = 0;
1691 return (NULL);
1692 }
1693 *period = MAX(*period, transinfo->period);
1694 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1695 }
1696
1697 /*
1698 * Look up the valid period to SCSIRATE conversion in our table.
1699 * Return the period and offset that should be sent to the target
1700 * if this was the beginning of an SDTR.
1701 */
1702 struct ahc_syncrate *
ahc_find_syncrate(struct ahc_softc * ahc,u_int * period,u_int * ppr_options,u_int maxsync)1703 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1704 u_int *ppr_options, u_int maxsync)
1705 {
1706 struct ahc_syncrate *syncrate;
1707
1708 if ((ahc->features & AHC_DT) == 0)
1709 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1710
1711 /* Skip all DT only entries if DT is not available */
1712 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1713 && maxsync < AHC_SYNCRATE_ULTRA2)
1714 maxsync = AHC_SYNCRATE_ULTRA2;
1715
1716 for (syncrate = &ahc_syncrates[maxsync];
1717 syncrate->rate != NULL;
1718 syncrate++) {
1719 /*
1720 * The Ultra2 table doesn't go as low
1721 * as for the Fast/Ultra cards.
1722 */
1723 if ((ahc->features & AHC_ULTRA2) != 0
1724 && (syncrate->sxfr_u2 == 0))
1725 break;
1726
1727 if (*period <= syncrate->period) {
1728 /*
1729 * When responding to a target that requests
1730 * sync, the requested rate may fall between
1731 * two rates that we can output, but still be
1732 * a rate that we can receive. Because of this,
1733 * we want to respond to the target with
1734 * the same rate that it sent to us even
1735 * if the period we use to send data to it
1736 * is lower. Only lower the response period
1737 * if we must.
1738 */
1739 if (syncrate == &ahc_syncrates[maxsync])
1740 *period = syncrate->period;
1741
1742 /*
1743 * At some speeds, we only support
1744 * ST transfers.
1745 */
1746 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1747 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1748 break;
1749 }
1750 }
1751
1752 if ((*period == 0)
1753 || (syncrate->rate == NULL)
1754 || ((ahc->features & AHC_ULTRA2) != 0
1755 && (syncrate->sxfr_u2 == 0))) {
1756 /* Use asynchronous transfers. */
1757 *period = 0;
1758 syncrate = NULL;
1759 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1760 }
1761 return (syncrate);
1762 }
1763
1764 /*
1765 * Convert from an entry in our syncrate table to the SCSI equivalent
1766 * sync "period" factor.
1767 */
1768 u_int
ahc_find_period(struct ahc_softc * ahc,u_int scsirate,u_int maxsync)1769 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1770 {
1771 struct ahc_syncrate *syncrate;
1772
1773 if ((ahc->features & AHC_ULTRA2) != 0)
1774 scsirate &= SXFR_ULTRA2;
1775 else
1776 scsirate &= SXFR;
1777
1778 syncrate = &ahc_syncrates[maxsync];
1779 while (syncrate->rate != NULL) {
1780 if ((ahc->features & AHC_ULTRA2) != 0) {
1781 if (syncrate->sxfr_u2 == 0)
1782 break;
1783 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1784 return (syncrate->period);
1785 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1786 return (syncrate->period);
1787 }
1788 syncrate++;
1789 }
1790 return (0); /* async */
1791 }
1792
1793 /*
1794 * Truncate the given synchronous offset to a value the
1795 * current adapter type and syncrate are capable of.
1796 */
1797 void
ahc_validate_offset(struct ahc_softc * ahc,struct ahc_initiator_tinfo * tinfo,struct ahc_syncrate * syncrate,u_int * offset,int wide,role_t role)1798 ahc_validate_offset(struct ahc_softc *ahc,
1799 struct ahc_initiator_tinfo *tinfo,
1800 struct ahc_syncrate *syncrate,
1801 u_int *offset, int wide, role_t role)
1802 {
1803 u_int maxoffset;
1804
1805 /* Limit offset to what we can do */
1806 if (syncrate == NULL) {
1807 maxoffset = 0;
1808 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1809 maxoffset = MAX_OFFSET_ULTRA2;
1810 } else {
1811 if (wide)
1812 maxoffset = MAX_OFFSET_16BIT;
1813 else
1814 maxoffset = MAX_OFFSET_8BIT;
1815 }
1816 *offset = MIN(*offset, maxoffset);
1817 if (tinfo != NULL) {
1818 if (role == ROLE_TARGET)
1819 *offset = MIN(*offset, tinfo->user.offset);
1820 else
1821 *offset = MIN(*offset, tinfo->goal.offset);
1822 }
1823 }
1824
1825 /*
1826 * Truncate the given transfer width parameter to a value the
1827 * current adapter type is capable of.
1828 */
1829 void
ahc_validate_width(struct ahc_softc * ahc,struct ahc_initiator_tinfo * tinfo,u_int * bus_width,role_t role)1830 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1831 u_int *bus_width, role_t role)
1832 {
1833 switch (*bus_width) {
1834 default:
1835 if (ahc->features & AHC_WIDE) {
1836 /* Respond Wide */
1837 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1838 break;
1839 }
1840 /* FALLTHROUGH */
1841 case MSG_EXT_WDTR_BUS_8_BIT:
1842 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1843 break;
1844 }
1845 if (tinfo != NULL) {
1846 if (role == ROLE_TARGET)
1847 *bus_width = MIN(tinfo->user.width, *bus_width);
1848 else
1849 *bus_width = MIN(tinfo->goal.width, *bus_width);
1850 }
1851 }
1852
1853 /*
1854 * Update the bitmask of targets for which the controller should
1855 * negotiate with at the next convenient opportunity. This currently
1856 * means the next time we send the initial identify messages for
1857 * a new transaction.
1858 */
1859 int
ahc_update_neg_request(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,struct ahc_tmode_tstate * tstate,struct ahc_initiator_tinfo * tinfo,ahc_neg_type neg_type)1860 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1861 struct ahc_tmode_tstate *tstate,
1862 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1863 {
1864 u_int auto_negotiate_orig;
1865
1866 auto_negotiate_orig = tstate->auto_negotiate;
1867 if (neg_type == AHC_NEG_ALWAYS) {
1868 /*
1869 * Force our "current" settings to be
1870 * unknown so that unless a bus reset
1871 * occurs the need to renegotiate is
1872 * recorded persistently.
1873 */
1874 if ((ahc->features & AHC_WIDE) != 0)
1875 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1876 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1877 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1878 }
1879 if (tinfo->curr.period != tinfo->goal.period
1880 || tinfo->curr.width != tinfo->goal.width
1881 || tinfo->curr.offset != tinfo->goal.offset
1882 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1883 || (neg_type == AHC_NEG_IF_NON_ASYNC
1884 && (tinfo->goal.offset != 0
1885 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1886 || tinfo->goal.ppr_options != 0)))
1887 tstate->auto_negotiate |= devinfo->target_mask;
1888 else
1889 tstate->auto_negotiate &= ~devinfo->target_mask;
1890
1891 return (auto_negotiate_orig != tstate->auto_negotiate);
1892 }
1893
1894 /*
1895 * Update the user/goal/curr tables of synchronous negotiation
1896 * parameters as well as, in the case of a current or active update,
1897 * any data structures on the host controller. In the case of an
1898 * active update, the specified target is currently talking to us on
1899 * the bus, so the transfer parameter update must take effect
1900 * immediately.
1901 */
1902 void
ahc_set_syncrate(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,struct ahc_syncrate * syncrate,u_int period,u_int offset,u_int ppr_options,u_int type,int paused)1903 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1904 struct ahc_syncrate *syncrate, u_int period,
1905 u_int offset, u_int ppr_options, u_int type, int paused)
1906 {
1907 struct ahc_initiator_tinfo *tinfo;
1908 struct ahc_tmode_tstate *tstate;
1909 u_int old_period;
1910 u_int old_offset;
1911 u_int old_ppr;
1912 int active;
1913 int update_needed;
1914
1915 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1916 update_needed = 0;
1917
1918 if (syncrate == NULL) {
1919 period = 0;
1920 offset = 0;
1921 }
1922
1923 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1924 devinfo->target, &tstate);
1925
1926 if ((type & AHC_TRANS_USER) != 0) {
1927 tinfo->user.period = period;
1928 tinfo->user.offset = offset;
1929 tinfo->user.ppr_options = ppr_options;
1930 }
1931
1932 if ((type & AHC_TRANS_GOAL) != 0) {
1933 tinfo->goal.period = period;
1934 tinfo->goal.offset = offset;
1935 tinfo->goal.ppr_options = ppr_options;
1936 }
1937
1938 old_period = tinfo->curr.period;
1939 old_offset = tinfo->curr.offset;
1940 old_ppr = tinfo->curr.ppr_options;
1941
1942 if ((type & AHC_TRANS_CUR) != 0
1943 && (old_period != period
1944 || old_offset != offset
1945 || old_ppr != ppr_options)) {
1946 u_int scsirate;
1947
1948 update_needed++;
1949 scsirate = tinfo->scsirate;
1950 if ((ahc->features & AHC_ULTRA2) != 0) {
1951 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1952 if (syncrate != NULL) {
1953 scsirate |= syncrate->sxfr_u2;
1954 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1955 scsirate |= ENABLE_CRC;
1956 else
1957 scsirate |= SINGLE_EDGE;
1958 }
1959 } else {
1960 scsirate &= ~(SXFR|SOFS);
1961 /*
1962 * Ensure Ultra mode is set properly for
1963 * this target.
1964 */
1965 tstate->ultraenb &= ~devinfo->target_mask;
1966 if (syncrate != NULL) {
1967 if (syncrate->sxfr & ULTRA_SXFR) {
1968 tstate->ultraenb |=
1969 devinfo->target_mask;
1970 }
1971 scsirate |= syncrate->sxfr & SXFR;
1972 scsirate |= offset & SOFS;
1973 }
1974 if (active) {
1975 u_int sxfrctl0;
1976
1977 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1978 sxfrctl0 &= ~FAST20;
1979 if (tstate->ultraenb & devinfo->target_mask)
1980 sxfrctl0 |= FAST20;
1981 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1982 }
1983 }
1984 if (active) {
1985 ahc_outb(ahc, SCSIRATE, scsirate);
1986 if ((ahc->features & AHC_ULTRA2) != 0)
1987 ahc_outb(ahc, SCSIOFFSET, offset);
1988 }
1989
1990 tinfo->scsirate = scsirate;
1991 tinfo->curr.period = period;
1992 tinfo->curr.offset = offset;
1993 tinfo->curr.ppr_options = ppr_options;
1994
1995 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1996 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1997 if (bootverbose) {
1998 if (offset != 0) {
1999 printf("%s: target %d synchronous at %sMHz%s, "
2000 "offset = 0x%x\n", ahc_name(ahc),
2001 devinfo->target, syncrate->rate,
2002 (ppr_options & MSG_EXT_PPR_DT_REQ)
2003 ? " DT" : "", offset);
2004 } else {
2005 printf("%s: target %d using "
2006 "asynchronous transfers\n",
2007 ahc_name(ahc), devinfo->target);
2008 }
2009 }
2010 }
2011
2012 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2013 tinfo, AHC_NEG_TO_GOAL);
2014
2015 if (update_needed)
2016 ahc_update_pending_scbs(ahc);
2017 }
2018
2019 /*
2020 * Update the user/goal/curr tables of wide negotiation
2021 * parameters as well as, in the case of a current or active update,
2022 * any data structures on the host controller. In the case of an
2023 * active update, the specified target is currently talking to us on
2024 * the bus, so the transfer parameter update must take effect
2025 * immediately.
2026 */
2027 void
ahc_set_width(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,u_int width,u_int type,int paused)2028 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2029 u_int width, u_int type, int paused)
2030 {
2031 struct ahc_initiator_tinfo *tinfo;
2032 struct ahc_tmode_tstate *tstate;
2033 u_int oldwidth;
2034 int active;
2035 int update_needed;
2036
2037 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2038 update_needed = 0;
2039 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2040 devinfo->target, &tstate);
2041
2042 if ((type & AHC_TRANS_USER) != 0)
2043 tinfo->user.width = width;
2044
2045 if ((type & AHC_TRANS_GOAL) != 0)
2046 tinfo->goal.width = width;
2047
2048 oldwidth = tinfo->curr.width;
2049 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2050 u_int scsirate;
2051
2052 update_needed++;
2053 scsirate = tinfo->scsirate;
2054 scsirate &= ~WIDEXFER;
2055 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2056 scsirate |= WIDEXFER;
2057
2058 tinfo->scsirate = scsirate;
2059
2060 if (active)
2061 ahc_outb(ahc, SCSIRATE, scsirate);
2062
2063 tinfo->curr.width = width;
2064
2065 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2066 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2067 if (bootverbose) {
2068 printf("%s: target %d using %dbit transfers\n",
2069 ahc_name(ahc), devinfo->target,
2070 8 * (0x01 << width));
2071 }
2072 }
2073
2074 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2075 tinfo, AHC_NEG_TO_GOAL);
2076 if (update_needed)
2077 ahc_update_pending_scbs(ahc);
2078 }
2079
2080 /*
2081 * Update the current state of tagged queuing for a given target.
2082 */
2083 void
ahc_set_tags(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,ahc_queue_alg alg)2084 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2085 ahc_queue_alg alg)
2086 {
2087 ahc_platform_set_tags(ahc, devinfo, alg);
2088 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2089 devinfo->lun, AC_TRANSFER_NEG, &alg);
2090 }
2091
2092 /*
2093 * When the transfer settings for a connection change, update any
2094 * in-transit SCBs to contain the new data so the hardware will
2095 * be set correctly during future (re)selections.
2096 */
2097 static void
ahc_update_pending_scbs(struct ahc_softc * ahc)2098 ahc_update_pending_scbs(struct ahc_softc *ahc)
2099 {
2100 struct scb *pending_scb;
2101 int pending_scb_count;
2102 int i;
2103 int paused;
2104 u_int saved_scbptr;
2105
2106 /*
2107 * Traverse the pending SCB list and ensure that all of the
2108 * SCBs there have the proper settings.
2109 */
2110 pending_scb_count = 0;
2111 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2112 struct ahc_devinfo devinfo;
2113 struct hardware_scb *pending_hscb;
2114 struct ahc_initiator_tinfo *tinfo;
2115 struct ahc_tmode_tstate *tstate;
2116
2117 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2118 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2119 devinfo.our_scsiid,
2120 devinfo.target, &tstate);
2121 pending_hscb = pending_scb->hscb;
2122 pending_hscb->control &= ~ULTRAENB;
2123 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2124 pending_hscb->control |= ULTRAENB;
2125 pending_hscb->scsirate = tinfo->scsirate;
2126 pending_hscb->scsioffset = tinfo->curr.offset;
2127 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2128 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2129 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2130 pending_hscb->control &= ~MK_MESSAGE;
2131 }
2132 ahc_sync_scb(ahc, pending_scb,
2133 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2134 pending_scb_count++;
2135 }
2136
2137 if (pending_scb_count == 0)
2138 return;
2139
2140 if (ahc_is_paused(ahc)) {
2141 paused = 1;
2142 } else {
2143 paused = 0;
2144 ahc_pause(ahc);
2145 }
2146
2147 saved_scbptr = ahc_inb(ahc, SCBPTR);
2148 /* Ensure that the hscbs down on the card match the new information */
2149 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2150 struct hardware_scb *pending_hscb;
2151 u_int control;
2152 u_int scb_tag;
2153
2154 ahc_outb(ahc, SCBPTR, i);
2155 scb_tag = ahc_inb(ahc, SCB_TAG);
2156 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2157 if (pending_scb == NULL)
2158 continue;
2159
2160 pending_hscb = pending_scb->hscb;
2161 control = ahc_inb(ahc, SCB_CONTROL);
2162 control &= ~(ULTRAENB|MK_MESSAGE);
2163 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2164 ahc_outb(ahc, SCB_CONTROL, control);
2165 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2166 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2167 }
2168 ahc_outb(ahc, SCBPTR, saved_scbptr);
2169
2170 if (paused == 0)
2171 ahc_unpause(ahc);
2172 }
2173
2174 /**************************** Pathing Information *****************************/
2175 static void
ahc_fetch_devinfo(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)2176 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2177 {
2178 u_int saved_scsiid;
2179 role_t role;
2180 int our_id;
2181
2182 if (ahc_inb(ahc, SSTAT0) & TARGET)
2183 role = ROLE_TARGET;
2184 else
2185 role = ROLE_INITIATOR;
2186
2187 if (role == ROLE_TARGET
2188 && (ahc->features & AHC_MULTI_TID) != 0
2189 && (ahc_inb(ahc, SEQ_FLAGS)
2190 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2191 /* We were selected, so pull our id from TARGIDIN */
2192 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2193 } else if ((ahc->features & AHC_ULTRA2) != 0)
2194 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2195 else
2196 our_id = ahc_inb(ahc, SCSIID) & OID;
2197
2198 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2199 ahc_compile_devinfo(devinfo,
2200 our_id,
2201 SCSIID_TARGET(ahc, saved_scsiid),
2202 ahc_inb(ahc, SAVED_LUN),
2203 SCSIID_CHANNEL(ahc, saved_scsiid),
2204 role);
2205 }
2206
2207 struct ahc_phase_table_entry*
ahc_lookup_phase_entry(int phase)2208 ahc_lookup_phase_entry(int phase)
2209 {
2210 struct ahc_phase_table_entry *entry;
2211 struct ahc_phase_table_entry *last_entry;
2212
2213 /*
2214 * num_phases doesn't include the default entry which
2215 * will be returned if the phase doesn't match.
2216 */
2217 last_entry = &ahc_phase_table[num_phases];
2218 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2219 if (phase == entry->phase)
2220 break;
2221 }
2222 return (entry);
2223 }
2224
2225 void
ahc_compile_devinfo(struct ahc_devinfo * devinfo,u_int our_id,u_int target,u_int lun,char channel,role_t role)2226 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2227 u_int lun, char channel, role_t role)
2228 {
2229 devinfo->our_scsiid = our_id;
2230 devinfo->target = target;
2231 devinfo->lun = lun;
2232 devinfo->target_offset = target;
2233 devinfo->channel = channel;
2234 devinfo->role = role;
2235 if (channel == 'B')
2236 devinfo->target_offset += 8;
2237 devinfo->target_mask = (0x01 << devinfo->target_offset);
2238 }
2239
2240 void
ahc_print_devinfo(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)2241 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2242 {
2243 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2244 devinfo->target, devinfo->lun);
2245 }
2246
2247 static void
ahc_scb_devinfo(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,struct scb * scb)2248 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2249 struct scb *scb)
2250 {
2251 role_t role;
2252 int our_id;
2253
2254 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2255 role = ROLE_INITIATOR;
2256 if ((scb->flags & SCB_TARGET_SCB) != 0)
2257 role = ROLE_TARGET;
2258 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2259 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2260 }
2261
2262 /************************ Message Phase Processing ****************************/
2263 static void
ahc_assert_atn(struct ahc_softc * ahc)2264 ahc_assert_atn(struct ahc_softc *ahc)
2265 {
2266 u_int scsisigo;
2267
2268 scsisigo = ATNO;
2269 if ((ahc->features & AHC_DT) == 0)
2270 scsisigo |= ahc_inb(ahc, SCSISIGI);
2271 ahc_outb(ahc, SCSISIGO, scsisigo);
2272 }
2273
2274 /*
2275 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2276 * or enters the initial message out phase, we are interrupted. Fill our
2277 * outgoing message buffer with the appropriate message and beging handing
2278 * the message phase(s) manually.
2279 */
2280 static void
ahc_setup_initiator_msgout(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,struct scb * scb)2281 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2282 struct scb *scb)
2283 {
2284 /*
2285 * To facilitate adding multiple messages together,
2286 * each routine should increment the index and len
2287 * variables instead of setting them explicitly.
2288 */
2289 ahc->msgout_index = 0;
2290 ahc->msgout_len = 0;
2291
2292 if ((scb->flags & SCB_DEVICE_RESET) == 0
2293 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2294 u_int identify_msg;
2295
2296 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2297 if ((scb->hscb->control & DISCENB) != 0)
2298 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2299 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2300 ahc->msgout_len++;
2301
2302 if ((scb->hscb->control & TAG_ENB) != 0) {
2303 ahc->msgout_buf[ahc->msgout_index++] =
2304 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2305 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2306 ahc->msgout_len += 2;
2307 }
2308 }
2309
2310 if (scb->flags & SCB_DEVICE_RESET) {
2311 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2312 ahc->msgout_len++;
2313 ahc_print_path(ahc, scb);
2314 printf("Bus Device Reset Message Sent\n");
2315 /*
2316 * Clear our selection hardware in advance of
2317 * the busfree. We may have an entry in the waiting
2318 * Q for this target, and we don't want to go about
2319 * selecting while we handle the busfree and blow it
2320 * away.
2321 */
2322 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2323 } else if ((scb->flags & SCB_ABORT) != 0) {
2324 if ((scb->hscb->control & TAG_ENB) != 0)
2325 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2326 else
2327 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2328 ahc->msgout_len++;
2329 ahc_print_path(ahc, scb);
2330 printf("Abort%s Message Sent\n",
2331 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2332 /*
2333 * Clear our selection hardware in advance of
2334 * the busfree. We may have an entry in the waiting
2335 * Q for this target, and we don't want to go about
2336 * selecting while we handle the busfree and blow it
2337 * away.
2338 */
2339 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2340 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2341 ahc_build_transfer_msg(ahc, devinfo);
2342 } else {
2343 printf("ahc_intr: AWAITING_MSG for an SCB that "
2344 "does not have a waiting message\n");
2345 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2346 devinfo->target_mask);
2347 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2348 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2349 ahc_inb(ahc, MSG_OUT), scb->flags);
2350 }
2351
2352 /*
2353 * Clear the MK_MESSAGE flag from the SCB so we aren't
2354 * asked to send this message again.
2355 */
2356 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2357 scb->hscb->control &= ~MK_MESSAGE;
2358 ahc->msgout_index = 0;
2359 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2360 }
2361
2362 /*
2363 * Build an appropriate transfer negotiation message for the
2364 * currently active target.
2365 */
2366 static void
ahc_build_transfer_msg(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)2367 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2368 {
2369 /*
2370 * We need to initiate transfer negotiations.
2371 * If our current and goal settings are identical,
2372 * we want to renegotiate due to a check condition.
2373 */
2374 struct ahc_initiator_tinfo *tinfo;
2375 struct ahc_tmode_tstate *tstate;
2376 struct ahc_syncrate *rate;
2377 int dowide;
2378 int dosync;
2379 int doppr;
2380 u_int period;
2381 u_int ppr_options;
2382 u_int offset;
2383
2384 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2385 devinfo->target, &tstate);
2386 /*
2387 * Filter our period based on the current connection.
2388 * If we can't perform DT transfers on this segment (not in LVD
2389 * mode for instance), then our decision to issue a PPR message
2390 * may change.
2391 */
2392 period = tinfo->goal.period;
2393 offset = tinfo->goal.offset;
2394 ppr_options = tinfo->goal.ppr_options;
2395 /* Target initiated PPR is not allowed in the SCSI spec */
2396 if (devinfo->role == ROLE_TARGET)
2397 ppr_options = 0;
2398 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2399 &ppr_options, devinfo->role);
2400 dowide = tinfo->curr.width != tinfo->goal.width;
2401 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2402 /*
2403 * Only use PPR if we have options that need it, even if the device
2404 * claims to support it. There might be an expander in the way
2405 * that doesn't.
2406 */
2407 doppr = ppr_options != 0;
2408
2409 if (!dowide && !dosync && !doppr) {
2410 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2411 dosync = tinfo->goal.offset != 0;
2412 }
2413
2414 if (!dowide && !dosync && !doppr) {
2415 /*
2416 * Force async with a WDTR message if we have a wide bus,
2417 * or just issue an SDTR with a 0 offset.
2418 */
2419 if ((ahc->features & AHC_WIDE) != 0)
2420 dowide = 1;
2421 else
2422 dosync = 1;
2423
2424 if (bootverbose) {
2425 ahc_print_devinfo(ahc, devinfo);
2426 printf("Ensuring async\n");
2427 }
2428 }
2429
2430 /* Target initiated PPR is not allowed in the SCSI spec */
2431 if (devinfo->role == ROLE_TARGET)
2432 doppr = 0;
2433
2434 /*
2435 * Both the PPR message and SDTR message require the
2436 * goal syncrate to be limited to what the target device
2437 * is capable of handling (based on whether an LVD->SE
2438 * expander is on the bus), so combine these two cases.
2439 * Regardless, guarantee that if we are using WDTR and SDTR
2440 * messages that WDTR comes first.
2441 */
2442 if (doppr || (dosync && !dowide)) {
2443 offset = tinfo->goal.offset;
2444 ahc_validate_offset(ahc, tinfo, rate, &offset,
2445 doppr ? tinfo->goal.width
2446 : tinfo->curr.width,
2447 devinfo->role);
2448 if (doppr) {
2449 ahc_construct_ppr(ahc, devinfo, period, offset,
2450 tinfo->goal.width, ppr_options);
2451 } else {
2452 ahc_construct_sdtr(ahc, devinfo, period, offset);
2453 }
2454 } else {
2455 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2456 }
2457 }
2458
2459 /*
2460 * Build a synchronous negotiation message in our message
2461 * buffer based on the input parameters.
2462 */
2463 static void
ahc_construct_sdtr(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,u_int period,u_int offset)2464 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2465 u_int period, u_int offset)
2466 {
2467 if (offset == 0)
2468 period = AHC_ASYNC_XFER_PERIOD;
2469 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2470 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2471 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2472 ahc->msgout_buf[ahc->msgout_index++] = period;
2473 ahc->msgout_buf[ahc->msgout_index++] = offset;
2474 ahc->msgout_len += 5;
2475 if (bootverbose) {
2476 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2477 ahc_name(ahc), devinfo->channel, devinfo->target,
2478 devinfo->lun, period, offset);
2479 }
2480 }
2481
2482 /*
2483 * Build a wide negotiation message in our message
2484 * buffer based on the input parameters.
2485 */
2486 static void
ahc_construct_wdtr(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,u_int bus_width)2487 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2488 u_int bus_width)
2489 {
2490 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2491 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2492 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2493 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2494 ahc->msgout_len += 4;
2495 if (bootverbose) {
2496 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2497 ahc_name(ahc), devinfo->channel, devinfo->target,
2498 devinfo->lun, bus_width);
2499 }
2500 }
2501
2502 /*
2503 * Build a parallel protocol request message in our message
2504 * buffer based on the input parameters.
2505 */
2506 static void
ahc_construct_ppr(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,u_int period,u_int offset,u_int bus_width,u_int ppr_options)2507 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2508 u_int period, u_int offset, u_int bus_width,
2509 u_int ppr_options)
2510 {
2511 if (offset == 0)
2512 period = AHC_ASYNC_XFER_PERIOD;
2513 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2514 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2515 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2516 ahc->msgout_buf[ahc->msgout_index++] = period;
2517 ahc->msgout_buf[ahc->msgout_index++] = 0;
2518 ahc->msgout_buf[ahc->msgout_index++] = offset;
2519 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2520 ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2521 ahc->msgout_len += 8;
2522 if (bootverbose) {
2523 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2524 "offset %x, ppr_options %x\n", ahc_name(ahc),
2525 devinfo->channel, devinfo->target, devinfo->lun,
2526 bus_width, period, offset, ppr_options);
2527 }
2528 }
2529
2530 /*
2531 * Clear any active message state.
2532 */
2533 static void
ahc_clear_msg_state(struct ahc_softc * ahc)2534 ahc_clear_msg_state(struct ahc_softc *ahc)
2535 {
2536 ahc->msgout_len = 0;
2537 ahc->msgin_index = 0;
2538 ahc->msg_type = MSG_TYPE_NONE;
2539 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2540 /*
2541 * The target didn't care to respond to our
2542 * message request, so clear ATN.
2543 */
2544 ahc_outb(ahc, CLRSINT1, CLRATNO);
2545 }
2546 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2547 ahc_outb(ahc, SEQ_FLAGS2,
2548 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2549 }
2550
2551 static void
ahc_handle_proto_violation(struct ahc_softc * ahc)2552 ahc_handle_proto_violation(struct ahc_softc *ahc)
2553 {
2554 struct ahc_devinfo devinfo;
2555 struct scb *scb;
2556 u_int scbid;
2557 u_int seq_flags;
2558 u_int curphase;
2559 u_int lastphase;
2560 int found;
2561
2562 ahc_fetch_devinfo(ahc, &devinfo);
2563 scbid = ahc_inb(ahc, SCB_TAG);
2564 scb = ahc_lookup_scb(ahc, scbid);
2565 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2566 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2567 lastphase = ahc_inb(ahc, LASTPHASE);
2568 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2569 /*
2570 * The reconnecting target either did not send an
2571 * identify message, or did, but we didn't find an SCB
2572 * to match.
2573 */
2574 ahc_print_devinfo(ahc, &devinfo);
2575 printf("Target did not send an IDENTIFY message. "
2576 "LASTPHASE = 0x%x.\n", lastphase);
2577 scb = NULL;
2578 } else if (scb == NULL) {
2579 /*
2580 * We don't seem to have an SCB active for this
2581 * transaction. Print an error and reset the bus.
2582 */
2583 ahc_print_devinfo(ahc, &devinfo);
2584 printf("No SCB found during protocol violation\n");
2585 goto proto_violation_reset;
2586 } else {
2587 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2588 if ((seq_flags & NO_CDB_SENT) != 0) {
2589 ahc_print_path(ahc, scb);
2590 printf("No or incomplete CDB sent to device.\n");
2591 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2592 /*
2593 * The target never bothered to provide status to
2594 * us prior to completing the command. Since we don't
2595 * know the disposition of this command, we must attempt
2596 * to abort it. Assert ATN and prepare to send an abort
2597 * message.
2598 */
2599 ahc_print_path(ahc, scb);
2600 printf("Completed command without status.\n");
2601 } else {
2602 ahc_print_path(ahc, scb);
2603 printf("Unknown protocol violation.\n");
2604 ahc_dump_card_state(ahc);
2605 }
2606 }
2607 if ((lastphase & ~P_DATAIN_DT) == 0
2608 || lastphase == P_COMMAND) {
2609 proto_violation_reset:
2610 /*
2611 * Target either went directly to data/command
2612 * phase or didn't respond to our ATN.
2613 * The only safe thing to do is to blow
2614 * it away with a bus reset.
2615 */
2616 found = ahc_reset_channel(ahc, 'A', TRUE);
2617 printf("%s: Issued Channel %c Bus Reset. "
2618 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2619 } else {
2620 /*
2621 * Leave the selection hardware off in case
2622 * this abort attempt will affect yet to
2623 * be sent commands.
2624 */
2625 ahc_outb(ahc, SCSISEQ,
2626 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2627 ahc_assert_atn(ahc);
2628 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2629 if (scb == NULL) {
2630 ahc_print_devinfo(ahc, &devinfo);
2631 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2632 ahc->msgout_len = 1;
2633 ahc->msgout_index = 0;
2634 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2635 } else {
2636 ahc_print_path(ahc, scb);
2637 scb->flags |= SCB_ABORT;
2638 }
2639 printf("Protocol violation %s. Attempting to abort.\n",
2640 ahc_lookup_phase_entry(curphase)->phasemsg);
2641 }
2642 }
2643
2644 /*
2645 * Manual message loop handler.
2646 */
2647 static void
ahc_handle_message_phase(struct ahc_softc * ahc)2648 ahc_handle_message_phase(struct ahc_softc *ahc)
2649 {
2650 struct ahc_devinfo devinfo;
2651 u_int bus_phase;
2652 int end_session;
2653
2654 ahc_fetch_devinfo(ahc, &devinfo);
2655 end_session = FALSE;
2656 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2657
2658 reswitch:
2659 switch (ahc->msg_type) {
2660 case MSG_TYPE_INITIATOR_MSGOUT:
2661 {
2662 int lastbyte;
2663 int phasemis;
2664 int msgdone;
2665
2666 if (ahc->msgout_len == 0)
2667 panic("HOST_MSG_LOOP interrupt with no active message");
2668
2669 #ifdef AHC_DEBUG
2670 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2671 ahc_print_devinfo(ahc, &devinfo);
2672 printf("INITIATOR_MSG_OUT");
2673 }
2674 #endif
2675 phasemis = bus_phase != P_MESGOUT;
2676 if (phasemis) {
2677 #ifdef AHC_DEBUG
2678 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2679 printf(" PHASEMIS %s\n",
2680 ahc_lookup_phase_entry(bus_phase)
2681 ->phasemsg);
2682 }
2683 #endif
2684 if (bus_phase == P_MESGIN) {
2685 /*
2686 * Change gears and see if
2687 * this messages is of interest to
2688 * us or should be passed back to
2689 * the sequencer.
2690 */
2691 ahc_outb(ahc, CLRSINT1, CLRATNO);
2692 ahc->send_msg_perror = FALSE;
2693 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2694 ahc->msgin_index = 0;
2695 goto reswitch;
2696 }
2697 end_session = TRUE;
2698 break;
2699 }
2700
2701 if (ahc->send_msg_perror) {
2702 ahc_outb(ahc, CLRSINT1, CLRATNO);
2703 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2704 #ifdef AHC_DEBUG
2705 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2706 printf(" byte 0x%x\n", ahc->send_msg_perror);
2707 #endif
2708 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2709 break;
2710 }
2711
2712 msgdone = ahc->msgout_index == ahc->msgout_len;
2713 if (msgdone) {
2714 /*
2715 * The target has requested a retry.
2716 * Re-assert ATN, reset our message index to
2717 * 0, and try again.
2718 */
2719 ahc->msgout_index = 0;
2720 ahc_assert_atn(ahc);
2721 }
2722
2723 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2724 if (lastbyte) {
2725 /* Last byte is signified by dropping ATN */
2726 ahc_outb(ahc, CLRSINT1, CLRATNO);
2727 }
2728
2729 /*
2730 * Clear our interrupt status and present
2731 * the next byte on the bus.
2732 */
2733 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2734 #ifdef AHC_DEBUG
2735 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2736 printf(" byte 0x%x\n",
2737 ahc->msgout_buf[ahc->msgout_index]);
2738 #endif
2739 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2740 break;
2741 }
2742 case MSG_TYPE_INITIATOR_MSGIN:
2743 {
2744 int phasemis;
2745 int message_done;
2746
2747 #ifdef AHC_DEBUG
2748 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2749 ahc_print_devinfo(ahc, &devinfo);
2750 printf("INITIATOR_MSG_IN");
2751 }
2752 #endif
2753 phasemis = bus_phase != P_MESGIN;
2754 if (phasemis) {
2755 #ifdef AHC_DEBUG
2756 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2757 printf(" PHASEMIS %s\n",
2758 ahc_lookup_phase_entry(bus_phase)
2759 ->phasemsg);
2760 }
2761 #endif
2762 ahc->msgin_index = 0;
2763 if (bus_phase == P_MESGOUT
2764 && (ahc->send_msg_perror == TRUE
2765 || (ahc->msgout_len != 0
2766 && ahc->msgout_index == 0))) {
2767 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2768 goto reswitch;
2769 }
2770 end_session = TRUE;
2771 break;
2772 }
2773
2774 /* Pull the byte in without acking it */
2775 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2776 #ifdef AHC_DEBUG
2777 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2778 printf(" byte 0x%x\n",
2779 ahc->msgin_buf[ahc->msgin_index]);
2780 #endif
2781
2782 message_done = ahc_parse_msg(ahc, &devinfo);
2783
2784 if (message_done) {
2785 /*
2786 * Clear our incoming message buffer in case there
2787 * is another message following this one.
2788 */
2789 ahc->msgin_index = 0;
2790
2791 /*
2792 * If this message illicited a response,
2793 * assert ATN so the target takes us to the
2794 * message out phase.
2795 */
2796 if (ahc->msgout_len != 0) {
2797 #ifdef AHC_DEBUG
2798 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2799 ahc_print_devinfo(ahc, &devinfo);
2800 printf("Asserting ATN for response\n");
2801 }
2802 #endif
2803 ahc_assert_atn(ahc);
2804 }
2805 } else
2806 ahc->msgin_index++;
2807
2808 if (message_done == MSGLOOP_TERMINATED) {
2809 end_session = TRUE;
2810 } else {
2811 /* Ack the byte */
2812 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2813 ahc_inb(ahc, SCSIDATL);
2814 }
2815 break;
2816 }
2817 case MSG_TYPE_TARGET_MSGIN:
2818 {
2819 int msgdone;
2820
2821 if (ahc->msgout_len == 0)
2822 panic("Target MSGIN with no active message");
2823
2824 #ifdef AHC_DEBUG
2825 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2826 ahc_print_devinfo(ahc, &devinfo);
2827 printf("TARGET_MSG_IN");
2828 }
2829 #endif
2830
2831 /*
2832 * If we interrupted a mesgout session, the initiator
2833 * will not know this until our first REQ. So, we
2834 * only honor mesgout requests after we've sent our
2835 * first byte.
2836 */
2837 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2838 && ahc->msgout_index > 0) {
2839 /*
2840 * Change gears and see if this messages is
2841 * of interest to us or should be passed back
2842 * to the sequencer.
2843 */
2844 #ifdef AHC_DEBUG
2845 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2846 printf(" Honoring ATN Request.\n");
2847 #endif
2848 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2849
2850 /*
2851 * Disable SCSI Programmed I/O during the
2852 * phase change so as to avoid phantom REQs.
2853 */
2854 ahc_outb(ahc, SXFRCTL0,
2855 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2856
2857 /*
2858 * Since SPIORDY asserts when ACK is asserted
2859 * for P_MSGOUT, and SPIORDY's assertion triggered
2860 * our entry into this routine, wait for ACK to
2861 * *de-assert* before changing phases.
2862 */
2863 while ((ahc_inb(ahc, SCSISIGI) & ACKI) != 0)
2864 ;
2865
2866 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2867
2868 /*
2869 * All phase line changes require a bus
2870 * settle delay before REQ is asserted.
2871 * [SCSI SPI4 10.7.1]
2872 */
2873 ahc_flush_device_writes(ahc);
2874 aic_delay(AHC_BUSSETTLE_DELAY);
2875
2876 ahc->msgin_index = 0;
2877 /* Enable SCSI Programmed I/O to REQ for first byte */
2878 ahc_outb(ahc, SXFRCTL0,
2879 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2880 break;
2881 }
2882
2883 msgdone = ahc->msgout_index == ahc->msgout_len;
2884 if (msgdone) {
2885 ahc_outb(ahc, SXFRCTL0,
2886 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2887 end_session = TRUE;
2888 break;
2889 }
2890
2891 /*
2892 * Present the next byte on the bus.
2893 */
2894 #ifdef AHC_DEBUG
2895 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2896 printf(" byte 0x%x\n",
2897 ahc->msgout_buf[ahc->msgout_index]);
2898 #endif
2899 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2900 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2901 break;
2902 }
2903 case MSG_TYPE_TARGET_MSGOUT:
2904 {
2905 int lastbyte;
2906 int msgdone;
2907
2908 #ifdef AHC_DEBUG
2909 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2910 ahc_print_devinfo(ahc, &devinfo);
2911 printf("TARGET_MSG_OUT");
2912 }
2913 #endif
2914 /*
2915 * The initiator signals that this is
2916 * the last byte by dropping ATN.
2917 */
2918 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2919
2920 /*
2921 * Read the latched byte, but turn off SPIOEN first
2922 * so that we don't inadvertently cause a REQ for the
2923 * next byte.
2924 */
2925 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2926 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2927
2928 #ifdef AHC_DEBUG
2929 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2930 printf(" byte 0x%x\n",
2931 ahc->msgin_buf[ahc->msgin_index]);
2932 #endif
2933
2934 msgdone = ahc_parse_msg(ahc, &devinfo);
2935 if (msgdone == MSGLOOP_TERMINATED) {
2936 /*
2937 * The message is *really* done in that it caused
2938 * us to go to bus free. The sequencer has already
2939 * been reset at this point, so pull the ejection
2940 * handle.
2941 */
2942 return;
2943 }
2944
2945 ahc->msgin_index++;
2946
2947 /*
2948 * XXX Read spec about initiator dropping ATN too soon
2949 * and use msgdone to detect it.
2950 */
2951 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2952 ahc->msgin_index = 0;
2953
2954 /*
2955 * If this message illicited a response, transition
2956 * to the Message in phase and send it.
2957 */
2958 if (ahc->msgout_len != 0) {
2959 #ifdef AHC_DEBUG
2960 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2961 ahc_print_devinfo(ahc, &devinfo);
2962 printf(" preparing response.\n");
2963 }
2964 #endif
2965 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2966
2967 /*
2968 * All phase line changes require a bus
2969 * settle delay before REQ is asserted.
2970 * [SCSI SPI4 10.7.1] When transitioning
2971 * from an OUT to an IN phase, we must
2972 * also wait a data release delay to allow
2973 * the initiator time to release the data
2974 * lines. [SCSI SPI4 10.12]
2975 */
2976 ahc_flush_device_writes(ahc);
2977 aic_delay(AHC_BUSSETTLE_DELAY
2978 + AHC_DATARELEASE_DELAY);
2979
2980 /*
2981 * Enable SCSI Programmed I/O. This will
2982 * immediately cause SPIORDY to assert,
2983 * and the sequencer will call our message
2984 * loop again.
2985 */
2986 ahc_outb(ahc, SXFRCTL0,
2987 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2988 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2989 ahc->msgin_index = 0;
2990 break;
2991 }
2992 }
2993
2994 if (lastbyte)
2995 end_session = TRUE;
2996 else {
2997 /* Ask for the next byte. */
2998 ahc_outb(ahc, SXFRCTL0,
2999 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3000 }
3001
3002 break;
3003 }
3004 default:
3005 panic("Unknown REQINIT message type");
3006 }
3007
3008 if (end_session) {
3009 ahc_clear_msg_state(ahc);
3010 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3011 } else
3012 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3013 }
3014
3015 /*
3016 * See if we sent a particular extended message to the target.
3017 * If "full" is true, return true only if the target saw the full
3018 * message. If "full" is false, return true if the target saw at
3019 * least the first byte of the message.
3020 */
3021 static int
ahc_sent_msg(struct ahc_softc * ahc,ahc_msgtype type,u_int msgval,int full)3022 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3023 {
3024 int found;
3025 u_int index;
3026
3027 found = FALSE;
3028 index = 0;
3029
3030 while (index < ahc->msgout_len) {
3031 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3032 u_int end_index;
3033
3034 end_index = index + 1 + ahc->msgout_buf[index + 1];
3035 if (ahc->msgout_buf[index+2] == msgval
3036 && type == AHCMSG_EXT) {
3037 if (full) {
3038 if (ahc->msgout_index > end_index)
3039 found = TRUE;
3040 } else if (ahc->msgout_index > index)
3041 found = TRUE;
3042 }
3043 index = end_index;
3044 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3045 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3046 /* Skip tag type and tag id or residue param*/
3047 index += 2;
3048 } else {
3049 /* Single byte message */
3050 if (type == AHCMSG_1B
3051 && ahc->msgout_buf[index] == msgval
3052 && ahc->msgout_index > index)
3053 found = TRUE;
3054 index++;
3055 }
3056
3057 if (found)
3058 break;
3059 }
3060 return (found);
3061 }
3062
3063 /*
3064 * Wait for a complete incoming message, parse it, and respond accordingly.
3065 */
3066 static int
ahc_parse_msg(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)3067 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3068 {
3069 struct ahc_initiator_tinfo *tinfo;
3070 struct ahc_tmode_tstate *tstate;
3071 int reject;
3072 int done;
3073 int response;
3074 u_int targ_scsirate;
3075
3076 done = MSGLOOP_IN_PROG;
3077 response = FALSE;
3078 reject = FALSE;
3079 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3080 devinfo->target, &tstate);
3081 targ_scsirate = tinfo->scsirate;
3082
3083 /*
3084 * Parse as much of the message as is available,
3085 * rejecting it if we don't support it. When
3086 * the entire message is available and has been
3087 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3088 * that we have parsed an entire message.
3089 *
3090 * In the case of extended messages, we accept the length
3091 * byte outright and perform more checking once we know the
3092 * extended message type.
3093 */
3094 switch (ahc->msgin_buf[0]) {
3095 case MSG_DISCONNECT:
3096 case MSG_SAVEDATAPOINTER:
3097 case MSG_CMDCOMPLETE:
3098 case MSG_RESTOREPOINTERS:
3099 case MSG_IGN_WIDE_RESIDUE:
3100 /*
3101 * End our message loop as these are messages
3102 * the sequencer handles on its own.
3103 */
3104 done = MSGLOOP_TERMINATED;
3105 break;
3106 case MSG_MESSAGE_REJECT:
3107 response = ahc_handle_msg_reject(ahc, devinfo);
3108 /* FALLTHROUGH */
3109 case MSG_NOOP:
3110 done = MSGLOOP_MSGCOMPLETE;
3111 break;
3112 case MSG_EXTENDED:
3113 {
3114 /* Wait for enough of the message to begin validation */
3115 if (ahc->msgin_index < 2)
3116 break;
3117 switch (ahc->msgin_buf[2]) {
3118 case MSG_EXT_SDTR:
3119 {
3120 struct ahc_syncrate *syncrate;
3121 u_int period;
3122 u_int ppr_options;
3123 u_int offset;
3124 u_int saved_offset;
3125
3126 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3127 reject = TRUE;
3128 break;
3129 }
3130
3131 /*
3132 * Wait until we have both args before validating
3133 * and acting on this message.
3134 *
3135 * Add one to MSG_EXT_SDTR_LEN to account for
3136 * the extended message preamble.
3137 */
3138 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3139 break;
3140
3141 period = ahc->msgin_buf[3];
3142 ppr_options = 0;
3143 saved_offset = offset = ahc->msgin_buf[4];
3144 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3145 &ppr_options,
3146 devinfo->role);
3147 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3148 targ_scsirate & WIDEXFER,
3149 devinfo->role);
3150 if (bootverbose) {
3151 printf("(%s:%c:%d:%d): Received "
3152 "SDTR period %x, offset %x\n\t"
3153 "Filtered to period %x, offset %x\n",
3154 ahc_name(ahc), devinfo->channel,
3155 devinfo->target, devinfo->lun,
3156 ahc->msgin_buf[3], saved_offset,
3157 period, offset);
3158 }
3159 ahc_set_syncrate(ahc, devinfo,
3160 syncrate, period,
3161 offset, ppr_options,
3162 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3163 /*paused*/TRUE);
3164
3165 /*
3166 * See if we initiated Sync Negotiation
3167 * and didn't have to fall down to async
3168 * transfers.
3169 */
3170 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3171 /* We started it */
3172 if (saved_offset != offset) {
3173 /* Went too low - force async */
3174 reject = TRUE;
3175 }
3176 } else {
3177 /*
3178 * Send our own SDTR in reply
3179 */
3180 if (bootverbose
3181 && devinfo->role == ROLE_INITIATOR) {
3182 printf("(%s:%c:%d:%d): Target "
3183 "Initiated SDTR\n",
3184 ahc_name(ahc), devinfo->channel,
3185 devinfo->target, devinfo->lun);
3186 }
3187 ahc->msgout_index = 0;
3188 ahc->msgout_len = 0;
3189 ahc_construct_sdtr(ahc, devinfo,
3190 period, offset);
3191 ahc->msgout_index = 0;
3192 response = TRUE;
3193 }
3194 done = MSGLOOP_MSGCOMPLETE;
3195 break;
3196 }
3197 case MSG_EXT_WDTR:
3198 {
3199 u_int bus_width;
3200 u_int saved_width;
3201 u_int sending_reply;
3202
3203 sending_reply = FALSE;
3204 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3205 reject = TRUE;
3206 break;
3207 }
3208
3209 /*
3210 * Wait until we have our arg before validating
3211 * and acting on this message.
3212 *
3213 * Add one to MSG_EXT_WDTR_LEN to account for
3214 * the extended message preamble.
3215 */
3216 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3217 break;
3218
3219 bus_width = ahc->msgin_buf[3];
3220 saved_width = bus_width;
3221 ahc_validate_width(ahc, tinfo, &bus_width,
3222 devinfo->role);
3223 if (bootverbose) {
3224 printf("(%s:%c:%d:%d): Received WDTR "
3225 "%x filtered to %x\n",
3226 ahc_name(ahc), devinfo->channel,
3227 devinfo->target, devinfo->lun,
3228 saved_width, bus_width);
3229 }
3230
3231 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3232 /*
3233 * Don't send a WDTR back to the
3234 * target, since we asked first.
3235 * If the width went higher than our
3236 * request, reject it.
3237 */
3238 if (saved_width > bus_width) {
3239 reject = TRUE;
3240 printf("(%s:%c:%d:%d): requested %dBit "
3241 "transfers. Rejecting...\n",
3242 ahc_name(ahc), devinfo->channel,
3243 devinfo->target, devinfo->lun,
3244 8 * (0x01 << bus_width));
3245 bus_width = 0;
3246 }
3247 } else {
3248 /*
3249 * Send our own WDTR in reply
3250 */
3251 if (bootverbose
3252 && devinfo->role == ROLE_INITIATOR) {
3253 printf("(%s:%c:%d:%d): Target "
3254 "Initiated WDTR\n",
3255 ahc_name(ahc), devinfo->channel,
3256 devinfo->target, devinfo->lun);
3257 }
3258 ahc->msgout_index = 0;
3259 ahc->msgout_len = 0;
3260 ahc_construct_wdtr(ahc, devinfo, bus_width);
3261 ahc->msgout_index = 0;
3262 response = TRUE;
3263 sending_reply = TRUE;
3264 }
3265 /*
3266 * After a wide message, we are async, but
3267 * some devices don't seem to honor this portion
3268 * of the spec. Force a renegotiation of the
3269 * sync component of our transfer agreement even
3270 * if our goal is async. By updating our width
3271 * after forcing the negotiation, we avoid
3272 * renegotiating for width.
3273 */
3274 ahc_update_neg_request(ahc, devinfo, tstate,
3275 tinfo, AHC_NEG_ALWAYS);
3276 ahc_set_width(ahc, devinfo, bus_width,
3277 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3278 /*paused*/TRUE);
3279 if (sending_reply == FALSE && reject == FALSE) {
3280 /*
3281 * We will always have an SDTR to send.
3282 */
3283 ahc->msgout_index = 0;
3284 ahc->msgout_len = 0;
3285 ahc_build_transfer_msg(ahc, devinfo);
3286 ahc->msgout_index = 0;
3287 response = TRUE;
3288 }
3289 done = MSGLOOP_MSGCOMPLETE;
3290 break;
3291 }
3292 case MSG_EXT_PPR:
3293 {
3294 struct ahc_syncrate *syncrate;
3295 u_int period;
3296 u_int offset;
3297 u_int bus_width;
3298 u_int ppr_options;
3299 u_int saved_width;
3300 u_int saved_offset;
3301 u_int saved_ppr_options;
3302
3303 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3304 reject = TRUE;
3305 break;
3306 }
3307
3308 /*
3309 * Wait until we have all args before validating
3310 * and acting on this message.
3311 *
3312 * Add one to MSG_EXT_PPR_LEN to account for
3313 * the extended message preamble.
3314 */
3315 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3316 break;
3317
3318 period = ahc->msgin_buf[3];
3319 offset = ahc->msgin_buf[5];
3320 bus_width = ahc->msgin_buf[6];
3321 saved_width = bus_width;
3322 ppr_options = ahc->msgin_buf[7];
3323 /*
3324 * According to the spec, a DT only
3325 * period factor with no DT option
3326 * set implies async.
3327 */
3328 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3329 && period == 9)
3330 offset = 0;
3331 saved_ppr_options = ppr_options;
3332 saved_offset = offset;
3333
3334 /*
3335 * Mask out any options we don't support
3336 * on any controller. Transfer options are
3337 * only available if we are negotiating wide.
3338 */
3339 ppr_options &= MSG_EXT_PPR_DT_REQ;
3340 if (bus_width == 0)
3341 ppr_options = 0;
3342
3343 ahc_validate_width(ahc, tinfo, &bus_width,
3344 devinfo->role);
3345 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3346 &ppr_options,
3347 devinfo->role);
3348 ahc_validate_offset(ahc, tinfo, syncrate,
3349 &offset, bus_width,
3350 devinfo->role);
3351
3352 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3353 /*
3354 * If we are unable to do any of the
3355 * requested options (we went too low),
3356 * then we'll have to reject the message.
3357 */
3358 if (saved_width > bus_width
3359 || saved_offset != offset
3360 || saved_ppr_options != ppr_options) {
3361 reject = TRUE;
3362 period = 0;
3363 offset = 0;
3364 bus_width = 0;
3365 ppr_options = 0;
3366 syncrate = NULL;
3367 }
3368 } else {
3369 if (devinfo->role != ROLE_TARGET)
3370 printf("(%s:%c:%d:%d): Target "
3371 "Initiated PPR\n",
3372 ahc_name(ahc), devinfo->channel,
3373 devinfo->target, devinfo->lun);
3374 else
3375 printf("(%s:%c:%d:%d): Initiator "
3376 "Initiated PPR\n",
3377 ahc_name(ahc), devinfo->channel,
3378 devinfo->target, devinfo->lun);
3379 ahc->msgout_index = 0;
3380 ahc->msgout_len = 0;
3381 ahc_construct_ppr(ahc, devinfo, period, offset,
3382 bus_width, ppr_options);
3383 ahc->msgout_index = 0;
3384 response = TRUE;
3385 }
3386 if (bootverbose) {
3387 printf("(%s:%c:%d:%d): Received PPR width %x, "
3388 "period %x, offset %x,options %x\n"
3389 "\tFiltered to width %x, period %x, "
3390 "offset %x, options %x\n",
3391 ahc_name(ahc), devinfo->channel,
3392 devinfo->target, devinfo->lun,
3393 saved_width, ahc->msgin_buf[3],
3394 saved_offset, saved_ppr_options,
3395 bus_width, period, offset, ppr_options);
3396 }
3397 ahc_set_width(ahc, devinfo, bus_width,
3398 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3399 /*paused*/TRUE);
3400 ahc_set_syncrate(ahc, devinfo,
3401 syncrate, period,
3402 offset, ppr_options,
3403 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3404 /*paused*/TRUE);
3405 done = MSGLOOP_MSGCOMPLETE;
3406 break;
3407 }
3408 default:
3409 /* Unknown extended message. Reject it. */
3410 reject = TRUE;
3411 break;
3412 }
3413 break;
3414 }
3415 #ifdef AHC_TARGET_MODE
3416 case MSG_BUS_DEV_RESET:
3417 ahc_handle_devreset(ahc, devinfo,
3418 CAM_BDR_SENT,
3419 "Bus Device Reset Received",
3420 /*verbose_level*/0);
3421 ahc_restart(ahc);
3422 done = MSGLOOP_TERMINATED;
3423 break;
3424 case MSG_ABORT_TAG:
3425 case MSG_ABORT:
3426 case MSG_CLEAR_QUEUE:
3427 {
3428 int tag;
3429
3430 /* Target mode messages */
3431 if (devinfo->role != ROLE_TARGET) {
3432 reject = TRUE;
3433 break;
3434 }
3435 tag = SCB_LIST_NULL;
3436 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3437 tag = ahc_inb(ahc, INITIATOR_TAG);
3438 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3439 devinfo->lun, tag, ROLE_TARGET,
3440 CAM_REQ_ABORTED);
3441
3442 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3443 if (tstate != NULL) {
3444 struct ahc_tmode_lstate* lstate;
3445
3446 lstate = tstate->enabled_luns[devinfo->lun];
3447 if (lstate != NULL) {
3448 ahc_queue_lstate_event(ahc, lstate,
3449 devinfo->our_scsiid,
3450 ahc->msgin_buf[0],
3451 /*arg*/tag);
3452 ahc_send_lstate_events(ahc, lstate);
3453 }
3454 }
3455 ahc_restart(ahc);
3456 done = MSGLOOP_TERMINATED;
3457 break;
3458 }
3459 #endif
3460 case MSG_TERM_IO_PROC:
3461 default:
3462 reject = TRUE;
3463 break;
3464 }
3465
3466 if (reject) {
3467 /*
3468 * Setup to reject the message.
3469 */
3470 ahc->msgout_index = 0;
3471 ahc->msgout_len = 1;
3472 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3473 done = MSGLOOP_MSGCOMPLETE;
3474 response = TRUE;
3475 }
3476
3477 if (done != MSGLOOP_IN_PROG && !response)
3478 /* Clear the outgoing message buffer */
3479 ahc->msgout_len = 0;
3480
3481 return (done);
3482 }
3483
3484 /*
3485 * Process a message reject message.
3486 */
3487 static int
ahc_handle_msg_reject(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)3488 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3489 {
3490 /*
3491 * What we care about here is if we had an
3492 * outstanding SDTR or WDTR message for this
3493 * target. If we did, this is a signal that
3494 * the target is refusing negotiation.
3495 */
3496 struct scb *scb;
3497 struct ahc_initiator_tinfo *tinfo;
3498 struct ahc_tmode_tstate *tstate;
3499 u_int scb_index;
3500 u_int last_msg;
3501 int response = 0;
3502
3503 scb_index = ahc_inb(ahc, SCB_TAG);
3504 scb = ahc_lookup_scb(ahc, scb_index);
3505 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3506 devinfo->our_scsiid,
3507 devinfo->target, &tstate);
3508 /* Might be necessary */
3509 last_msg = ahc_inb(ahc, LAST_MSG);
3510
3511 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3512 /*
3513 * Target does not support the PPR message.
3514 * Attempt to negotiate SPI-2 style.
3515 */
3516 if (bootverbose) {
3517 printf("(%s:%c:%d:%d): PPR Rejected. "
3518 "Trying WDTR/SDTR\n",
3519 ahc_name(ahc), devinfo->channel,
3520 devinfo->target, devinfo->lun);
3521 }
3522 tinfo->goal.ppr_options = 0;
3523 tinfo->curr.transport_version = 2;
3524 tinfo->goal.transport_version = 2;
3525 ahc->msgout_index = 0;
3526 ahc->msgout_len = 0;
3527 ahc_build_transfer_msg(ahc, devinfo);
3528 ahc->msgout_index = 0;
3529 response = 1;
3530 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3531 /* note 8bit xfers */
3532 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3533 "8bit transfers\n", ahc_name(ahc),
3534 devinfo->channel, devinfo->target, devinfo->lun);
3535 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3536 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3537 /*paused*/TRUE);
3538 /*
3539 * No need to clear the sync rate. If the target
3540 * did not accept the command, our syncrate is
3541 * unaffected. If the target started the negotiation,
3542 * but rejected our response, we already cleared the
3543 * sync rate before sending our WDTR.
3544 */
3545 if (tinfo->goal.offset != tinfo->curr.offset) {
3546 /* Start the sync negotiation */
3547 ahc->msgout_index = 0;
3548 ahc->msgout_len = 0;
3549 ahc_build_transfer_msg(ahc, devinfo);
3550 ahc->msgout_index = 0;
3551 response = 1;
3552 }
3553 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3554 /* note asynch xfers and clear flag */
3555 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3556 /*offset*/0, /*ppr_options*/0,
3557 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3558 /*paused*/TRUE);
3559 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3560 "Using asynchronous transfers\n",
3561 ahc_name(ahc), devinfo->channel,
3562 devinfo->target, devinfo->lun);
3563 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3564 int tag_type;
3565 int mask;
3566
3567 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3568
3569 if (tag_type == MSG_SIMPLE_TASK) {
3570 printf("(%s:%c:%d:%d): refuses tagged commands. "
3571 "Performing non-tagged I/O\n", ahc_name(ahc),
3572 devinfo->channel, devinfo->target, devinfo->lun);
3573 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3574 mask = ~0x23;
3575 } else {
3576 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3577 "Performing simple queue tagged I/O only\n",
3578 ahc_name(ahc), devinfo->channel, devinfo->target,
3579 devinfo->lun, tag_type == MSG_ORDERED_TASK
3580 ? "ordered" : "head of queue");
3581 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3582 mask = ~0x03;
3583 }
3584
3585 /*
3586 * Resend the identify for this CCB as the target
3587 * may believe that the selection is invalid otherwise.
3588 */
3589 ahc_outb(ahc, SCB_CONTROL,
3590 ahc_inb(ahc, SCB_CONTROL) & mask);
3591 scb->hscb->control &= mask;
3592 aic_set_transaction_tag(scb, /*enabled*/FALSE,
3593 /*type*/MSG_SIMPLE_TASK);
3594 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3595 ahc_assert_atn(ahc);
3596
3597 /*
3598 * This transaction is now at the head of
3599 * the untagged queue for this target.
3600 */
3601 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3602 struct scb_tailq *untagged_q;
3603
3604 untagged_q =
3605 &(ahc->untagged_queues[devinfo->target_offset]);
3606 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3607 scb->flags |= SCB_UNTAGGEDQ;
3608 }
3609 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3610 scb->hscb->tag);
3611
3612 /*
3613 * Requeue all tagged commands for this target
3614 * currently in our possession so they can be
3615 * converted to untagged commands.
3616 */
3617 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3618 SCB_GET_CHANNEL(ahc, scb),
3619 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3620 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3621 SEARCH_COMPLETE);
3622 } else {
3623 /*
3624 * Otherwise, we ignore it.
3625 */
3626 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3627 ahc_name(ahc), devinfo->channel, devinfo->target,
3628 last_msg);
3629 }
3630 return (response);
3631 }
3632
3633 /*
3634 * Process an ignore wide residue message.
3635 */
3636 static void
ahc_handle_ign_wide_residue(struct ahc_softc * ahc,struct ahc_devinfo * devinfo)3637 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3638 {
3639 u_int scb_index;
3640 struct scb *scb;
3641
3642 scb_index = ahc_inb(ahc, SCB_TAG);
3643 scb = ahc_lookup_scb(ahc, scb_index);
3644 /*
3645 * XXX Actually check data direction in the sequencer?
3646 * Perhaps add datadir to some spare bits in the hscb?
3647 */
3648 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3649 || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
3650 /*
3651 * Ignore the message if we haven't
3652 * seen an appropriate data phase yet.
3653 */
3654 } else {
3655 /*
3656 * If the residual occurred on the last
3657 * transfer and the transfer request was
3658 * expected to end on an odd count, do
3659 * nothing. Otherwise, subtract a byte
3660 * and update the residual count accordingly.
3661 */
3662 uint32_t sgptr;
3663
3664 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3665 if ((sgptr & SG_LIST_NULL) != 0
3666 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3667 /*
3668 * If the residual occurred on the last
3669 * transfer and the transfer request was
3670 * expected to end on an odd count, do
3671 * nothing.
3672 */
3673 } else {
3674 struct ahc_dma_seg *sg;
3675 uint32_t data_cnt;
3676 uint32_t sglen;
3677
3678 /* Pull in all of the sgptr */
3679 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3680 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3681
3682 if ((sgptr & SG_LIST_NULL) != 0) {
3683 /*
3684 * The residual data count is not updated
3685 * for the command run to completion case.
3686 * Explicitly zero the count.
3687 */
3688 data_cnt &= ~AHC_SG_LEN_MASK;
3689 }
3690
3691 data_cnt += 1;
3692 sgptr &= SG_PTR_MASK;
3693
3694 sg = ahc_sg_bus_to_virt(scb, sgptr);
3695
3696 /*
3697 * The residual sg ptr points to the next S/G
3698 * to load so we must go back one.
3699 */
3700 sg--;
3701 sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
3702 if (sg != scb->sg_list
3703 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3704 sg--;
3705 sglen = aic_le32toh(sg->len);
3706 /*
3707 * Preserve High Address and SG_LIST bits
3708 * while setting the count to 1.
3709 */
3710 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3711
3712 /*
3713 * Increment sg so it points to the
3714 * "next" sg.
3715 */
3716 sg++;
3717 sgptr = ahc_sg_virt_to_bus(scb, sg);
3718 }
3719 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3720 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3721 /*
3722 * Toggle the "oddness" of the transfer length
3723 * to handle this mid-transfer ignore wide
3724 * residue. This ensures that the oddness is
3725 * correct for subsequent data transfers.
3726 */
3727 ahc_outb(ahc, SCB_LUN,
3728 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3729 }
3730 }
3731 }
3732
3733 /*
3734 * Reinitialize the data pointers for the active transfer
3735 * based on its current residual.
3736 */
3737 static void
ahc_reinitialize_dataptrs(struct ahc_softc * ahc)3738 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3739 {
3740 struct scb *scb;
3741 struct ahc_dma_seg *sg;
3742 u_int scb_index;
3743 uint32_t sgptr;
3744 uint32_t resid;
3745 uint32_t dataptr;
3746
3747 scb_index = ahc_inb(ahc, SCB_TAG);
3748 scb = ahc_lookup_scb(ahc, scb_index);
3749 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3750 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3751 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3752 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3753
3754 sgptr &= SG_PTR_MASK;
3755 sg = ahc_sg_bus_to_virt(scb, sgptr);
3756
3757 /* The residual sg_ptr always points to the next sg */
3758 sg--;
3759
3760 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3761 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3762 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3763
3764 dataptr = aic_le32toh(sg->addr)
3765 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK)
3766 - resid;
3767 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3768 u_int dscommand1;
3769
3770 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3771 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3772 ahc_outb(ahc, HADDR,
3773 (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3774 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3775 }
3776 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3777 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3778 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3779 ahc_outb(ahc, HADDR, dataptr);
3780 ahc_outb(ahc, HCNT + 2, resid >> 16);
3781 ahc_outb(ahc, HCNT + 1, resid >> 8);
3782 ahc_outb(ahc, HCNT, resid);
3783 if ((ahc->features & AHC_ULTRA2) == 0) {
3784 ahc_outb(ahc, STCNT + 2, resid >> 16);
3785 ahc_outb(ahc, STCNT + 1, resid >> 8);
3786 ahc_outb(ahc, STCNT, resid);
3787 }
3788 }
3789
3790 /*
3791 * Handle the effects of issuing a bus device reset message.
3792 */
3793 static void
ahc_handle_devreset(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,cam_status status,char * message,int verbose_level)3794 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3795 cam_status status, char *message, int verbose_level)
3796 {
3797 #ifdef AHC_TARGET_MODE
3798 struct ahc_tmode_tstate* tstate;
3799 u_int lun;
3800 #endif
3801 int found;
3802
3803 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3804 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3805 status);
3806
3807 #ifdef AHC_TARGET_MODE
3808 /*
3809 * Send an immediate notify ccb to all target mord peripheral
3810 * drivers affected by this action.
3811 */
3812 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3813 if (tstate != NULL) {
3814 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3815 struct ahc_tmode_lstate* lstate;
3816
3817 lstate = tstate->enabled_luns[lun];
3818 if (lstate == NULL)
3819 continue;
3820
3821 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3822 MSG_BUS_DEV_RESET, /*arg*/0);
3823 ahc_send_lstate_events(ahc, lstate);
3824 }
3825 }
3826 #endif
3827
3828 /*
3829 * Go back to async/narrow transfers and renegotiate.
3830 */
3831 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3832 AHC_TRANS_CUR, /*paused*/TRUE);
3833 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3834 /*period*/0, /*offset*/0, /*ppr_options*/0,
3835 AHC_TRANS_CUR, /*paused*/TRUE);
3836
3837 if (status != CAM_SEL_TIMEOUT)
3838 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3839 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3840
3841 if (message != NULL
3842 && (verbose_level <= bootverbose))
3843 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3844 message, devinfo->channel, devinfo->target, found);
3845 }
3846
3847 #ifdef AHC_TARGET_MODE
3848 static void
ahc_setup_target_msgin(struct ahc_softc * ahc,struct ahc_devinfo * devinfo,struct scb * scb)3849 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3850 struct scb *scb)
3851 {
3852
3853 /*
3854 * To facilitate adding multiple messages together,
3855 * each routine should increment the index and len
3856 * variables instead of setting them explicitly.
3857 */
3858 ahc->msgout_index = 0;
3859 ahc->msgout_len = 0;
3860
3861 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3862 ahc_build_transfer_msg(ahc, devinfo);
3863 else
3864 panic("ahc_intr: AWAITING target message with no message");
3865
3866 ahc->msgout_index = 0;
3867 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3868 }
3869 #endif
3870 /**************************** Initialization **********************************/
3871 /*
3872 * Allocate a controller structure for a new device
3873 * and perform initial initializion.
3874 */
3875 struct ahc_softc *
ahc_alloc(void * platform_arg,char * name)3876 ahc_alloc(void *platform_arg, char *name)
3877 {
3878 struct ahc_softc *ahc;
3879 int i;
3880
3881 #ifndef __FreeBSD__
3882 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3883 if (!ahc) {
3884 printf("aic7xxx: cannot malloc softc!\n");
3885 free(name, M_DEVBUF);
3886 return NULL;
3887 }
3888 #else
3889 ahc = device_get_softc((device_t)platform_arg);
3890 #endif
3891 memset(ahc, 0, sizeof(*ahc));
3892 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3893 M_DEVBUF, M_NOWAIT);
3894 if (ahc->seep_config == NULL) {
3895 #ifndef __FreeBSD__
3896 free(ahc, M_DEVBUF);
3897 #endif
3898 free(name, M_DEVBUF);
3899 return (NULL);
3900 }
3901 LIST_INIT(&ahc->pending_scbs);
3902 LIST_INIT(&ahc->timedout_scbs);
3903 /* We don't know our unit number until the OSM sets it */
3904 ahc->name = name;
3905 ahc->unit = -1;
3906 ahc->description = NULL;
3907 ahc->channel = 'A';
3908 ahc->channel_b = 'B';
3909 ahc->chip = AHC_NONE;
3910 ahc->features = AHC_FENONE;
3911 ahc->bugs = AHC_BUGNONE;
3912 ahc->flags = AHC_FNONE;
3913 /*
3914 * Default to all error reporting enabled with the
3915 * sequencer operating at its fastest speed.
3916 * The bus attach code may modify this.
3917 */
3918 ahc->seqctl = FASTMODE;
3919
3920 for (i = 0; i < AHC_NUM_TARGETS; i++)
3921 TAILQ_INIT(&ahc->untagged_queues[i]);
3922 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3923 ahc_free(ahc);
3924 ahc = NULL;
3925 }
3926 ahc_lockinit(ahc);
3927 return (ahc);
3928 }
3929
3930 int
ahc_softc_init(struct ahc_softc * ahc)3931 ahc_softc_init(struct ahc_softc *ahc)
3932 {
3933
3934 /* The IRQMS bit is only valid on VL and EISA chips */
3935 if ((ahc->chip & AHC_PCI) == 0)
3936 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3937 else
3938 ahc->unpause = 0;
3939 ahc->pause = ahc->unpause | PAUSE;
3940 /* XXX The shared scb data stuff should be deprecated */
3941 if (ahc->scb_data == NULL) {
3942 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3943 M_DEVBUF, M_NOWAIT);
3944 if (ahc->scb_data == NULL)
3945 return (ENOMEM);
3946 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3947 }
3948
3949 return (0);
3950 }
3951
3952 void
ahc_softc_insert(struct ahc_softc * ahc)3953 ahc_softc_insert(struct ahc_softc *ahc)
3954 {
3955 struct ahc_softc *list_ahc;
3956
3957 #if AIC_PCI_CONFIG > 0
3958 /*
3959 * Second Function PCI devices need to inherit some
3960 * settings from function 0.
3961 */
3962 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3963 && (ahc->features & AHC_MULTI_FUNC) != 0) {
3964 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3965 aic_dev_softc_t list_pci;
3966 aic_dev_softc_t pci;
3967
3968 list_pci = list_ahc->dev_softc;
3969 pci = ahc->dev_softc;
3970 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
3971 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
3972 struct ahc_softc *master;
3973 struct ahc_softc *slave;
3974
3975 if (aic_get_pci_function(list_pci) == 0) {
3976 master = list_ahc;
3977 slave = ahc;
3978 } else {
3979 master = ahc;
3980 slave = list_ahc;
3981 }
3982 slave->flags &= ~AHC_BIOS_ENABLED;
3983 slave->flags |=
3984 master->flags & AHC_BIOS_ENABLED;
3985 slave->flags &= ~AHC_PRIMARY_CHANNEL;
3986 slave->flags |=
3987 master->flags & AHC_PRIMARY_CHANNEL;
3988 break;
3989 }
3990 }
3991 }
3992 #endif
3993
3994 /*
3995 * Insertion sort into our list of softcs.
3996 */
3997 list_ahc = TAILQ_FIRST(&ahc_tailq);
3998 while (list_ahc != NULL
3999 && ahc_softc_comp(ahc, list_ahc) <= 0)
4000 list_ahc = TAILQ_NEXT(list_ahc, links);
4001 if (list_ahc != NULL)
4002 TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
4003 else
4004 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
4005 ahc->init_level++;
4006 }
4007
4008 void
ahc_set_unit(struct ahc_softc * ahc,int unit)4009 ahc_set_unit(struct ahc_softc *ahc, int unit)
4010 {
4011 ahc->unit = unit;
4012 }
4013
4014 void
ahc_set_name(struct ahc_softc * ahc,char * name)4015 ahc_set_name(struct ahc_softc *ahc, char *name)
4016 {
4017 if (ahc->name != NULL)
4018 free(ahc->name, M_DEVBUF);
4019 ahc->name = name;
4020 }
4021
4022 void
ahc_free(struct ahc_softc * ahc)4023 ahc_free(struct ahc_softc *ahc)
4024 {
4025 int i;
4026
4027 ahc_terminate_recovery_thread(ahc);
4028 switch (ahc->init_level) {
4029 default:
4030 case 5:
4031 ahc_shutdown(ahc);
4032 /* FALLTHROUGH */
4033 case 4:
4034 aic_dmamap_unload(ahc, ahc->shared_data_dmat,
4035 ahc->shared_data_dmamap);
4036 /* FALLTHROUGH */
4037 case 3:
4038 aic_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
4039 ahc->shared_data_dmamap);
4040 /* FALLTHROUGH */
4041 case 2:
4042 aic_dma_tag_destroy(ahc, ahc->shared_data_dmat);
4043 case 1:
4044 #ifndef __linux__
4045 aic_dma_tag_destroy(ahc, ahc->buffer_dmat);
4046 #endif
4047 break;
4048 case 0:
4049 break;
4050 }
4051
4052 #ifndef __linux__
4053 aic_dma_tag_destroy(ahc, ahc->parent_dmat);
4054 #endif
4055 ahc_platform_free(ahc);
4056 ahc_fini_scbdata(ahc);
4057 for (i = 0; i < AHC_NUM_TARGETS; i++) {
4058 struct ahc_tmode_tstate *tstate;
4059
4060 tstate = ahc->enabled_targets[i];
4061 if (tstate != NULL) {
4062 #ifdef AHC_TARGET_MODE
4063 int j;
4064
4065 for (j = 0; j < AHC_NUM_LUNS; j++) {
4066 struct ahc_tmode_lstate *lstate;
4067
4068 lstate = tstate->enabled_luns[j];
4069 if (lstate != NULL) {
4070 xpt_free_path(lstate->path);
4071 free(lstate, M_DEVBUF);
4072 }
4073 }
4074 #endif
4075 free(tstate, M_DEVBUF);
4076 }
4077 }
4078 #ifdef AHC_TARGET_MODE
4079 if (ahc->black_hole != NULL) {
4080 xpt_free_path(ahc->black_hole->path);
4081 free(ahc->black_hole, M_DEVBUF);
4082 }
4083 #endif
4084 if (ahc->name != NULL)
4085 free(ahc->name, M_DEVBUF);
4086 if (ahc->seep_config != NULL)
4087 free(ahc->seep_config, M_DEVBUF);
4088 #ifndef __FreeBSD__
4089 free(ahc, M_DEVBUF);
4090 #endif
4091 return;
4092 }
4093
4094 void
ahc_shutdown(void * arg)4095 ahc_shutdown(void *arg)
4096 {
4097 struct ahc_softc *ahc;
4098 int i;
4099
4100 ahc = (struct ahc_softc *)arg;
4101
4102 /* This will reset most registers to 0, but not all */
4103 ahc_reset(ahc, /*reinit*/FALSE);
4104 ahc_outb(ahc, SCSISEQ, 0);
4105 ahc_outb(ahc, SXFRCTL0, 0);
4106 ahc_outb(ahc, DSPCISTATUS, 0);
4107
4108 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4109 ahc_outb(ahc, i, 0);
4110 }
4111
4112 /*
4113 * Reset the controller and record some information about it
4114 * that is only available just after a reset. If "reinit" is
4115 * non-zero, this reset occurred after initial configuration
4116 * and the caller requests that the chip be fully reinitialized
4117 * to a runable state. Chip interrupts are *not* enabled after
4118 * a reinitialization. The caller must enable interrupts via
4119 * ahc_intr_enable().
4120 */
4121 int
ahc_reset(struct ahc_softc * ahc,int reinit)4122 ahc_reset(struct ahc_softc *ahc, int reinit)
4123 {
4124 u_int sblkctl;
4125 u_int sxfrctl1_a, sxfrctl1_b;
4126 int error;
4127 int wait;
4128
4129 /*
4130 * Preserve the value of the SXFRCTL1 register for all channels.
4131 * It contains settings that affect termination and we don't want
4132 * to disturb the integrity of the bus.
4133 */
4134 ahc_pause(ahc);
4135 sxfrctl1_b = 0;
4136 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4137 u_int sblkctl;
4138
4139 /*
4140 * Save channel B's settings in case this chip
4141 * is setup for TWIN channel operation.
4142 */
4143 sblkctl = ahc_inb(ahc, SBLKCTL);
4144 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4145 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4146 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4147 }
4148 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4149
4150 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4151
4152 /*
4153 * Ensure that the reset has finished. We delay 1000us
4154 * prior to reading the register to make sure the chip
4155 * has sufficiently completed its reset to handle register
4156 * accesses.
4157 */
4158 wait = 1000;
4159 do {
4160 aic_delay(1000);
4161 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4162
4163 if (wait == 0) {
4164 printf("%s: WARNING - Failed chip reset! "
4165 "Trying to initialize anyway.\n", ahc_name(ahc));
4166 }
4167 ahc_outb(ahc, HCNTRL, ahc->pause);
4168
4169 /* Determine channel configuration */
4170 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4171 /* No Twin Channel PCI cards */
4172 if ((ahc->chip & AHC_PCI) != 0)
4173 sblkctl &= ~SELBUSB;
4174 switch (sblkctl) {
4175 case 0:
4176 /* Single Narrow Channel */
4177 break;
4178 case 2:
4179 /* Wide Channel */
4180 ahc->features |= AHC_WIDE;
4181 break;
4182 case 8:
4183 /* Twin Channel */
4184 ahc->features |= AHC_TWIN;
4185 break;
4186 default:
4187 printf(" Unsupported adapter type. Ignoring\n");
4188 return(-1);
4189 }
4190
4191 /*
4192 * Reload sxfrctl1.
4193 *
4194 * We must always initialize STPWEN to 1 before we
4195 * restore the saved values. STPWEN is initialized
4196 * to a tri-state condition which can only be cleared
4197 * by turning it on.
4198 */
4199 if ((ahc->features & AHC_TWIN) != 0) {
4200 u_int sblkctl;
4201
4202 sblkctl = ahc_inb(ahc, SBLKCTL);
4203 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4204 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4205 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4206 }
4207 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4208
4209 error = 0;
4210 if (reinit != 0)
4211 /*
4212 * If a recovery action has forced a chip reset,
4213 * re-initialize the chip to our liking.
4214 */
4215 error = ahc->bus_chip_init(ahc);
4216 #ifdef AHC_DUMP_SEQ
4217 else
4218 ahc_dumpseq(ahc);
4219 #endif
4220
4221 return (error);
4222 }
4223
4224 /*
4225 * Determine the number of SCBs available on the controller
4226 */
4227 int
ahc_probe_scbs(struct ahc_softc * ahc)4228 ahc_probe_scbs(struct ahc_softc *ahc) {
4229 int i;
4230
4231 for (i = 0; i < AHC_SCB_MAX; i++) {
4232 ahc_outb(ahc, SCBPTR, i);
4233 ahc_outb(ahc, SCB_BASE, i);
4234 if (ahc_inb(ahc, SCB_BASE) != i)
4235 break;
4236 ahc_outb(ahc, SCBPTR, 0);
4237 if (ahc_inb(ahc, SCB_BASE) != 0)
4238 break;
4239 }
4240 return (i);
4241 }
4242
4243 static void
ahc_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)4244 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4245 {
4246 bus_addr_t *baddr;
4247
4248 baddr = (bus_addr_t *)arg;
4249 *baddr = segs->ds_addr;
4250 }
4251
4252 static void
ahc_build_free_scb_list(struct ahc_softc * ahc)4253 ahc_build_free_scb_list(struct ahc_softc *ahc)
4254 {
4255 int scbsize;
4256 int i;
4257
4258 scbsize = 32;
4259 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4260 scbsize = 64;
4261
4262 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4263 int j;
4264
4265 ahc_outb(ahc, SCBPTR, i);
4266
4267 /*
4268 * Touch all SCB bytes to avoid parity errors
4269 * should one of our debugging routines read
4270 * an otherwise uninitiatlized byte.
4271 */
4272 for (j = 0; j < scbsize; j++)
4273 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4274
4275 /* Clear the control byte. */
4276 ahc_outb(ahc, SCB_CONTROL, 0);
4277
4278 /* Set the next pointer */
4279 if ((ahc->flags & AHC_PAGESCBS) != 0)
4280 ahc_outb(ahc, SCB_NEXT, i+1);
4281 else
4282 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4283
4284 /* Make the tag number, SCSIID, and lun invalid */
4285 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4286 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4287 ahc_outb(ahc, SCB_LUN, 0xFF);
4288 }
4289
4290 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4291 /* SCB 0 heads the free list. */
4292 ahc_outb(ahc, FREE_SCBH, 0);
4293 } else {
4294 /* No free list. */
4295 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4296 }
4297
4298 /* Make sure that the last SCB terminates the free list */
4299 ahc_outb(ahc, SCBPTR, i-1);
4300 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4301 }
4302
4303 static int
ahc_init_scbdata(struct ahc_softc * ahc)4304 ahc_init_scbdata(struct ahc_softc *ahc)
4305 {
4306 struct scb_data *scb_data;
4307
4308 scb_data = ahc->scb_data;
4309 SLIST_INIT(&scb_data->free_scbs);
4310 SLIST_INIT(&scb_data->sg_maps);
4311
4312 /* Allocate SCB resources */
4313 scb_data->scbarray =
4314 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4315 M_DEVBUF, M_NOWAIT);
4316 if (scb_data->scbarray == NULL)
4317 return (ENOMEM);
4318 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4319
4320 /* Determine the number of hardware SCBs and initialize them */
4321
4322 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4323 if (ahc->scb_data->maxhscbs == 0) {
4324 printf("%s: No SCB space found\n", ahc_name(ahc));
4325 return (ENXIO);
4326 }
4327
4328 /*
4329 * Create our DMA tags. These tags define the kinds of device
4330 * accessible memory allocations and memory mappings we will
4331 * need to perform during normal operation.
4332 *
4333 * Unless we need to further restrict the allocation, we rely
4334 * on the restrictions of the parent dmat, hence the common
4335 * use of MAXADDR and MAXSIZE.
4336 */
4337
4338 /* DMA tag for our hardware scb structures */
4339 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4340 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4341 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4342 /*highaddr*/BUS_SPACE_MAXADDR,
4343 /*filter*/NULL, /*filterarg*/NULL,
4344 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4345 /*nsegments*/1,
4346 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4347 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4348 goto error_exit;
4349 }
4350
4351 scb_data->init_level++;
4352
4353 /* Allocation for our hscbs */
4354 if (aic_dmamem_alloc(ahc, scb_data->hscb_dmat,
4355 (void **)&scb_data->hscbs,
4356 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4357 &scb_data->hscb_dmamap) != 0) {
4358 goto error_exit;
4359 }
4360
4361 scb_data->init_level++;
4362
4363 /* And permanently map them */
4364 aic_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4365 scb_data->hscbs,
4366 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4367 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4368
4369 scb_data->init_level++;
4370
4371 /* DMA tag for our sense buffers */
4372 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4373 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4374 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4375 /*highaddr*/BUS_SPACE_MAXADDR,
4376 /*filter*/NULL, /*filterarg*/NULL,
4377 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4378 /*nsegments*/1,
4379 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4380 /*flags*/0, &scb_data->sense_dmat) != 0) {
4381 goto error_exit;
4382 }
4383
4384 scb_data->init_level++;
4385
4386 /* Allocate them */
4387 if (aic_dmamem_alloc(ahc, scb_data->sense_dmat,
4388 (void **)&scb_data->sense,
4389 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4390 goto error_exit;
4391 }
4392
4393 scb_data->init_level++;
4394
4395 /* And permanently map them */
4396 aic_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4397 scb_data->sense,
4398 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4399 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4400
4401 scb_data->init_level++;
4402
4403 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4404 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4405 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4406 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4407 /*highaddr*/BUS_SPACE_MAXADDR,
4408 /*filter*/NULL, /*filterarg*/NULL,
4409 PAGE_SIZE, /*nsegments*/1,
4410 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4411 /*flags*/0, &scb_data->sg_dmat) != 0) {
4412 goto error_exit;
4413 }
4414
4415 scb_data->init_level++;
4416
4417 /* Perform initial CCB allocation */
4418 memset(scb_data->hscbs, 0,
4419 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4420 while (ahc_alloc_scbs(ahc) != 0)
4421 ;
4422
4423 if (scb_data->numscbs == 0) {
4424 printf("%s: ahc_init_scbdata - "
4425 "Unable to allocate initial scbs\n",
4426 ahc_name(ahc));
4427 goto error_exit;
4428 }
4429
4430 /*
4431 * Reserve the next queued SCB.
4432 */
4433 ahc->next_queued_scb = ahc_get_scb(ahc);
4434
4435 /*
4436 * Note that we were successful
4437 */
4438 return (0);
4439
4440 error_exit:
4441
4442 return (ENOMEM);
4443 }
4444
4445 static void
ahc_fini_scbdata(struct ahc_softc * ahc)4446 ahc_fini_scbdata(struct ahc_softc *ahc)
4447 {
4448 struct scb_data *scb_data;
4449
4450 scb_data = ahc->scb_data;
4451 if (scb_data == NULL)
4452 return;
4453
4454 switch (scb_data->init_level) {
4455 default:
4456 case 7:
4457 {
4458 struct sg_map_node *sg_map;
4459
4460 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4461 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4462 aic_dmamap_unload(ahc, scb_data->sg_dmat,
4463 sg_map->sg_dmamap);
4464 aic_dmamem_free(ahc, scb_data->sg_dmat,
4465 sg_map->sg_vaddr,
4466 sg_map->sg_dmamap);
4467 free(sg_map, M_DEVBUF);
4468 }
4469 aic_dma_tag_destroy(ahc, scb_data->sg_dmat);
4470 }
4471 case 6:
4472 aic_dmamap_unload(ahc, scb_data->sense_dmat,
4473 scb_data->sense_dmamap);
4474 case 5:
4475 aic_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4476 scb_data->sense_dmamap);
4477 case 4:
4478 aic_dma_tag_destroy(ahc, scb_data->sense_dmat);
4479 case 3:
4480 aic_dmamap_unload(ahc, scb_data->hscb_dmat,
4481 scb_data->hscb_dmamap);
4482 case 2:
4483 aic_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4484 scb_data->hscb_dmamap);
4485 case 1:
4486 aic_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4487 break;
4488 case 0:
4489 break;
4490 }
4491 if (scb_data->scbarray != NULL)
4492 free(scb_data->scbarray, M_DEVBUF);
4493 }
4494
4495 int
ahc_alloc_scbs(struct ahc_softc * ahc)4496 ahc_alloc_scbs(struct ahc_softc *ahc)
4497 {
4498 struct scb_data *scb_data;
4499 struct scb *next_scb;
4500 struct sg_map_node *sg_map;
4501 bus_addr_t physaddr;
4502 struct ahc_dma_seg *segs;
4503 int newcount;
4504 int i;
4505
4506 scb_data = ahc->scb_data;
4507 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4508 /* Can't allocate any more */
4509 return (0);
4510
4511 next_scb = &scb_data->scbarray[scb_data->numscbs];
4512
4513 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4514
4515 if (sg_map == NULL)
4516 return (0);
4517
4518 /* Allocate S/G space for the next batch of SCBS */
4519 if (aic_dmamem_alloc(ahc, scb_data->sg_dmat,
4520 (void **)&sg_map->sg_vaddr,
4521 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4522 &sg_map->sg_dmamap) != 0) {
4523 free(sg_map, M_DEVBUF);
4524 return (0);
4525 }
4526
4527 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4528
4529 aic_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4530 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4531 &sg_map->sg_physaddr, /*flags*/0);
4532
4533 segs = sg_map->sg_vaddr;
4534 physaddr = sg_map->sg_physaddr;
4535
4536 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4537 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4538 for (i = 0; i < newcount; i++) {
4539 struct scb_platform_data *pdata;
4540 #ifndef __linux__
4541 int error;
4542 #endif
4543 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4544 M_DEVBUF, M_NOWAIT);
4545 if (pdata == NULL)
4546 break;
4547 next_scb->platform_data = pdata;
4548 next_scb->sg_map = sg_map;
4549 next_scb->sg_list = segs;
4550 /*
4551 * The sequencer always starts with the second entry.
4552 * The first entry is embedded in the scb.
4553 */
4554 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4555 next_scb->ahc_softc = ahc;
4556 next_scb->flags = SCB_FLAG_NONE;
4557 #ifndef __linux__
4558 error = aic_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4559 &next_scb->dmamap);
4560 if (error != 0)
4561 break;
4562 #endif
4563 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4564 next_scb->hscb->tag = ahc->scb_data->numscbs;
4565 aic_timer_init(&next_scb->io_timer);
4566 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4567 next_scb, links.sle);
4568 segs += AHC_NSEG;
4569 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4570 next_scb++;
4571 ahc->scb_data->numscbs++;
4572 }
4573 return (i);
4574 }
4575
4576 void
ahc_controller_info(struct ahc_softc * ahc,char * buf)4577 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4578 {
4579 int len;
4580
4581 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4582 buf += len;
4583 if ((ahc->features & AHC_TWIN) != 0)
4584 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4585 "B SCSI Id=%d, primary %c, ",
4586 ahc->our_id, ahc->our_id_b,
4587 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4588 else {
4589 const char *speed;
4590 const char *type;
4591
4592 speed = "";
4593 if ((ahc->features & AHC_ULTRA) != 0) {
4594 speed = "Ultra ";
4595 } else if ((ahc->features & AHC_DT) != 0) {
4596 speed = "Ultra160 ";
4597 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4598 speed = "Ultra2 ";
4599 }
4600 if ((ahc->features & AHC_WIDE) != 0) {
4601 type = "Wide";
4602 } else {
4603 type = "Single";
4604 }
4605 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4606 speed, type, ahc->channel, ahc->our_id);
4607 }
4608 buf += len;
4609
4610 if ((ahc->flags & AHC_PAGESCBS) != 0)
4611 sprintf(buf, "%d/%d SCBs",
4612 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4613 else
4614 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4615 }
4616
4617 int
ahc_chip_init(struct ahc_softc * ahc)4618 ahc_chip_init(struct ahc_softc *ahc)
4619 {
4620 int term;
4621 int error;
4622 u_int i;
4623 u_int scsi_conf;
4624 u_int scsiseq_template;
4625 uint32_t physaddr;
4626
4627 ahc_outb(ahc, SEQ_FLAGS, 0);
4628 ahc_outb(ahc, SEQ_FLAGS2, 0);
4629
4630 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4631 if (ahc->features & AHC_TWIN) {
4632 /*
4633 * Setup Channel B first.
4634 */
4635 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4636 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4637 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4638 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4639 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4640 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4641 if ((ahc->features & AHC_ULTRA2) != 0)
4642 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4643 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4644 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4645
4646 /* Select Channel A */
4647 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4648 }
4649 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4650 if ((ahc->features & AHC_ULTRA2) != 0)
4651 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4652 else
4653 ahc_outb(ahc, SCSIID, ahc->our_id);
4654 scsi_conf = ahc_inb(ahc, SCSICONF);
4655 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4656 |term|ahc->seltime
4657 |ENSTIMER|ACTNEGEN);
4658 if ((ahc->features & AHC_ULTRA2) != 0)
4659 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4660 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4661 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4662
4663 /* There are no untagged SCBs active yet. */
4664 for (i = 0; i < 16; i++) {
4665 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4666 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4667 int lun;
4668
4669 /*
4670 * The SCB based BTT allows an entry per
4671 * target and lun pair.
4672 */
4673 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4674 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4675 }
4676 }
4677
4678 /* All of our queues are empty */
4679 for (i = 0; i < 256; i++)
4680 ahc->qoutfifo[i] = SCB_LIST_NULL;
4681 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4682
4683 for (i = 0; i < 256; i++)
4684 ahc->qinfifo[i] = SCB_LIST_NULL;
4685
4686 if ((ahc->features & AHC_MULTI_TID) != 0) {
4687 ahc_outb(ahc, TARGID, 0);
4688 ahc_outb(ahc, TARGID + 1, 0);
4689 }
4690
4691 /*
4692 * Tell the sequencer where it can find our arrays in memory.
4693 */
4694 physaddr = ahc->scb_data->hscb_busaddr;
4695 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4696 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4697 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4698 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4699
4700 physaddr = ahc->shared_data_busaddr;
4701 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4702 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4703 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4704 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4705
4706 /*
4707 * Initialize the group code to command length table.
4708 * This overrides the values in TARG_SCSIRATE, so only
4709 * setup the table after we have processed that information.
4710 */
4711 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4712 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4713 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4714 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4715 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4716 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4717 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4718 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4719
4720 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4721 ahc_outb(ahc, HS_MAILBOX, 0);
4722
4723 /* Tell the sequencer of our initial queue positions */
4724 if ((ahc->features & AHC_TARGETMODE) != 0) {
4725 ahc->tqinfifonext = 1;
4726 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4727 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4728 }
4729 ahc->qinfifonext = 0;
4730 ahc->qoutfifonext = 0;
4731 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4732 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4733 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4734 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4735 ahc_outb(ahc, SDSCB_QOFF, 0);
4736 } else {
4737 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4738 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4739 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4740 }
4741
4742 /* We don't have any waiting selections */
4743 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4744
4745 /* Our disconnection list is empty too */
4746 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4747
4748 /* Message out buffer starts empty */
4749 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4750
4751 /*
4752 * Setup the allowed SCSI Sequences based on operational mode.
4753 * If we are a target, we'll enalbe select in operations once
4754 * we've had a lun enabled.
4755 */
4756 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4757 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4758 scsiseq_template |= ENRSELI;
4759 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4760
4761 /* Initialize our list of free SCBs. */
4762 ahc_build_free_scb_list(ahc);
4763
4764 /*
4765 * Tell the sequencer which SCB will be the next one it receives.
4766 */
4767 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4768
4769 /*
4770 * Load the Sequencer program and Enable the adapter
4771 * in "fast" mode.
4772 */
4773 if (bootverbose)
4774 printf("%s: Downloading Sequencer Program...",
4775 ahc_name(ahc));
4776
4777 error = ahc_loadseq(ahc);
4778 if (error != 0)
4779 return (error);
4780
4781 if ((ahc->features & AHC_ULTRA2) != 0) {
4782 int wait;
4783
4784 /*
4785 * Wait for up to 500ms for our transceivers
4786 * to settle. If the adapter does not have
4787 * a cable attached, the transceivers may
4788 * never settle, so don't complain if we
4789 * fail here.
4790 */
4791 for (wait = 5000;
4792 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4793 wait--)
4794 aic_delay(100);
4795 }
4796 ahc_restart(ahc);
4797 return (0);
4798 }
4799
4800 /*
4801 * Start the board, ready for normal operation
4802 */
4803 int
ahc_init(struct ahc_softc * ahc)4804 ahc_init(struct ahc_softc *ahc)
4805 {
4806 int max_targ;
4807 int error;
4808 u_int i;
4809 u_int scsi_conf;
4810 u_int ultraenb;
4811 u_int discenable;
4812 u_int tagenable;
4813 size_t driver_data_size;
4814
4815 #ifdef AHC_DEBUG
4816 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4817 ahc->flags |= AHC_SEQUENCER_DEBUG;
4818 #endif
4819
4820 #ifdef AHC_PRINT_SRAM
4821 printf("Scratch Ram:");
4822 for (i = 0x20; i < 0x5f; i++) {
4823 if (((i % 8) == 0) && (i != 0)) {
4824 printf ("\n ");
4825 }
4826 printf (" 0x%x", ahc_inb(ahc, i));
4827 }
4828 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4829 for (i = 0x70; i < 0x7f; i++) {
4830 if (((i % 8) == 0) && (i != 0)) {
4831 printf ("\n ");
4832 }
4833 printf (" 0x%x", ahc_inb(ahc, i));
4834 }
4835 }
4836 printf ("\n");
4837 /*
4838 * Reading uninitialized scratch ram may
4839 * generate parity errors.
4840 */
4841 ahc_outb(ahc, CLRINT, CLRPARERR);
4842 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4843 #endif
4844 max_targ = 15;
4845
4846 /*
4847 * Assume we have a board at this stage and it has been reset.
4848 */
4849 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4850 ahc->our_id = ahc->our_id_b = 7;
4851
4852 /*
4853 * Default to allowing initiator operations.
4854 */
4855 ahc->flags |= AHC_INITIATORROLE;
4856
4857 /*
4858 * Only allow target mode features if this unit has them enabled.
4859 */
4860 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4861 ahc->features &= ~AHC_TARGETMODE;
4862
4863 #ifndef __linux__
4864 /* DMA tag for mapping buffers into device visible space. */
4865 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4866 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4867 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4868 ? (bus_addr_t)0x7FFFFFFFFFULL
4869 : BUS_SPACE_MAXADDR_32BIT,
4870 /*highaddr*/BUS_SPACE_MAXADDR,
4871 /*filter*/NULL, /*filterarg*/NULL,
4872 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4873 /*nsegments*/AHC_NSEG,
4874 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4875 /*flags*/BUS_DMA_ALLOCNOW,
4876 &ahc->buffer_dmat) != 0) {
4877 return (ENOMEM);
4878 }
4879 #endif
4880
4881 ahc->init_level++;
4882
4883 /*
4884 * DMA tag for our command fifos and other data in system memory
4885 * the card's sequencer must be able to access. For initiator
4886 * roles, we need to allocate space for the qinfifo and qoutfifo.
4887 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4888 * When providing for the target mode role, we must additionally
4889 * provide space for the incoming target command fifo and an extra
4890 * byte to deal with a dma bug in some chip versions.
4891 */
4892 driver_data_size = 2 * 256 * sizeof(uint8_t);
4893 if ((ahc->features & AHC_TARGETMODE) != 0)
4894 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4895 + /*DMA WideOdd Bug Buffer*/1;
4896 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4897 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4898 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4899 /*highaddr*/BUS_SPACE_MAXADDR,
4900 /*filter*/NULL, /*filterarg*/NULL,
4901 driver_data_size,
4902 /*nsegments*/1,
4903 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4904 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4905 return (ENOMEM);
4906 }
4907
4908 ahc->init_level++;
4909
4910 /* Allocation of driver data */
4911 if (aic_dmamem_alloc(ahc, ahc->shared_data_dmat,
4912 (void **)&ahc->qoutfifo,
4913 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
4914 &ahc->shared_data_dmamap) != 0) {
4915 return (ENOMEM);
4916 }
4917
4918 ahc->init_level++;
4919
4920 /* And permanently map it in */
4921 aic_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4922 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4923 &ahc->shared_data_busaddr, /*flags*/0);
4924
4925 if ((ahc->features & AHC_TARGETMODE) != 0) {
4926 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4927 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4928 ahc->dma_bug_buf = ahc->shared_data_busaddr
4929 + driver_data_size - 1;
4930 /* All target command blocks start out invalid. */
4931 for (i = 0; i < AHC_TMODE_CMDS; i++)
4932 ahc->targetcmds[i].cmd_valid = 0;
4933 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4934 }
4935 ahc->qinfifo = &ahc->qoutfifo[256];
4936
4937 ahc->init_level++;
4938
4939 /* Allocate SCB data now that buffer_dmat is initialized */
4940 if (ahc->scb_data->maxhscbs == 0)
4941 if (ahc_init_scbdata(ahc) != 0)
4942 return (ENOMEM);
4943
4944 /*
4945 * Allocate a tstate to house information for our
4946 * initiator presence on the bus as well as the user
4947 * data for any target mode initiator.
4948 */
4949 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4950 printf("%s: unable to allocate ahc_tmode_tstate. "
4951 "Failing attach\n", ahc_name(ahc));
4952 return (ENOMEM);
4953 }
4954
4955 if ((ahc->features & AHC_TWIN) != 0) {
4956 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4957 printf("%s: unable to allocate ahc_tmode_tstate. "
4958 "Failing attach\n", ahc_name(ahc));
4959 return (ENOMEM);
4960 }
4961 }
4962
4963 /*
4964 * Fire up a recovery thread for this controller.
4965 */
4966 error = ahc_spawn_recovery_thread(ahc);
4967 if (error != 0)
4968 return (error);
4969
4970 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4971 ahc->flags |= AHC_PAGESCBS;
4972 } else {
4973 ahc->flags &= ~AHC_PAGESCBS;
4974 }
4975
4976 #ifdef AHC_DEBUG
4977 if (ahc_debug & AHC_SHOW_MISC) {
4978 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4979 "ahc_dma %u bytes\n",
4980 ahc_name(ahc),
4981 (u_int)sizeof(struct hardware_scb),
4982 (u_int)sizeof(struct scb),
4983 (u_int)sizeof(struct ahc_dma_seg));
4984 }
4985 #endif /* AHC_DEBUG */
4986
4987 /*
4988 * Look at the information that board initialization or
4989 * the board bios has left us.
4990 */
4991 if (ahc->features & AHC_TWIN) {
4992 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4993 if ((scsi_conf & RESET_SCSI) != 0
4994 && (ahc->flags & AHC_INITIATORROLE) != 0)
4995 ahc->flags |= AHC_RESET_BUS_B;
4996 }
4997
4998 scsi_conf = ahc_inb(ahc, SCSICONF);
4999 if ((scsi_conf & RESET_SCSI) != 0
5000 && (ahc->flags & AHC_INITIATORROLE) != 0)
5001 ahc->flags |= AHC_RESET_BUS_A;
5002
5003 ultraenb = 0;
5004 tagenable = ALL_TARGETS_MASK;
5005
5006 /* Grab the disconnection disable table and invert it for our needs */
5007 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
5008 printf("%s: Host Adapter Bios disabled. Using default SCSI "
5009 "device parameters\n", ahc_name(ahc));
5010 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
5011 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
5012 discenable = ALL_TARGETS_MASK;
5013 if ((ahc->features & AHC_ULTRA) != 0)
5014 ultraenb = ALL_TARGETS_MASK;
5015 } else {
5016 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
5017 | ahc_inb(ahc, DISC_DSB));
5018 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
5019 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
5020 | ahc_inb(ahc, ULTRA_ENB);
5021 }
5022
5023 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
5024 max_targ = 7;
5025
5026 for (i = 0; i <= max_targ; i++) {
5027 struct ahc_initiator_tinfo *tinfo;
5028 struct ahc_tmode_tstate *tstate;
5029 u_int our_id;
5030 u_int target_id;
5031 char channel;
5032
5033 channel = 'A';
5034 our_id = ahc->our_id;
5035 target_id = i;
5036 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
5037 channel = 'B';
5038 our_id = ahc->our_id_b;
5039 target_id = i % 8;
5040 }
5041 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
5042 target_id, &tstate);
5043 /* Default to async narrow across the board */
5044 memset(tinfo, 0, sizeof(*tinfo));
5045 if (ahc->flags & AHC_USEDEFAULTS) {
5046 if ((ahc->features & AHC_WIDE) != 0)
5047 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5048
5049 /*
5050 * These will be truncated when we determine the
5051 * connection type we have with the target.
5052 */
5053 tinfo->user.period = ahc_syncrates->period;
5054 tinfo->user.offset = MAX_OFFSET;
5055 } else {
5056 u_int scsirate;
5057 uint16_t mask;
5058
5059 /* Take the settings leftover in scratch RAM. */
5060 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5061 mask = (0x01 << i);
5062 if ((ahc->features & AHC_ULTRA2) != 0) {
5063 u_int offset;
5064 u_int maxsync;
5065
5066 if ((scsirate & SOFS) == 0x0F) {
5067 /*
5068 * Haven't negotiated yet,
5069 * so the format is different.
5070 */
5071 scsirate = (scsirate & SXFR) >> 4
5072 | (ultraenb & mask)
5073 ? 0x08 : 0x0
5074 | (scsirate & WIDEXFER);
5075 offset = MAX_OFFSET_ULTRA2;
5076 } else
5077 offset = ahc_inb(ahc, TARG_OFFSET + i);
5078 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5079 /* Set to the lowest sync rate, 5MHz */
5080 scsirate |= 0x1c;
5081 maxsync = AHC_SYNCRATE_ULTRA2;
5082 if ((ahc->features & AHC_DT) != 0)
5083 maxsync = AHC_SYNCRATE_DT;
5084 tinfo->user.period =
5085 ahc_find_period(ahc, scsirate, maxsync);
5086 if (offset == 0)
5087 tinfo->user.period = 0;
5088 else
5089 tinfo->user.offset = MAX_OFFSET;
5090 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5091 && (ahc->features & AHC_DT) != 0)
5092 tinfo->user.ppr_options =
5093 MSG_EXT_PPR_DT_REQ;
5094 } else if ((scsirate & SOFS) != 0) {
5095 if ((scsirate & SXFR) == 0x40
5096 && (ultraenb & mask) != 0) {
5097 /* Treat 10MHz as a non-ultra speed */
5098 scsirate &= ~SXFR;
5099 ultraenb &= ~mask;
5100 }
5101 tinfo->user.period =
5102 ahc_find_period(ahc, scsirate,
5103 (ultraenb & mask)
5104 ? AHC_SYNCRATE_ULTRA
5105 : AHC_SYNCRATE_FAST);
5106 if (tinfo->user.period != 0)
5107 tinfo->user.offset = MAX_OFFSET;
5108 }
5109 if (tinfo->user.period == 0)
5110 tinfo->user.offset = 0;
5111 if ((scsirate & WIDEXFER) != 0
5112 && (ahc->features & AHC_WIDE) != 0)
5113 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5114 tinfo->user.protocol_version = 4;
5115 if ((ahc->features & AHC_DT) != 0)
5116 tinfo->user.transport_version = 3;
5117 else
5118 tinfo->user.transport_version = 2;
5119 tinfo->goal.protocol_version = 2;
5120 tinfo->goal.transport_version = 2;
5121 tinfo->curr.protocol_version = 2;
5122 tinfo->curr.transport_version = 2;
5123 }
5124 tstate->ultraenb = 0;
5125 }
5126 ahc->user_discenable = discenable;
5127 ahc->user_tagenable = tagenable;
5128
5129 return (ahc->bus_chip_init(ahc));
5130 }
5131
5132 void
ahc_intr_enable(struct ahc_softc * ahc,int enable)5133 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5134 {
5135 u_int hcntrl;
5136
5137 hcntrl = ahc_inb(ahc, HCNTRL);
5138 hcntrl &= ~INTEN;
5139 ahc->pause &= ~INTEN;
5140 ahc->unpause &= ~INTEN;
5141 if (enable) {
5142 hcntrl |= INTEN;
5143 ahc->pause |= INTEN;
5144 ahc->unpause |= INTEN;
5145 }
5146 ahc_outb(ahc, HCNTRL, hcntrl);
5147 }
5148
5149 /*
5150 * Ensure that the card is paused in a location
5151 * outside of all critical sections and that all
5152 * pending work is completed prior to returning.
5153 * This routine should only be called from outside
5154 * an interrupt context.
5155 */
5156 void
ahc_pause_and_flushwork(struct ahc_softc * ahc)5157 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5158 {
5159 int intstat;
5160 int maxloops;
5161 int paused;
5162
5163 maxloops = 1000;
5164 ahc->flags |= AHC_ALL_INTERRUPTS;
5165 paused = FALSE;
5166 do {
5167 if (paused) {
5168 ahc_unpause(ahc);
5169 /*
5170 * Give the sequencer some time to service
5171 * any active selections.
5172 */
5173 aic_delay(500);
5174 }
5175 ahc_intr(ahc);
5176 ahc_pause(ahc);
5177 paused = TRUE;
5178 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5179 intstat = ahc_inb(ahc, INTSTAT);
5180 if ((intstat & INT_PEND) == 0) {
5181 ahc_clear_critical_section(ahc);
5182 intstat = ahc_inb(ahc, INTSTAT);
5183 }
5184 } while (--maxloops
5185 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5186 && ((intstat & INT_PEND) != 0
5187 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5188 if (maxloops == 0) {
5189 printf("Infinite interrupt loop, INTSTAT = %x",
5190 ahc_inb(ahc, INTSTAT));
5191 }
5192 ahc_platform_flushwork(ahc);
5193 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5194 }
5195
5196 int
ahc_suspend(struct ahc_softc * ahc)5197 ahc_suspend(struct ahc_softc *ahc)
5198 {
5199
5200 ahc_pause_and_flushwork(ahc);
5201
5202 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5203 ahc_unpause(ahc);
5204 return (EBUSY);
5205 }
5206
5207 #ifdef AHC_TARGET_MODE
5208 /*
5209 * XXX What about ATIOs that have not yet been serviced?
5210 * Perhaps we should just refuse to be suspended if we
5211 * are acting in a target role.
5212 */
5213 if (ahc->pending_device != NULL) {
5214 ahc_unpause(ahc);
5215 return (EBUSY);
5216 }
5217 #endif
5218 ahc_shutdown(ahc);
5219 return (0);
5220 }
5221
5222 int
ahc_resume(struct ahc_softc * ahc)5223 ahc_resume(struct ahc_softc *ahc)
5224 {
5225
5226 ahc_reset(ahc, /*reinit*/TRUE);
5227 ahc_intr_enable(ahc, TRUE);
5228 ahc_restart(ahc);
5229 return (0);
5230 }
5231
5232 /************************** Busy Target Table *********************************/
5233 /*
5234 * Return the untagged transaction id for a given target/channel lun.
5235 * Optionally, clear the entry.
5236 */
5237 u_int
ahc_index_busy_tcl(struct ahc_softc * ahc,u_int tcl)5238 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5239 {
5240 u_int scbid;
5241 u_int target_offset;
5242
5243 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5244 u_int saved_scbptr;
5245
5246 saved_scbptr = ahc_inb(ahc, SCBPTR);
5247 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5248 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5249 ahc_outb(ahc, SCBPTR, saved_scbptr);
5250 } else {
5251 target_offset = TCL_TARGET_OFFSET(tcl);
5252 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5253 }
5254
5255 return (scbid);
5256 }
5257
5258 void
ahc_unbusy_tcl(struct ahc_softc * ahc,u_int tcl)5259 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5260 {
5261 u_int target_offset;
5262
5263 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5264 u_int saved_scbptr;
5265
5266 saved_scbptr = ahc_inb(ahc, SCBPTR);
5267 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5268 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5269 ahc_outb(ahc, SCBPTR, saved_scbptr);
5270 } else {
5271 target_offset = TCL_TARGET_OFFSET(tcl);
5272 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5273 }
5274 }
5275
5276 void
ahc_busy_tcl(struct ahc_softc * ahc,u_int tcl,u_int scbid)5277 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5278 {
5279 u_int target_offset;
5280
5281 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5282 u_int saved_scbptr;
5283
5284 saved_scbptr = ahc_inb(ahc, SCBPTR);
5285 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5286 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5287 ahc_outb(ahc, SCBPTR, saved_scbptr);
5288 } else {
5289 target_offset = TCL_TARGET_OFFSET(tcl);
5290 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5291 }
5292 }
5293
5294 /************************** SCB and SCB queue management **********************/
5295 int
ahc_match_scb(struct ahc_softc * ahc,struct scb * scb,int target,char channel,int lun,u_int tag,role_t role)5296 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5297 char channel, int lun, u_int tag, role_t role)
5298 {
5299 int targ = SCB_GET_TARGET(ahc, scb);
5300 char chan = SCB_GET_CHANNEL(ahc, scb);
5301 int slun = SCB_GET_LUN(scb);
5302 int match;
5303
5304 match = ((chan == channel) || (channel == ALL_CHANNELS));
5305 if (match != 0)
5306 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5307 if (match != 0)
5308 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5309 if (match != 0) {
5310 #ifdef AHC_TARGET_MODE
5311 int group;
5312
5313 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5314 if (role == ROLE_INITIATOR) {
5315 match = (group != XPT_FC_GROUP_TMODE)
5316 && ((tag == scb->hscb->tag)
5317 || (tag == SCB_LIST_NULL));
5318 } else if (role == ROLE_TARGET) {
5319 match = (group == XPT_FC_GROUP_TMODE)
5320 && ((tag == scb->io_ctx->csio.tag_id)
5321 || (tag == SCB_LIST_NULL));
5322 }
5323 #else /* !AHC_TARGET_MODE */
5324 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5325 #endif /* AHC_TARGET_MODE */
5326 }
5327
5328 return match;
5329 }
5330
5331 void
ahc_freeze_devq(struct ahc_softc * ahc,struct scb * scb)5332 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5333 {
5334 int target;
5335 char channel;
5336 int lun;
5337
5338 target = SCB_GET_TARGET(ahc, scb);
5339 lun = SCB_GET_LUN(scb);
5340 channel = SCB_GET_CHANNEL(ahc, scb);
5341
5342 ahc_search_qinfifo(ahc, target, channel, lun,
5343 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5344 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5345
5346 ahc_platform_freeze_devq(ahc, scb);
5347 }
5348
5349 void
ahc_qinfifo_requeue_tail(struct ahc_softc * ahc,struct scb * scb)5350 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5351 {
5352 struct scb *prev_scb;
5353
5354 prev_scb = NULL;
5355 if (ahc_qinfifo_count(ahc) != 0) {
5356 u_int prev_tag;
5357 uint8_t prev_pos;
5358
5359 prev_pos = ahc->qinfifonext - 1;
5360 prev_tag = ahc->qinfifo[prev_pos];
5361 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5362 }
5363 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5364 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5365 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5366 } else {
5367 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5368 }
5369 }
5370
5371 static void
ahc_qinfifo_requeue(struct ahc_softc * ahc,struct scb * prev_scb,struct scb * scb)5372 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5373 struct scb *scb)
5374 {
5375 if (prev_scb == NULL) {
5376 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5377 } else {
5378 prev_scb->hscb->next = scb->hscb->tag;
5379 ahc_sync_scb(ahc, prev_scb,
5380 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5381 }
5382 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5383 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5384 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5385 }
5386
5387 static int
ahc_qinfifo_count(struct ahc_softc * ahc)5388 ahc_qinfifo_count(struct ahc_softc *ahc)
5389 {
5390 uint8_t qinpos;
5391 uint8_t diff;
5392
5393 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5394 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5395 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5396 } else
5397 qinpos = ahc_inb(ahc, QINPOS);
5398 diff = ahc->qinfifonext - qinpos;
5399 return (diff);
5400 }
5401
5402 int
ahc_search_qinfifo(struct ahc_softc * ahc,int target,char channel,int lun,u_int tag,role_t role,uint32_t status,ahc_search_action action)5403 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5404 int lun, u_int tag, role_t role, uint32_t status,
5405 ahc_search_action action)
5406 {
5407 struct scb *scb;
5408 struct scb *prev_scb;
5409 uint8_t qinstart;
5410 uint8_t qinpos;
5411 uint8_t qintail;
5412 uint8_t next;
5413 uint8_t prev;
5414 uint8_t curscbptr;
5415 int found;
5416 int have_qregs;
5417
5418 qintail = ahc->qinfifonext;
5419 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5420 if (have_qregs) {
5421 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5422 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5423 } else
5424 qinstart = ahc_inb(ahc, QINPOS);
5425 qinpos = qinstart;
5426 found = 0;
5427 prev_scb = NULL;
5428
5429 if (action == SEARCH_COMPLETE) {
5430 /*
5431 * Don't attempt to run any queued untagged transactions
5432 * until we are done with the abort process.
5433 */
5434 ahc_freeze_untagged_queues(ahc);
5435 }
5436
5437 /*
5438 * Start with an empty queue. Entries that are not chosen
5439 * for removal will be re-added to the queue as we go.
5440 */
5441 ahc->qinfifonext = qinpos;
5442 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5443
5444 while (qinpos != qintail) {
5445 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5446 if (scb == NULL) {
5447 printf("qinpos = %d, SCB index = %d\n",
5448 qinpos, ahc->qinfifo[qinpos]);
5449 panic("Loop 1\n");
5450 }
5451
5452 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5453 /*
5454 * We found an scb that needs to be acted on.
5455 */
5456 found++;
5457 switch (action) {
5458 case SEARCH_COMPLETE:
5459 {
5460 cam_status ostat;
5461 cam_status cstat;
5462
5463 ostat = aic_get_transaction_status(scb);
5464 if (ostat == CAM_REQ_INPROG)
5465 aic_set_transaction_status(scb, status);
5466 cstat = aic_get_transaction_status(scb);
5467 if (cstat != CAM_REQ_CMP)
5468 aic_freeze_scb(scb);
5469 if ((scb->flags & SCB_ACTIVE) == 0)
5470 printf("Inactive SCB in qinfifo\n");
5471 ahc_done(ahc, scb);
5472
5473 /* FALLTHROUGH */
5474 }
5475 case SEARCH_REMOVE:
5476 break;
5477 case SEARCH_COUNT:
5478 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5479 prev_scb = scb;
5480 break;
5481 }
5482 } else {
5483 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5484 prev_scb = scb;
5485 }
5486 qinpos++;
5487 }
5488
5489 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5490 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5491 } else {
5492 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5493 }
5494
5495 if (action != SEARCH_COUNT
5496 && (found != 0)
5497 && (qinstart != ahc->qinfifonext)) {
5498 /*
5499 * The sequencer may be in the process of dmaing
5500 * down the SCB at the beginning of the queue.
5501 * This could be problematic if either the first,
5502 * or the second SCB is removed from the queue
5503 * (the first SCB includes a pointer to the "next"
5504 * SCB to dma). If we have removed any entries, swap
5505 * the first element in the queue with the next HSCB
5506 * so the sequencer will notice that NEXT_QUEUED_SCB
5507 * has changed during its dma attempt and will retry
5508 * the DMA.
5509 */
5510 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5511
5512 if (scb == NULL) {
5513 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5514 found, qinstart, ahc->qinfifonext);
5515 panic("First/Second Qinfifo fixup\n");
5516 }
5517 /*
5518 * ahc_swap_with_next_hscb forces our next pointer to
5519 * point to the reserved SCB for future commands. Save
5520 * and restore our original next pointer to maintain
5521 * queue integrity.
5522 */
5523 next = scb->hscb->next;
5524 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5525 ahc_swap_with_next_hscb(ahc, scb);
5526 scb->hscb->next = next;
5527 ahc->qinfifo[qinstart] = scb->hscb->tag;
5528
5529 /* Tell the card about the new head of the qinfifo. */
5530 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5531
5532 /* Fixup the tail "next" pointer. */
5533 qintail = ahc->qinfifonext - 1;
5534 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5535 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5536 }
5537
5538 /*
5539 * Search waiting for selection list.
5540 */
5541 curscbptr = ahc_inb(ahc, SCBPTR);
5542 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5543 prev = SCB_LIST_NULL;
5544
5545 while (next != SCB_LIST_NULL) {
5546 uint8_t scb_index;
5547
5548 ahc_outb(ahc, SCBPTR, next);
5549 scb_index = ahc_inb(ahc, SCB_TAG);
5550 if (scb_index >= ahc->scb_data->numscbs) {
5551 printf("Waiting List inconsistency. "
5552 "SCB index == %d, yet numscbs == %d.",
5553 scb_index, ahc->scb_data->numscbs);
5554 ahc_dump_card_state(ahc);
5555 panic("for safety");
5556 }
5557 scb = ahc_lookup_scb(ahc, scb_index);
5558 if (scb == NULL) {
5559 printf("scb_index = %d, next = %d\n",
5560 scb_index, next);
5561 panic("Waiting List traversal\n");
5562 }
5563 if (ahc_match_scb(ahc, scb, target, channel,
5564 lun, SCB_LIST_NULL, role)) {
5565 /*
5566 * We found an scb that needs to be acted on.
5567 */
5568 found++;
5569 switch (action) {
5570 case SEARCH_COMPLETE:
5571 {
5572 cam_status ostat;
5573 cam_status cstat;
5574
5575 ostat = aic_get_transaction_status(scb);
5576 if (ostat == CAM_REQ_INPROG)
5577 aic_set_transaction_status(scb,
5578 status);
5579 cstat = aic_get_transaction_status(scb);
5580 if (cstat != CAM_REQ_CMP)
5581 aic_freeze_scb(scb);
5582 if ((scb->flags & SCB_ACTIVE) == 0)
5583 printf("Inactive SCB in Wait List\n");
5584 ahc_done(ahc, scb);
5585 /* FALLTHROUGH */
5586 }
5587 case SEARCH_REMOVE:
5588 next = ahc_rem_wscb(ahc, next, prev);
5589 break;
5590 case SEARCH_COUNT:
5591 prev = next;
5592 next = ahc_inb(ahc, SCB_NEXT);
5593 break;
5594 }
5595 } else {
5596
5597 prev = next;
5598 next = ahc_inb(ahc, SCB_NEXT);
5599 }
5600 }
5601 ahc_outb(ahc, SCBPTR, curscbptr);
5602
5603 found += ahc_search_untagged_queues(ahc, /*aic_io_ctx_t*/NULL, target,
5604 channel, lun, status, action);
5605
5606 if (action == SEARCH_COMPLETE)
5607 ahc_release_untagged_queues(ahc);
5608 return (found);
5609 }
5610
5611 int
ahc_search_untagged_queues(struct ahc_softc * ahc,aic_io_ctx_t ctx,int target,char channel,int lun,uint32_t status,ahc_search_action action)5612 ahc_search_untagged_queues(struct ahc_softc *ahc, aic_io_ctx_t ctx,
5613 int target, char channel, int lun, uint32_t status,
5614 ahc_search_action action)
5615 {
5616 struct scb *scb;
5617 int maxtarget;
5618 int found;
5619 int i;
5620
5621 if (action == SEARCH_COMPLETE) {
5622 /*
5623 * Don't attempt to run any queued untagged transactions
5624 * until we are done with the abort process.
5625 */
5626 ahc_freeze_untagged_queues(ahc);
5627 }
5628
5629 found = 0;
5630 i = 0;
5631 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5632 maxtarget = 16;
5633 if (target != CAM_TARGET_WILDCARD) {
5634 i = target;
5635 if (channel == 'B')
5636 i += 8;
5637 maxtarget = i + 1;
5638 }
5639 } else {
5640 maxtarget = 0;
5641 }
5642
5643 for (; i < maxtarget; i++) {
5644 struct scb_tailq *untagged_q;
5645 struct scb *next_scb;
5646
5647 untagged_q = &(ahc->untagged_queues[i]);
5648 next_scb = TAILQ_FIRST(untagged_q);
5649 while (next_scb != NULL) {
5650 scb = next_scb;
5651 next_scb = TAILQ_NEXT(scb, links.tqe);
5652
5653 /*
5654 * The head of the list may be the currently
5655 * active untagged command for a device.
5656 * We're only searching for commands that
5657 * have not been started. A transaction
5658 * marked active but still in the qinfifo
5659 * is removed by the qinfifo scanning code
5660 * above.
5661 */
5662 if ((scb->flags & SCB_ACTIVE) != 0)
5663 continue;
5664
5665 if (ahc_match_scb(ahc, scb, target, channel, lun,
5666 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5667 || (ctx != NULL && ctx != scb->io_ctx))
5668 continue;
5669
5670 /*
5671 * We found an scb that needs to be acted on.
5672 */
5673 found++;
5674 switch (action) {
5675 case SEARCH_COMPLETE:
5676 {
5677 cam_status ostat;
5678 cam_status cstat;
5679
5680 ostat = aic_get_transaction_status(scb);
5681 if (ostat == CAM_REQ_INPROG)
5682 aic_set_transaction_status(scb, status);
5683 cstat = aic_get_transaction_status(scb);
5684 if (cstat != CAM_REQ_CMP)
5685 aic_freeze_scb(scb);
5686 ahc_done(ahc, scb);
5687 break;
5688 }
5689 case SEARCH_REMOVE:
5690 scb->flags &= ~SCB_UNTAGGEDQ;
5691 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5692 break;
5693 case SEARCH_COUNT:
5694 break;
5695 }
5696 }
5697 }
5698
5699 if (action == SEARCH_COMPLETE)
5700 ahc_release_untagged_queues(ahc);
5701 return (found);
5702 }
5703
5704 int
ahc_search_disc_list(struct ahc_softc * ahc,int target,char channel,int lun,u_int tag,int stop_on_first,int remove,int save_state)5705 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5706 int lun, u_int tag, int stop_on_first, int remove,
5707 int save_state)
5708 {
5709 struct scb *scbp;
5710 u_int next;
5711 u_int prev;
5712 u_int count;
5713 u_int active_scb;
5714
5715 count = 0;
5716 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5717 prev = SCB_LIST_NULL;
5718
5719 if (save_state) {
5720 /* restore this when we're done */
5721 active_scb = ahc_inb(ahc, SCBPTR);
5722 } else
5723 /* Silence compiler */
5724 active_scb = SCB_LIST_NULL;
5725
5726 while (next != SCB_LIST_NULL) {
5727 u_int scb_index;
5728
5729 ahc_outb(ahc, SCBPTR, next);
5730 scb_index = ahc_inb(ahc, SCB_TAG);
5731 if (scb_index >= ahc->scb_data->numscbs) {
5732 printf("Disconnected List inconsistency. "
5733 "SCB index == %d, yet numscbs == %d.",
5734 scb_index, ahc->scb_data->numscbs);
5735 ahc_dump_card_state(ahc);
5736 panic("for safety");
5737 }
5738
5739 if (next == prev) {
5740 panic("Disconnected List Loop. "
5741 "cur SCBPTR == %x, prev SCBPTR == %x.",
5742 next, prev);
5743 }
5744 scbp = ahc_lookup_scb(ahc, scb_index);
5745 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5746 tag, ROLE_INITIATOR)) {
5747 count++;
5748 if (remove) {
5749 next =
5750 ahc_rem_scb_from_disc_list(ahc, prev, next);
5751 } else {
5752 prev = next;
5753 next = ahc_inb(ahc, SCB_NEXT);
5754 }
5755 if (stop_on_first)
5756 break;
5757 } else {
5758 prev = next;
5759 next = ahc_inb(ahc, SCB_NEXT);
5760 }
5761 }
5762 if (save_state)
5763 ahc_outb(ahc, SCBPTR, active_scb);
5764 return (count);
5765 }
5766
5767 /*
5768 * Remove an SCB from the on chip list of disconnected transactions.
5769 * This is empty/unused if we are not performing SCB paging.
5770 */
5771 static u_int
ahc_rem_scb_from_disc_list(struct ahc_softc * ahc,u_int prev,u_int scbptr)5772 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5773 {
5774 u_int next;
5775
5776 ahc_outb(ahc, SCBPTR, scbptr);
5777 next = ahc_inb(ahc, SCB_NEXT);
5778
5779 ahc_outb(ahc, SCB_CONTROL, 0);
5780
5781 ahc_add_curscb_to_free_list(ahc);
5782
5783 if (prev != SCB_LIST_NULL) {
5784 ahc_outb(ahc, SCBPTR, prev);
5785 ahc_outb(ahc, SCB_NEXT, next);
5786 } else
5787 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5788
5789 return (next);
5790 }
5791
5792 /*
5793 * Add the SCB as selected by SCBPTR onto the on chip list of
5794 * free hardware SCBs. This list is empty/unused if we are not
5795 * performing SCB paging.
5796 */
5797 static void
ahc_add_curscb_to_free_list(struct ahc_softc * ahc)5798 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5799 {
5800 /*
5801 * Invalidate the tag so that our abort
5802 * routines don't think it's active.
5803 */
5804 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5805
5806 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5807 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5808 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5809 }
5810 }
5811
5812 /*
5813 * Manipulate the waiting for selection list and return the
5814 * scb that follows the one that we remove.
5815 */
5816 static u_int
ahc_rem_wscb(struct ahc_softc * ahc,u_int scbpos,u_int prev)5817 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5818 {
5819 u_int curscb, next;
5820
5821 /*
5822 * Select the SCB we want to abort and
5823 * pull the next pointer out of it.
5824 */
5825 curscb = ahc_inb(ahc, SCBPTR);
5826 ahc_outb(ahc, SCBPTR, scbpos);
5827 next = ahc_inb(ahc, SCB_NEXT);
5828
5829 /* Clear the necessary fields */
5830 ahc_outb(ahc, SCB_CONTROL, 0);
5831
5832 ahc_add_curscb_to_free_list(ahc);
5833
5834 /* update the waiting list */
5835 if (prev == SCB_LIST_NULL) {
5836 /* First in the list */
5837 ahc_outb(ahc, WAITING_SCBH, next);
5838
5839 /*
5840 * Ensure we aren't attempting to perform
5841 * selection for this entry.
5842 */
5843 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5844 } else {
5845 /*
5846 * Select the scb that pointed to us
5847 * and update its next pointer.
5848 */
5849 ahc_outb(ahc, SCBPTR, prev);
5850 ahc_outb(ahc, SCB_NEXT, next);
5851 }
5852
5853 /*
5854 * Point us back at the original scb position.
5855 */
5856 ahc_outb(ahc, SCBPTR, curscb);
5857 return next;
5858 }
5859
5860 /******************************** Error Handling ******************************/
5861 /*
5862 * Abort all SCBs that match the given description (target/channel/lun/tag),
5863 * setting their status to the passed in status if the status has not already
5864 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5865 * is paused before it is called.
5866 */
5867 int
ahc_abort_scbs(struct ahc_softc * ahc,int target,char channel,int lun,u_int tag,role_t role,uint32_t status)5868 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5869 int lun, u_int tag, role_t role, uint32_t status)
5870 {
5871 struct scb *scbp;
5872 struct scb *scbp_next;
5873 u_int active_scb;
5874 int i, j;
5875 int maxtarget;
5876 int minlun;
5877 int maxlun;
5878
5879 int found;
5880
5881 /*
5882 * Don't attempt to run any queued untagged transactions
5883 * until we are done with the abort process.
5884 */
5885 ahc_freeze_untagged_queues(ahc);
5886
5887 /* restore this when we're done */
5888 active_scb = ahc_inb(ahc, SCBPTR);
5889
5890 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5891 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5892
5893 /*
5894 * Clean out the busy target table for any untagged commands.
5895 */
5896 i = 0;
5897 maxtarget = 16;
5898 if (target != CAM_TARGET_WILDCARD) {
5899 i = target;
5900 if (channel == 'B')
5901 i += 8;
5902 maxtarget = i + 1;
5903 }
5904
5905 if (lun == CAM_LUN_WILDCARD) {
5906 /*
5907 * Unless we are using an SCB based
5908 * busy targets table, there is only
5909 * one table entry for all luns of
5910 * a target.
5911 */
5912 minlun = 0;
5913 maxlun = 1;
5914 if ((ahc->flags & AHC_SCB_BTT) != 0)
5915 maxlun = AHC_NUM_LUNS;
5916 } else {
5917 minlun = lun;
5918 maxlun = lun + 1;
5919 }
5920
5921 if (role != ROLE_TARGET) {
5922 for (;i < maxtarget; i++) {
5923 for (j = minlun;j < maxlun; j++) {
5924 u_int scbid;
5925 u_int tcl;
5926
5927 tcl = BUILD_TCL(i << 4, j);
5928 scbid = ahc_index_busy_tcl(ahc, tcl);
5929 scbp = ahc_lookup_scb(ahc, scbid);
5930 if (scbp == NULL
5931 || ahc_match_scb(ahc, scbp, target, channel,
5932 lun, tag, role) == 0)
5933 continue;
5934 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5935 }
5936 }
5937
5938 /*
5939 * Go through the disconnected list and remove any entries we
5940 * have queued for completion, 0'ing their control byte too.
5941 * We save the active SCB and restore it ourselves, so there
5942 * is no reason for this search to restore it too.
5943 */
5944 ahc_search_disc_list(ahc, target, channel, lun, tag,
5945 /*stop_on_first*/FALSE, /*remove*/TRUE,
5946 /*save_state*/FALSE);
5947 }
5948
5949 /*
5950 * Go through the hardware SCB array looking for commands that
5951 * were active but not on any list. In some cases, these remnants
5952 * might not still have mappings in the scbindex array (e.g. unexpected
5953 * bus free with the same scb queued for an abort). Don't hold this
5954 * against them.
5955 */
5956 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5957 u_int scbid;
5958
5959 ahc_outb(ahc, SCBPTR, i);
5960 scbid = ahc_inb(ahc, SCB_TAG);
5961 scbp = ahc_lookup_scb(ahc, scbid);
5962 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5963 || (scbp != NULL
5964 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5965 ahc_add_curscb_to_free_list(ahc);
5966 }
5967
5968 /*
5969 * Go through the pending CCB list and look for
5970 * commands for this target that are still active.
5971 * These are other tagged commands that were
5972 * disconnected when the reset occurred.
5973 */
5974 scbp_next = LIST_FIRST(&ahc->pending_scbs);
5975 while (scbp_next != NULL) {
5976 scbp = scbp_next;
5977 scbp_next = LIST_NEXT(scbp, pending_links);
5978 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5979 cam_status ostat;
5980
5981 ostat = aic_get_transaction_status(scbp);
5982 if (ostat == CAM_REQ_INPROG)
5983 aic_set_transaction_status(scbp, status);
5984 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
5985 aic_freeze_scb(scbp);
5986 if ((scbp->flags & SCB_ACTIVE) == 0)
5987 printf("Inactive SCB on pending list\n");
5988 ahc_done(ahc, scbp);
5989 found++;
5990 }
5991 }
5992 ahc_outb(ahc, SCBPTR, active_scb);
5993 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
5994 ahc_release_untagged_queues(ahc);
5995 return found;
5996 }
5997
5998 static void
ahc_reset_current_bus(struct ahc_softc * ahc)5999 ahc_reset_current_bus(struct ahc_softc *ahc)
6000 {
6001 uint8_t scsiseq;
6002
6003 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
6004 scsiseq = ahc_inb(ahc, SCSISEQ);
6005 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
6006 ahc_flush_device_writes(ahc);
6007 aic_delay(AHC_BUSRESET_DELAY);
6008 /* Turn off the bus reset */
6009 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
6010
6011 ahc_clear_intstat(ahc);
6012
6013 /* Re-enable reset interrupts */
6014 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
6015 }
6016
6017 int
ahc_reset_channel(struct ahc_softc * ahc,char channel,int initiate_reset)6018 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6019 {
6020 struct ahc_devinfo devinfo;
6021 u_int initiator, target, max_scsiid;
6022 u_int sblkctl;
6023 u_int scsiseq;
6024 u_int simode1;
6025 int found;
6026 int restart_needed;
6027 char cur_channel;
6028
6029 ahc->pending_device = NULL;
6030
6031 ahc_compile_devinfo(&devinfo,
6032 CAM_TARGET_WILDCARD,
6033 CAM_TARGET_WILDCARD,
6034 CAM_LUN_WILDCARD,
6035 channel, ROLE_UNKNOWN);
6036 ahc_pause(ahc);
6037
6038 /* Make sure the sequencer is in a safe location. */
6039 ahc_clear_critical_section(ahc);
6040
6041 /*
6042 * Run our command complete fifos to ensure that we perform
6043 * completion processing on any commands that 'completed'
6044 * before the reset occurred.
6045 */
6046 ahc_run_qoutfifo(ahc);
6047 #ifdef AHC_TARGET_MODE
6048 /*
6049 * XXX - In Twin mode, the tqinfifo may have commands
6050 * for an unaffected channel in it. However, if
6051 * we have run out of ATIO resources to drain that
6052 * queue, we may not get them all out here. Further,
6053 * the blocked transactions for the reset channel
6054 * should just be killed off, irrespective of whether
6055 * we are blocked on ATIO resources. Write a routine
6056 * to compact the tqinfifo appropriately.
6057 */
6058 if ((ahc->flags & AHC_TARGETROLE) != 0) {
6059 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6060 }
6061 #endif
6062
6063 /*
6064 * Reset the bus if we are initiating this reset
6065 */
6066 sblkctl = ahc_inb(ahc, SBLKCTL);
6067 cur_channel = 'A';
6068 if ((ahc->features & AHC_TWIN) != 0
6069 && ((sblkctl & SELBUSB) != 0))
6070 cur_channel = 'B';
6071 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6072 if (cur_channel != channel) {
6073 /* Case 1: Command for another bus is active
6074 * Stealthily reset the other bus without
6075 * upsetting the current bus.
6076 */
6077 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6078 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6079 #ifdef AHC_TARGET_MODE
6080 /*
6081 * Bus resets clear ENSELI, so we cannot
6082 * defer re-enabling bus reset interrupts
6083 * if we are in target mode.
6084 */
6085 if ((ahc->flags & AHC_TARGETROLE) != 0)
6086 simode1 |= ENSCSIRST;
6087 #endif
6088 ahc_outb(ahc, SIMODE1, simode1);
6089 if (initiate_reset)
6090 ahc_reset_current_bus(ahc);
6091 ahc_clear_intstat(ahc);
6092 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6093 ahc_outb(ahc, SBLKCTL, sblkctl);
6094 restart_needed = FALSE;
6095 } else {
6096 /* Case 2: A command from this bus is active or we're idle */
6097 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6098 #ifdef AHC_TARGET_MODE
6099 /*
6100 * Bus resets clear ENSELI, so we cannot
6101 * defer re-enabling bus reset interrupts
6102 * if we are in target mode.
6103 */
6104 if ((ahc->flags & AHC_TARGETROLE) != 0)
6105 simode1 |= ENSCSIRST;
6106 #endif
6107 ahc_outb(ahc, SIMODE1, simode1);
6108 if (initiate_reset)
6109 ahc_reset_current_bus(ahc);
6110 ahc_clear_intstat(ahc);
6111 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6112 restart_needed = TRUE;
6113 }
6114
6115 /*
6116 * Clean up all the state information for the
6117 * pending transactions on this bus.
6118 */
6119 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6120 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6121 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6122
6123 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6124
6125 #ifdef AHC_TARGET_MODE
6126 /*
6127 * Send an immediate notify ccb to all target more peripheral
6128 * drivers affected by this action.
6129 */
6130 for (target = 0; target <= max_scsiid; target++) {
6131 struct ahc_tmode_tstate* tstate;
6132 u_int lun;
6133
6134 tstate = ahc->enabled_targets[target];
6135 if (tstate == NULL)
6136 continue;
6137 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6138 struct ahc_tmode_lstate* lstate;
6139
6140 lstate = tstate->enabled_luns[lun];
6141 if (lstate == NULL)
6142 continue;
6143
6144 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6145 EVENT_TYPE_BUS_RESET, /*arg*/0);
6146 ahc_send_lstate_events(ahc, lstate);
6147 }
6148 }
6149 #endif
6150 /* Notify the XPT that a bus reset occurred */
6151 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6152 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
6153
6154 /*
6155 * Revert to async/narrow transfers until we renegotiate.
6156 */
6157 for (target = 0; target <= max_scsiid; target++) {
6158 if (ahc->enabled_targets[target] == NULL)
6159 continue;
6160 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6161 struct ahc_devinfo devinfo;
6162
6163 ahc_compile_devinfo(&devinfo, target, initiator,
6164 CAM_LUN_WILDCARD,
6165 channel, ROLE_UNKNOWN);
6166 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6167 AHC_TRANS_CUR, /*paused*/TRUE);
6168 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6169 /*period*/0, /*offset*/0,
6170 /*ppr_options*/0, AHC_TRANS_CUR,
6171 /*paused*/TRUE);
6172 }
6173 }
6174
6175 if (restart_needed)
6176 ahc_restart(ahc);
6177 else
6178 ahc_unpause(ahc);
6179 return found;
6180 }
6181
6182 /***************************** Residual Processing ****************************/
6183 /*
6184 * Calculate the residual for a just completed SCB.
6185 */
6186 void
ahc_calc_residual(struct ahc_softc * ahc,struct scb * scb)6187 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6188 {
6189 struct hardware_scb *hscb;
6190 struct status_pkt *spkt;
6191 uint32_t sgptr;
6192 uint32_t resid_sgptr;
6193 uint32_t resid;
6194
6195 /*
6196 * 5 cases.
6197 * 1) No residual.
6198 * SG_RESID_VALID clear in sgptr.
6199 * 2) Transferless command
6200 * 3) Never performed any transfers.
6201 * sgptr has SG_FULL_RESID set.
6202 * 4) No residual but target did not
6203 * save data pointers after the
6204 * last transfer, so sgptr was
6205 * never updated.
6206 * 5) We have a partial residual.
6207 * Use residual_sgptr to determine
6208 * where we are.
6209 */
6210
6211 hscb = scb->hscb;
6212 sgptr = aic_le32toh(hscb->sgptr);
6213 if ((sgptr & SG_RESID_VALID) == 0)
6214 /* Case 1 */
6215 return;
6216 sgptr &= ~SG_RESID_VALID;
6217
6218 if ((sgptr & SG_LIST_NULL) != 0)
6219 /* Case 2 */
6220 return;
6221
6222 spkt = &hscb->shared_data.status;
6223 resid_sgptr = aic_le32toh(spkt->residual_sg_ptr);
6224 if ((sgptr & SG_FULL_RESID) != 0) {
6225 /* Case 3 */
6226 resid = aic_get_transfer_length(scb);
6227 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6228 /* Case 4 */
6229 return;
6230 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6231 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6232 /* NOTREACHED */
6233 return;
6234 } else {
6235 struct ahc_dma_seg *sg;
6236
6237 /*
6238 * Remainder of the SG where the transfer
6239 * stopped.
6240 */
6241 resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6242 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6243
6244 /* The residual sg_ptr always points to the next sg */
6245 sg--;
6246
6247 /*
6248 * Add up the contents of all residual
6249 * SG segments that are after the SG where
6250 * the transfer stopped.
6251 */
6252 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6253 sg++;
6254 resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
6255 }
6256 }
6257 if ((scb->flags & SCB_SENSE) == 0)
6258 aic_set_residual(scb, resid);
6259 else
6260 aic_set_sense_residual(scb, resid);
6261
6262 #ifdef AHC_DEBUG
6263 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6264 ahc_print_path(ahc, scb);
6265 printf("Handled %sResidual of %d bytes\n",
6266 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6267 }
6268 #endif
6269 }
6270
6271 /******************************* Target Mode **********************************/
6272 #ifdef AHC_TARGET_MODE
6273 /*
6274 * Add a target mode event to this lun's queue
6275 */
6276 static void
ahc_queue_lstate_event(struct ahc_softc * ahc,struct ahc_tmode_lstate * lstate,u_int initiator_id,u_int event_type,u_int event_arg)6277 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6278 u_int initiator_id, u_int event_type, u_int event_arg)
6279 {
6280 struct ahc_tmode_event *event;
6281 int pending;
6282
6283 xpt_freeze_devq(lstate->path, /*count*/1);
6284 if (lstate->event_w_idx >= lstate->event_r_idx)
6285 pending = lstate->event_w_idx - lstate->event_r_idx;
6286 else
6287 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6288 - (lstate->event_r_idx - lstate->event_w_idx);
6289
6290 if (event_type == EVENT_TYPE_BUS_RESET
6291 || event_type == MSG_BUS_DEV_RESET) {
6292 /*
6293 * Any earlier events are irrelevant, so reset our buffer.
6294 * This has the effect of allowing us to deal with reset
6295 * floods (an external device holding down the reset line)
6296 * without losing the event that is really interesting.
6297 */
6298 lstate->event_r_idx = 0;
6299 lstate->event_w_idx = 0;
6300 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6301 }
6302
6303 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6304 xpt_print_path(lstate->path);
6305 printf("immediate event %x:%x lost\n",
6306 lstate->event_buffer[lstate->event_r_idx].event_type,
6307 lstate->event_buffer[lstate->event_r_idx].event_arg);
6308 lstate->event_r_idx++;
6309 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6310 lstate->event_r_idx = 0;
6311 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6312 }
6313
6314 event = &lstate->event_buffer[lstate->event_w_idx];
6315 event->initiator_id = initiator_id;
6316 event->event_type = event_type;
6317 event->event_arg = event_arg;
6318 lstate->event_w_idx++;
6319 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6320 lstate->event_w_idx = 0;
6321 }
6322
6323 /*
6324 * Send any target mode events queued up waiting
6325 * for immediate notify resources.
6326 */
6327 void
ahc_send_lstate_events(struct ahc_softc * ahc,struct ahc_tmode_lstate * lstate)6328 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6329 {
6330 struct ccb_hdr *ccbh;
6331 struct ccb_immediate_notify *inot;
6332
6333 while (lstate->event_r_idx != lstate->event_w_idx
6334 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6335 struct ahc_tmode_event *event;
6336
6337 event = &lstate->event_buffer[lstate->event_r_idx];
6338 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6339 inot = (struct ccb_immediate_notify *)ccbh;
6340 switch (event->event_type) {
6341 case EVENT_TYPE_BUS_RESET:
6342 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6343 break;
6344 default:
6345 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6346 inot->arg = event->event_type;
6347 inot->seq_id = event->event_arg;
6348 break;
6349 }
6350 inot->initiator_id = event->initiator_id;
6351 xpt_done((union ccb *)inot);
6352 lstate->event_r_idx++;
6353 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6354 lstate->event_r_idx = 0;
6355 }
6356 }
6357 #endif
6358
6359 /******************** Sequencer Program Patching/Download *********************/
6360
6361 #ifdef AHC_DUMP_SEQ
6362 void
ahc_dumpseq(struct ahc_softc * ahc)6363 ahc_dumpseq(struct ahc_softc* ahc)
6364 {
6365 int i;
6366
6367 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6368 ahc_outb(ahc, SEQADDR0, 0);
6369 ahc_outb(ahc, SEQADDR1, 0);
6370 for (i = 0; i < ahc->instruction_ram_size; i++) {
6371 uint8_t ins_bytes[4];
6372
6373 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6374 printf("0x%08x\n", ins_bytes[0] << 24
6375 | ins_bytes[1] << 16
6376 | ins_bytes[2] << 8
6377 | ins_bytes[3]);
6378 }
6379 }
6380 #endif
6381
6382 static int
ahc_loadseq(struct ahc_softc * ahc)6383 ahc_loadseq(struct ahc_softc *ahc)
6384 {
6385 struct cs cs_table[num_critical_sections];
6386 u_int begin_set[num_critical_sections];
6387 u_int end_set[num_critical_sections];
6388 struct patch *cur_patch;
6389 u_int cs_count;
6390 u_int cur_cs;
6391 u_int i;
6392 u_int skip_addr;
6393 u_int sg_prefetch_cnt;
6394 int downloaded;
6395 uint8_t download_consts[7];
6396
6397 /*
6398 * Start out with 0 critical sections
6399 * that apply to this firmware load.
6400 */
6401 cs_count = 0;
6402 cur_cs = 0;
6403 memset(begin_set, 0, sizeof(begin_set));
6404 memset(end_set, 0, sizeof(end_set));
6405
6406 /* Setup downloadable constant table */
6407 download_consts[QOUTFIFO_OFFSET] = 0;
6408 if (ahc->targetcmds != NULL)
6409 download_consts[QOUTFIFO_OFFSET] += 32;
6410 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6411 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6412 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6413 sg_prefetch_cnt = ahc->pci_cachesize;
6414 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6415 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6416 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6417 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6418 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6419
6420 cur_patch = patches;
6421 downloaded = 0;
6422 skip_addr = 0;
6423 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6424 ahc_outb(ahc, SEQADDR0, 0);
6425 ahc_outb(ahc, SEQADDR1, 0);
6426
6427 for (i = 0; i < sizeof(seqprog)/4; i++) {
6428 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6429 /*
6430 * Don't download this instruction as it
6431 * is in a patch that was removed.
6432 */
6433 continue;
6434 }
6435
6436 if (downloaded == ahc->instruction_ram_size) {
6437 /*
6438 * We're about to exceed the instruction
6439 * storage capacity for this chip. Fail
6440 * the load.
6441 */
6442 printf("\n%s: Program too large for instruction memory "
6443 "size of %d!\n", ahc_name(ahc),
6444 ahc->instruction_ram_size);
6445 return (ENOMEM);
6446 }
6447
6448 /*
6449 * Move through the CS table until we find a CS
6450 * that might apply to this instruction.
6451 */
6452 for (; cur_cs < num_critical_sections; cur_cs++) {
6453 if (critical_sections[cur_cs].end <= i) {
6454 if (begin_set[cs_count] == TRUE
6455 && end_set[cs_count] == FALSE) {
6456 cs_table[cs_count].end = downloaded;
6457 end_set[cs_count] = TRUE;
6458 cs_count++;
6459 }
6460 continue;
6461 }
6462 if (critical_sections[cur_cs].begin <= i
6463 && begin_set[cs_count] == FALSE) {
6464 cs_table[cs_count].begin = downloaded;
6465 begin_set[cs_count] = TRUE;
6466 }
6467 break;
6468 }
6469 ahc_download_instr(ahc, i, download_consts);
6470 downloaded++;
6471 }
6472
6473 ahc->num_critical_sections = cs_count;
6474 if (cs_count != 0) {
6475 cs_count *= sizeof(struct cs);
6476 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6477 if (ahc->critical_sections == NULL)
6478 panic("ahc_loadseq: Could not malloc");
6479 memcpy(ahc->critical_sections, cs_table, cs_count);
6480 }
6481 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6482
6483 if (bootverbose) {
6484 printf(" %d instructions downloaded\n", downloaded);
6485 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6486 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6487 }
6488 return (0);
6489 }
6490
6491 static int
ahc_check_patch(struct ahc_softc * ahc,struct patch ** start_patch,u_int start_instr,u_int * skip_addr)6492 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6493 u_int start_instr, u_int *skip_addr)
6494 {
6495 struct patch *cur_patch;
6496 struct patch *last_patch;
6497 u_int num_patches;
6498
6499 num_patches = sizeof(patches)/sizeof(struct patch);
6500 last_patch = &patches[num_patches];
6501 cur_patch = *start_patch;
6502
6503 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6504 if (cur_patch->patch_func(ahc) == 0) {
6505 /* Start rejecting code */
6506 *skip_addr = start_instr + cur_patch->skip_instr;
6507 cur_patch += cur_patch->skip_patch;
6508 } else {
6509 /* Accepted this patch. Advance to the next
6510 * one and wait for our instruction pointer to
6511 * hit this point.
6512 */
6513 cur_patch++;
6514 }
6515 }
6516
6517 *start_patch = cur_patch;
6518 if (start_instr < *skip_addr)
6519 /* Still skipping */
6520 return (0);
6521
6522 return (1);
6523 }
6524
6525 static void
ahc_download_instr(struct ahc_softc * ahc,u_int instrptr,uint8_t * dconsts)6526 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6527 {
6528 union ins_formats instr;
6529 struct ins_format1 *fmt1_ins;
6530 struct ins_format3 *fmt3_ins;
6531 u_int opcode;
6532
6533 /*
6534 * The firmware is always compiled into a little endian format.
6535 */
6536 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6537
6538 fmt1_ins = &instr.format1;
6539 fmt3_ins = NULL;
6540
6541 /* Pull the opcode */
6542 opcode = instr.format1.opcode;
6543 switch (opcode) {
6544 case AIC_OP_JMP:
6545 case AIC_OP_JC:
6546 case AIC_OP_JNC:
6547 case AIC_OP_CALL:
6548 case AIC_OP_JNE:
6549 case AIC_OP_JNZ:
6550 case AIC_OP_JE:
6551 case AIC_OP_JZ:
6552 {
6553 struct patch *cur_patch;
6554 int address_offset;
6555 u_int address;
6556 u_int skip_addr;
6557 u_int i;
6558
6559 fmt3_ins = &instr.format3;
6560 address_offset = 0;
6561 address = fmt3_ins->address;
6562 cur_patch = patches;
6563 skip_addr = 0;
6564
6565 for (i = 0; i < address;) {
6566 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6567
6568 if (skip_addr > i) {
6569 int end_addr;
6570
6571 end_addr = MIN(address, skip_addr);
6572 address_offset += end_addr - i;
6573 i = skip_addr;
6574 } else {
6575 i++;
6576 }
6577 }
6578 address -= address_offset;
6579 fmt3_ins->address = address;
6580 /* FALLTHROUGH */
6581 }
6582 case AIC_OP_OR:
6583 case AIC_OP_AND:
6584 case AIC_OP_XOR:
6585 case AIC_OP_ADD:
6586 case AIC_OP_ADC:
6587 case AIC_OP_BMOV:
6588 if (fmt1_ins->parity != 0) {
6589 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6590 }
6591 fmt1_ins->parity = 0;
6592 if ((ahc->features & AHC_CMD_CHAN) == 0
6593 && opcode == AIC_OP_BMOV) {
6594 /*
6595 * Block move was added at the same time
6596 * as the command channel. Verify that
6597 * this is only a move of a single element
6598 * and convert the BMOV to a MOV
6599 * (AND with an immediate of FF).
6600 */
6601 if (fmt1_ins->immediate != 1)
6602 panic("%s: BMOV not supported\n",
6603 ahc_name(ahc));
6604 fmt1_ins->opcode = AIC_OP_AND;
6605 fmt1_ins->immediate = 0xff;
6606 }
6607 /* FALLTHROUGH */
6608 case AIC_OP_ROL:
6609 if ((ahc->features & AHC_ULTRA2) != 0) {
6610 int i, count;
6611
6612 /* Calculate odd parity for the instruction */
6613 for (i = 0, count = 0; i < 31; i++) {
6614 uint32_t mask;
6615
6616 mask = 0x01 << i;
6617 if ((instr.integer & mask) != 0)
6618 count++;
6619 }
6620 if ((count & 0x01) == 0)
6621 instr.format1.parity = 1;
6622 } else {
6623 /* Compress the instruction for older sequencers */
6624 if (fmt3_ins != NULL) {
6625 instr.integer =
6626 fmt3_ins->immediate
6627 | (fmt3_ins->source << 8)
6628 | (fmt3_ins->address << 16)
6629 | (fmt3_ins->opcode << 25);
6630 } else {
6631 instr.integer =
6632 fmt1_ins->immediate
6633 | (fmt1_ins->source << 8)
6634 | (fmt1_ins->destination << 16)
6635 | (fmt1_ins->ret << 24)
6636 | (fmt1_ins->opcode << 25);
6637 }
6638 }
6639 /* The sequencer is a little endian cpu */
6640 instr.integer = aic_htole32(instr.integer);
6641 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6642 break;
6643 default:
6644 panic("Unknown opcode encountered in seq program");
6645 break;
6646 }
6647 }
6648
6649 int
ahc_print_register(ahc_reg_parse_entry_t * table,u_int num_entries,const char * name,u_int address,u_int value,u_int * cur_column,u_int wrap_point)6650 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6651 const char *name, u_int address, u_int value,
6652 u_int *cur_column, u_int wrap_point)
6653 {
6654 int printed;
6655 u_int printed_mask;
6656 u_int dummy_column;
6657
6658 if (cur_column == NULL) {
6659 dummy_column = 0;
6660 cur_column = &dummy_column;
6661 }
6662
6663 if (*cur_column >= wrap_point) {
6664 printf("\n");
6665 *cur_column = 0;
6666 }
6667 printed = printf("%s[0x%x]", name, value);
6668 if (table == NULL) {
6669 printed += printf(" ");
6670 *cur_column += printed;
6671 return (printed);
6672 }
6673 printed_mask = 0;
6674 while (printed_mask != 0xFF) {
6675 int entry;
6676
6677 for (entry = 0; entry < num_entries; entry++) {
6678 if (((value & table[entry].mask)
6679 != table[entry].value)
6680 || ((printed_mask & table[entry].mask)
6681 == table[entry].mask))
6682 continue;
6683
6684 printed += printf("%s%s",
6685 printed_mask == 0 ? ":(" : "|",
6686 table[entry].name);
6687 printed_mask |= table[entry].mask;
6688
6689 break;
6690 }
6691 if (entry >= num_entries)
6692 break;
6693 }
6694 if (printed_mask != 0)
6695 printed += printf(") ");
6696 else
6697 printed += printf(" ");
6698 if (cur_column != NULL)
6699 *cur_column += printed;
6700 return (printed);
6701 }
6702
6703 void
ahc_dump_card_state(struct ahc_softc * ahc)6704 ahc_dump_card_state(struct ahc_softc *ahc)
6705 {
6706 struct scb *scb;
6707 struct scb_tailq *untagged_q;
6708 u_int cur_col;
6709 int paused;
6710 int target;
6711 int maxtarget;
6712 int i;
6713 uint8_t last_phase;
6714 uint8_t qinpos;
6715 uint8_t qintail;
6716 uint8_t qoutpos;
6717 uint8_t scb_index;
6718 uint8_t saved_scbptr;
6719
6720 if (ahc_is_paused(ahc)) {
6721 paused = 1;
6722 } else {
6723 paused = 0;
6724 ahc_pause(ahc);
6725 }
6726
6727 saved_scbptr = ahc_inb(ahc, SCBPTR);
6728 last_phase = ahc_inb(ahc, LASTPHASE);
6729 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6730 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6731 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6732 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6733 if (paused)
6734 printf("Card was paused\n");
6735 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6736 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6737 ahc_inb(ahc, ARG_2));
6738 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6739 ahc_inb(ahc, SCBPTR));
6740 cur_col = 0;
6741 if ((ahc->features & AHC_DT) != 0)
6742 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6743 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6744 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6745 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6746 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6747 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6748 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6749 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6750 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6751 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6752 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6753 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6754 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6755 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6756 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6757 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6758 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6759 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6760 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6761 if (cur_col != 0)
6762 printf("\n");
6763 printf("STACK:");
6764 for (i = 0; i < STACK_SIZE; i++)
6765 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6766 printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6767 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6768 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6769 /* QINFIFO */
6770 printf("QINFIFO entries: ");
6771 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6772 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6773 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6774 } else
6775 qinpos = ahc_inb(ahc, QINPOS);
6776 qintail = ahc->qinfifonext;
6777 while (qinpos != qintail) {
6778 printf("%d ", ahc->qinfifo[qinpos]);
6779 qinpos++;
6780 }
6781 printf("\n");
6782
6783 printf("Waiting Queue entries: ");
6784 scb_index = ahc_inb(ahc, WAITING_SCBH);
6785 i = 0;
6786 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6787 ahc_outb(ahc, SCBPTR, scb_index);
6788 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6789 scb_index = ahc_inb(ahc, SCB_NEXT);
6790 }
6791 printf("\n");
6792
6793 printf("Disconnected Queue entries: ");
6794 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6795 i = 0;
6796 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6797 ahc_outb(ahc, SCBPTR, scb_index);
6798 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6799 scb_index = ahc_inb(ahc, SCB_NEXT);
6800 }
6801 printf("\n");
6802
6803 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6804 printf("QOUTFIFO entries: ");
6805 qoutpos = ahc->qoutfifonext;
6806 i = 0;
6807 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6808 printf("%d ", ahc->qoutfifo[qoutpos]);
6809 qoutpos++;
6810 }
6811 printf("\n");
6812
6813 printf("Sequencer Free SCB List: ");
6814 scb_index = ahc_inb(ahc, FREE_SCBH);
6815 i = 0;
6816 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6817 ahc_outb(ahc, SCBPTR, scb_index);
6818 printf("%d ", scb_index);
6819 scb_index = ahc_inb(ahc, SCB_NEXT);
6820 }
6821 printf("\n");
6822
6823 printf("Sequencer SCB Info: ");
6824 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6825 ahc_outb(ahc, SCBPTR, i);
6826 cur_col = printf("\n%3d ", i);
6827
6828 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6829 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6830 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6831 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6832 }
6833 printf("\n");
6834
6835 printf("Pending list: ");
6836 i = 0;
6837 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6838 if (i++ > 256)
6839 break;
6840 cur_col = printf("\n%3d ", scb->hscb->tag);
6841 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6842 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6843 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6844 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6845 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6846 printf("(");
6847 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6848 &cur_col, 60);
6849 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6850 printf(")");
6851 }
6852 }
6853 printf("\n");
6854
6855 printf("Kernel Free SCB list: ");
6856 i = 0;
6857 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6858 if (i++ > 256)
6859 break;
6860 printf("%d ", scb->hscb->tag);
6861 }
6862 printf("\n");
6863
6864 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6865 for (target = 0; target <= maxtarget; target++) {
6866 untagged_q = &ahc->untagged_queues[target];
6867 if (TAILQ_FIRST(untagged_q) == NULL)
6868 continue;
6869 printf("Untagged Q(%d): ", target);
6870 i = 0;
6871 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6872 if (i++ > 256)
6873 break;
6874 printf("%d ", scb->hscb->tag);
6875 }
6876 printf("\n");
6877 }
6878
6879 ahc_platform_dump_card_state(ahc);
6880 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6881 ahc_outb(ahc, SCBPTR, saved_scbptr);
6882 if (paused == 0)
6883 ahc_unpause(ahc);
6884 }
6885
6886 /*************************** Timeout Handling *********************************/
6887 void
ahc_timeout(struct scb * scb)6888 ahc_timeout(struct scb *scb)
6889 {
6890 struct ahc_softc *ahc;
6891
6892 ahc = scb->ahc_softc;
6893 if ((scb->flags & SCB_ACTIVE) != 0) {
6894 if ((scb->flags & SCB_TIMEDOUT) == 0) {
6895 LIST_INSERT_HEAD(&ahc->timedout_scbs, scb,
6896 timedout_links);
6897 scb->flags |= SCB_TIMEDOUT;
6898 }
6899 ahc_wakeup_recovery_thread(ahc);
6900 }
6901 }
6902
6903 /*
6904 * Re-schedule a timeout for the passed in SCB if we determine that some
6905 * other SCB is in the process of recovery or an SCB with a longer
6906 * timeout is still pending. Limit our search to just "other_scb"
6907 * if it is non-NULL.
6908 */
6909 static int
ahc_other_scb_timeout(struct ahc_softc * ahc,struct scb * scb,struct scb * other_scb)6910 ahc_other_scb_timeout(struct ahc_softc *ahc, struct scb *scb,
6911 struct scb *other_scb)
6912 {
6913 u_int newtimeout;
6914 int found;
6915
6916 ahc_print_path(ahc, scb);
6917 printf("Other SCB Timeout%s",
6918 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
6919 ? " again\n" : "\n");
6920
6921 newtimeout = aic_get_timeout(scb);
6922 scb->flags |= SCB_OTHERTCL_TIMEOUT;
6923 found = 0;
6924 if (other_scb != NULL) {
6925 if ((other_scb->flags
6926 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6927 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6928 found++;
6929 newtimeout = MAX(aic_get_timeout(other_scb),
6930 newtimeout);
6931 }
6932 } else {
6933 LIST_FOREACH(other_scb, &ahc->pending_scbs, pending_links) {
6934 if ((other_scb->flags
6935 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
6936 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
6937 found++;
6938 newtimeout =
6939 MAX(aic_get_timeout(other_scb),
6940 newtimeout);
6941 }
6942 }
6943 }
6944
6945 if (found != 0)
6946 aic_scb_timer_reset(scb, newtimeout);
6947 else {
6948 ahc_print_path(ahc, scb);
6949 printf("No other SCB worth waiting for...\n");
6950 }
6951
6952 return (found != 0);
6953 }
6954
6955 /*
6956 * ahc_recover_commands determines if any of the commands that have currently
6957 * timedout are the root cause for this timeout. Innocent commands are given
6958 * a new timeout while we wait for the command executing on the bus to timeout.
6959 * This routine is invoked from a thread context so we are allowed to sleep.
6960 * Our lock is not held on entry.
6961 */
6962 void
ahc_recover_commands(struct ahc_softc * ahc)6963 ahc_recover_commands(struct ahc_softc *ahc)
6964 {
6965 struct scb *scb;
6966 int found;
6967 int restart_needed;
6968 u_int last_phase;
6969
6970 /*
6971 * Pause the controller and manually flush any
6972 * commands that have just completed but that our
6973 * interrupt handler has yet to see.
6974 */
6975 ahc_pause_and_flushwork(ahc);
6976
6977 if (LIST_EMPTY(&ahc->timedout_scbs) != 0) {
6978 /*
6979 * The timedout commands have already
6980 * completed. This typically means
6981 * that either the timeout value was on
6982 * the hairy edge of what the device
6983 * requires or - more likely - interrupts
6984 * are not happening.
6985 */
6986 printf("%s: Timedout SCBs already complete. "
6987 "Interrupts may not be functioning.\n", ahc_name(ahc));
6988 ahc_unpause(ahc);
6989 return;
6990 }
6991
6992 restart_needed = 0;
6993 printf("%s: Recovery Initiated\n", ahc_name(ahc));
6994 ahc_dump_card_state(ahc);
6995
6996 last_phase = ahc_inb(ahc, LASTPHASE);
6997 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
6998 u_int active_scb_index;
6999 u_int saved_scbptr;
7000 int target;
7001 int lun;
7002 int i;
7003 char channel;
7004
7005 target = SCB_GET_TARGET(ahc, scb);
7006 channel = SCB_GET_CHANNEL(ahc, scb);
7007 lun = SCB_GET_LUN(scb);
7008
7009 ahc_print_path(ahc, scb);
7010 printf("SCB 0x%x - timed out\n", scb->hscb->tag);
7011 if (scb->sg_count > 0) {
7012 for (i = 0; i < scb->sg_count; i++) {
7013 printf("sg[%d] - Addr 0x%x : Length %d\n",
7014 i,
7015 scb->sg_list[i].addr,
7016 scb->sg_list[i].len & AHC_SG_LEN_MASK);
7017 }
7018 }
7019 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
7020 /*
7021 * Been down this road before.
7022 * Do a full bus reset.
7023 */
7024 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
7025 bus_reset:
7026 found = ahc_reset_channel(ahc, channel,
7027 /*Initiate Reset*/TRUE);
7028 printf("%s: Issued Channel %c Bus Reset. "
7029 "%d SCBs aborted\n", ahc_name(ahc), channel,
7030 found);
7031 continue;
7032 }
7033
7034 /*
7035 * Remove the command from the timedout list in
7036 * preparation for requeing it.
7037 */
7038 LIST_REMOVE(scb, timedout_links);
7039 scb->flags &= ~SCB_TIMEDOUT;
7040
7041 /*
7042 * If we are a target, transition to bus free and report
7043 * the timeout.
7044 *
7045 * The target/initiator that is holding up the bus may not
7046 * be the same as the one that triggered this timeout
7047 * (different commands have different timeout lengths).
7048 * If the bus is idle and we are actiing as the initiator
7049 * for this request, queue a BDR message to the timed out
7050 * target. Otherwise, if the timed out transaction is
7051 * active:
7052 * Initiator transaction:
7053 * Stuff the message buffer with a BDR message and assert
7054 * ATN in the hopes that the target will let go of the bus
7055 * and go to the mesgout phase. If this fails, we'll
7056 * get another timeout 2 seconds later which will attempt
7057 * a bus reset.
7058 *
7059 * Target transaction:
7060 * Transition to BUS FREE and report the error.
7061 * It's good to be the target!
7062 */
7063 saved_scbptr = ahc_inb(ahc, SCBPTR);
7064 active_scb_index = ahc_inb(ahc, SCB_TAG);
7065
7066 if ((ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) == 0
7067 && (active_scb_index < ahc->scb_data->numscbs)) {
7068 struct scb *active_scb;
7069
7070 /*
7071 * If the active SCB is not us, assume that
7072 * the active SCB has a longer timeout than
7073 * the timedout SCB, and wait for the active
7074 * SCB to timeout.
7075 */
7076 active_scb = ahc_lookup_scb(ahc, active_scb_index);
7077 if (active_scb != scb) {
7078 if (ahc_other_scb_timeout(ahc, scb,
7079 active_scb) == 0)
7080 goto bus_reset;
7081 continue;
7082 }
7083
7084 /* It's us */
7085 if ((scb->flags & SCB_TARGET_SCB) != 0) {
7086 /*
7087 * Send back any queued up transactions
7088 * and properly record the error condition.
7089 */
7090 ahc_abort_scbs(ahc, SCB_GET_TARGET(ahc, scb),
7091 SCB_GET_CHANNEL(ahc, scb),
7092 SCB_GET_LUN(scb),
7093 scb->hscb->tag,
7094 ROLE_TARGET,
7095 CAM_CMD_TIMEOUT);
7096
7097 /* Will clear us from the bus */
7098 restart_needed = 1;
7099 break;
7100 }
7101
7102 ahc_set_recoveryscb(ahc, active_scb);
7103 ahc_outb(ahc, MSG_OUT, HOST_MSG);
7104 ahc_outb(ahc, SCSISIGO, last_phase|ATNO);
7105 ahc_print_path(ahc, active_scb);
7106 printf("BDR message in message buffer\n");
7107 active_scb->flags |= SCB_DEVICE_RESET;
7108 aic_scb_timer_reset(scb, 2 * 1000);
7109 } else if (last_phase != P_BUSFREE
7110 && (ahc_inb(ahc, SSTAT1) & REQINIT) == 0) {
7111 /*
7112 * SCB is not identified, there
7113 * is no pending REQ, and the sequencer
7114 * has not seen a busfree. Looks like
7115 * a stuck connection waiting to
7116 * go busfree. Reset the bus.
7117 */
7118 printf("%s: Connection stuck awaiting busfree or "
7119 "Identify Msg.\n", ahc_name(ahc));
7120 goto bus_reset;
7121 } else {
7122 int disconnected;
7123
7124 if (last_phase != P_BUSFREE
7125 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) {
7126 /* Hung target selection. Goto busfree */
7127 printf("%s: Hung target selection\n",
7128 ahc_name(ahc));
7129 restart_needed = 1;
7130 break;
7131 }
7132
7133 /* XXX Shouldn't panic. Just punt instead? */
7134 if ((scb->flags & SCB_TARGET_SCB) != 0)
7135 panic("Timed-out target SCB but bus idle");
7136
7137 if (ahc_search_qinfifo(ahc, target, channel, lun,
7138 scb->hscb->tag, ROLE_INITIATOR,
7139 /*status*/0, SEARCH_COUNT) > 0) {
7140 disconnected = FALSE;
7141 } else {
7142 disconnected = TRUE;
7143 }
7144
7145 if (disconnected) {
7146 ahc_set_recoveryscb(ahc, scb);
7147 /*
7148 * Actually re-queue this SCB in an attempt
7149 * to select the device before it reconnects.
7150 * In either case (selection or reselection),
7151 * we will now issue a target reset to the
7152 * timed-out device.
7153 *
7154 * Set the MK_MESSAGE control bit indicating
7155 * that we desire to send a message. We
7156 * also set the disconnected flag since
7157 * in the paging case there is no guarantee
7158 * that our SCB control byte matches the
7159 * version on the card. We don't want the
7160 * sequencer to abort the command thinking
7161 * an unsolicited reselection occurred.
7162 */
7163 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
7164 scb->flags |= SCB_DEVICE_RESET;
7165
7166 /*
7167 * Remove any cached copy of this SCB in the
7168 * disconnected list in preparation for the
7169 * queuing of our abort SCB. We use the
7170 * same element in the SCB, SCB_NEXT, for
7171 * both the qinfifo and the disconnected list.
7172 */
7173 ahc_search_disc_list(ahc, target, channel,
7174 lun, scb->hscb->tag,
7175 /*stop_on_first*/TRUE,
7176 /*remove*/TRUE,
7177 /*save_state*/FALSE);
7178
7179 /*
7180 * In the non-paging case, the sequencer will
7181 * never re-reference the in-core SCB.
7182 * To make sure we are notified during
7183 * reselection, set the MK_MESSAGE flag in
7184 * the card's copy of the SCB.
7185 */
7186 if ((ahc->flags & AHC_PAGESCBS) == 0) {
7187 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
7188 ahc_outb(ahc, SCB_CONTROL,
7189 ahc_inb(ahc, SCB_CONTROL)
7190 | MK_MESSAGE);
7191 }
7192
7193 /*
7194 * Clear out any entries in the QINFIFO first
7195 * so we are the next SCB for this target
7196 * to run.
7197 */
7198 ahc_search_qinfifo(ahc,
7199 SCB_GET_TARGET(ahc, scb),
7200 channel, SCB_GET_LUN(scb),
7201 SCB_LIST_NULL,
7202 ROLE_INITIATOR,
7203 CAM_REQUEUE_REQ,
7204 SEARCH_COMPLETE);
7205 ahc_print_path(ahc, scb);
7206 printf("Queuing a BDR SCB\n");
7207 ahc_qinfifo_requeue_tail(ahc, scb);
7208 ahc_outb(ahc, SCBPTR, saved_scbptr);
7209 aic_scb_timer_reset(scb, 2 * 1000);
7210 } else {
7211 /* Go "immediately" to the bus reset */
7212 /* This shouldn't happen */
7213 ahc_set_recoveryscb(ahc, scb);
7214 ahc_print_path(ahc, scb);
7215 printf("SCB %d: Immediate reset. "
7216 "Flags = 0x%x\n", scb->hscb->tag,
7217 scb->flags);
7218 goto bus_reset;
7219 }
7220 }
7221 break;
7222 }
7223
7224 /*
7225 * Any remaining SCBs were not the "culprit", so remove
7226 * them from the timeout list. The timer for these commands
7227 * will be reset once the recovery SCB completes.
7228 */
7229 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) {
7230 LIST_REMOVE(scb, timedout_links);
7231 scb->flags &= ~SCB_TIMEDOUT;
7232 }
7233
7234 if (restart_needed)
7235 ahc_restart(ahc);
7236 else
7237 ahc_unpause(ahc);
7238 }
7239
7240 /************************* Target Mode ****************************************/
7241 #ifdef AHC_TARGET_MODE
7242 cam_status
ahc_find_tmode_devs(struct ahc_softc * ahc,struct cam_sim * sim,union ccb * ccb,struct ahc_tmode_tstate ** tstate,struct ahc_tmode_lstate ** lstate,int notfound_failure)7243 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
7244 struct ahc_tmode_tstate **tstate,
7245 struct ahc_tmode_lstate **lstate,
7246 int notfound_failure)
7247 {
7248
7249 if ((ahc->features & AHC_TARGETMODE) == 0)
7250 return (CAM_REQ_INVALID);
7251
7252 /*
7253 * Handle the 'black hole' device that sucks up
7254 * requests to unattached luns on enabled targets.
7255 */
7256 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
7257 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
7258 *tstate = NULL;
7259 *lstate = ahc->black_hole;
7260 } else {
7261 u_int max_id;
7262
7263 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
7264 if (ccb->ccb_h.target_id > max_id)
7265 return (CAM_TID_INVALID);
7266
7267 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
7268 return (CAM_LUN_INVALID);
7269
7270 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
7271 *lstate = NULL;
7272 if (*tstate != NULL)
7273 *lstate =
7274 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
7275 }
7276
7277 if (notfound_failure != 0 && *lstate == NULL)
7278 return (CAM_PATH_INVALID);
7279
7280 return (CAM_REQ_CMP);
7281 }
7282
7283 void
ahc_handle_en_lun(struct ahc_softc * ahc,struct cam_sim * sim,union ccb * ccb)7284 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
7285 {
7286 struct ahc_tmode_tstate *tstate;
7287 struct ahc_tmode_lstate *lstate;
7288 struct ccb_en_lun *cel;
7289 cam_status status;
7290 u_int target;
7291 u_int lun;
7292 u_int target_mask;
7293 u_int our_id;
7294 int error;
7295 char channel;
7296
7297 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
7298 /*notfound_failure*/FALSE);
7299
7300 if (status != CAM_REQ_CMP) {
7301 ccb->ccb_h.status = status;
7302 return;
7303 }
7304
7305 if (cam_sim_bus(sim) == 0)
7306 our_id = ahc->our_id;
7307 else
7308 our_id = ahc->our_id_b;
7309
7310 if (ccb->ccb_h.target_id != our_id
7311 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7312 /*
7313 * our_id represents our initiator ID, or
7314 * the ID of the first target to have an
7315 * enabled lun in target mode. There are
7316 * two cases that may preclude enabling a
7317 * target id other than our_id.
7318 *
7319 * o our_id is for an active initiator role.
7320 * Since the hardware does not support
7321 * reselections to the initiator role at
7322 * anything other than our_id, and our_id
7323 * is used by the hardware to indicate the
7324 * ID to use for both select-out and
7325 * reselect-out operations, the only target
7326 * ID we can support in this mode is our_id.
7327 *
7328 * o The MULTARGID feature is not available and
7329 * a previous target mode ID has been enabled.
7330 */
7331 if ((ahc->features & AHC_MULTIROLE) != 0) {
7332 if ((ahc->features & AHC_MULTI_TID) != 0
7333 && (ahc->flags & AHC_INITIATORROLE) != 0) {
7334 /*
7335 * Only allow additional targets if
7336 * the initiator role is disabled.
7337 * The hardware cannot handle a re-select-in
7338 * on the initiator id during a re-select-out
7339 * on a different target id.
7340 */
7341 status = CAM_TID_INVALID;
7342 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
7343 || ahc->enabled_luns > 0) {
7344 /*
7345 * Only allow our target id to change
7346 * if the initiator role is not configured
7347 * and there are no enabled luns which
7348 * are attached to the currently registered
7349 * scsi id.
7350 */
7351 status = CAM_TID_INVALID;
7352 }
7353 } else if ((ahc->features & AHC_MULTI_TID) == 0
7354 && ahc->enabled_luns > 0) {
7355 status = CAM_TID_INVALID;
7356 }
7357 }
7358
7359 if (status != CAM_REQ_CMP) {
7360 ccb->ccb_h.status = status;
7361 return;
7362 }
7363
7364 /*
7365 * We now have an id that is valid.
7366 * If we aren't in target mode, switch modes.
7367 */
7368 if ((ahc->flags & AHC_TARGETROLE) == 0
7369 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7370 ahc_flag saved_flags;
7371
7372 printf("Configuring Target Mode\n");
7373 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
7374 ccb->ccb_h.status = CAM_BUSY;
7375 return;
7376 }
7377 saved_flags = ahc->flags;
7378 ahc->flags |= AHC_TARGETROLE;
7379 if ((ahc->features & AHC_MULTIROLE) == 0)
7380 ahc->flags &= ~AHC_INITIATORROLE;
7381 ahc_pause(ahc);
7382 error = ahc_loadseq(ahc);
7383 if (error != 0) {
7384 /*
7385 * Restore original configuration and notify
7386 * the caller that we cannot support target mode.
7387 * Since the adapter started out in this
7388 * configuration, the firmware load will succeed,
7389 * so there is no point in checking ahc_loadseq's
7390 * return value.
7391 */
7392 ahc->flags = saved_flags;
7393 (void)ahc_loadseq(ahc);
7394 ahc_restart(ahc);
7395 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
7396 return;
7397 }
7398 ahc_restart(ahc);
7399 }
7400 cel = &ccb->cel;
7401 target = ccb->ccb_h.target_id;
7402 lun = ccb->ccb_h.target_lun;
7403 channel = SIM_CHANNEL(ahc, sim);
7404 target_mask = 0x01 << target;
7405 if (channel == 'B')
7406 target_mask <<= 8;
7407
7408 if (cel->enable != 0) {
7409 u_int scsiseq;
7410
7411 /* Are we already enabled?? */
7412 if (lstate != NULL) {
7413 xpt_print_path(ccb->ccb_h.path);
7414 printf("Lun already enabled\n");
7415 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7416 return;
7417 }
7418
7419 if (cel->grp6_len != 0
7420 || cel->grp7_len != 0) {
7421 /*
7422 * Don't (yet?) support vendor
7423 * specific commands.
7424 */
7425 ccb->ccb_h.status = CAM_REQ_INVALID;
7426 printf("Non-zero Group Codes\n");
7427 return;
7428 }
7429
7430 /*
7431 * Seems to be okay.
7432 * Setup our data structures.
7433 */
7434 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7435 tstate = ahc_alloc_tstate(ahc, target, channel);
7436 if (tstate == NULL) {
7437 xpt_print_path(ccb->ccb_h.path);
7438 printf("Couldn't allocate tstate\n");
7439 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7440 return;
7441 }
7442 }
7443 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
7444 if (lstate == NULL) {
7445 xpt_print_path(ccb->ccb_h.path);
7446 printf("Couldn't allocate lstate\n");
7447 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7448 return;
7449 }
7450 memset(lstate, 0, sizeof(*lstate));
7451 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7452 xpt_path_path_id(ccb->ccb_h.path),
7453 xpt_path_target_id(ccb->ccb_h.path),
7454 xpt_path_lun_id(ccb->ccb_h.path));
7455 if (status != CAM_REQ_CMP) {
7456 free(lstate, M_DEVBUF);
7457 xpt_print_path(ccb->ccb_h.path);
7458 printf("Couldn't allocate path\n");
7459 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7460 return;
7461 }
7462 SLIST_INIT(&lstate->accept_tios);
7463 SLIST_INIT(&lstate->immed_notifies);
7464 ahc_pause(ahc);
7465 if (target != CAM_TARGET_WILDCARD) {
7466 tstate->enabled_luns[lun] = lstate;
7467 ahc->enabled_luns++;
7468
7469 if ((ahc->features & AHC_MULTI_TID) != 0) {
7470 u_int targid_mask;
7471
7472 targid_mask = ahc_inb(ahc, TARGID)
7473 | (ahc_inb(ahc, TARGID + 1) << 8);
7474
7475 targid_mask |= target_mask;
7476 ahc_outb(ahc, TARGID, targid_mask);
7477 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7478
7479 ahc_update_scsiid(ahc, targid_mask);
7480 } else {
7481 u_int our_id;
7482 char channel;
7483
7484 channel = SIM_CHANNEL(ahc, sim);
7485 our_id = SIM_SCSI_ID(ahc, sim);
7486
7487 /*
7488 * This can only happen if selections
7489 * are not enabled
7490 */
7491 if (target != our_id) {
7492 u_int sblkctl;
7493 char cur_channel;
7494 int swap;
7495
7496 sblkctl = ahc_inb(ahc, SBLKCTL);
7497 cur_channel = (sblkctl & SELBUSB)
7498 ? 'B' : 'A';
7499 if ((ahc->features & AHC_TWIN) == 0)
7500 cur_channel = 'A';
7501 swap = cur_channel != channel;
7502 if (channel == 'A')
7503 ahc->our_id = target;
7504 else
7505 ahc->our_id_b = target;
7506
7507 if (swap)
7508 ahc_outb(ahc, SBLKCTL,
7509 sblkctl ^ SELBUSB);
7510
7511 ahc_outb(ahc, SCSIID, target);
7512
7513 if (swap)
7514 ahc_outb(ahc, SBLKCTL, sblkctl);
7515 }
7516 }
7517 } else
7518 ahc->black_hole = lstate;
7519 /* Allow select-in operations */
7520 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7521 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7522 scsiseq |= ENSELI;
7523 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7524 scsiseq = ahc_inb(ahc, SCSISEQ);
7525 scsiseq |= ENSELI;
7526 ahc_outb(ahc, SCSISEQ, scsiseq);
7527 }
7528 ahc_unpause(ahc);
7529 ccb->ccb_h.status = CAM_REQ_CMP;
7530 xpt_print_path(ccb->ccb_h.path);
7531 printf("Lun now enabled for target mode\n");
7532 } else {
7533 struct scb *scb;
7534 int i, empty;
7535
7536 if (lstate == NULL) {
7537 ccb->ccb_h.status = CAM_LUN_INVALID;
7538 return;
7539 }
7540
7541 ccb->ccb_h.status = CAM_REQ_CMP;
7542 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7543 struct ccb_hdr *ccbh;
7544
7545 ccbh = &scb->io_ctx->ccb_h;
7546 if (ccbh->func_code == XPT_CONT_TARGET_IO
7547 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7548 printf("CTIO pending\n");
7549 ccb->ccb_h.status = CAM_REQ_INVALID;
7550 return;
7551 }
7552 }
7553
7554 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7555 printf("ATIOs pending\n");
7556 ccb->ccb_h.status = CAM_REQ_INVALID;
7557 }
7558
7559 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7560 printf("INOTs pending\n");
7561 ccb->ccb_h.status = CAM_REQ_INVALID;
7562 }
7563
7564 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7565 return;
7566 }
7567
7568 xpt_print_path(ccb->ccb_h.path);
7569 printf("Target mode disabled\n");
7570 xpt_free_path(lstate->path);
7571 free(lstate, M_DEVBUF);
7572
7573 ahc_pause(ahc);
7574 /* Can we clean up the target too? */
7575 if (target != CAM_TARGET_WILDCARD) {
7576 tstate->enabled_luns[lun] = NULL;
7577 ahc->enabled_luns--;
7578 for (empty = 1, i = 0; i < 8; i++)
7579 if (tstate->enabled_luns[i] != NULL) {
7580 empty = 0;
7581 break;
7582 }
7583
7584 if (empty) {
7585 ahc_free_tstate(ahc, target, channel,
7586 /*force*/FALSE);
7587 if (ahc->features & AHC_MULTI_TID) {
7588 u_int targid_mask;
7589
7590 targid_mask = ahc_inb(ahc, TARGID)
7591 | (ahc_inb(ahc, TARGID + 1)
7592 << 8);
7593
7594 targid_mask &= ~target_mask;
7595 ahc_outb(ahc, TARGID, targid_mask);
7596 ahc_outb(ahc, TARGID+1,
7597 (targid_mask >> 8));
7598 ahc_update_scsiid(ahc, targid_mask);
7599 }
7600 }
7601 } else {
7602 ahc->black_hole = NULL;
7603
7604 /*
7605 * We can't allow selections without
7606 * our black hole device.
7607 */
7608 empty = TRUE;
7609 }
7610 if (ahc->enabled_luns == 0) {
7611 /* Disallow select-in */
7612 u_int scsiseq;
7613
7614 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7615 scsiseq &= ~ENSELI;
7616 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7617 scsiseq = ahc_inb(ahc, SCSISEQ);
7618 scsiseq &= ~ENSELI;
7619 ahc_outb(ahc, SCSISEQ, scsiseq);
7620
7621 if ((ahc->features & AHC_MULTIROLE) == 0) {
7622 printf("Configuring Initiator Mode\n");
7623 ahc->flags &= ~AHC_TARGETROLE;
7624 ahc->flags |= AHC_INITIATORROLE;
7625 /*
7626 * Returning to a configuration that
7627 * fit previously will always succeed.
7628 */
7629 (void)ahc_loadseq(ahc);
7630 ahc_restart(ahc);
7631 /*
7632 * Unpaused. The extra unpause
7633 * that follows is harmless.
7634 */
7635 }
7636 }
7637 ahc_unpause(ahc);
7638 }
7639 }
7640
7641 static void
ahc_update_scsiid(struct ahc_softc * ahc,u_int targid_mask)7642 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7643 {
7644 u_int scsiid_mask;
7645 u_int scsiid;
7646
7647 if ((ahc->features & AHC_MULTI_TID) == 0)
7648 panic("ahc_update_scsiid called on non-multitid unit\n");
7649
7650 /*
7651 * Since we will rely on the TARGID mask
7652 * for selection enables, ensure that OID
7653 * in SCSIID is not set to some other ID
7654 * that we don't want to allow selections on.
7655 */
7656 if ((ahc->features & AHC_ULTRA2) != 0)
7657 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7658 else
7659 scsiid = ahc_inb(ahc, SCSIID);
7660 scsiid_mask = 0x1 << (scsiid & OID);
7661 if ((targid_mask & scsiid_mask) == 0) {
7662 u_int our_id;
7663
7664 /* ffs counts from 1 */
7665 our_id = ffs(targid_mask);
7666 if (our_id == 0)
7667 our_id = ahc->our_id;
7668 else
7669 our_id--;
7670 scsiid &= TID;
7671 scsiid |= our_id;
7672 }
7673 if ((ahc->features & AHC_ULTRA2) != 0)
7674 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7675 else
7676 ahc_outb(ahc, SCSIID, scsiid);
7677 }
7678
7679 void
ahc_run_tqinfifo(struct ahc_softc * ahc,int paused)7680 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7681 {
7682 struct target_cmd *cmd;
7683
7684 /*
7685 * If the card supports auto-access pause,
7686 * we can access the card directly regardless
7687 * of whether it is paused or not.
7688 */
7689 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7690 paused = TRUE;
7691
7692 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7693 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7694 /*
7695 * Only advance through the queue if we
7696 * have the resources to process the command.
7697 */
7698 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7699 break;
7700
7701 cmd->cmd_valid = 0;
7702 aic_dmamap_sync(ahc, ahc->shared_data_dmat,
7703 ahc->shared_data_dmamap,
7704 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7705 sizeof(struct target_cmd),
7706 BUS_DMASYNC_PREREAD);
7707 ahc->tqinfifonext++;
7708
7709 /*
7710 * Lazily update our position in the target mode incoming
7711 * command queue as seen by the sequencer.
7712 */
7713 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7714 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7715 u_int hs_mailbox;
7716
7717 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7718 hs_mailbox &= ~HOST_TQINPOS;
7719 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7720 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7721 } else {
7722 if (!paused)
7723 ahc_pause(ahc);
7724 ahc_outb(ahc, KERNEL_TQINPOS,
7725 ahc->tqinfifonext & HOST_TQINPOS);
7726 if (!paused)
7727 ahc_unpause(ahc);
7728 }
7729 }
7730 }
7731 }
7732
7733 static int
ahc_handle_target_cmd(struct ahc_softc * ahc,struct target_cmd * cmd)7734 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7735 {
7736 struct ahc_tmode_tstate *tstate;
7737 struct ahc_tmode_lstate *lstate;
7738 struct ccb_accept_tio *atio;
7739 uint8_t *byte;
7740 int initiator;
7741 int target;
7742 int lun;
7743
7744 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7745 target = SCSIID_OUR_ID(cmd->scsiid);
7746 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7747
7748 byte = cmd->bytes;
7749 tstate = ahc->enabled_targets[target];
7750 lstate = NULL;
7751 if (tstate != NULL)
7752 lstate = tstate->enabled_luns[lun];
7753
7754 /*
7755 * Commands for disabled luns go to the black hole driver.
7756 */
7757 if (lstate == NULL)
7758 lstate = ahc->black_hole;
7759
7760 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7761 if (atio == NULL) {
7762 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7763 /*
7764 * Wait for more ATIOs from the peripheral driver for this lun.
7765 */
7766 if (bootverbose)
7767 printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7768 return (1);
7769 } else
7770 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7771 #ifdef AHC_DEBUG
7772 if (ahc_debug & AHC_SHOW_TQIN) {
7773 printf("Incoming command from %d for %d:%d%s\n",
7774 initiator, target, lun,
7775 lstate == ahc->black_hole ? "(Black Holed)" : "");
7776 }
7777 #endif
7778 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7779
7780 if (lstate == ahc->black_hole) {
7781 /* Fill in the wildcards */
7782 atio->ccb_h.target_id = target;
7783 atio->ccb_h.target_lun = lun;
7784 }
7785
7786 /*
7787 * Package it up and send it off to
7788 * whomever has this lun enabled.
7789 */
7790 atio->sense_len = 0;
7791 atio->init_id = initiator;
7792 if (byte[0] != 0xFF) {
7793 /* Tag was included */
7794 atio->tag_action = *byte++;
7795 atio->tag_id = *byte++;
7796 atio->ccb_h.flags |= CAM_TAG_ACTION_VALID;
7797 } else {
7798 atio->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
7799 }
7800 byte++;
7801
7802 /* Okay. Now determine the cdb size based on the command code */
7803 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7804 case 0:
7805 atio->cdb_len = 6;
7806 break;
7807 case 1:
7808 case 2:
7809 atio->cdb_len = 10;
7810 break;
7811 case 4:
7812 atio->cdb_len = 16;
7813 break;
7814 case 5:
7815 atio->cdb_len = 12;
7816 break;
7817 case 3:
7818 default:
7819 /* Only copy the opcode. */
7820 atio->cdb_len = 1;
7821 printf("Reserved or VU command code type encountered\n");
7822 break;
7823 }
7824
7825 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7826
7827 atio->ccb_h.status |= CAM_CDB_RECVD;
7828
7829 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7830 /*
7831 * We weren't allowed to disconnect.
7832 * We're hanging on the bus until a
7833 * continue target I/O comes in response
7834 * to this accept tio.
7835 */
7836 #ifdef AHC_DEBUG
7837 if (ahc_debug & AHC_SHOW_TQIN) {
7838 printf("Received Immediate Command %d:%d:%d - %p\n",
7839 initiator, target, lun, ahc->pending_device);
7840 }
7841 #endif
7842 ahc->pending_device = lstate;
7843 aic_freeze_ccb((union ccb *)atio);
7844 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7845 } else {
7846 atio->ccb_h.flags &= ~CAM_DIS_DISCONNECT;
7847 }
7848
7849 xpt_done((union ccb*)atio);
7850 return (0);
7851 }
7852
7853 #endif
7854