1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright 2014 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/clock/imx6sx-clock.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include "imx6sx-pinfunc.h" 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 /* 15 * The decompressor and also some bootloaders rely on a 16 * pre-existing /chosen node to be available to insert the 17 * command line and merge other ATAGS info. 18 */ 19 chosen {}; 20 21 aliases { 22 can0 = &flexcan1; 23 can1 = &flexcan2; 24 ethernet0 = &fec1; 25 ethernet1 = &fec2; 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 gpio4 = &gpio5; 31 gpio5 = &gpio6; 32 gpio6 = &gpio7; 33 i2c0 = &i2c1; 34 i2c1 = &i2c2; 35 i2c2 = &i2c3; 36 i2c3 = &i2c4; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 mmc2 = &usdhc3; 40 mmc3 = &usdhc4; 41 serial0 = &uart1; 42 serial1 = &uart2; 43 serial2 = &uart3; 44 serial3 = &uart4; 45 serial4 = &uart5; 46 serial5 = &uart6; 47 spi0 = &ecspi1; 48 spi1 = &ecspi2; 49 spi2 = &ecspi3; 50 spi3 = &ecspi4; 51 spi4 = &ecspi5; 52 usbphy0 = &usbphy1; 53 usbphy1 = &usbphy2; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a9"; 62 device_type = "cpu"; 63 reg = <0>; 64 next-level-cache = <&L2>; 65 operating-points = < 66 /* kHz uV */ 67 996000 1250000 68 792000 1175000 69 396000 1075000 70 198000 975000 71 >; 72 fsl,soc-operating-points = < 73 /* ARM kHz SOC uV */ 74 996000 1175000 75 792000 1175000 76 396000 1175000 77 198000 1175000 78 >; 79 clock-latency = <61036>; /* two CLK32 periods */ 80 #cooling-cells = <2>; 81 clocks = <&clks IMX6SX_CLK_ARM>, 82 <&clks IMX6SX_CLK_PLL2_PFD2>, 83 <&clks IMX6SX_CLK_STEP>, 84 <&clks IMX6SX_CLK_PLL1_SW>, 85 <&clks IMX6SX_CLK_PLL1_SYS>; 86 clock-names = "arm", "pll2_pfd2_396m", "step", 87 "pll1_sw", "pll1_sys"; 88 arm-supply = <®_arm>; 89 soc-supply = <®_soc>; 90 }; 91 }; 92 93 intc: interrupt-controller@a01000 { 94 compatible = "arm,cortex-a9-gic"; 95 #interrupt-cells = <3>; 96 interrupt-controller; 97 reg = <0x00a01000 0x1000>, 98 <0x00a00100 0x100>; 99 interrupt-parent = <&intc>; 100 }; 101 102 ckil: clock-ckil { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <32768>; 106 clock-output-names = "ckil"; 107 }; 108 109 osc: clock-osc { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <24000000>; 113 clock-output-names = "osc"; 114 }; 115 116 ipp_di0: clock-ipp-di0 { 117 compatible = "fixed-clock"; 118 #clock-cells = <0>; 119 clock-frequency = <0>; 120 clock-output-names = "ipp_di0"; 121 }; 122 123 ipp_di1: clock-ipp-di1 { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 clock-frequency = <0>; 127 clock-output-names = "ipp_di1"; 128 }; 129 130 anaclk1: clock-anaclk1 { 131 compatible = "fixed-clock"; 132 #clock-cells = <0>; 133 clock-frequency = <0>; 134 clock-output-names = "anaclk1"; 135 }; 136 137 anaclk2: clock-anaclk2 { 138 compatible = "fixed-clock"; 139 #clock-cells = <0>; 140 clock-frequency = <0>; 141 clock-output-names = "anaclk2"; 142 }; 143 144 tempmon: tempmon { 145 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; 146 interrupt-parent = <&gpc>; 147 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 148 fsl,tempmon = <&anatop>; 149 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 150 nvmem-cell-names = "calib", "temp_grade"; 151 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; 152 }; 153 154 pmu { 155 compatible = "arm,cortex-a9-pmu"; 156 interrupt-parent = <&gpc>; 157 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 158 }; 159 160 usbphynop1: usbphynop1 { 161 compatible = "usb-nop-xceiv"; 162 #phy-cells = <0>; 163 }; 164 165 soc { 166 #address-cells = <1>; 167 #size-cells = <1>; 168 compatible = "simple-bus"; 169 interrupt-parent = <&gpc>; 170 ranges; 171 172 ocram_s: sram@8f8000 { 173 compatible = "mmio-sram"; 174 reg = <0x008f8000 0x4000>; 175 clocks = <&clks IMX6SX_CLK_OCRAM_S>; 176 }; 177 178 ocram: sram@900000 { 179 compatible = "mmio-sram"; 180 reg = <0x00900000 0x20000>; 181 clocks = <&clks IMX6SX_CLK_OCRAM>; 182 }; 183 184 L2: l2-cache@a02000 { 185 compatible = "arm,pl310-cache"; 186 reg = <0x00a02000 0x1000>; 187 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 188 cache-unified; 189 cache-level = <2>; 190 arm,tag-latency = <4 2 3>; 191 arm,data-latency = <4 2 3>; 192 }; 193 194 gpu: gpu@1800000 { 195 compatible = "vivante,gc"; 196 reg = <0x01800000 0x4000>; 197 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&clks IMX6SX_CLK_GPU>, 199 <&clks IMX6SX_CLK_GPU>, 200 <&clks IMX6SX_CLK_GPU>; 201 clock-names = "bus", "core", "shader"; 202 power-domains = <&pd_pu>; 203 }; 204 205 dma_apbh: dma-apbh@1804000 { 206 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; 207 reg = <0x01804000 0x2000>; 208 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 213 #dma-cells = <1>; 214 dma-channels = <4>; 215 clocks = <&clks IMX6SX_CLK_APBH_DMA>; 216 }; 217 218 gpmi: gpmi-nand@1806000{ 219 compatible = "fsl,imx6sx-gpmi-nand"; 220 #address-cells = <1>; 221 #size-cells = <1>; 222 reg = <0x01806000 0x2000>, <0x01808000 0x4000>; 223 reg-names = "gpmi-nand", "bch"; 224 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 225 interrupt-names = "bch"; 226 clocks = <&clks IMX6SX_CLK_GPMI_IO>, 227 <&clks IMX6SX_CLK_GPMI_APB>, 228 <&clks IMX6SX_CLK_GPMI_BCH>, 229 <&clks IMX6SX_CLK_GPMI_BCH_APB>, 230 <&clks IMX6SX_CLK_PER1_BCH>; 231 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 232 "gpmi_bch_apb", "per1_bch"; 233 dmas = <&dma_apbh 0>; 234 dma-names = "rx-tx"; 235 status = "disabled"; 236 }; 237 238 aips1: aips-bus@2000000 { 239 compatible = "fsl,aips-bus", "simple-bus"; 240 #address-cells = <1>; 241 #size-cells = <1>; 242 reg = <0x02000000 0x100000>; 243 ranges; 244 245 spba-bus@2000000 { 246 compatible = "fsl,spba-bus", "simple-bus"; 247 #address-cells = <1>; 248 #size-cells = <1>; 249 reg = <0x02000000 0x40000>; 250 ranges; 251 252 spdif: spdif@2004000 { 253 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; 254 reg = <0x02004000 0x4000>; 255 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 256 dmas = <&sdma 14 18 0>, 257 <&sdma 15 18 0>; 258 dma-names = "rx", "tx"; 259 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, 260 <&clks IMX6SX_CLK_OSC>, 261 <&clks IMX6SX_CLK_SPDIF>, 262 <&clks 0>, <&clks 0>, <&clks 0>, 263 <&clks IMX6SX_CLK_IPG>, 264 <&clks 0>, <&clks 0>, 265 <&clks IMX6SX_CLK_SPBA>; 266 clock-names = "core", "rxtx0", 267 "rxtx1", "rxtx2", 268 "rxtx3", "rxtx4", 269 "rxtx5", "rxtx6", 270 "rxtx7", "spba"; 271 status = "disabled"; 272 }; 273 274 ecspi1: spi@2008000 { 275 #address-cells = <1>; 276 #size-cells = <0>; 277 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 278 reg = <0x02008000 0x4000>; 279 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&clks IMX6SX_CLK_ECSPI1>, 281 <&clks IMX6SX_CLK_ECSPI1>; 282 clock-names = "ipg", "per"; 283 status = "disabled"; 284 }; 285 286 ecspi2: spi@200c000 { 287 #address-cells = <1>; 288 #size-cells = <0>; 289 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 290 reg = <0x0200c000 0x4000>; 291 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&clks IMX6SX_CLK_ECSPI2>, 293 <&clks IMX6SX_CLK_ECSPI2>; 294 clock-names = "ipg", "per"; 295 status = "disabled"; 296 }; 297 298 ecspi3: spi@2010000 { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 302 reg = <0x02010000 0x4000>; 303 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&clks IMX6SX_CLK_ECSPI3>, 305 <&clks IMX6SX_CLK_ECSPI3>; 306 clock-names = "ipg", "per"; 307 status = "disabled"; 308 }; 309 310 ecspi4: spi@2014000 { 311 #address-cells = <1>; 312 #size-cells = <0>; 313 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 314 reg = <0x02014000 0x4000>; 315 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&clks IMX6SX_CLK_ECSPI4>, 317 <&clks IMX6SX_CLK_ECSPI4>; 318 clock-names = "ipg", "per"; 319 status = "disabled"; 320 }; 321 322 uart1: serial@2020000 { 323 compatible = "fsl,imx6sx-uart", 324 "fsl,imx6q-uart", "fsl,imx21-uart"; 325 reg = <0x02020000 0x4000>; 326 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&clks IMX6SX_CLK_UART_IPG>, 328 <&clks IMX6SX_CLK_UART_SERIAL>; 329 clock-names = "ipg", "per"; 330 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 331 dma-names = "rx", "tx"; 332 status = "disabled"; 333 }; 334 335 esai: esai@2024000 { 336 reg = <0x02024000 0x4000>; 337 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&clks IMX6SX_CLK_ESAI_IPG>, 339 <&clks IMX6SX_CLK_ESAI_MEM>, 340 <&clks IMX6SX_CLK_ESAI_EXTAL>, 341 <&clks IMX6SX_CLK_ESAI_IPG>, 342 <&clks IMX6SX_CLK_SPBA>; 343 clock-names = "core", "mem", "extal", 344 "fsys", "spba"; 345 status = "disabled"; 346 }; 347 348 ssi1: ssi@2028000 { 349 #sound-dai-cells = <0>; 350 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 351 reg = <0x02028000 0x4000>; 352 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&clks IMX6SX_CLK_SSI1_IPG>, 354 <&clks IMX6SX_CLK_SSI1>; 355 clock-names = "ipg", "baud"; 356 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; 357 dma-names = "rx", "tx"; 358 fsl,fifo-depth = <15>; 359 status = "disabled"; 360 }; 361 362 ssi2: ssi@202c000 { 363 #sound-dai-cells = <0>; 364 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 365 reg = <0x0202c000 0x4000>; 366 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&clks IMX6SX_CLK_SSI2_IPG>, 368 <&clks IMX6SX_CLK_SSI2>; 369 clock-names = "ipg", "baud"; 370 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; 371 dma-names = "rx", "tx"; 372 fsl,fifo-depth = <15>; 373 status = "disabled"; 374 }; 375 376 ssi3: ssi@2030000 { 377 #sound-dai-cells = <0>; 378 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 379 reg = <0x02030000 0x4000>; 380 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&clks IMX6SX_CLK_SSI3_IPG>, 382 <&clks IMX6SX_CLK_SSI3>; 383 clock-names = "ipg", "baud"; 384 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; 385 dma-names = "rx", "tx"; 386 fsl,fifo-depth = <15>; 387 status = "disabled"; 388 }; 389 390 asrc: asrc@2034000 { 391 reg = <0x02034000 0x4000>; 392 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&clks IMX6SX_CLK_ASRC_MEM>, 394 <&clks IMX6SX_CLK_ASRC_IPG>, 395 <&clks IMX6SX_CLK_SPDIF>, 396 <&clks IMX6SX_CLK_SPBA>; 397 clock-names = "mem", "ipg", "asrck", "spba"; 398 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, 399 <&sdma 19 20 1>, <&sdma 20 20 1>, 400 <&sdma 21 20 1>, <&sdma 22 20 1>; 401 dma-names = "rxa", "rxb", "rxc", 402 "txa", "txb", "txc"; 403 status = "okay"; 404 }; 405 }; 406 407 pwm1: pwm@2080000 { 408 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 409 reg = <0x02080000 0x4000>; 410 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&clks IMX6SX_CLK_PWM1>, 412 <&clks IMX6SX_CLK_PWM1>; 413 clock-names = "ipg", "per"; 414 #pwm-cells = <2>; 415 }; 416 417 pwm2: pwm@2084000 { 418 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 419 reg = <0x02084000 0x4000>; 420 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&clks IMX6SX_CLK_PWM2>, 422 <&clks IMX6SX_CLK_PWM2>; 423 clock-names = "ipg", "per"; 424 #pwm-cells = <2>; 425 }; 426 427 pwm3: pwm@2088000 { 428 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 429 reg = <0x02088000 0x4000>; 430 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&clks IMX6SX_CLK_PWM3>, 432 <&clks IMX6SX_CLK_PWM3>; 433 clock-names = "ipg", "per"; 434 #pwm-cells = <2>; 435 }; 436 437 pwm4: pwm@208c000 { 438 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 439 reg = <0x0208c000 0x4000>; 440 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clks IMX6SX_CLK_PWM4>, 442 <&clks IMX6SX_CLK_PWM4>; 443 clock-names = "ipg", "per"; 444 #pwm-cells = <2>; 445 }; 446 447 flexcan1: can@2090000 { 448 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 449 reg = <0x02090000 0x4000>; 450 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&clks IMX6SX_CLK_CAN1_IPG>, 452 <&clks IMX6SX_CLK_CAN1_SERIAL>; 453 clock-names = "ipg", "per"; 454 fsl,stop-mode = <&gpr 0x10 1 0x10 17>; 455 status = "disabled"; 456 }; 457 458 flexcan2: can@2094000 { 459 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 460 reg = <0x02094000 0x4000>; 461 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&clks IMX6SX_CLK_CAN2_IPG>, 463 <&clks IMX6SX_CLK_CAN2_SERIAL>; 464 clock-names = "ipg", "per"; 465 fsl,stop-mode = <&gpr 0x10 2 0x10 18>; 466 status = "disabled"; 467 }; 468 469 gpt: gpt@2098000 { 470 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; 471 reg = <0x02098000 0x4000>; 472 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&clks IMX6SX_CLK_GPT_BUS>, 474 <&clks IMX6SX_CLK_GPT_3M>; 475 clock-names = "ipg", "per"; 476 }; 477 478 gpio1: gpio@209c000 { 479 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 480 reg = <0x0209c000 0x4000>; 481 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 483 gpio-controller; 484 #gpio-cells = <2>; 485 interrupt-controller; 486 #interrupt-cells = <2>; 487 gpio-ranges = <&iomuxc 0 5 26>; 488 }; 489 490 gpio2: gpio@20a0000 { 491 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 492 reg = <0x020a0000 0x4000>; 493 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 gpio-ranges = <&iomuxc 0 31 20>; 500 }; 501 502 gpio3: gpio@20a4000 { 503 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 504 reg = <0x020a4000 0x4000>; 505 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 507 gpio-controller; 508 #gpio-cells = <2>; 509 interrupt-controller; 510 #interrupt-cells = <2>; 511 gpio-ranges = <&iomuxc 0 51 29>; 512 }; 513 514 gpio4: gpio@20a8000 { 515 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 516 reg = <0x020a8000 0x4000>; 517 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 gpio-ranges = <&iomuxc 0 80 32>; 524 }; 525 526 gpio5: gpio@20ac000 { 527 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 528 reg = <0x020ac000 0x4000>; 529 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 gpio-ranges = <&iomuxc 0 112 24>; 536 }; 537 538 gpio6: gpio@20b0000 { 539 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 540 reg = <0x020b0000 0x4000>; 541 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 543 gpio-controller; 544 #gpio-cells = <2>; 545 interrupt-controller; 546 #interrupt-cells = <2>; 547 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; 548 }; 549 550 gpio7: gpio@20b4000 { 551 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 552 reg = <0x020b4000 0x4000>; 553 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 555 gpio-controller; 556 #gpio-cells = <2>; 557 interrupt-controller; 558 #interrupt-cells = <2>; 559 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; 560 }; 561 562 kpp: kpp@20b8000 { 563 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; 564 reg = <0x020b8000 0x4000>; 565 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&clks IMX6SX_CLK_IPG>; 567 status = "disabled"; 568 }; 569 570 wdog1: wdog@20bc000 { 571 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 572 reg = <0x020bc000 0x4000>; 573 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&clks IMX6SX_CLK_IPG>; 575 }; 576 577 wdog2: wdog@20c0000 { 578 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 579 reg = <0x020c0000 0x4000>; 580 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&clks IMX6SX_CLK_IPG>; 582 status = "disabled"; 583 }; 584 585 clks: ccm@20c4000 { 586 compatible = "fsl,imx6sx-ccm"; 587 reg = <0x020c4000 0x4000>; 588 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 590 #clock-cells = <1>; 591 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; 592 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; 593 }; 594 595 anatop: anatop@20c8000 { 596 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", 597 "syscon", "simple-bus"; 598 reg = <0x020c8000 0x1000>; 599 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 602 603 regulator-1p1 { 604 compatible = "fsl,anatop-regulator"; 605 regulator-name = "vdd1p1"; 606 regulator-min-microvolt = <1000000>; 607 regulator-max-microvolt = <1200000>; 608 regulator-always-on; 609 anatop-reg-offset = <0x110>; 610 anatop-vol-bit-shift = <8>; 611 anatop-vol-bit-width = <5>; 612 anatop-min-bit-val = <4>; 613 anatop-min-voltage = <800000>; 614 anatop-max-voltage = <1375000>; 615 anatop-enable-bit = <0>; 616 }; 617 618 regulator-3p0 { 619 compatible = "fsl,anatop-regulator"; 620 regulator-name = "vdd3p0"; 621 regulator-min-microvolt = <2800000>; 622 regulator-max-microvolt = <3150000>; 623 regulator-always-on; 624 anatop-reg-offset = <0x120>; 625 anatop-vol-bit-shift = <8>; 626 anatop-vol-bit-width = <5>; 627 anatop-min-bit-val = <0>; 628 anatop-min-voltage = <2625000>; 629 anatop-max-voltage = <3400000>; 630 anatop-enable-bit = <0>; 631 }; 632 633 regulator-2p5 { 634 compatible = "fsl,anatop-regulator"; 635 regulator-name = "vdd2p5"; 636 regulator-min-microvolt = <2250000>; 637 regulator-max-microvolt = <2750000>; 638 regulator-always-on; 639 anatop-reg-offset = <0x130>; 640 anatop-vol-bit-shift = <8>; 641 anatop-vol-bit-width = <5>; 642 anatop-min-bit-val = <0>; 643 anatop-min-voltage = <2100000>; 644 anatop-max-voltage = <2875000>; 645 anatop-enable-bit = <0>; 646 }; 647 648 reg_arm: regulator-vddcore { 649 compatible = "fsl,anatop-regulator"; 650 regulator-name = "vddarm"; 651 regulator-min-microvolt = <725000>; 652 regulator-max-microvolt = <1450000>; 653 regulator-always-on; 654 anatop-reg-offset = <0x140>; 655 anatop-vol-bit-shift = <0>; 656 anatop-vol-bit-width = <5>; 657 anatop-delay-reg-offset = <0x170>; 658 anatop-delay-bit-shift = <24>; 659 anatop-delay-bit-width = <2>; 660 anatop-min-bit-val = <1>; 661 anatop-min-voltage = <725000>; 662 anatop-max-voltage = <1450000>; 663 }; 664 665 reg_pcie: regulator-vddpcie { 666 compatible = "fsl,anatop-regulator"; 667 regulator-name = "vddpcie"; 668 regulator-min-microvolt = <725000>; 669 regulator-max-microvolt = <1450000>; 670 anatop-reg-offset = <0x140>; 671 anatop-vol-bit-shift = <9>; 672 anatop-vol-bit-width = <5>; 673 anatop-delay-reg-offset = <0x170>; 674 anatop-delay-bit-shift = <26>; 675 anatop-delay-bit-width = <2>; 676 anatop-min-bit-val = <1>; 677 anatop-min-voltage = <725000>; 678 anatop-max-voltage = <1450000>; 679 }; 680 681 reg_soc: regulator-vddsoc { 682 compatible = "fsl,anatop-regulator"; 683 regulator-name = "vddsoc"; 684 regulator-min-microvolt = <725000>; 685 regulator-max-microvolt = <1450000>; 686 regulator-always-on; 687 anatop-reg-offset = <0x140>; 688 anatop-vol-bit-shift = <18>; 689 anatop-vol-bit-width = <5>; 690 anatop-delay-reg-offset = <0x170>; 691 anatop-delay-bit-shift = <28>; 692 anatop-delay-bit-width = <2>; 693 anatop-min-bit-val = <1>; 694 anatop-min-voltage = <725000>; 695 anatop-max-voltage = <1450000>; 696 }; 697 }; 698 699 usbphy1: usbphy@20c9000 { 700 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 701 reg = <0x020c9000 0x1000>; 702 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&clks IMX6SX_CLK_USBPHY1>; 704 fsl,anatop = <&anatop>; 705 }; 706 707 usbphy2: usbphy@20ca000 { 708 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 709 reg = <0x020ca000 0x1000>; 710 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&clks IMX6SX_CLK_USBPHY2>; 712 fsl,anatop = <&anatop>; 713 }; 714 715 snvs: snvs@20cc000 { 716 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 717 reg = <0x020cc000 0x4000>; 718 719 snvs_rtc: snvs-rtc-lp { 720 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 721 regmap = <&snvs>; 722 offset = <0x34>; 723 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 724 }; 725 726 snvs_poweroff: snvs-poweroff { 727 compatible = "syscon-poweroff"; 728 regmap = <&snvs>; 729 offset = <0x38>; 730 value = <0x60>; 731 mask = <0x60>; 732 status = "disabled"; 733 }; 734 735 snvs_pwrkey: snvs-powerkey { 736 compatible = "fsl,sec-v4.0-pwrkey"; 737 regmap = <&snvs>; 738 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 739 linux,keycode = <KEY_POWER>; 740 wakeup-source; 741 }; 742 }; 743 744 epit1: epit@20d0000 { 745 reg = <0x020d0000 0x4000>; 746 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 747 }; 748 749 epit2: epit@20d4000 { 750 reg = <0x020d4000 0x4000>; 751 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 752 }; 753 754 src: src@20d8000 { 755 compatible = "fsl,imx6sx-src", "fsl,imx51-src"; 756 reg = <0x020d8000 0x4000>; 757 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 759 #reset-cells = <1>; 760 }; 761 762 gpc: gpc@20dc000 { 763 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; 764 reg = <0x020dc000 0x4000>; 765 interrupt-controller; 766 #interrupt-cells = <3>; 767 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 768 interrupt-parent = <&intc>; 769 clocks = <&clks IMX6SX_CLK_IPG>; 770 clock-names = "ipg"; 771 772 pgc { 773 #address-cells = <1>; 774 #size-cells = <0>; 775 776 power-domain@0 { 777 reg = <0>; 778 #power-domain-cells = <0>; 779 }; 780 781 pd_pu: power-domain@1 { 782 reg = <1>; 783 #power-domain-cells = <0>; 784 power-supply = <®_soc>; 785 clocks = <&clks IMX6SX_CLK_GPU>; 786 }; 787 788 pd_disp: power-domain@2 { 789 reg = <2>; 790 #power-domain-cells = <0>; 791 clocks = <&clks IMX6SX_CLK_PXP_AXI>, 792 <&clks IMX6SX_CLK_DISPLAY_AXI>, 793 <&clks IMX6SX_CLK_LCDIF1_PIX>, 794 <&clks IMX6SX_CLK_LCDIF_APB>, 795 <&clks IMX6SX_CLK_LCDIF2_PIX>, 796 <&clks IMX6SX_CLK_CSI>, 797 <&clks IMX6SX_CLK_VADC>; 798 }; 799 800 pd_pci: power-domain@3 { 801 reg = <3>; 802 #power-domain-cells = <0>; 803 power-supply = <®_pcie>; 804 }; 805 }; 806 }; 807 808 iomuxc: iomuxc@20e0000 { 809 compatible = "fsl,imx6sx-iomuxc"; 810 reg = <0x020e0000 0x4000>; 811 }; 812 813 gpr: iomuxc-gpr@20e4000 { 814 compatible = "fsl,imx6sx-iomuxc-gpr", 815 "fsl,imx6q-iomuxc-gpr", "syscon"; 816 reg = <0x020e4000 0x4000>; 817 }; 818 819 sdma: sdma@20ec000 { 820 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; 821 reg = <0x020ec000 0x4000>; 822 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&clks IMX6SX_CLK_SDMA>, 824 <&clks IMX6SX_CLK_SDMA>; 825 clock-names = "ipg", "ahb"; 826 #dma-cells = <3>; 827 /* imx6sx reuses imx6q sdma firmware */ 828 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 829 }; 830 }; 831 832 aips2: aips-bus@2100000 { 833 compatible = "fsl,aips-bus", "simple-bus"; 834 #address-cells = <1>; 835 #size-cells = <1>; 836 reg = <0x02100000 0x100000>; 837 ranges; 838 839 crypto: caam@2100000 { 840 compatible = "fsl,sec-v4.0"; 841 #address-cells = <1>; 842 #size-cells = <1>; 843 reg = <0x2100000 0x10000>; 844 ranges = <0 0x2100000 0x10000>; 845 interrupt-parent = <&intc>; 846 clocks = <&clks IMX6SX_CLK_CAAM_MEM>, 847 <&clks IMX6SX_CLK_CAAM_ACLK>, 848 <&clks IMX6SX_CLK_CAAM_IPG>, 849 <&clks IMX6SX_CLK_EIM_SLOW>; 850 clock-names = "mem", "aclk", "ipg", "emi_slow"; 851 852 sec_jr0: jr0@1000 { 853 compatible = "fsl,sec-v4.0-job-ring"; 854 reg = <0x1000 0x1000>; 855 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 856 }; 857 858 sec_jr1: jr1@2000 { 859 compatible = "fsl,sec-v4.0-job-ring"; 860 reg = <0x2000 0x1000>; 861 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 862 }; 863 }; 864 865 usbotg1: usb@2184000 { 866 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 867 reg = <0x02184000 0x200>; 868 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&clks IMX6SX_CLK_USBOH3>; 870 fsl,usbphy = <&usbphy1>; 871 fsl,usbmisc = <&usbmisc 0>; 872 fsl,anatop = <&anatop>; 873 ahb-burst-config = <0x0>; 874 tx-burst-size-dword = <0x10>; 875 rx-burst-size-dword = <0x10>; 876 status = "disabled"; 877 }; 878 879 usbotg2: usb@2184200 { 880 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 881 reg = <0x02184200 0x200>; 882 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&clks IMX6SX_CLK_USBOH3>; 884 fsl,usbphy = <&usbphy2>; 885 fsl,usbmisc = <&usbmisc 1>; 886 ahb-burst-config = <0x0>; 887 tx-burst-size-dword = <0x10>; 888 rx-burst-size-dword = <0x10>; 889 status = "disabled"; 890 }; 891 892 usbh: usb@2184400 { 893 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 894 reg = <0x02184400 0x200>; 895 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&clks IMX6SX_CLK_USBOH3>; 897 fsl,usbphy = <&usbphynop1>; 898 fsl,usbmisc = <&usbmisc 2>; 899 phy_type = "hsic"; 900 fsl,anatop = <&anatop>; 901 dr_mode = "host"; 902 ahb-burst-config = <0x0>; 903 tx-burst-size-dword = <0x10>; 904 rx-burst-size-dword = <0x10>; 905 status = "disabled"; 906 }; 907 908 usbmisc: usbmisc@2184800 { 909 #index-cells = <1>; 910 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; 911 reg = <0x02184800 0x200>; 912 clocks = <&clks IMX6SX_CLK_USBOH3>; 913 }; 914 915 fec1: ethernet@2188000 { 916 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 917 reg = <0x02188000 0x4000>; 918 interrupt-names = "int0", "pps"; 919 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&clks IMX6SX_CLK_ENET>, 922 <&clks IMX6SX_CLK_ENET_AHB>, 923 <&clks IMX6SX_CLK_ENET_PTP>, 924 <&clks IMX6SX_CLK_ENET_REF>, 925 <&clks IMX6SX_CLK_ENET_PTP>; 926 clock-names = "ipg", "ahb", "ptp", 927 "enet_clk_ref", "enet_out"; 928 fsl,num-tx-queues=<3>; 929 fsl,num-rx-queues=<3>; 930 status = "disabled"; 931 }; 932 933 mlb: mlb@218c000 { 934 reg = <0x0218c000 0x4000>; 935 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&clks IMX6SX_CLK_MLB>; 939 status = "disabled"; 940 }; 941 942 usdhc1: usdhc@2190000 { 943 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 944 reg = <0x02190000 0x4000>; 945 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&clks IMX6SX_CLK_USDHC1>, 947 <&clks IMX6SX_CLK_USDHC1>, 948 <&clks IMX6SX_CLK_USDHC1>; 949 clock-names = "ipg", "ahb", "per"; 950 bus-width = <4>; 951 status = "disabled"; 952 }; 953 954 usdhc2: usdhc@2194000 { 955 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 956 reg = <0x02194000 0x4000>; 957 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&clks IMX6SX_CLK_USDHC2>, 959 <&clks IMX6SX_CLK_USDHC2>, 960 <&clks IMX6SX_CLK_USDHC2>; 961 clock-names = "ipg", "ahb", "per"; 962 bus-width = <4>; 963 status = "disabled"; 964 }; 965 966 usdhc3: usdhc@2198000 { 967 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 968 reg = <0x02198000 0x4000>; 969 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&clks IMX6SX_CLK_USDHC3>, 971 <&clks IMX6SX_CLK_USDHC3>, 972 <&clks IMX6SX_CLK_USDHC3>; 973 clock-names = "ipg", "ahb", "per"; 974 bus-width = <4>; 975 status = "disabled"; 976 }; 977 978 usdhc4: usdhc@219c000 { 979 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 980 reg = <0x0219c000 0x4000>; 981 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clks IMX6SX_CLK_USDHC4>, 983 <&clks IMX6SX_CLK_USDHC4>, 984 <&clks IMX6SX_CLK_USDHC4>; 985 clock-names = "ipg", "ahb", "per"; 986 bus-width = <4>; 987 status = "disabled"; 988 }; 989 990 i2c1: i2c@21a0000 { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 994 reg = <0x021a0000 0x4000>; 995 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&clks IMX6SX_CLK_I2C1>; 997 status = "disabled"; 998 }; 999 1000 i2c2: i2c@21a4000 { 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1004 reg = <0x021a4000 0x4000>; 1005 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&clks IMX6SX_CLK_I2C2>; 1007 status = "disabled"; 1008 }; 1009 1010 i2c3: i2c@21a8000 { 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1014 reg = <0x021a8000 0x4000>; 1015 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&clks IMX6SX_CLK_I2C3>; 1017 status = "disabled"; 1018 }; 1019 1020 mmdc: mmdc@21b0000 { 1021 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; 1022 reg = <0x021b0000 0x4000>; 1023 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; 1024 }; 1025 1026 fec2: ethernet@21b4000 { 1027 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 1028 reg = <0x021b4000 0x4000>; 1029 interrupt-names = "int0", "pps"; 1030 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&clks IMX6SX_CLK_ENET>, 1033 <&clks IMX6SX_CLK_ENET_AHB>, 1034 <&clks IMX6SX_CLK_ENET_PTP>, 1035 <&clks IMX6SX_CLK_ENET2_REF_125M>, 1036 <&clks IMX6SX_CLK_ENET_PTP>; 1037 clock-names = "ipg", "ahb", "ptp", 1038 "enet_clk_ref", "enet_out"; 1039 status = "disabled"; 1040 }; 1041 1042 weim: weim@21b8000 { 1043 #address-cells = <2>; 1044 #size-cells = <1>; 1045 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; 1046 reg = <0x021b8000 0x4000>; 1047 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&clks IMX6SX_CLK_EIM_SLOW>; 1049 fsl,weim-cs-gpr = <&gpr>; 1050 status = "disabled"; 1051 }; 1052 1053 ocotp: ocotp@21bc000 { 1054 #address-cells = <1>; 1055 #size-cells = <1>; 1056 compatible = "fsl,imx6sx-ocotp", "syscon"; 1057 reg = <0x021bc000 0x4000>; 1058 clocks = <&clks IMX6SX_CLK_OCOTP>; 1059 1060 tempmon_calib: calib@38 { 1061 reg = <0x38 4>; 1062 }; 1063 1064 tempmon_temp_grade: temp-grade@20 { 1065 reg = <0x20 4>; 1066 }; 1067 }; 1068 1069 sai1: sai@21d4000 { 1070 compatible = "fsl,imx6sx-sai"; 1071 reg = <0x021d4000 0x4000>; 1072 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&clks IMX6SX_CLK_SAI1_IPG>, 1074 <&clks IMX6SX_CLK_SAI1>, 1075 <&clks 0>, <&clks 0>; 1076 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1077 dma-names = "rx", "tx"; 1078 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; 1079 status = "disabled"; 1080 }; 1081 1082 audmux: audmux@21d8000 { 1083 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; 1084 reg = <0x021d8000 0x4000>; 1085 status = "disabled"; 1086 }; 1087 1088 sai2: sai@21dc000 { 1089 compatible = "fsl,imx6sx-sai"; 1090 reg = <0x021dc000 0x4000>; 1091 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&clks IMX6SX_CLK_SAI2_IPG>, 1093 <&clks IMX6SX_CLK_SAI2>, 1094 <&clks 0>, <&clks 0>; 1095 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1096 dma-names = "rx", "tx"; 1097 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; 1098 status = "disabled"; 1099 }; 1100 1101 qspi1: spi@21e0000 { 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 compatible = "fsl,imx6sx-qspi"; 1105 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 1106 reg-names = "QuadSPI", "QuadSPI-memory"; 1107 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&clks IMX6SX_CLK_QSPI1>, 1109 <&clks IMX6SX_CLK_QSPI1>; 1110 clock-names = "qspi_en", "qspi"; 1111 status = "disabled"; 1112 }; 1113 1114 qspi2: spi@21e4000 { 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 compatible = "fsl,imx6sx-qspi"; 1118 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; 1119 reg-names = "QuadSPI", "QuadSPI-memory"; 1120 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&clks IMX6SX_CLK_QSPI2>, 1122 <&clks IMX6SX_CLK_QSPI2>; 1123 clock-names = "qspi_en", "qspi"; 1124 status = "disabled"; 1125 }; 1126 1127 uart2: serial@21e8000 { 1128 compatible = "fsl,imx6sx-uart", 1129 "fsl,imx6q-uart", "fsl,imx21-uart"; 1130 reg = <0x021e8000 0x4000>; 1131 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1133 <&clks IMX6SX_CLK_UART_SERIAL>; 1134 clock-names = "ipg", "per"; 1135 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1136 dma-names = "rx", "tx"; 1137 status = "disabled"; 1138 }; 1139 1140 uart3: serial@21ec000 { 1141 compatible = "fsl,imx6sx-uart", 1142 "fsl,imx6q-uart", "fsl,imx21-uart"; 1143 reg = <0x021ec000 0x4000>; 1144 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1146 <&clks IMX6SX_CLK_UART_SERIAL>; 1147 clock-names = "ipg", "per"; 1148 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1149 dma-names = "rx", "tx"; 1150 status = "disabled"; 1151 }; 1152 1153 uart4: serial@21f0000 { 1154 compatible = "fsl,imx6sx-uart", 1155 "fsl,imx6q-uart", "fsl,imx21-uart"; 1156 reg = <0x021f0000 0x4000>; 1157 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1159 <&clks IMX6SX_CLK_UART_SERIAL>; 1160 clock-names = "ipg", "per"; 1161 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1162 dma-names = "rx", "tx"; 1163 status = "disabled"; 1164 }; 1165 1166 uart5: serial@21f4000 { 1167 compatible = "fsl,imx6sx-uart", 1168 "fsl,imx6q-uart", "fsl,imx21-uart"; 1169 reg = <0x021f4000 0x4000>; 1170 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1172 <&clks IMX6SX_CLK_UART_SERIAL>; 1173 clock-names = "ipg", "per"; 1174 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1175 dma-names = "rx", "tx"; 1176 status = "disabled"; 1177 }; 1178 1179 i2c4: i2c@21f8000 { 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1183 reg = <0x021f8000 0x4000>; 1184 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1185 clocks = <&clks IMX6SX_CLK_I2C4>; 1186 status = "disabled"; 1187 }; 1188 }; 1189 1190 aips3: aips-bus@2200000 { 1191 compatible = "fsl,aips-bus", "simple-bus"; 1192 #address-cells = <1>; 1193 #size-cells = <1>; 1194 reg = <0x02200000 0x100000>; 1195 ranges; 1196 1197 spba-bus@2240000 { 1198 compatible = "fsl,spba-bus", "simple-bus"; 1199 #address-cells = <1>; 1200 #size-cells = <1>; 1201 reg = <0x02240000 0x40000>; 1202 ranges; 1203 1204 csi1: csi@2214000 { 1205 reg = <0x02214000 0x4000>; 1206 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1208 <&clks IMX6SX_CLK_CSI>, 1209 <&clks IMX6SX_CLK_DCIC1>; 1210 clock-names = "disp-axi", "csi_mclk", "dcic"; 1211 status = "disabled"; 1212 }; 1213 1214 pxp: pxp@2218000 { 1215 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; 1216 reg = <0x02218000 0x4000>; 1217 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1218 clocks = <&clks IMX6SX_CLK_PXP_AXI>; 1219 clock-names = "axi"; 1220 power-domains = <&pd_disp>; 1221 status = "disabled"; 1222 }; 1223 1224 csi2: csi@221c000 { 1225 reg = <0x0221c000 0x4000>; 1226 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1228 <&clks IMX6SX_CLK_CSI>, 1229 <&clks IMX6SX_CLK_DCIC2>; 1230 clock-names = "disp-axi", "csi_mclk", "dcic"; 1231 status = "disabled"; 1232 }; 1233 1234 lcdif1: lcdif@2220000 { 1235 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1236 reg = <0x02220000 0x4000>; 1237 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>; 1238 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, 1239 <&clks IMX6SX_CLK_LCDIF_APB>, 1240 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1241 clock-names = "pix", "axi", "disp_axi"; 1242 power-domains = <&pd_disp>; 1243 status = "disabled"; 1244 }; 1245 1246 lcdif2: lcdif@2224000 { 1247 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1248 reg = <0x02224000 0x4000>; 1249 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>; 1250 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, 1251 <&clks IMX6SX_CLK_LCDIF_APB>, 1252 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1253 clock-names = "pix", "axi", "disp_axi"; 1254 power-domains = <&pd_disp>; 1255 status = "disabled"; 1256 }; 1257 1258 vadc: vadc@2228000 { 1259 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; 1260 reg-names = "vadc-vafe", "vadc-vdec"; 1261 clocks = <&clks IMX6SX_CLK_VADC>, 1262 <&clks IMX6SX_CLK_CSI>; 1263 clock-names = "vadc", "csi"; 1264 power-domains = <&pd_disp>; 1265 status = "disabled"; 1266 }; 1267 }; 1268 1269 adc1: adc@2280000 { 1270 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1271 reg = <0x02280000 0x4000>; 1272 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1273 clocks = <&clks IMX6SX_CLK_IPG>; 1274 clock-names = "adc"; 1275 fsl,adck-max-frequency = <30000000>, <40000000>, 1276 <20000000>; 1277 status = "disabled"; 1278 }; 1279 1280 adc2: adc@2284000 { 1281 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1282 reg = <0x02284000 0x4000>; 1283 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&clks IMX6SX_CLK_IPG>; 1285 clock-names = "adc"; 1286 fsl,adck-max-frequency = <30000000>, <40000000>, 1287 <20000000>; 1288 status = "disabled"; 1289 }; 1290 1291 wdog3: wdog@2288000 { 1292 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 1293 reg = <0x02288000 0x4000>; 1294 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1295 clocks = <&clks IMX6SX_CLK_IPG>; 1296 status = "disabled"; 1297 }; 1298 1299 ecspi5: spi@228c000 { 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 1303 reg = <0x0228c000 0x4000>; 1304 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1305 clocks = <&clks IMX6SX_CLK_ECSPI5>, 1306 <&clks IMX6SX_CLK_ECSPI5>; 1307 clock-names = "ipg", "per"; 1308 status = "disabled"; 1309 }; 1310 1311 uart6: serial@22a0000 { 1312 compatible = "fsl,imx6sx-uart", 1313 "fsl,imx6q-uart", "fsl,imx21-uart"; 1314 reg = <0x022a0000 0x4000>; 1315 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1317 <&clks IMX6SX_CLK_UART_SERIAL>; 1318 clock-names = "ipg", "per"; 1319 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; 1320 dma-names = "rx", "tx"; 1321 status = "disabled"; 1322 }; 1323 1324 pwm5: pwm@22a4000 { 1325 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1326 reg = <0x022a4000 0x4000>; 1327 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1328 clocks = <&clks IMX6SX_CLK_PWM5>, 1329 <&clks IMX6SX_CLK_PWM5>; 1330 clock-names = "ipg", "per"; 1331 #pwm-cells = <2>; 1332 }; 1333 1334 pwm6: pwm@22a8000 { 1335 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1336 reg = <0x022a8000 0x4000>; 1337 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1338 clocks = <&clks IMX6SX_CLK_PWM6>, 1339 <&clks IMX6SX_CLK_PWM6>; 1340 clock-names = "ipg", "per"; 1341 #pwm-cells = <2>; 1342 }; 1343 1344 pwm7: pwm@22ac000 { 1345 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1346 reg = <0x022ac000 0x4000>; 1347 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1348 clocks = <&clks IMX6SX_CLK_PWM7>, 1349 <&clks IMX6SX_CLK_PWM7>; 1350 clock-names = "ipg", "per"; 1351 #pwm-cells = <2>; 1352 }; 1353 1354 pwm8: pwm@22b0000 { 1355 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1356 reg = <0x0022b0000 0x4000>; 1357 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1358 clocks = <&clks IMX6SX_CLK_PWM8>, 1359 <&clks IMX6SX_CLK_PWM8>; 1360 clock-names = "ipg", "per"; 1361 #pwm-cells = <2>; 1362 }; 1363 }; 1364 1365 pcie: pcie@8ffc000 { 1366 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; 1367 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; 1368 reg-names = "dbi", "config"; 1369 #address-cells = <3>; 1370 #size-cells = <2>; 1371 device_type = "pci"; 1372 bus-range = <0x00 0xff>; 1373 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ 1374 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ 1375 num-lanes = <1>; 1376 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1377 interrupt-names = "msi"; 1378 #interrupt-cells = <1>; 1379 interrupt-map-mask = <0 0 0 0x7>; 1380 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1381 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1382 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1383 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&clks IMX6SX_CLK_PCIE_AXI>, 1385 <&clks IMX6SX_CLK_LVDS1_OUT>, 1386 <&clks IMX6SX_CLK_PCIE_REF_125M>, 1387 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1388 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; 1389 power-domains = <&pd_disp>, <&pd_pci>; 1390 power-domain-names = "pcie", "pcie_phy"; 1391 status = "disabled"; 1392 }; 1393 }; 1394}; 1395