1 /* $FreeBSD$ */ 2 /* $NecBSD: ncr53c500reg.h,v 1.5.14.1 2001/06/08 06:27:44 honda Exp $ */ 3 /* $NetBSD$ */ 4 5 /*- 6 * SPDX-License-Identifier: BSD-3-Clause 7 * 8 * [NetBSD for NEC PC-98 series] 9 * Copyright (c) 1995, 1996, 1997, 1998 10 * NetBSD/pc98 porting staff. All rights reserved. 11 * Copyright (c) 1995, 1996, 1997, 1998 12 * Naofumi HONDA. All rights reserved. 13 * Copyright (c) 1995, 1996, 1997, 1998 14 * Kouichi Matsuda. All rights reserved. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 29 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 30 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 31 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 36 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _NCR53C500REG_H_ 41 #define _NCR53C500REG_H_ 42 43 /* Control Register Set 0 */ 44 #define NCVIOSZ 0x10 45 46 #define cr0_tclsb 0x00 /* RW - Transfer Count Low */ 47 #define cr0_tcmsb 0x01 /* RW - Transfer Count Mid */ 48 #define cr0_sfifo 0x02 /* RW - FIFO data */ 49 #define cr0_cmd 0x03 /* RW - Command (2 deep) */ 50 #define cr0_stat 0x04 /* RO - Status */ 51 #define cr0_dstid 0x04 /* WO - Select/Reselect Bus ID */ 52 #define cr0_istat 0x05 /* RO - Interrupt */ 53 #define cr0_srtout 0x05 /* WO - Select/Reselect Timeout */ 54 #define cr0_seq 0x06 /* RO - Sequence Step */ 55 #define cr0_period 0x06 /* WO - Synch Transfer Period */ 56 #define cr0_sffl 0x07 /* RO - FIFO FLags */ 57 #define cr0_offs 0x07 /* WO - Synch Ofset */ 58 #define cr0_cfg1 0x08 /* RW - Configuration #1 */ 59 #define cr0_clk 0x09 /* WO - Clock Conversion Factor */ 60 #define cr0_tst 0x0a /* WO - Test (Chip Test Only) */ 61 #define cr0_cfg2 0x0b /* RW - Configuration #2 */ 62 #define cr0_cfg3 0x0c /* RW - Configuration #3 */ 63 #define cr0_cfg4 0x0d /* RW - Configuration #4 */ 64 #define cr0_tchsb 0x0e /* RW - Transfer Count High */ 65 #define cr0_fifo_bottom 0x0f /* WO - FIFO bottom */ 66 67 /* Control Register Set 1 */ 68 #define cr1_jumper 0x00 /* RW - Jumper Sense Port */ 69 #define cr1_sram_ptr 0x01 /* RW - SRAM Address Pointer */ 70 #define cr1_sram_data 0x02 /* RW - SRAM Data */ 71 #define cr1_fdata 0x04 /* RW - PIO FIFO */ 72 #define cr1_fstat 0x08 /* RW - PIO Status */ 73 #define cr1_atacmd 0x09 /* RW - ATA Command/Status */ 74 #define cr1_ataerr 0x0a /* RW - ATA Features/Error */ 75 #define cr1_pflag 0x0b /* RW - PIO Flag Interrupt Enable */ 76 #define cr1_cfg5 0x0d /* RW - Configuration #5 */ 77 #define cr1_sig 0x0e /* RO - Signature */ 78 #define cr1_cfg6 0x0f /* RW - Configuration #6 */ 79 80 /* atacmd (MPS110 ONLY) */ 81 #define ATACMD_POWDOWN 0x2d 82 #define ATACMD_ENGAGE 0x24 83 84 /* cr0_sffl regster */ 85 #define CR0_SFFLR_BMASK 0x1f /* scsi fifo byte mask */ 86 87 /* cfg4 */ 88 #define C4_ANE 0x04 89 90 /* cfg2 */ 91 #define C2_SCSI2 0x08 /* SCSI-2 Enable */ 92 #define C2_FE 0x40 /* Features Enable */ 93 94 /* cfg1 */ 95 #define C1_SLOW 0x80 /* Slow Cable Mode */ 96 #define C1_SRR 0x40 /* SCSI Reset Rep Int Dis */ 97 #define C1_PARENB 0x10 /* Enable Parity Check */ 98 99 /* clk factor */ 100 #define CLK_40M_F 0x00 101 #define CLK_25M_F 0x05 102 #define CLK_30M_F 0x06 103 #define CLK_35M_F 0x07 104 105 /* interrupt status register */ 106 #define INTR_SBR 0x80 /* SCSI Bus Reset */ 107 #define INTR_ILL 0x40 /* Illegal Command */ 108 #define INTR_DIS 0x20 /* Disconnect */ 109 #define INTR_BS 0x10 /* Bus Service */ 110 #define INTR_FC 0x08 /* Function Complete */ 111 #define INTR_RESEL 0x04 /* Reselected */ 112 #define INTR_SELATN 0x02 /* Select with ATN */ 113 #define INTR_SEL 0x01 /* Selected */ 114 #define INTR_RESELECT (INTR_RESEL | INTR_FC) 115 116 /* status register */ 117 #define STAT_INT 0x80 /* Interrupt */ 118 #define STAT_GE 0x40 /* Gross Error */ 119 #define STAT_PE 0x20 /* Parity Error */ 120 #define STAT_TC 0x10 /* Terminal Count */ 121 122 /* phase bits */ 123 #define IOI 0x01 124 #define CDI 0x02 125 #define MSGI 0x04 126 127 /* Information transfer phases */ 128 #define DATA_OUT_PHASE (0) 129 #define DATA_IN_PHASE (IOI) 130 #define COMMAND_PHASE (CDI) 131 #define STATUS_PHASE (CDI|IOI) 132 #define MESSAGE_OUT_PHASE (MSGI|CDI) 133 #define MESSAGE_IN_PHASE (MSGI|CDI|IOI) 134 135 #define PHASE_MASK (MSGI|CDI|IOI) 136 137 /* fifo status register */ 138 #define FIFO_SMASK 0x1e 139 #define FIFO_E 0x10 /* fifo empty */ 140 #define FIFO_B 0x00 /* there exists any */ 141 #define FIFO_1 0x08 /* 1/3 <= bytes < 2/3 */ 142 #define FIFO_2 0x04 /* 2/3 <= bytes < full */ 143 #define FIFO_F 0x02 /* full */ 144 #define FIFO_EN 0x01 /* fifo direction */ 145 #define FIFO_BRK 0x40 /* phase miss */ 146 147 #define FIFO_F_SZ 128 148 #define FIFO_1_SZ 44 149 #define FIFO_2_SZ 84 150 151 /* pflags */ 152 #define PFR_WRITE 0x01 153 154 /* Commands */ 155 #define CMD_DMA 0x80 /* DMA Bit */ 156 #define CMD_NOP 0x00 /* No Operation */ 157 #define CMD_FLUSH 0x01 /* Flush FIFO */ 158 #define CMD_RSTCHIP 0x02 /* Reset Chip */ 159 #define CMD_RSTSCSI 0x03 /* Reset SCSI Bus */ 160 #define CMD_RESEL 0x40 /* Reselect Sequence */ 161 #define CMD_SELNATN 0x41 /* Select without ATN */ 162 #define CMD_SELATN 0x42 /* Select with ATN */ 163 #define CMD_SELATNS 0x43 /* Select with ATN & Stop */ 164 #define CMD_ENSEL 0x44 /* Enable (Re)Selection */ 165 #define CMD_DISSEL 0x45 /* Disable (Re)Selection */ 166 #define CMD_SELATN3 0x46 /* Select with ATN3 */ 167 #define CMD_RESEL3 0x47 /* Reselect3 Sequence */ 168 #define CMD_SNDMSG 0x20 /* Send Message */ 169 #define CMD_SNDSTAT 0x21 /* Send Status */ 170 #define CMD_SNDDATA 0x22 /* Send Data */ 171 #define CMD_DISCSEQ 0x23 /* Disconnect Sequence */ 172 #define CMD_TERMSEQ 0x24 /* Terminate Sequence */ 173 #define CMD_TCCS 0x25 /* Target Command Comp Seq */ 174 #define CMD_DISC 0x27 /* Disconnect */ 175 #define CMD_RECMSG 0x28 /* Receive Message */ 176 #define CMD_RECCMD 0x29 /* Receive Command */ 177 #define CMD_RECDATA 0x2a /* Receive Data */ 178 #define CMD_RECCSEQ 0x2b /* Receive Command Sequence */ 179 #define CMD_ABORT 0x04 /* Target Abort DMA */ 180 #define CMD_TRANS 0x10 /* Transfer Information */ 181 #define CMD_ICCS 0x11 /* Initiator Cmd Comp Seq */ 182 #define CMD_MSGOK 0x12 /* Message Accepted */ 183 #define CMD_TRPAD 0x18 /* Transfer Pad */ 184 #define CMD_SETATN 0x1a /* Set ATN */ 185 #define CMD_RSTATN 0x1b /* Reset ATN */ 186 187 /* Default timeout */ 188 #define SEL_TOUT 0xa3 189 #endif /* !_NCR53C500REG_H_ */ 190