1 /*-
2 * Copyright (c) 2015 The FreeBSD Foundation
3 * Copyright (c) 2016 Ruslan Bukin <[email protected]>
4 * All rights reserved.
5 *
6 * Portions of this software were developed by Andrew Turner under
7 * sponsorship from the FreeBSD Foundation.
8 *
9 * Portions of this software were developed by SRI International and the
10 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
12 *
13 * Portions of this software were developed by the University of Cambridge
14 * Computer Laboratory as part of the CTSRD Project, with support from the
15 * UK Higher Education Innovation Fund (HEIF).
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 */
38
39 #include "opt_kstack_pages.h"
40 #include "opt_platform.h"
41
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/bus.h>
48 #include <sys/cpu.h>
49 #include <sys/cpuset.h>
50 #include <sys/kernel.h>
51 #include <sys/ktr.h>
52 #include <sys/malloc.h>
53 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/proc.h>
56 #include <sys/sched.h>
57 #include <sys/smp.h>
58
59 #include <vm/vm.h>
60 #include <vm/pmap.h>
61 #include <vm/vm_extern.h>
62 #include <vm/vm_kern.h>
63 #include <vm/vm_map.h>
64
65 #include <machine/intr.h>
66 #include <machine/smp.h>
67 #include <machine/sbi.h>
68
69 #ifdef FDT
70 #include <dev/ofw/openfirm.h>
71 #include <dev/ofw/ofw_cpu.h>
72 #endif
73
74 boolean_t ofw_cpu_reg(phandle_t node, u_int, cell_t *);
75
76 uint32_t __riscv_boot_ap[MAXCPU];
77
78 static enum {
79 CPUS_UNKNOWN,
80 #ifdef FDT
81 CPUS_FDT,
82 #endif
83 } cpu_enum_method;
84
85 static device_identify_t riscv64_cpu_identify;
86 static device_probe_t riscv64_cpu_probe;
87 static device_attach_t riscv64_cpu_attach;
88
89 static int ipi_handler(void *);
90
91 struct pcb stoppcbs[MAXCPU];
92
93 extern uint32_t boot_hart;
94 extern cpuset_t all_harts;
95
96 #ifdef INVARIANTS
97 static uint32_t cpu_reg[MAXCPU][2];
98 #endif
99 static device_t cpu_list[MAXCPU];
100
101 void mpentry(u_long hartid);
102 void init_secondary(uint64_t);
103
104 static struct mtx ap_boot_mtx;
105
106 /* Stacks for AP initialization, discarded once idle threads are started. */
107 void *bootstack;
108 static void *bootstacks[MAXCPU];
109
110 /* Count of started APs, used to synchronize access to bootstack. */
111 static volatile int aps_started;
112
113 /* Set to 1 once we're ready to let the APs out of the pen. */
114 static volatile int aps_ready;
115
116 /* Temporary variables for init_secondary() */
117 void *dpcpu[MAXCPU - 1];
118
119 static device_method_t riscv64_cpu_methods[] = {
120 /* Device interface */
121 DEVMETHOD(device_identify, riscv64_cpu_identify),
122 DEVMETHOD(device_probe, riscv64_cpu_probe),
123 DEVMETHOD(device_attach, riscv64_cpu_attach),
124
125 DEVMETHOD_END
126 };
127
128 static devclass_t riscv64_cpu_devclass;
129 static driver_t riscv64_cpu_driver = {
130 "riscv64_cpu",
131 riscv64_cpu_methods,
132 0
133 };
134
135 DRIVER_MODULE(riscv64_cpu, cpu, riscv64_cpu_driver, riscv64_cpu_devclass, 0, 0);
136
137 static void
riscv64_cpu_identify(driver_t * driver,device_t parent)138 riscv64_cpu_identify(driver_t *driver, device_t parent)
139 {
140
141 if (device_find_child(parent, "riscv64_cpu", -1) != NULL)
142 return;
143 if (BUS_ADD_CHILD(parent, 0, "riscv64_cpu", -1) == NULL)
144 device_printf(parent, "add child failed\n");
145 }
146
147 static int
riscv64_cpu_probe(device_t dev)148 riscv64_cpu_probe(device_t dev)
149 {
150 u_int cpuid;
151
152 cpuid = device_get_unit(dev);
153 if (cpuid >= MAXCPU || cpuid > mp_maxid)
154 return (EINVAL);
155
156 device_quiet(dev);
157 return (0);
158 }
159
160 static int
riscv64_cpu_attach(device_t dev)161 riscv64_cpu_attach(device_t dev)
162 {
163 const uint32_t *reg;
164 size_t reg_size;
165 u_int cpuid;
166 int i;
167
168 cpuid = device_get_unit(dev);
169
170 if (cpuid >= MAXCPU || cpuid > mp_maxid)
171 return (EINVAL);
172 KASSERT(cpu_list[cpuid] == NULL, ("Already have cpu %u", cpuid));
173
174 reg = cpu_get_cpuid(dev, ®_size);
175 if (reg == NULL)
176 return (EINVAL);
177
178 if (bootverbose) {
179 device_printf(dev, "register <");
180 for (i = 0; i < reg_size; i++)
181 printf("%s%x", (i == 0) ? "" : " ", reg[i]);
182 printf(">\n");
183 }
184
185 /* Set the device to start it later */
186 cpu_list[cpuid] = dev;
187
188 return (0);
189 }
190
191 static void
release_aps(void * dummy __unused)192 release_aps(void *dummy __unused)
193 {
194 cpuset_t mask;
195 int i;
196
197 if (mp_ncpus == 1)
198 return;
199
200 /* Setup the IPI handler */
201 riscv_setup_ipihandler(ipi_handler);
202
203 atomic_store_rel_int(&aps_ready, 1);
204
205 /* Wake up the other CPUs */
206 mask = all_harts;
207 CPU_CLR(boot_hart, &mask);
208
209 printf("Release APs\n");
210
211 sbi_send_ipi(mask.__bits);
212
213 for (i = 0; i < 2000; i++) {
214 if (smp_started)
215 return;
216 DELAY(1000);
217 }
218
219 printf("APs not started\n");
220 }
221 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
222
223 void
init_secondary(uint64_t hart)224 init_secondary(uint64_t hart)
225 {
226 struct pcpu *pcpup;
227 u_int cpuid;
228
229 /* Renumber this cpu */
230 cpuid = hart;
231 if (cpuid < boot_hart)
232 cpuid += mp_maxid + 1;
233 cpuid -= boot_hart;
234
235 /* Setup the pcpu pointer */
236 pcpup = &__pcpu[cpuid];
237 __asm __volatile("mv tp, %0" :: "r"(pcpup));
238
239 /* Workaround: make sure wfi doesn't halt the hart */
240 csr_set(sie, SIE_SSIE);
241 csr_set(sip, SIE_SSIE);
242
243 /* Signal the BSP and spin until it has released all APs. */
244 atomic_add_int(&aps_started, 1);
245 while (!atomic_load_int(&aps_ready))
246 __asm __volatile("wfi");
247
248 /* Initialize curthread */
249 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
250 pcpup->pc_curthread = pcpup->pc_idlethread;
251 schedinit_ap();
252
253 /*
254 * Identify current CPU. This is necessary to setup
255 * affinity registers and to provide support for
256 * runtime chip identification.
257 */
258 identify_cpu();
259
260 /* Enable software interrupts */
261 riscv_unmask_ipi();
262
263 #ifndef EARLY_AP_STARTUP
264 /* Start per-CPU event timers. */
265 cpu_initclocks_ap();
266 #endif
267
268 /* Enable external (PLIC) interrupts */
269 csr_set(sie, SIE_SEIE);
270
271 /* Activate this hart in the kernel pmap. */
272 CPU_SET_ATOMIC(hart, &kernel_pmap->pm_active);
273
274 /* Activate process 0's pmap. */
275 pmap_activate_boot(vmspace_pmap(proc0.p_vmspace));
276
277 mtx_lock_spin(&ap_boot_mtx);
278
279 atomic_add_rel_32(&smp_cpus, 1);
280
281 if (smp_cpus == mp_ncpus) {
282 /* enable IPI's, tlb shootdown, freezes etc */
283 atomic_store_rel_int(&smp_started, 1);
284 }
285
286 mtx_unlock_spin(&ap_boot_mtx);
287
288 /*
289 * Assert that smp_after_idle_runnable condition is reasonable.
290 */
291 MPASS(PCPU_GET(curpcb) == NULL);
292
293 /* Enter the scheduler */
294 sched_throw(NULL);
295
296 panic("scheduler returned us to init_secondary");
297 /* NOTREACHED */
298 }
299
300 static void
smp_after_idle_runnable(void * arg __unused)301 smp_after_idle_runnable(void *arg __unused)
302 {
303 struct pcpu *pc;
304 int cpu;
305
306 for (cpu = 1; cpu <= mp_maxid; cpu++) {
307 if (bootstacks[cpu] != NULL) {
308 pc = pcpu_find(cpu);
309 while (atomic_load_ptr(&pc->pc_curpcb) == NULL)
310 cpu_spinwait();
311 kmem_free((vm_offset_t)bootstacks[cpu], PAGE_SIZE);
312 }
313 }
314 }
315 SYSINIT(smp_after_idle_runnable, SI_SUB_SMP, SI_ORDER_ANY,
316 smp_after_idle_runnable, NULL);
317
318 static int
ipi_handler(void * arg)319 ipi_handler(void *arg)
320 {
321 u_int ipi_bitmap;
322 u_int cpu, ipi;
323 int bit;
324
325 csr_clear(sip, SIP_SSIP);
326
327 cpu = PCPU_GET(cpuid);
328
329 mb();
330
331 ipi_bitmap = atomic_readandclear_int(PCPU_PTR(pending_ipis));
332 if (ipi_bitmap == 0)
333 return (FILTER_HANDLED);
334
335 while ((bit = ffs(ipi_bitmap))) {
336 bit = (bit - 1);
337 ipi = (1 << bit);
338 ipi_bitmap &= ~ipi;
339
340 mb();
341
342 switch (ipi) {
343 case IPI_AST:
344 CTR0(KTR_SMP, "IPI_AST");
345 break;
346 case IPI_PREEMPT:
347 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
348 sched_preempt(curthread);
349 break;
350 case IPI_RENDEZVOUS:
351 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
352 smp_rendezvous_action();
353 break;
354 case IPI_STOP:
355 case IPI_STOP_HARD:
356 CTR0(KTR_SMP, (ipi == IPI_STOP) ? "IPI_STOP" : "IPI_STOP_HARD");
357 savectx(&stoppcbs[cpu]);
358
359 /* Indicate we are stopped */
360 CPU_SET_ATOMIC(cpu, &stopped_cpus);
361
362 /* Wait for restart */
363 while (!CPU_ISSET(cpu, &started_cpus))
364 cpu_spinwait();
365
366 CPU_CLR_ATOMIC(cpu, &started_cpus);
367 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
368 CTR0(KTR_SMP, "IPI_STOP (restart)");
369
370 /*
371 * The kernel debugger might have set a breakpoint,
372 * so flush the instruction cache.
373 */
374 fence_i();
375 break;
376 case IPI_HARDCLOCK:
377 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
378 hardclockintr();
379 break;
380 default:
381 panic("Unknown IPI %#0x on cpu %d", ipi, curcpu);
382 }
383 }
384
385 return (FILTER_HANDLED);
386 }
387
388 struct cpu_group *
cpu_topo(void)389 cpu_topo(void)
390 {
391
392 return (smp_topo_none());
393 }
394
395 /* Determine if we running MP machine */
396 int
cpu_mp_probe(void)397 cpu_mp_probe(void)
398 {
399
400 return (mp_ncpus > 1);
401 }
402
403 #ifdef FDT
404 static boolean_t
cpu_init_fdt(u_int id,phandle_t node,u_int addr_size,pcell_t * reg)405 cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
406 {
407 struct pcpu *pcpup;
408 vm_paddr_t start_addr;
409 uint64_t hart;
410 u_int cpuid;
411 int naps;
412 int error;
413
414 /* Check if this hart supports MMU. */
415 if (OF_getproplen(node, "mmu-type") < 0)
416 return (0);
417
418 KASSERT(id < MAXCPU, ("Too many CPUs"));
419
420 KASSERT(addr_size == 1 || addr_size == 2, ("Invalid register size"));
421 #ifdef INVARIANTS
422 cpu_reg[id][0] = reg[0];
423 if (addr_size == 2)
424 cpu_reg[id][1] = reg[1];
425 #endif
426
427 hart = reg[0];
428 if (addr_size == 2) {
429 hart <<= 32;
430 hart |= reg[1];
431 }
432
433 KASSERT(hart < MAXCPU, ("Too many harts."));
434
435 /* We are already running on this cpu */
436 if (hart == boot_hart)
437 return (1);
438
439 /*
440 * Rotate the CPU IDs to put the boot CPU as CPU 0.
441 * We keep the other CPUs ordered.
442 */
443 cpuid = hart;
444 if (cpuid < boot_hart)
445 cpuid += mp_maxid + 1;
446 cpuid -= boot_hart;
447
448 /* Check if we are able to start this cpu */
449 if (cpuid > mp_maxid)
450 return (0);
451
452 /*
453 * Depending on the SBI implementation, APs are waiting either in
454 * locore.S or to be activated explicitly, via SBI call.
455 */
456 if (sbi_probe_extension(SBI_EXT_ID_HSM) != 0) {
457 start_addr = pmap_kextract((vm_offset_t)mpentry);
458 error = sbi_hsm_hart_start(hart, start_addr, 0);
459 if (error != 0) {
460 mp_ncpus--;
461
462 /* Send a warning to the user and continue. */
463 printf("AP %u (hart %lu) failed to start, error %d\n",
464 cpuid, hart, error);
465 return (0);
466 }
467 }
468
469 pcpup = &__pcpu[cpuid];
470 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
471 pcpup->pc_hart = hart;
472
473 dpcpu[cpuid - 1] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
474 dpcpu_init(dpcpu[cpuid - 1], cpuid);
475
476 bootstacks[cpuid] = (void *)kmem_malloc(PAGE_SIZE, M_WAITOK | M_ZERO);
477
478 naps = atomic_load_int(&aps_started);
479 bootstack = (char *)bootstacks[cpuid] + PAGE_SIZE;
480
481 printf("Starting CPU %u (hart %lx)\n", cpuid, hart);
482 atomic_store_32(&__riscv_boot_ap[hart], 1);
483
484 /* Wait for the AP to switch to its boot stack. */
485 while (atomic_load_int(&aps_started) < naps + 1)
486 cpu_spinwait();
487
488 CPU_SET(cpuid, &all_cpus);
489 CPU_SET(hart, &all_harts);
490
491 return (1);
492 }
493 #endif
494
495 /* Initialize and fire up non-boot processors */
496 void
cpu_mp_start(void)497 cpu_mp_start(void)
498 {
499
500 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
501
502 CPU_SET(0, &all_cpus);
503 CPU_SET(boot_hart, &all_harts);
504
505 switch(cpu_enum_method) {
506 #ifdef FDT
507 case CPUS_FDT:
508 ofw_cpu_early_foreach(cpu_init_fdt, true);
509 break;
510 #endif
511 case CPUS_UNKNOWN:
512 break;
513 }
514 }
515
516 /* Introduce rest of cores to the world */
517 void
cpu_mp_announce(void)518 cpu_mp_announce(void)
519 {
520 }
521
522 static boolean_t
cpu_check_mmu(u_int id,phandle_t node,u_int addr_size,pcell_t * reg)523 cpu_check_mmu(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
524 {
525
526 /* Check if this hart supports MMU. */
527 if (OF_getproplen(node, "mmu-type") < 0)
528 return (0);
529
530 return (1);
531 }
532
533 void
cpu_mp_setmaxid(void)534 cpu_mp_setmaxid(void)
535 {
536 #ifdef FDT
537 int cores;
538
539 cores = ofw_cpu_early_foreach(cpu_check_mmu, true);
540 if (cores > 0) {
541 cores = MIN(cores, MAXCPU);
542 if (bootverbose)
543 printf("Found %d CPUs in the device tree\n", cores);
544 mp_ncpus = cores;
545 mp_maxid = cores - 1;
546 cpu_enum_method = CPUS_FDT;
547 return;
548 }
549 #endif
550
551 if (bootverbose)
552 printf("No CPU data, limiting to 1 core\n");
553 mp_ncpus = 1;
554 mp_maxid = 0;
555 }
556