1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) 2019 Marvell International Ltd. 3 */ 4 5 #ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_ 6 #define _OTX2_CRYPTODEV_HW_ACCESS_H_ 7 8 #include <stdint.h> 9 10 #include <rte_cryptodev.h> 11 #include <rte_memory.h> 12 13 #include "cpt_common.h" 14 #include "cpt_hw_types.h" 15 #include "cpt_mcode_defines.h" 16 17 #include "otx2_dev.h" 18 #include "otx2_cryptodev_qp.h" 19 20 /* CPT instruction queue length */ 21 #define OTX2_CPT_IQ_LEN 8200 22 23 #define OTX2_CPT_DEFAULT_CMD_QLEN OTX2_CPT_IQ_LEN 24 25 /* Mask which selects all engine groups */ 26 #define OTX2_CPT_ENG_GRPS_MASK 0xFF 27 28 /* Register offsets */ 29 30 /* LMT LF registers */ 31 #define OTX2_LMT_LF_LMTLINE(a) (0x0ull | (uint64_t)(a) << 3) 32 33 /* CPT LF registers */ 34 #define OTX2_CPT_LF_CTL 0x10ull 35 #define OTX2_CPT_LF_INPROG 0x40ull 36 #define OTX2_CPT_LF_MISC_INT 0xb0ull 37 #define OTX2_CPT_LF_MISC_INT_ENA_W1S 0xd0ull 38 #define OTX2_CPT_LF_MISC_INT_ENA_W1C 0xe0ull 39 #define OTX2_CPT_LF_Q_BASE 0xf0ull 40 #define OTX2_CPT_LF_Q_SIZE 0x100ull 41 #define OTX2_CPT_LF_Q_GRP_PTR 0x120ull 42 #define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3) 43 44 #define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3) 45 #define OTX2_CPT_AF_LF_CTL2(a) (0x29000ull | (uint64_t)(a) << 3) 46 47 #define OTX2_CPT_LF_BAR2(vf, q_id) \ 48 ((vf)->otx2_dev.bar2 + \ 49 ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12))) 50 51 #define OTX2_CPT_QUEUE_HI_PRIO 0x1 52 53 union otx2_cpt_lf_ctl { 54 uint64_t u; 55 struct { 56 uint64_t ena : 1; 57 uint64_t fc_ena : 1; 58 uint64_t fc_up_crossing : 1; 59 uint64_t reserved_3_3 : 1; 60 uint64_t fc_hyst_bits : 4; 61 uint64_t reserved_8_63 : 56; 62 } s; 63 }; 64 65 union otx2_cpt_lf_inprog { 66 uint64_t u; 67 struct { 68 uint64_t inflight : 9; 69 uint64_t reserved_9_15 : 7; 70 uint64_t eena : 1; 71 uint64_t grp_drp : 1; 72 uint64_t reserved_18_30 : 13; 73 uint64_t grb_partial : 1; 74 uint64_t grb_cnt : 8; 75 uint64_t gwb_cnt : 8; 76 uint64_t reserved_48_63 : 16; 77 } s; 78 }; 79 80 union otx2_cpt_lf_q_base { 81 uint64_t u; 82 struct { 83 uint64_t fault : 1; 84 uint64_t stopped : 1; 85 uint64_t reserved_2_6 : 5; 86 uint64_t addr : 46; 87 uint64_t reserved_53_63 : 11; 88 } s; 89 }; 90 91 union otx2_cpt_lf_q_size { 92 uint64_t u; 93 struct { 94 uint64_t size_div40 : 15; 95 uint64_t reserved_15_63 : 49; 96 } s; 97 }; 98 99 union otx2_cpt_af_lf_ctl { 100 uint64_t u; 101 struct { 102 uint64_t pri : 1; 103 uint64_t reserved_1_8 : 8; 104 uint64_t pf_func_inst : 1; 105 uint64_t cont_err : 1; 106 uint64_t reserved_11_15 : 5; 107 uint64_t nixtx_en : 1; 108 uint64_t reserved_17_47 : 31; 109 uint64_t grp : 8; 110 uint64_t reserved_56_63 : 8; 111 } s; 112 }; 113 114 union otx2_cpt_af_lf_ctl2 { 115 uint64_t u; 116 struct { 117 uint64_t exe_no_swap : 1; 118 uint64_t exe_ldwb : 1; 119 uint64_t reserved_2_31 : 30; 120 uint64_t sso_pf_func : 16; 121 uint64_t nix_pf_func : 16; 122 } s; 123 }; 124 125 union otx2_cpt_lf_q_grp_ptr { 126 uint64_t u; 127 struct { 128 uint64_t dq_ptr : 15; 129 uint64_t reserved_31_15 : 17; 130 uint64_t nq_ptr : 15; 131 uint64_t reserved_47_62 : 16; 132 uint64_t xq_xor : 1; 133 } s; 134 }; 135 136 /* 137 * Enumeration cpt_9x_comp_e 138 * 139 * CPT 9X Completion Enumeration 140 * Enumerates the values of CPT_RES_S[COMPCODE]. 141 */ 142 enum cpt_9x_comp_e { 143 CPT_9X_COMP_E_NOTDONE = 0x00, 144 CPT_9X_COMP_E_GOOD = 0x01, 145 CPT_9X_COMP_E_FAULT = 0x02, 146 CPT_9X_COMP_E_HWERR = 0x04, 147 CPT_9X_COMP_E_INSTERR = 0x05, 148 CPT_9X_COMP_E_LAST_ENTRY = 0x06 149 }; 150 151 void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev); 152 153 int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev); 154 155 int otx2_cpt_iq_enable(const struct rte_cryptodev *dev, 156 const struct otx2_cpt_qp *qp, uint8_t grp_mask, 157 uint8_t pri, uint32_t size_div40); 158 159 void otx2_cpt_iq_disable(struct otx2_cpt_qp *qp); 160 161 #endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */ 162