1 /* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 * Invertex AEON / Hifn 7751 driver
7 * Copyright (c) 1999 Invertex Inc. All rights reserved.
8 * Copyright (c) 1999 Theo de Raadt
9 * Copyright (c) 2000-2001 Network Security Technologies, Inc.
10 * http://www.netsec.net
11 * Copyright (c) 2003 Hifn Inc.
12 *
13 * This driver is based on a previous driver by Invertex, for which they
14 * requested: Please send any comments, feedback, bug-fixes, or feature
15 * requests to [email protected].
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. The name of the author may not be used to endorse or promote products
27 * derived from this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
31 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
32 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
34 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
38 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Effort sponsored in part by the Defense Advanced Research Projects
41 * Agency (DARPA) and Air Force Research Laboratory, Air Force
42 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
43 */
44
45 #include <sys/cdefs.h>
46 /*
47 * Driver for various Hifn encryption processors.
48 */
49 #include "opt_hifn.h"
50
51 #include <sys/param.h>
52 #include <sys/systm.h>
53 #include <sys/proc.h>
54 #include <sys/errno.h>
55 #include <sys/malloc.h>
56 #include <sys/kernel.h>
57 #include <sys/module.h>
58 #include <sys/mbuf.h>
59 #include <sys/lock.h>
60 #include <sys/mutex.h>
61 #include <sys/sysctl.h>
62 #include <sys/uio.h>
63
64 #include <vm/vm.h>
65 #include <vm/pmap.h>
66
67 #include <machine/bus.h>
68 #include <machine/resource.h>
69 #include <sys/bus.h>
70 #include <sys/rman.h>
71
72 #include <opencrypto/cryptodev.h>
73 #include <opencrypto/xform_auth.h>
74 #include <sys/random.h>
75 #include <sys/kobj.h>
76
77 #include "cryptodev_if.h"
78
79 #include <dev/pci/pcivar.h>
80 #include <dev/pci/pcireg.h>
81
82 #ifdef HIFN_RNDTEST
83 #include <dev/rndtest/rndtest.h>
84 #endif
85 #include <dev/hifn/hifn7751reg.h>
86 #include <dev/hifn/hifn7751var.h>
87
88 #ifdef HIFN_VULCANDEV
89 #include <sys/conf.h>
90 #include <sys/uio.h>
91
92 static struct cdevsw vulcanpk_cdevsw; /* forward declaration */
93 #endif
94
95 /*
96 * Prototypes and count for the pci_device structure
97 */
98 static int hifn_probe(device_t);
99 static int hifn_attach(device_t);
100 static int hifn_detach(device_t);
101 static int hifn_suspend(device_t);
102 static int hifn_resume(device_t);
103 static int hifn_shutdown(device_t);
104
105 static int hifn_probesession(device_t, const struct crypto_session_params *);
106 static int hifn_newsession(device_t, crypto_session_t,
107 const struct crypto_session_params *);
108 static int hifn_process(device_t, struct cryptop *, int);
109
110 static device_method_t hifn_methods[] = {
111 /* Device interface */
112 DEVMETHOD(device_probe, hifn_probe),
113 DEVMETHOD(device_attach, hifn_attach),
114 DEVMETHOD(device_detach, hifn_detach),
115 DEVMETHOD(device_suspend, hifn_suspend),
116 DEVMETHOD(device_resume, hifn_resume),
117 DEVMETHOD(device_shutdown, hifn_shutdown),
118
119 /* crypto device methods */
120 DEVMETHOD(cryptodev_probesession, hifn_probesession),
121 DEVMETHOD(cryptodev_newsession, hifn_newsession),
122 DEVMETHOD(cryptodev_process, hifn_process),
123
124 DEVMETHOD_END
125 };
126
127 static driver_t hifn_driver = {
128 "hifn",
129 hifn_methods,
130 sizeof (struct hifn_softc)
131 };
132
133 DRIVER_MODULE(hifn, pci, hifn_driver, 0, 0);
134 MODULE_DEPEND(hifn, crypto, 1, 1, 1);
135 #ifdef HIFN_RNDTEST
136 MODULE_DEPEND(hifn, rndtest, 1, 1, 1);
137 #endif
138
139 static void hifn_reset_board(struct hifn_softc *, int);
140 static void hifn_reset_puc(struct hifn_softc *);
141 static void hifn_puc_wait(struct hifn_softc *);
142 static int hifn_enable_crypto(struct hifn_softc *);
143 static void hifn_set_retry(struct hifn_softc *sc);
144 static void hifn_init_dma(struct hifn_softc *);
145 static void hifn_init_pci_registers(struct hifn_softc *);
146 static int hifn_sramsize(struct hifn_softc *);
147 static int hifn_dramsize(struct hifn_softc *);
148 static int hifn_ramtype(struct hifn_softc *);
149 static void hifn_sessions(struct hifn_softc *);
150 static void hifn_intr(void *);
151 static u_int hifn_write_command(struct hifn_command *, u_int8_t *);
152 static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);
153 static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *);
154 static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int);
155 static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *);
156 static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *);
157 static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *);
158 static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *);
159 static int hifn_init_pubrng(struct hifn_softc *);
160 static void hifn_rng(void *);
161 static void hifn_tick(void *);
162 static void hifn_abort(struct hifn_softc *);
163 static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *);
164
165 static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t);
166 static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t);
167
168 static __inline u_int32_t
READ_REG_0(struct hifn_softc * sc,bus_size_t reg)169 READ_REG_0(struct hifn_softc *sc, bus_size_t reg)
170 {
171 u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg);
172 sc->sc_bar0_lastreg = (bus_size_t) -1;
173 return (v);
174 }
175 #define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val)
176
177 static __inline u_int32_t
READ_REG_1(struct hifn_softc * sc,bus_size_t reg)178 READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
179 {
180 u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg);
181 sc->sc_bar1_lastreg = (bus_size_t) -1;
182 return (v);
183 }
184 #define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val)
185
186 static SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
187 "Hifn driver parameters");
188
189 #ifdef HIFN_DEBUG
190 static int hifn_debug = 0;
191 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug,
192 0, "control debugging msgs");
193 #endif
194
195 static struct hifn_stats hifnstats;
196 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats,
197 hifn_stats, "driver statistics");
198 static int hifn_maxbatch = 1;
199 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch,
200 0, "max ops to batch w/o interrupt");
201
202 /*
203 * Probe for a supported device. The PCI vendor and device
204 * IDs are used to detect devices we know how to handle.
205 */
206 static int
hifn_probe(device_t dev)207 hifn_probe(device_t dev)
208 {
209 if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX &&
210 pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON)
211 return (BUS_PROBE_DEFAULT);
212 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
213 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 ||
214 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
215 pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
216 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 ||
217 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811))
218 return (BUS_PROBE_DEFAULT);
219 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
220 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751)
221 return (BUS_PROBE_DEFAULT);
222 return (ENXIO);
223 }
224
225 static void
hifn_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)226 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
227 {
228 bus_addr_t *paddr = (bus_addr_t*) arg;
229 *paddr = segs->ds_addr;
230 }
231
232 static const char*
hifn_partname(struct hifn_softc * sc)233 hifn_partname(struct hifn_softc *sc)
234 {
235 /* XXX sprintf numbers when not decoded */
236 switch (pci_get_vendor(sc->sc_dev)) {
237 case PCI_VENDOR_HIFN:
238 switch (pci_get_device(sc->sc_dev)) {
239 case PCI_PRODUCT_HIFN_6500: return "Hifn 6500";
240 case PCI_PRODUCT_HIFN_7751: return "Hifn 7751";
241 case PCI_PRODUCT_HIFN_7811: return "Hifn 7811";
242 case PCI_PRODUCT_HIFN_7951: return "Hifn 7951";
243 case PCI_PRODUCT_HIFN_7955: return "Hifn 7955";
244 case PCI_PRODUCT_HIFN_7956: return "Hifn 7956";
245 }
246 return "Hifn unknown-part";
247 case PCI_VENDOR_INVERTEX:
248 switch (pci_get_device(sc->sc_dev)) {
249 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON";
250 }
251 return "Invertex unknown-part";
252 case PCI_VENDOR_NETSEC:
253 switch (pci_get_device(sc->sc_dev)) {
254 case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751";
255 }
256 return "NetSec unknown-part";
257 }
258 return "Unknown-vendor unknown-part";
259 }
260
261 static void
default_harvest(struct rndtest_state * rsp,void * buf,u_int count)262 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
263 {
264 /* MarkM: FIX!! Check that this does not swamp the harvester! */
265 random_harvest_queue(buf, count, RANDOM_PURE_HIFN);
266 }
267
268 static u_int
checkmaxmin(device_t dev,const char * what,u_int v,u_int min,u_int max)269 checkmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max)
270 {
271 if (v > max) {
272 device_printf(dev, "Warning, %s %u out of range, "
273 "using max %u\n", what, v, max);
274 v = max;
275 } else if (v < min) {
276 device_printf(dev, "Warning, %s %u out of range, "
277 "using min %u\n", what, v, min);
278 v = min;
279 }
280 return v;
281 }
282
283 /*
284 * Select PLL configuration for 795x parts. This is complicated in
285 * that we cannot determine the optimal parameters without user input.
286 * The reference clock is derived from an external clock through a
287 * multiplier. The external clock is either the host bus (i.e. PCI)
288 * or an external clock generator. When using the PCI bus we assume
289 * the clock is either 33 or 66 MHz; for an external source we cannot
290 * tell the speed.
291 *
292 * PLL configuration is done with a string: "pci" for PCI bus, or "ext"
293 * for an external source, followed by the frequency. We calculate
294 * the appropriate multiplier and PLL register contents accordingly.
295 * When no configuration is given we default to "pci66" since that
296 * always will allow the card to work. If a card is using the PCI
297 * bus clock and in a 33MHz slot then it will be operating at half
298 * speed until the correct information is provided.
299 *
300 * We use a default setting of "ext66" because according to Mike Ham
301 * of HiFn, almost every board in existence has an external crystal
302 * populated at 66Mhz. Using PCI can be a problem on modern motherboards,
303 * because PCI33 can have clocks from 0 to 33Mhz, and some have
304 * non-PCI-compliant spread-spectrum clocks, which can confuse the pll.
305 */
306 static void
hifn_getpllconfig(device_t dev,u_int * pll)307 hifn_getpllconfig(device_t dev, u_int *pll)
308 {
309 const char *pllspec;
310 u_int freq, mul, fl, fh;
311 u_int32_t pllconfig;
312 char *nxt;
313
314 if (resource_string_value("hifn", device_get_unit(dev),
315 "pllconfig", &pllspec))
316 pllspec = "ext66";
317 fl = 33, fh = 66;
318 pllconfig = 0;
319 if (strncmp(pllspec, "ext", 3) == 0) {
320 pllspec += 3;
321 pllconfig |= HIFN_PLL_REF_SEL;
322 switch (pci_get_device(dev)) {
323 case PCI_PRODUCT_HIFN_7955:
324 case PCI_PRODUCT_HIFN_7956:
325 fl = 20, fh = 100;
326 break;
327 #ifdef notyet
328 case PCI_PRODUCT_HIFN_7954:
329 fl = 20, fh = 66;
330 break;
331 #endif
332 }
333 } else if (strncmp(pllspec, "pci", 3) == 0)
334 pllspec += 3;
335 freq = strtoul(pllspec, &nxt, 10);
336 if (nxt == pllspec)
337 freq = 66;
338 else
339 freq = checkmaxmin(dev, "frequency", freq, fl, fh);
340 /*
341 * Calculate multiplier. We target a Fck of 266 MHz,
342 * allowing only even values, possibly rounded down.
343 * Multipliers > 8 must set the charge pump current.
344 */
345 mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12);
346 pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT;
347 if (mul > 8)
348 pllconfig |= HIFN_PLL_IS;
349 *pll = pllconfig;
350 }
351
352 /*
353 * Attach an interface that successfully probed.
354 */
355 static int
hifn_attach(device_t dev)356 hifn_attach(device_t dev)
357 {
358 struct hifn_softc *sc = device_get_softc(dev);
359 caddr_t kva;
360 int rseg, rid;
361 char rbase;
362 uint16_t rev;
363
364 sc->sc_dev = dev;
365
366 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF);
367
368 /* XXX handle power management */
369
370 /*
371 * The 7951 and 795x have a random number generator and
372 * public key support; note this.
373 */
374 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
375 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
376 pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
377 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956))
378 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC;
379 /*
380 * The 7811 has a random number generator and
381 * we also note it's identity 'cuz of some quirks.
382 */
383 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
384 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
385 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG;
386
387 /*
388 * The 795x parts support AES.
389 */
390 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
391 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
392 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) {
393 sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES;
394 /*
395 * Select PLL configuration. This depends on the
396 * bus and board design and must be manually configured
397 * if the default setting is unacceptable.
398 */
399 hifn_getpllconfig(dev, &sc->sc_pllconfig);
400 }
401
402 /*
403 * Setup PCI resources. Note that we record the bus
404 * tag and handle for each register mapping, this is
405 * used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
406 * and WRITE_REG_1 macros throughout the driver.
407 */
408 pci_enable_busmaster(dev);
409
410 rid = HIFN_BAR0;
411 sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
412 RF_ACTIVE);
413 if (sc->sc_bar0res == NULL) {
414 device_printf(dev, "cannot map bar%d register space\n", 0);
415 goto fail_pci;
416 }
417 sc->sc_st0 = rman_get_bustag(sc->sc_bar0res);
418 sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res);
419 sc->sc_bar0_lastreg = (bus_size_t) -1;
420
421 rid = HIFN_BAR1;
422 sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
423 RF_ACTIVE);
424 if (sc->sc_bar1res == NULL) {
425 device_printf(dev, "cannot map bar%d register space\n", 1);
426 goto fail_io0;
427 }
428 sc->sc_st1 = rman_get_bustag(sc->sc_bar1res);
429 sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res);
430 sc->sc_bar1_lastreg = (bus_size_t) -1;
431
432 hifn_set_retry(sc);
433
434 /*
435 * Setup the area where the Hifn DMA's descriptors
436 * and associated data structures.
437 */
438 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* PCI parent */
439 1, 0, /* alignment,boundary */
440 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
441 BUS_SPACE_MAXADDR, /* highaddr */
442 NULL, NULL, /* filter, filterarg */
443 HIFN_MAX_DMALEN, /* maxsize */
444 MAX_SCATTER, /* nsegments */
445 HIFN_MAX_SEGLEN, /* maxsegsize */
446 BUS_DMA_ALLOCNOW, /* flags */
447 NULL, /* lockfunc */
448 NULL, /* lockarg */
449 &sc->sc_dmat)) {
450 device_printf(dev, "cannot allocate DMA tag\n");
451 goto fail_io1;
452 }
453 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
454 device_printf(dev, "cannot create dma map\n");
455 bus_dma_tag_destroy(sc->sc_dmat);
456 goto fail_io1;
457 }
458 if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
459 device_printf(dev, "cannot alloc dma buffer\n");
460 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
461 bus_dma_tag_destroy(sc->sc_dmat);
462 goto fail_io1;
463 }
464 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva,
465 sizeof (*sc->sc_dma),
466 hifn_dmamap_cb, &sc->sc_dma_physaddr,
467 BUS_DMA_NOWAIT)) {
468 device_printf(dev, "cannot load dma map\n");
469 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap);
470 bus_dma_tag_destroy(sc->sc_dmat);
471 goto fail_io1;
472 }
473 sc->sc_dma = (struct hifn_dma *)kva;
474 bzero(sc->sc_dma, sizeof(*sc->sc_dma));
475
476 KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!"));
477 KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!"));
478 KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!"));
479 KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!"));
480
481 /*
482 * Reset the board and do the ``secret handshake''
483 * to enable the crypto support. Then complete the
484 * initialization procedure by setting up the interrupt
485 * and hooking in to the system crypto support so we'll
486 * get used for system services like the crypto device,
487 * IPsec, RNG device, etc.
488 */
489 hifn_reset_board(sc, 0);
490
491 if (hifn_enable_crypto(sc) != 0) {
492 device_printf(dev, "crypto enabling failed\n");
493 goto fail_mem;
494 }
495 hifn_reset_puc(sc);
496
497 hifn_init_dma(sc);
498 hifn_init_pci_registers(sc);
499
500 /* XXX can't dynamically determine ram type for 795x; force dram */
501 if (sc->sc_flags & HIFN_IS_7956)
502 sc->sc_drammodel = 1;
503 else if (hifn_ramtype(sc))
504 goto fail_mem;
505
506 if (sc->sc_drammodel == 0)
507 hifn_sramsize(sc);
508 else
509 hifn_dramsize(sc);
510
511 /*
512 * Workaround for NetSec 7751 rev A: half ram size because two
513 * of the address lines were left floating
514 */
515 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
516 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 &&
517 pci_get_revid(dev) == 0x61) /*XXX???*/
518 sc->sc_ramsize >>= 1;
519
520 /*
521 * Arrange the interrupt line.
522 */
523 rid = 0;
524 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
525 RF_SHAREABLE|RF_ACTIVE);
526 if (sc->sc_irq == NULL) {
527 device_printf(dev, "could not map interrupt\n");
528 goto fail_mem;
529 }
530 /*
531 * NB: Network code assumes we are blocked with splimp()
532 * so make sure the IRQ is marked appropriately.
533 */
534 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
535 NULL, hifn_intr, sc, &sc->sc_intrhand)) {
536 device_printf(dev, "could not setup interrupt\n");
537 goto fail_intr2;
538 }
539
540 hifn_sessions(sc);
541
542 /*
543 * NB: Keep only the low 16 bits; this masks the chip id
544 * from the 7951.
545 */
546 rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff;
547
548 rseg = sc->sc_ramsize / 1024;
549 rbase = 'K';
550 if (sc->sc_ramsize >= (1024 * 1024)) {
551 rbase = 'M';
552 rseg /= 1024;
553 }
554 device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram",
555 hifn_partname(sc), rev,
556 rseg, rbase, sc->sc_drammodel ? 'd' : 's');
557 if (sc->sc_flags & HIFN_IS_7956)
558 printf(", pll=0x%x<%s clk, %ux mult>",
559 sc->sc_pllconfig,
560 sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci",
561 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11));
562 printf("\n");
563
564 WRITE_REG_0(sc, HIFN_0_PUCNFG,
565 READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID);
566 sc->sc_ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
567
568 switch (sc->sc_ena) {
569 case HIFN_PUSTAT_ENA_2:
570 case HIFN_PUSTAT_ENA_1:
571 sc->sc_cid = crypto_get_driverid(dev,
572 sizeof(struct hifn_session), CRYPTOCAP_F_HARDWARE);
573 if (sc->sc_cid < 0) {
574 device_printf(dev, "could not get crypto driver id\n");
575 goto fail_intr;
576 }
577 break;
578 }
579
580 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
581 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
582
583 if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG))
584 hifn_init_pubrng(sc);
585
586 callout_init(&sc->sc_tickto, 1);
587 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
588
589 return (0);
590
591 fail_intr:
592 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
593 fail_intr2:
594 /* XXX don't store rid */
595 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
596 fail_mem:
597 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
598 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
599 bus_dma_tag_destroy(sc->sc_dmat);
600
601 /* Turn off DMA polling */
602 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
603 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
604 fail_io1:
605 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
606 fail_io0:
607 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
608 fail_pci:
609 mtx_destroy(&sc->sc_mtx);
610 return (ENXIO);
611 }
612
613 /*
614 * Detach an interface that successfully probed.
615 */
616 static int
hifn_detach(device_t dev)617 hifn_detach(device_t dev)
618 {
619 struct hifn_softc *sc = device_get_softc(dev);
620
621 KASSERT(sc != NULL, ("hifn_detach: null software carrier!"));
622
623 /* disable interrupts */
624 WRITE_REG_1(sc, HIFN_1_DMA_IER, 0);
625
626 /*XXX other resources */
627 callout_stop(&sc->sc_tickto);
628 callout_stop(&sc->sc_rngto);
629 #ifdef HIFN_RNDTEST
630 if (sc->sc_rndtest)
631 rndtest_detach(sc->sc_rndtest);
632 #endif
633
634 /* Turn off DMA polling */
635 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
636 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
637
638 crypto_unregister_all(sc->sc_cid);
639
640 bus_generic_detach(dev); /*XXX should be no children, right? */
641
642 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
643 /* XXX don't store rid */
644 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
645
646 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
647 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
648 bus_dma_tag_destroy(sc->sc_dmat);
649
650 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
651 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
652
653 mtx_destroy(&sc->sc_mtx);
654
655 return (0);
656 }
657
658 /*
659 * Stop all chip I/O so that the kernel's probe routines don't
660 * get confused by errant DMAs when rebooting.
661 */
662 static int
hifn_shutdown(device_t dev)663 hifn_shutdown(device_t dev)
664 {
665 #ifdef notyet
666 hifn_stop(device_get_softc(dev));
667 #endif
668 return (0);
669 }
670
671 /*
672 * Device suspend routine. Stop the interface and save some PCI
673 * settings in case the BIOS doesn't restore them properly on
674 * resume.
675 */
676 static int
hifn_suspend(device_t dev)677 hifn_suspend(device_t dev)
678 {
679 struct hifn_softc *sc = device_get_softc(dev);
680 #ifdef notyet
681 hifn_stop(sc);
682 #endif
683 sc->sc_suspended = 1;
684
685 return (0);
686 }
687
688 /*
689 * Device resume routine. Restore some PCI settings in case the BIOS
690 * doesn't, re-enable busmastering, and restart the interface if
691 * appropriate.
692 */
693 static int
hifn_resume(device_t dev)694 hifn_resume(device_t dev)
695 {
696 struct hifn_softc *sc = device_get_softc(dev);
697 #ifdef notyet
698 /* reinitialize interface if necessary */
699 if (ifp->if_flags & IFF_UP)
700 rl_init(sc);
701 #endif
702 sc->sc_suspended = 0;
703
704 return (0);
705 }
706
707 static int
hifn_init_pubrng(struct hifn_softc * sc)708 hifn_init_pubrng(struct hifn_softc *sc)
709 {
710 u_int32_t r;
711 int i;
712
713 #ifdef HIFN_RNDTEST
714 sc->sc_rndtest = rndtest_attach(sc->sc_dev);
715 if (sc->sc_rndtest)
716 sc->sc_harvest = rndtest_harvest;
717 else
718 sc->sc_harvest = default_harvest;
719 #else
720 sc->sc_harvest = default_harvest;
721 #endif
722 if ((sc->sc_flags & HIFN_IS_7811) == 0) {
723 /* Reset 7951 public key/rng engine */
724 WRITE_REG_1(sc, HIFN_1_PUB_RESET,
725 READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET);
726
727 for (i = 0; i < 100; i++) {
728 DELAY(1000);
729 if ((READ_REG_1(sc, HIFN_1_PUB_RESET) &
730 HIFN_PUBRST_RESET) == 0)
731 break;
732 }
733
734 if (i == 100) {
735 device_printf(sc->sc_dev, "public key init failed\n");
736 return (1);
737 }
738 }
739
740 /* Enable the rng, if available */
741 if (sc->sc_flags & HIFN_HAS_RNG) {
742 if (sc->sc_flags & HIFN_IS_7811) {
743 r = READ_REG_1(sc, HIFN_1_7811_RNGENA);
744 if (r & HIFN_7811_RNGENA_ENA) {
745 r &= ~HIFN_7811_RNGENA_ENA;
746 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
747 }
748 WRITE_REG_1(sc, HIFN_1_7811_RNGCFG,
749 HIFN_7811_RNGCFG_DEFL);
750 r |= HIFN_7811_RNGENA_ENA;
751 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
752 } else
753 WRITE_REG_1(sc, HIFN_1_RNG_CONFIG,
754 READ_REG_1(sc, HIFN_1_RNG_CONFIG) |
755 HIFN_RNGCFG_ENA);
756
757 sc->sc_rngfirst = 1;
758 if (hz >= 100)
759 sc->sc_rnghz = hz / 100;
760 else
761 sc->sc_rnghz = 1;
762 callout_init(&sc->sc_rngto, 1);
763 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
764 }
765
766 /* Enable public key engine, if available */
767 if (sc->sc_flags & HIFN_HAS_PUBLIC) {
768 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
769 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE;
770 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
771 #ifdef HIFN_VULCANDEV
772 sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0,
773 UID_ROOT, GID_WHEEL, 0666,
774 "vulcanpk");
775 sc->sc_pkdev->si_drv1 = sc;
776 #endif
777 }
778
779 return (0);
780 }
781
782 static void
hifn_rng(void * vsc)783 hifn_rng(void *vsc)
784 {
785 #define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0
786 struct hifn_softc *sc = vsc;
787 u_int32_t sts, num[2];
788 int i;
789
790 if (sc->sc_flags & HIFN_IS_7811) {
791 /* ONLY VALID ON 7811!!!! */
792 for (i = 0; i < 5; i++) {
793 sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
794 if (sts & HIFN_7811_RNGSTS_UFL) {
795 device_printf(sc->sc_dev,
796 "RNG underflow: disabling\n");
797 return;
798 }
799 if ((sts & HIFN_7811_RNGSTS_RDY) == 0)
800 break;
801
802 /*
803 * There are at least two words in the RNG FIFO
804 * at this point.
805 */
806 num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
807 num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
808 /* NB: discard first data read */
809 if (sc->sc_rngfirst)
810 sc->sc_rngfirst = 0;
811 else
812 (*sc->sc_harvest)(sc->sc_rndtest,
813 num, sizeof (num));
814 }
815 } else {
816 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA);
817
818 /* NB: discard first data read */
819 if (sc->sc_rngfirst)
820 sc->sc_rngfirst = 0;
821 else
822 (*sc->sc_harvest)(sc->sc_rndtest,
823 num, sizeof (num[0]));
824 }
825
826 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
827 #undef RANDOM_BITS
828 }
829
830 static void
hifn_puc_wait(struct hifn_softc * sc)831 hifn_puc_wait(struct hifn_softc *sc)
832 {
833 int i;
834 int reg = HIFN_0_PUCTRL;
835
836 if (sc->sc_flags & HIFN_IS_7956) {
837 reg = HIFN_0_PUCTRL2;
838 }
839
840 for (i = 5000; i > 0; i--) {
841 DELAY(1);
842 if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET))
843 break;
844 }
845 if (!i)
846 device_printf(sc->sc_dev, "proc unit did not reset\n");
847 }
848
849 /*
850 * Reset the processing unit.
851 */
852 static void
hifn_reset_puc(struct hifn_softc * sc)853 hifn_reset_puc(struct hifn_softc *sc)
854 {
855 /* Reset processing unit */
856 int reg = HIFN_0_PUCTRL;
857
858 if (sc->sc_flags & HIFN_IS_7956) {
859 reg = HIFN_0_PUCTRL2;
860 }
861 WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA);
862
863 hifn_puc_wait(sc);
864 }
865
866 /*
867 * Set the Retry and TRDY registers; note that we set them to
868 * zero because the 7811 locks up when forced to retry (section
869 * 3.6 of "Specification Update SU-0014-04". Not clear if we
870 * should do this for all Hifn parts, but it doesn't seem to hurt.
871 */
872 static void
hifn_set_retry(struct hifn_softc * sc)873 hifn_set_retry(struct hifn_softc *sc)
874 {
875 /* NB: RETRY only responds to 8-bit reads/writes */
876 pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1);
877 pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 1);
878 }
879
880 /*
881 * Resets the board. Values in the registers are left as is
882 * from the reset (i.e. initial values are assigned elsewhere).
883 */
884 static void
hifn_reset_board(struct hifn_softc * sc,int full)885 hifn_reset_board(struct hifn_softc *sc, int full)
886 {
887 u_int32_t reg;
888
889 /*
890 * Set polling in the DMA configuration register to zero. 0x7 avoids
891 * resetting the board and zeros out the other fields.
892 */
893 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
894 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
895
896 /*
897 * Now that polling has been disabled, we have to wait 1 ms
898 * before resetting the board.
899 */
900 DELAY(1000);
901
902 /* Reset the DMA unit */
903 if (full) {
904 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
905 DELAY(1000);
906 } else {
907 WRITE_REG_1(sc, HIFN_1_DMA_CNFG,
908 HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET);
909 hifn_reset_puc(sc);
910 }
911
912 KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!"));
913 bzero(sc->sc_dma, sizeof(*sc->sc_dma));
914
915 /* Bring dma unit out of reset */
916 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
917 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
918
919 hifn_puc_wait(sc);
920 hifn_set_retry(sc);
921
922 if (sc->sc_flags & HIFN_IS_7811) {
923 for (reg = 0; reg < 1000; reg++) {
924 if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) &
925 HIFN_MIPSRST_CRAMINIT)
926 break;
927 DELAY(1000);
928 }
929 if (reg == 1000)
930 printf(": cram init timeout\n");
931 } else {
932 /* set up DMA configuration register #2 */
933 /* turn off all PK and BAR0 swaps */
934 WRITE_REG_1(sc, HIFN_1_DMA_CNFG2,
935 (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)|
936 (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)|
937 (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)|
938 (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT));
939 }
940
941 }
942
943 static u_int32_t
hifn_next_signature(u_int32_t a,u_int cnt)944 hifn_next_signature(u_int32_t a, u_int cnt)
945 {
946 int i;
947 u_int32_t v;
948
949 for (i = 0; i < cnt; i++) {
950
951 /* get the parity */
952 v = a & 0x80080125;
953 v ^= v >> 16;
954 v ^= v >> 8;
955 v ^= v >> 4;
956 v ^= v >> 2;
957 v ^= v >> 1;
958
959 a = (v & 1) ^ (a << 1);
960 }
961
962 return a;
963 }
964
965 struct pci2id {
966 u_short pci_vendor;
967 u_short pci_prod;
968 char card_id[13];
969 };
970 static struct pci2id pci2id[] = {
971 {
972 PCI_VENDOR_HIFN,
973 PCI_PRODUCT_HIFN_7951,
974 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
975 0x00, 0x00, 0x00, 0x00, 0x00 }
976 }, {
977 PCI_VENDOR_HIFN,
978 PCI_PRODUCT_HIFN_7955,
979 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
980 0x00, 0x00, 0x00, 0x00, 0x00 }
981 }, {
982 PCI_VENDOR_HIFN,
983 PCI_PRODUCT_HIFN_7956,
984 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
985 0x00, 0x00, 0x00, 0x00, 0x00 }
986 }, {
987 PCI_VENDOR_NETSEC,
988 PCI_PRODUCT_NETSEC_7751,
989 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
990 0x00, 0x00, 0x00, 0x00, 0x00 }
991 }, {
992 PCI_VENDOR_INVERTEX,
993 PCI_PRODUCT_INVERTEX_AEON,
994 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
995 0x00, 0x00, 0x00, 0x00, 0x00 }
996 }, {
997 PCI_VENDOR_HIFN,
998 PCI_PRODUCT_HIFN_7811,
999 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1000 0x00, 0x00, 0x00, 0x00, 0x00 }
1001 }, {
1002 /*
1003 * Other vendors share this PCI ID as well, such as
1004 * http://www.powercrypt.com, and obviously they also
1005 * use the same key.
1006 */
1007 PCI_VENDOR_HIFN,
1008 PCI_PRODUCT_HIFN_7751,
1009 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1010 0x00, 0x00, 0x00, 0x00, 0x00 }
1011 },
1012 };
1013
1014 /*
1015 * Checks to see if crypto is already enabled. If crypto isn't enable,
1016 * "hifn_enable_crypto" is called to enable it. The check is important,
1017 * as enabling crypto twice will lock the board.
1018 */
1019 static int
hifn_enable_crypto(struct hifn_softc * sc)1020 hifn_enable_crypto(struct hifn_softc *sc)
1021 {
1022 u_int32_t dmacfg, ramcfg, encl, addr, i;
1023 char *offtbl = NULL;
1024
1025 for (i = 0; i < nitems(pci2id); i++) {
1026 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) &&
1027 pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) {
1028 offtbl = pci2id[i].card_id;
1029 break;
1030 }
1031 }
1032 if (offtbl == NULL) {
1033 device_printf(sc->sc_dev, "Unknown card!\n");
1034 return (1);
1035 }
1036
1037 ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1038 dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG);
1039
1040 /*
1041 * The RAM config register's encrypt level bit needs to be set before
1042 * every read performed on the encryption level register.
1043 */
1044 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1045
1046 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1047
1048 /*
1049 * Make sure we don't re-unlock. Two unlocks kills chip until the
1050 * next reboot.
1051 */
1052 if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) {
1053 #ifdef HIFN_DEBUG
1054 if (hifn_debug)
1055 device_printf(sc->sc_dev,
1056 "Strong crypto already enabled!\n");
1057 #endif
1058 goto report;
1059 }
1060
1061 if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
1062 #ifdef HIFN_DEBUG
1063 if (hifn_debug)
1064 device_printf(sc->sc_dev,
1065 "Unknown encryption level 0x%x\n", encl);
1066 #endif
1067 return 1;
1068 }
1069
1070 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK |
1071 HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
1072 DELAY(1000);
1073 addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1);
1074 DELAY(1000);
1075 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0);
1076 DELAY(1000);
1077
1078 for (i = 0; i <= 12; i++) {
1079 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
1080 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr);
1081
1082 DELAY(1000);
1083 }
1084
1085 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1086 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1087
1088 #ifdef HIFN_DEBUG
1089 if (hifn_debug) {
1090 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
1091 device_printf(sc->sc_dev, "Engine is permanently "
1092 "locked until next system reset!\n");
1093 else
1094 device_printf(sc->sc_dev, "Engine enabled "
1095 "successfully!\n");
1096 }
1097 #endif
1098
1099 report:
1100 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg);
1101 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg);
1102
1103 switch (encl) {
1104 case HIFN_PUSTAT_ENA_1:
1105 case HIFN_PUSTAT_ENA_2:
1106 break;
1107 case HIFN_PUSTAT_ENA_0:
1108 default:
1109 device_printf(sc->sc_dev, "disabled");
1110 break;
1111 }
1112
1113 return 0;
1114 }
1115
1116 /*
1117 * Give initial values to the registers listed in the "Register Space"
1118 * section of the HIFN Software Development reference manual.
1119 */
1120 static void
hifn_init_pci_registers(struct hifn_softc * sc)1121 hifn_init_pci_registers(struct hifn_softc *sc)
1122 {
1123 /* write fixed values needed by the Initialization registers */
1124 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1125 WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1126 WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1127
1128 /* write all 4 ring address registers */
1129 WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr +
1130 offsetof(struct hifn_dma, cmdr[0]));
1131 WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr +
1132 offsetof(struct hifn_dma, srcr[0]));
1133 WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr +
1134 offsetof(struct hifn_dma, dstr[0]));
1135 WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr +
1136 offsetof(struct hifn_dma, resr[0]));
1137
1138 DELAY(2000);
1139
1140 /* write status register */
1141 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1142 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1143 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1144 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1145 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1146 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1147 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1148 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1149 HIFN_DMACSR_S_WAIT |
1150 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1151 HIFN_DMACSR_C_WAIT |
1152 HIFN_DMACSR_ENGINE |
1153 ((sc->sc_flags & HIFN_HAS_PUBLIC) ?
1154 HIFN_DMACSR_PUBDONE : 0) |
1155 ((sc->sc_flags & HIFN_IS_7811) ?
1156 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0));
1157
1158 sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
1159 sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1160 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1161 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1162 ((sc->sc_flags & HIFN_IS_7811) ?
1163 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0);
1164 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
1165 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1166
1167
1168 if (sc->sc_flags & HIFN_IS_7956) {
1169 u_int32_t pll;
1170
1171 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1172 HIFN_PUCNFG_TCALLPHASES |
1173 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32);
1174
1175 /* turn off the clocks and insure bypass is set */
1176 pll = READ_REG_1(sc, HIFN_1_PLL);
1177 pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL))
1178 | HIFN_PLL_BP | HIFN_PLL_MBSET;
1179 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1180 DELAY(10*1000); /* 10ms */
1181
1182 /* change configuration */
1183 pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig;
1184 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1185 DELAY(10*1000); /* 10ms */
1186
1187 /* disable bypass */
1188 pll &= ~HIFN_PLL_BP;
1189 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1190 /* enable clocks with new configuration */
1191 pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL;
1192 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1193 } else {
1194 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1195 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1196 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1197 (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
1198 }
1199
1200 WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1201 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1202 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1203 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1204 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1205 }
1206
1207 /*
1208 * The maximum number of sessions supported by the card
1209 * is dependent on the amount of context ram, which
1210 * encryption algorithms are enabled, and how compression
1211 * is configured. This should be configured before this
1212 * routine is called.
1213 */
1214 static void
hifn_sessions(struct hifn_softc * sc)1215 hifn_sessions(struct hifn_softc *sc)
1216 {
1217 u_int32_t pucnfg;
1218 int ctxsize;
1219
1220 pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1221
1222 if (pucnfg & HIFN_PUCNFG_COMPSING) {
1223 if (pucnfg & HIFN_PUCNFG_ENCCNFG)
1224 ctxsize = 128;
1225 else
1226 ctxsize = 512;
1227 /*
1228 * 7955/7956 has internal context memory of 32K
1229 */
1230 if (sc->sc_flags & HIFN_IS_7956)
1231 sc->sc_maxses = 32768 / ctxsize;
1232 else
1233 sc->sc_maxses = 1 +
1234 ((sc->sc_ramsize - 32768) / ctxsize);
1235 } else
1236 sc->sc_maxses = sc->sc_ramsize / 16384;
1237
1238 if (sc->sc_maxses > 2048)
1239 sc->sc_maxses = 2048;
1240 }
1241
1242 /*
1243 * Determine ram type (sram or dram). Board should be just out of a reset
1244 * state when this is called.
1245 */
1246 static int
hifn_ramtype(struct hifn_softc * sc)1247 hifn_ramtype(struct hifn_softc *sc)
1248 {
1249 u_int8_t data[8], dataexpect[8];
1250 int i;
1251
1252 for (i = 0; i < sizeof(data); i++)
1253 data[i] = dataexpect[i] = 0x55;
1254 if (hifn_writeramaddr(sc, 0, data))
1255 return (-1);
1256 if (hifn_readramaddr(sc, 0, data))
1257 return (-1);
1258 if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1259 sc->sc_drammodel = 1;
1260 return (0);
1261 }
1262
1263 for (i = 0; i < sizeof(data); i++)
1264 data[i] = dataexpect[i] = 0xaa;
1265 if (hifn_writeramaddr(sc, 0, data))
1266 return (-1);
1267 if (hifn_readramaddr(sc, 0, data))
1268 return (-1);
1269 if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1270 sc->sc_drammodel = 1;
1271 return (0);
1272 }
1273
1274 return (0);
1275 }
1276
1277 #define HIFN_SRAM_MAX (32 << 20)
1278 #define HIFN_SRAM_STEP_SIZE 16384
1279 #define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE)
1280
1281 static int
hifn_sramsize(struct hifn_softc * sc)1282 hifn_sramsize(struct hifn_softc *sc)
1283 {
1284 u_int32_t a;
1285 u_int8_t data[8];
1286 u_int8_t dataexpect[sizeof(data)];
1287 int32_t i;
1288
1289 for (i = 0; i < sizeof(data); i++)
1290 data[i] = dataexpect[i] = i ^ 0x5a;
1291
1292 for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) {
1293 a = i * HIFN_SRAM_STEP_SIZE;
1294 bcopy(&i, data, sizeof(i));
1295 hifn_writeramaddr(sc, a, data);
1296 }
1297
1298 for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) {
1299 a = i * HIFN_SRAM_STEP_SIZE;
1300 bcopy(&i, dataexpect, sizeof(i));
1301 if (hifn_readramaddr(sc, a, data) < 0)
1302 return (0);
1303 if (bcmp(data, dataexpect, sizeof(data)) != 0)
1304 return (0);
1305 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE;
1306 }
1307
1308 return (0);
1309 }
1310
1311 /*
1312 * XXX For dram boards, one should really try all of the
1313 * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG
1314 * is already set up correctly.
1315 */
1316 static int
hifn_dramsize(struct hifn_softc * sc)1317 hifn_dramsize(struct hifn_softc *sc)
1318 {
1319 u_int32_t cnfg;
1320
1321 if (sc->sc_flags & HIFN_IS_7956) {
1322 /*
1323 * 7955/7956 have a fixed internal ram of only 32K.
1324 */
1325 sc->sc_ramsize = 32768;
1326 } else {
1327 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
1328 HIFN_PUCNFG_DRAMMASK;
1329 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
1330 }
1331 return (0);
1332 }
1333
1334 static void
hifn_alloc_slot(struct hifn_softc * sc,int * cmdp,int * srcp,int * dstp,int * resp)1335 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp)
1336 {
1337 struct hifn_dma *dma = sc->sc_dma;
1338
1339 if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) {
1340 sc->sc_cmdi = 0;
1341 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1342 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1343 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1344 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1345 }
1346 *cmdp = sc->sc_cmdi++;
1347 sc->sc_cmdk = sc->sc_cmdi;
1348
1349 if (sc->sc_srci == HIFN_D_SRC_RSIZE) {
1350 sc->sc_srci = 0;
1351 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID |
1352 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1353 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1354 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1355 }
1356 *srcp = sc->sc_srci++;
1357 sc->sc_srck = sc->sc_srci;
1358
1359 if (sc->sc_dsti == HIFN_D_DST_RSIZE) {
1360 sc->sc_dsti = 0;
1361 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID |
1362 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1363 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE,
1364 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1365 }
1366 *dstp = sc->sc_dsti++;
1367 sc->sc_dstk = sc->sc_dsti;
1368
1369 if (sc->sc_resi == HIFN_D_RES_RSIZE) {
1370 sc->sc_resi = 0;
1371 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1372 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1373 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1374 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1375 }
1376 *resp = sc->sc_resi++;
1377 sc->sc_resk = sc->sc_resi;
1378 }
1379
1380 static int
hifn_writeramaddr(struct hifn_softc * sc,int addr,u_int8_t * data)1381 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1382 {
1383 struct hifn_dma *dma = sc->sc_dma;
1384 hifn_base_command_t wc;
1385 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1386 int r, cmdi, resi, srci, dsti;
1387
1388 wc.masks = htole16(3 << 13);
1389 wc.session_num = htole16(addr >> 14);
1390 wc.total_source_count = htole16(8);
1391 wc.total_dest_count = htole16(addr & 0x3fff);
1392
1393 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1394
1395 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1396 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1397 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1398
1399 /* build write command */
1400 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1401 *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc;
1402 bcopy(data, &dma->test_src, sizeof(dma->test_src));
1403
1404 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr
1405 + offsetof(struct hifn_dma, test_src));
1406 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr
1407 + offsetof(struct hifn_dma, test_dst));
1408
1409 dma->cmdr[cmdi].l = htole32(16 | masks);
1410 dma->srcr[srci].l = htole32(8 | masks);
1411 dma->dstr[dsti].l = htole32(4 | masks);
1412 dma->resr[resi].l = htole32(4 | masks);
1413
1414 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1415 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1416
1417 for (r = 10000; r >= 0; r--) {
1418 DELAY(10);
1419 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1420 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1421 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1422 break;
1423 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1424 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1425 }
1426 if (r == 0) {
1427 device_printf(sc->sc_dev, "writeramaddr -- "
1428 "result[%d](addr %d) still valid\n", resi, addr);
1429 r = -1;
1430 return (-1);
1431 } else
1432 r = 0;
1433
1434 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1435 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1436 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1437
1438 return (r);
1439 }
1440
1441 static int
hifn_readramaddr(struct hifn_softc * sc,int addr,u_int8_t * data)1442 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1443 {
1444 struct hifn_dma *dma = sc->sc_dma;
1445 hifn_base_command_t rc;
1446 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1447 int r, cmdi, srci, dsti, resi;
1448
1449 rc.masks = htole16(2 << 13);
1450 rc.session_num = htole16(addr >> 14);
1451 rc.total_source_count = htole16(addr & 0x3fff);
1452 rc.total_dest_count = htole16(8);
1453
1454 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1455
1456 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1457 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1458 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1459
1460 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1461 *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc;
1462
1463 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr +
1464 offsetof(struct hifn_dma, test_src));
1465 dma->test_src = 0;
1466 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr +
1467 offsetof(struct hifn_dma, test_dst));
1468 dma->test_dst = 0;
1469 dma->cmdr[cmdi].l = htole32(8 | masks);
1470 dma->srcr[srci].l = htole32(8 | masks);
1471 dma->dstr[dsti].l = htole32(8 | masks);
1472 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks);
1473
1474 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1475 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1476
1477 for (r = 10000; r >= 0; r--) {
1478 DELAY(10);
1479 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1480 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1481 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1482 break;
1483 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1484 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1485 }
1486 if (r == 0) {
1487 device_printf(sc->sc_dev, "readramaddr -- "
1488 "result[%d](addr %d) still valid\n", resi, addr);
1489 r = -1;
1490 } else {
1491 r = 0;
1492 bcopy(&dma->test_dst, data, sizeof(dma->test_dst));
1493 }
1494
1495 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1496 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1497 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1498
1499 return (r);
1500 }
1501
1502 /*
1503 * Initialize the descriptor rings.
1504 */
1505 static void
hifn_init_dma(struct hifn_softc * sc)1506 hifn_init_dma(struct hifn_softc *sc)
1507 {
1508 struct hifn_dma *dma = sc->sc_dma;
1509 int i;
1510
1511 hifn_set_retry(sc);
1512
1513 /* initialize static pointer values */
1514 for (i = 0; i < HIFN_D_CMD_RSIZE; i++)
1515 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr +
1516 offsetof(struct hifn_dma, command_bufs[i][0]));
1517 for (i = 0; i < HIFN_D_RES_RSIZE; i++)
1518 dma->resr[i].p = htole32(sc->sc_dma_physaddr +
1519 offsetof(struct hifn_dma, result_bufs[i][0]));
1520
1521 dma->cmdr[HIFN_D_CMD_RSIZE].p =
1522 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0]));
1523 dma->srcr[HIFN_D_SRC_RSIZE].p =
1524 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0]));
1525 dma->dstr[HIFN_D_DST_RSIZE].p =
1526 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0]));
1527 dma->resr[HIFN_D_RES_RSIZE].p =
1528 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0]));
1529
1530 sc->sc_cmdu = sc->sc_srcu = sc->sc_dstu = sc->sc_resu = 0;
1531 sc->sc_cmdi = sc->sc_srci = sc->sc_dsti = sc->sc_resi = 0;
1532 sc->sc_cmdk = sc->sc_srck = sc->sc_dstk = sc->sc_resk = 0;
1533 }
1534
1535 /*
1536 * Writes out the raw command buffer space. Returns the
1537 * command buffer size.
1538 */
1539 static u_int
hifn_write_command(struct hifn_command * cmd,u_int8_t * buf)1540 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
1541 {
1542 struct cryptop *crp;
1543 u_int8_t *buf_pos;
1544 hifn_base_command_t *base_cmd;
1545 hifn_mac_command_t *mac_cmd;
1546 hifn_crypt_command_t *cry_cmd;
1547 int using_mac, using_crypt, ivlen;
1548 u_int32_t dlen, slen;
1549
1550 crp = cmd->crp;
1551 buf_pos = buf;
1552 using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC;
1553 using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT;
1554
1555 base_cmd = (hifn_base_command_t *)buf_pos;
1556 base_cmd->masks = htole16(cmd->base_masks);
1557 slen = cmd->src_mapsize;
1558 if (cmd->sloplen)
1559 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t);
1560 else
1561 dlen = cmd->dst_mapsize;
1562 base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO);
1563 base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1564 dlen >>= 16;
1565 slen >>= 16;
1566 base_cmd->session_num = htole16(
1567 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1568 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1569 buf_pos += sizeof(hifn_base_command_t);
1570
1571 if (using_mac) {
1572 mac_cmd = (hifn_mac_command_t *)buf_pos;
1573 dlen = crp->crp_aad_length + crp->crp_payload_length;
1574 mac_cmd->source_count = htole16(dlen & 0xffff);
1575 dlen >>= 16;
1576 mac_cmd->masks = htole16(cmd->mac_masks |
1577 ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M));
1578 if (crp->crp_aad_length != 0)
1579 mac_cmd->header_skip = htole16(crp->crp_aad_start);
1580 else
1581 mac_cmd->header_skip = htole16(crp->crp_payload_start);
1582 mac_cmd->reserved = 0;
1583 buf_pos += sizeof(hifn_mac_command_t);
1584 }
1585
1586 if (using_crypt) {
1587 cry_cmd = (hifn_crypt_command_t *)buf_pos;
1588 dlen = crp->crp_payload_length;
1589 cry_cmd->source_count = htole16(dlen & 0xffff);
1590 dlen >>= 16;
1591 cry_cmd->masks = htole16(cmd->cry_masks |
1592 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M));
1593 cry_cmd->header_skip = htole16(crp->crp_payload_length);
1594 cry_cmd->reserved = 0;
1595 buf_pos += sizeof(hifn_crypt_command_t);
1596 }
1597
1598 if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) {
1599 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH);
1600 buf_pos += HIFN_MAC_KEY_LENGTH;
1601 }
1602
1603 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) {
1604 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1605 case HIFN_CRYPT_CMD_ALG_AES:
1606 /*
1607 * AES keys are variable 128, 192 and
1608 * 256 bits (16, 24 and 32 bytes).
1609 */
1610 bcopy(cmd->ck, buf_pos, cmd->cklen);
1611 buf_pos += cmd->cklen;
1612 break;
1613 }
1614 }
1615
1616 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
1617 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1618 case HIFN_CRYPT_CMD_ALG_AES:
1619 ivlen = HIFN_AES_IV_LENGTH;
1620 break;
1621 default:
1622 ivlen = HIFN_IV_LENGTH;
1623 break;
1624 }
1625 bcopy(cmd->iv, buf_pos, ivlen);
1626 buf_pos += ivlen;
1627 }
1628
1629 if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) {
1630 bzero(buf_pos, 8);
1631 buf_pos += 8;
1632 }
1633
1634 return (buf_pos - buf);
1635 }
1636
1637 static int
hifn_dmamap_aligned(struct hifn_operand * op)1638 hifn_dmamap_aligned(struct hifn_operand *op)
1639 {
1640 int i;
1641
1642 for (i = 0; i < op->nsegs; i++) {
1643 if (op->segs[i].ds_addr & 3)
1644 return (0);
1645 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3))
1646 return (0);
1647 }
1648 return (1);
1649 }
1650
1651 static __inline int
hifn_dmamap_dstwrap(struct hifn_softc * sc,int idx)1652 hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx)
1653 {
1654 struct hifn_dma *dma = sc->sc_dma;
1655
1656 if (++idx == HIFN_D_DST_RSIZE) {
1657 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP |
1658 HIFN_D_MASKDONEIRQ);
1659 HIFN_DSTR_SYNC(sc, idx,
1660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1661 idx = 0;
1662 }
1663 return (idx);
1664 }
1665
1666 static int
hifn_dmamap_load_dst(struct hifn_softc * sc,struct hifn_command * cmd)1667 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd)
1668 {
1669 struct hifn_dma *dma = sc->sc_dma;
1670 struct hifn_operand *dst = &cmd->dst;
1671 u_int32_t p, l;
1672 int idx, used = 0, i;
1673
1674 idx = sc->sc_dsti;
1675 for (i = 0; i < dst->nsegs - 1; i++) {
1676 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1677 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1678 HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len);
1679 HIFN_DSTR_SYNC(sc, idx,
1680 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1681 used++;
1682
1683 idx = hifn_dmamap_dstwrap(sc, idx);
1684 }
1685
1686 if (cmd->sloplen == 0) {
1687 p = dst->segs[i].ds_addr;
1688 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1689 dst->segs[i].ds_len;
1690 } else {
1691 p = sc->sc_dma_physaddr +
1692 offsetof(struct hifn_dma, slop[cmd->slopidx]);
1693 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1694 sizeof(u_int32_t);
1695
1696 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) {
1697 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1698 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1699 HIFN_D_MASKDONEIRQ |
1700 (dst->segs[i].ds_len - cmd->sloplen));
1701 HIFN_DSTR_SYNC(sc, idx,
1702 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1703 used++;
1704
1705 idx = hifn_dmamap_dstwrap(sc, idx);
1706 }
1707 }
1708 dma->dstr[idx].p = htole32(p);
1709 dma->dstr[idx].l = htole32(l);
1710 HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1711 used++;
1712
1713 idx = hifn_dmamap_dstwrap(sc, idx);
1714
1715 sc->sc_dsti = idx;
1716 sc->sc_dstu += used;
1717 return (idx);
1718 }
1719
1720 static __inline int
hifn_dmamap_srcwrap(struct hifn_softc * sc,int idx)1721 hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx)
1722 {
1723 struct hifn_dma *dma = sc->sc_dma;
1724
1725 if (++idx == HIFN_D_SRC_RSIZE) {
1726 dma->srcr[idx].l = htole32(HIFN_D_VALID |
1727 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1728 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1729 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1730 idx = 0;
1731 }
1732 return (idx);
1733 }
1734
1735 static int
hifn_dmamap_load_src(struct hifn_softc * sc,struct hifn_command * cmd)1736 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd)
1737 {
1738 struct hifn_dma *dma = sc->sc_dma;
1739 struct hifn_operand *src = &cmd->src;
1740 int idx, i;
1741 u_int32_t last = 0;
1742
1743 idx = sc->sc_srci;
1744 for (i = 0; i < src->nsegs; i++) {
1745 if (i == src->nsegs - 1)
1746 last = HIFN_D_LAST;
1747
1748 dma->srcr[idx].p = htole32(src->segs[i].ds_addr);
1749 dma->srcr[idx].l = htole32(src->segs[i].ds_len |
1750 HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last);
1751 HIFN_SRCR_SYNC(sc, idx,
1752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1753
1754 idx = hifn_dmamap_srcwrap(sc, idx);
1755 }
1756 sc->sc_srci = idx;
1757 sc->sc_srcu += src->nsegs;
1758 return (idx);
1759 }
1760
1761 static void
hifn_op_cb(void * arg,bus_dma_segment_t * seg,int nsegs,int error)1762 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, int error)
1763 {
1764 struct hifn_operand *op = arg;
1765
1766 KASSERT(nsegs <= MAX_SCATTER,
1767 ("hifn_op_cb: too many DMA segments (%u > %u) "
1768 "returned when mapping operand", nsegs, MAX_SCATTER));
1769 op->nsegs = nsegs;
1770 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1771 }
1772
1773 static int
hifn_crypto(struct hifn_softc * sc,struct hifn_command * cmd,struct cryptop * crp,int hint)1774 hifn_crypto(
1775 struct hifn_softc *sc,
1776 struct hifn_command *cmd,
1777 struct cryptop *crp,
1778 int hint)
1779 {
1780 struct hifn_dma *dma = sc->sc_dma;
1781 u_int32_t cmdlen, csr;
1782 int cmdi, resi, err = 0;
1783
1784 /*
1785 * need 1 cmd, and 1 res
1786 *
1787 * NB: check this first since it's easy.
1788 */
1789 HIFN_LOCK(sc);
1790 if ((sc->sc_cmdu + 1) > HIFN_D_CMD_RSIZE ||
1791 (sc->sc_resu + 1) > HIFN_D_RES_RSIZE) {
1792 #ifdef HIFN_DEBUG
1793 if (hifn_debug) {
1794 device_printf(sc->sc_dev,
1795 "cmd/result exhaustion, cmdu %u resu %u\n",
1796 sc->sc_cmdu, sc->sc_resu);
1797 }
1798 #endif
1799 hifnstats.hst_nomem_cr++;
1800 HIFN_UNLOCK(sc);
1801 return (ERESTART);
1802 }
1803
1804 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) {
1805 hifnstats.hst_nomem_map++;
1806 HIFN_UNLOCK(sc);
1807 return (ENOMEM);
1808 }
1809
1810 if (bus_dmamap_load_crp(sc->sc_dmat, cmd->src_map, crp, hifn_op_cb,
1811 &cmd->src, BUS_DMA_NOWAIT)) {
1812 hifnstats.hst_nomem_load++;
1813 err = ENOMEM;
1814 goto err_srcmap1;
1815 }
1816 cmd->src_mapsize = crypto_buffer_len(&crp->crp_buf);
1817
1818 if (hifn_dmamap_aligned(&cmd->src)) {
1819 cmd->sloplen = cmd->src_mapsize & 3;
1820 cmd->dst = cmd->src;
1821 } else if (crp->crp_buf.cb_type == CRYPTO_BUF_MBUF) {
1822 int totlen, len;
1823 struct mbuf *m, *m0, *mlast;
1824
1825 KASSERT(cmd->dst_m == NULL,
1826 ("hifn_crypto: dst_m initialized improperly"));
1827 hifnstats.hst_unaligned++;
1828
1829 /*
1830 * Source is not aligned on a longword boundary.
1831 * Copy the data to insure alignment. If we fail
1832 * to allocate mbufs or clusters while doing this
1833 * we return ERESTART so the operation is requeued
1834 * at the crypto later, but only if there are
1835 * ops already posted to the hardware; otherwise we
1836 * have no guarantee that we'll be re-entered.
1837 */
1838 totlen = cmd->src_mapsize;
1839 if (crp->crp_buf.cb_mbuf->m_flags & M_PKTHDR) {
1840 len = MHLEN;
1841 MGETHDR(m0, M_NOWAIT, MT_DATA);
1842 if (m0 && !m_dup_pkthdr(m0, crp->crp_buf.cb_mbuf,
1843 M_NOWAIT)) {
1844 m_free(m0);
1845 m0 = NULL;
1846 }
1847 } else {
1848 len = MLEN;
1849 MGET(m0, M_NOWAIT, MT_DATA);
1850 }
1851 if (m0 == NULL) {
1852 hifnstats.hst_nomem_mbuf++;
1853 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1854 goto err_srcmap;
1855 }
1856 if (totlen >= MINCLSIZE) {
1857 if (!(MCLGET(m0, M_NOWAIT))) {
1858 hifnstats.hst_nomem_mcl++;
1859 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1860 m_freem(m0);
1861 goto err_srcmap;
1862 }
1863 len = MCLBYTES;
1864 }
1865 totlen -= len;
1866 m0->m_pkthdr.len = m0->m_len = len;
1867 mlast = m0;
1868
1869 while (totlen > 0) {
1870 MGET(m, M_NOWAIT, MT_DATA);
1871 if (m == NULL) {
1872 hifnstats.hst_nomem_mbuf++;
1873 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1874 m_freem(m0);
1875 goto err_srcmap;
1876 }
1877 len = MLEN;
1878 if (totlen >= MINCLSIZE) {
1879 if (!(MCLGET(m, M_NOWAIT))) {
1880 hifnstats.hst_nomem_mcl++;
1881 err = sc->sc_cmdu ? ERESTART : ENOMEM;
1882 mlast->m_next = m;
1883 m_freem(m0);
1884 goto err_srcmap;
1885 }
1886 len = MCLBYTES;
1887 }
1888
1889 m->m_len = len;
1890 m0->m_pkthdr.len += len;
1891 totlen -= len;
1892
1893 mlast->m_next = m;
1894 mlast = m;
1895 }
1896 cmd->dst_m = m0;
1897
1898 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1899 &cmd->dst_map)) {
1900 hifnstats.hst_nomem_map++;
1901 err = ENOMEM;
1902 goto err_srcmap;
1903 }
1904
1905 if (bus_dmamap_load_mbuf_sg(sc->sc_dmat, cmd->dst_map, m0,
1906 cmd->dst_segs, &cmd->dst_nsegs, 0)) {
1907 hifnstats.hst_nomem_map++;
1908 err = ENOMEM;
1909 goto err_dstmap1;
1910 }
1911 cmd->dst_mapsize = m0->m_pkthdr.len;
1912 } else {
1913 err = EINVAL;
1914 goto err_srcmap;
1915 }
1916
1917 #ifdef HIFN_DEBUG
1918 if (hifn_debug) {
1919 device_printf(sc->sc_dev,
1920 "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n",
1921 READ_REG_1(sc, HIFN_1_DMA_CSR),
1922 READ_REG_1(sc, HIFN_1_DMA_IER),
1923 sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu,
1924 cmd->src_nsegs, cmd->dst_nsegs);
1925 }
1926 #endif
1927
1928 if (cmd->src_map == cmd->dst_map) {
1929 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1930 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1931 } else {
1932 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
1933 BUS_DMASYNC_PREWRITE);
1934 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
1935 BUS_DMASYNC_PREREAD);
1936 }
1937
1938 /*
1939 * need N src, and N dst
1940 */
1941 if ((sc->sc_srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE ||
1942 (sc->sc_dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) {
1943 #ifdef HIFN_DEBUG
1944 if (hifn_debug) {
1945 device_printf(sc->sc_dev,
1946 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n",
1947 sc->sc_srcu, cmd->src_nsegs,
1948 sc->sc_dstu, cmd->dst_nsegs);
1949 }
1950 #endif
1951 hifnstats.hst_nomem_sd++;
1952 err = ERESTART;
1953 goto err_dstmap;
1954 }
1955
1956 if (sc->sc_cmdi == HIFN_D_CMD_RSIZE) {
1957 sc->sc_cmdi = 0;
1958 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1959 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1960 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1961 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1962 }
1963 cmdi = sc->sc_cmdi++;
1964 cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]);
1965 HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE);
1966
1967 /* .p for command/result already set */
1968 dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
1969 HIFN_D_MASKDONEIRQ);
1970 HIFN_CMDR_SYNC(sc, cmdi,
1971 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1972 sc->sc_cmdu++;
1973
1974 /*
1975 * We don't worry about missing an interrupt (which a "command wait"
1976 * interrupt salvages us from), unless there is more than one command
1977 * in the queue.
1978 */
1979 if (sc->sc_cmdu > 1) {
1980 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT;
1981 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1982 }
1983
1984 hifnstats.hst_ipackets++;
1985 hifnstats.hst_ibytes += cmd->src_mapsize;
1986
1987 hifn_dmamap_load_src(sc, cmd);
1988
1989 /*
1990 * Unlike other descriptors, we don't mask done interrupt from
1991 * result descriptor.
1992 */
1993 #ifdef HIFN_DEBUG
1994 if (hifn_debug)
1995 printf("load res\n");
1996 #endif
1997 if (sc->sc_resi == HIFN_D_RES_RSIZE) {
1998 sc->sc_resi = 0;
1999 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
2000 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
2001 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
2002 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2003 }
2004 resi = sc->sc_resi++;
2005 KASSERT(sc->sc_hifn_commands[resi] == NULL,
2006 ("hifn_crypto: command slot %u busy", resi));
2007 sc->sc_hifn_commands[resi] = cmd;
2008 HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD);
2009 if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) {
2010 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2011 HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
2012 sc->sc_curbatch++;
2013 if (sc->sc_curbatch > hifnstats.hst_maxbatch)
2014 hifnstats.hst_maxbatch = sc->sc_curbatch;
2015 hifnstats.hst_totbatch++;
2016 } else {
2017 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2018 HIFN_D_VALID | HIFN_D_LAST);
2019 sc->sc_curbatch = 0;
2020 }
2021 HIFN_RESR_SYNC(sc, resi,
2022 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2023 sc->sc_resu++;
2024
2025 if (cmd->sloplen)
2026 cmd->slopidx = resi;
2027
2028 hifn_dmamap_load_dst(sc, cmd);
2029
2030 csr = 0;
2031 if (sc->sc_c_busy == 0) {
2032 csr |= HIFN_DMACSR_C_CTRL_ENA;
2033 sc->sc_c_busy = 1;
2034 }
2035 if (sc->sc_s_busy == 0) {
2036 csr |= HIFN_DMACSR_S_CTRL_ENA;
2037 sc->sc_s_busy = 1;
2038 }
2039 if (sc->sc_r_busy == 0) {
2040 csr |= HIFN_DMACSR_R_CTRL_ENA;
2041 sc->sc_r_busy = 1;
2042 }
2043 if (sc->sc_d_busy == 0) {
2044 csr |= HIFN_DMACSR_D_CTRL_ENA;
2045 sc->sc_d_busy = 1;
2046 }
2047 if (csr)
2048 WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr);
2049
2050 #ifdef HIFN_DEBUG
2051 if (hifn_debug) {
2052 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n",
2053 READ_REG_1(sc, HIFN_1_DMA_CSR),
2054 READ_REG_1(sc, HIFN_1_DMA_IER));
2055 }
2056 #endif
2057
2058 sc->sc_active = 5;
2059 HIFN_UNLOCK(sc);
2060 KASSERT(err == 0, ("hifn_crypto: success with error %u", err));
2061 return (err); /* success */
2062
2063 err_dstmap:
2064 if (cmd->src_map != cmd->dst_map)
2065 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2066 err_dstmap1:
2067 if (cmd->src_map != cmd->dst_map)
2068 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2069 err_srcmap:
2070 if (crp->crp_buf.cb_type == CRYPTO_BUF_MBUF) {
2071 if (cmd->dst_m != NULL)
2072 m_freem(cmd->dst_m);
2073 }
2074 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2075 err_srcmap1:
2076 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2077 HIFN_UNLOCK(sc);
2078 return (err);
2079 }
2080
2081 static void
hifn_tick(void * vsc)2082 hifn_tick(void* vsc)
2083 {
2084 struct hifn_softc *sc = vsc;
2085
2086 HIFN_LOCK(sc);
2087 if (sc->sc_active == 0) {
2088 u_int32_t r = 0;
2089
2090 if (sc->sc_cmdu == 0 && sc->sc_c_busy) {
2091 sc->sc_c_busy = 0;
2092 r |= HIFN_DMACSR_C_CTRL_DIS;
2093 }
2094 if (sc->sc_srcu == 0 && sc->sc_s_busy) {
2095 sc->sc_s_busy = 0;
2096 r |= HIFN_DMACSR_S_CTRL_DIS;
2097 }
2098 if (sc->sc_dstu == 0 && sc->sc_d_busy) {
2099 sc->sc_d_busy = 0;
2100 r |= HIFN_DMACSR_D_CTRL_DIS;
2101 }
2102 if (sc->sc_resu == 0 && sc->sc_r_busy) {
2103 sc->sc_r_busy = 0;
2104 r |= HIFN_DMACSR_R_CTRL_DIS;
2105 }
2106 if (r)
2107 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
2108 } else
2109 sc->sc_active--;
2110 HIFN_UNLOCK(sc);
2111 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
2112 }
2113
2114 static void
hifn_intr(void * arg)2115 hifn_intr(void *arg)
2116 {
2117 struct hifn_softc *sc = arg;
2118 struct hifn_dma *dma;
2119 u_int32_t dmacsr, restart;
2120 int i, u;
2121
2122 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
2123
2124 /* Nothing in the DMA unit interrupted */
2125 if ((dmacsr & sc->sc_dmaier) == 0)
2126 return;
2127
2128 HIFN_LOCK(sc);
2129
2130 dma = sc->sc_dma;
2131
2132 #ifdef HIFN_DEBUG
2133 if (hifn_debug) {
2134 device_printf(sc->sc_dev,
2135 "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n",
2136 dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier,
2137 sc->sc_cmdi, sc->sc_srci, sc->sc_dsti, sc->sc_resi,
2138 sc->sc_cmdk, sc->sc_srck, sc->sc_dstk, sc->sc_resk,
2139 sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu);
2140 }
2141 #endif
2142
2143 WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier);
2144
2145 if ((sc->sc_flags & HIFN_HAS_PUBLIC) &&
2146 (dmacsr & HIFN_DMACSR_PUBDONE))
2147 WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
2148 READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
2149
2150 restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER);
2151 if (restart)
2152 device_printf(sc->sc_dev, "overrun %x\n", dmacsr);
2153
2154 if (sc->sc_flags & HIFN_IS_7811) {
2155 if (dmacsr & HIFN_DMACSR_ILLR)
2156 device_printf(sc->sc_dev, "illegal read\n");
2157 if (dmacsr & HIFN_DMACSR_ILLW)
2158 device_printf(sc->sc_dev, "illegal write\n");
2159 }
2160
2161 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
2162 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
2163 if (restart) {
2164 device_printf(sc->sc_dev, "abort, resetting.\n");
2165 hifnstats.hst_abort++;
2166 hifn_abort(sc);
2167 HIFN_UNLOCK(sc);
2168 return;
2169 }
2170
2171 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (sc->sc_cmdu == 0)) {
2172 /*
2173 * If no slots to process and we receive a "waiting on
2174 * command" interrupt, we disable the "waiting on command"
2175 * (by clearing it).
2176 */
2177 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
2178 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2179 }
2180
2181 /* clear the rings */
2182 i = sc->sc_resk; u = sc->sc_resu;
2183 while (u != 0) {
2184 HIFN_RESR_SYNC(sc, i,
2185 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2186 if (dma->resr[i].l & htole32(HIFN_D_VALID)) {
2187 HIFN_RESR_SYNC(sc, i,
2188 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2189 break;
2190 }
2191
2192 if (i != HIFN_D_RES_RSIZE) {
2193 struct hifn_command *cmd;
2194 u_int8_t *macbuf = NULL;
2195
2196 HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD);
2197 cmd = sc->sc_hifn_commands[i];
2198 KASSERT(cmd != NULL,
2199 ("hifn_intr: null command slot %u", i));
2200 sc->sc_hifn_commands[i] = NULL;
2201
2202 if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2203 macbuf = dma->result_bufs[i];
2204 macbuf += 12;
2205 }
2206
2207 hifn_callback(sc, cmd, macbuf);
2208 hifnstats.hst_opackets++;
2209 u--;
2210 }
2211
2212 if (++i == (HIFN_D_RES_RSIZE + 1))
2213 i = 0;
2214 }
2215 sc->sc_resk = i; sc->sc_resu = u;
2216
2217 i = sc->sc_srck; u = sc->sc_srcu;
2218 while (u != 0) {
2219 if (i == HIFN_D_SRC_RSIZE)
2220 i = 0;
2221 HIFN_SRCR_SYNC(sc, i,
2222 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2223 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) {
2224 HIFN_SRCR_SYNC(sc, i,
2225 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2226 break;
2227 }
2228 i++, u--;
2229 }
2230 sc->sc_srck = i; sc->sc_srcu = u;
2231
2232 i = sc->sc_cmdk; u = sc->sc_cmdu;
2233 while (u != 0) {
2234 HIFN_CMDR_SYNC(sc, i,
2235 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2236 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
2237 HIFN_CMDR_SYNC(sc, i,
2238 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2239 break;
2240 }
2241 if (i != HIFN_D_CMD_RSIZE) {
2242 u--;
2243 HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE);
2244 }
2245 if (++i == (HIFN_D_CMD_RSIZE + 1))
2246 i = 0;
2247 }
2248 sc->sc_cmdk = i; sc->sc_cmdu = u;
2249
2250 HIFN_UNLOCK(sc);
2251
2252 if (sc->sc_needwakeup) { /* XXX check high watermark */
2253 int wakeup = sc->sc_needwakeup & CRYPTO_SYMQ;
2254 #ifdef HIFN_DEBUG
2255 if (hifn_debug)
2256 device_printf(sc->sc_dev,
2257 "wakeup crypto (%x) u %d/%d/%d/%d\n",
2258 sc->sc_needwakeup,
2259 sc->sc_cmdu, sc->sc_srcu, sc->sc_dstu, sc->sc_resu);
2260 #endif
2261 sc->sc_needwakeup &= ~wakeup;
2262 crypto_unblock(sc->sc_cid, wakeup);
2263 }
2264 }
2265
2266 static bool
hifn_auth_supported(struct hifn_softc * sc,const struct crypto_session_params * csp)2267 hifn_auth_supported(struct hifn_softc *sc,
2268 const struct crypto_session_params *csp)
2269 {
2270
2271 switch (sc->sc_ena) {
2272 case HIFN_PUSTAT_ENA_2:
2273 case HIFN_PUSTAT_ENA_1:
2274 break;
2275 default:
2276 return (false);
2277 }
2278
2279 switch (csp->csp_auth_alg) {
2280 case CRYPTO_SHA1:
2281 break;
2282 case CRYPTO_SHA1_HMAC:
2283 if (csp->csp_auth_klen > HIFN_MAC_KEY_LENGTH)
2284 return (false);
2285 break;
2286 default:
2287 return (false);
2288 }
2289
2290 return (true);
2291 }
2292
2293 static bool
hifn_cipher_supported(struct hifn_softc * sc,const struct crypto_session_params * csp)2294 hifn_cipher_supported(struct hifn_softc *sc,
2295 const struct crypto_session_params *csp)
2296 {
2297
2298 if (csp->csp_cipher_klen == 0)
2299 return (false);
2300 if (csp->csp_ivlen > HIFN_MAX_IV_LENGTH)
2301 return (false);
2302 switch (sc->sc_ena) {
2303 case HIFN_PUSTAT_ENA_2:
2304 switch (csp->csp_cipher_alg) {
2305 case CRYPTO_AES_CBC:
2306 if ((sc->sc_flags & HIFN_HAS_AES) == 0)
2307 return (false);
2308 switch (csp->csp_cipher_klen) {
2309 case 128:
2310 case 192:
2311 case 256:
2312 break;
2313 default:
2314 return (false);
2315 }
2316 return (true);
2317 }
2318 }
2319 return (false);
2320 }
2321
2322 static int
hifn_probesession(device_t dev,const struct crypto_session_params * csp)2323 hifn_probesession(device_t dev, const struct crypto_session_params *csp)
2324 {
2325 struct hifn_softc *sc;
2326
2327 sc = device_get_softc(dev);
2328 if (csp->csp_flags != 0)
2329 return (EINVAL);
2330 switch (csp->csp_mode) {
2331 case CSP_MODE_DIGEST:
2332 if (!hifn_auth_supported(sc, csp))
2333 return (EINVAL);
2334 break;
2335 case CSP_MODE_CIPHER:
2336 if (!hifn_cipher_supported(sc, csp))
2337 return (EINVAL);
2338 break;
2339 case CSP_MODE_ETA:
2340 if (!hifn_auth_supported(sc, csp) ||
2341 !hifn_cipher_supported(sc, csp))
2342 return (EINVAL);
2343 break;
2344 default:
2345 return (EINVAL);
2346 }
2347
2348 return (CRYPTODEV_PROBE_HARDWARE);
2349 }
2350
2351 /*
2352 * Allocate a new 'session'.
2353 */
2354 static int
hifn_newsession(device_t dev,crypto_session_t cses,const struct crypto_session_params * csp)2355 hifn_newsession(device_t dev, crypto_session_t cses,
2356 const struct crypto_session_params *csp)
2357 {
2358 struct hifn_session *ses;
2359
2360 ses = crypto_get_driver_session(cses);
2361
2362 if (csp->csp_auth_alg != 0) {
2363 if (csp->csp_auth_mlen == 0)
2364 ses->hs_mlen = crypto_auth_hash(csp)->hashsize;
2365 else
2366 ses->hs_mlen = csp->csp_auth_mlen;
2367 }
2368
2369 return (0);
2370 }
2371
2372 /*
2373 * XXX freesession routine should run a zero'd mac/encrypt key into context
2374 * ram. to blow away any keys already stored there.
2375 */
2376
2377 static int
hifn_process(device_t dev,struct cryptop * crp,int hint)2378 hifn_process(device_t dev, struct cryptop *crp, int hint)
2379 {
2380 const struct crypto_session_params *csp;
2381 struct hifn_softc *sc = device_get_softc(dev);
2382 struct hifn_command *cmd = NULL;
2383 const void *mackey;
2384 int err, keylen;
2385 struct hifn_session *ses;
2386
2387 ses = crypto_get_driver_session(crp->crp_session);
2388
2389 cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO);
2390 if (cmd == NULL) {
2391 hifnstats.hst_nomem++;
2392 err = ENOMEM;
2393 goto errout;
2394 }
2395
2396 csp = crypto_get_params(crp->crp_session);
2397
2398 /*
2399 * The driver only supports ETA requests where there is no
2400 * gap between the AAD and payload.
2401 */
2402 if (csp->csp_mode == CSP_MODE_ETA && crp->crp_aad_length != 0 &&
2403 crp->crp_aad_start + crp->crp_aad_length !=
2404 crp->crp_payload_start) {
2405 err = EINVAL;
2406 goto errout;
2407 }
2408
2409 switch (csp->csp_mode) {
2410 case CSP_MODE_CIPHER:
2411 case CSP_MODE_ETA:
2412 if (!CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
2413 cmd->base_masks |= HIFN_BASE_CMD_DECODE;
2414 cmd->base_masks |= HIFN_BASE_CMD_CRYPT;
2415 switch (csp->csp_cipher_alg) {
2416 case CRYPTO_AES_CBC:
2417 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES |
2418 HIFN_CRYPT_CMD_MODE_CBC |
2419 HIFN_CRYPT_CMD_NEW_IV;
2420 break;
2421 default:
2422 err = EINVAL;
2423 goto errout;
2424 }
2425 crypto_read_iv(crp, cmd->iv);
2426
2427 if (crp->crp_cipher_key != NULL)
2428 cmd->ck = crp->crp_cipher_key;
2429 else
2430 cmd->ck = csp->csp_cipher_key;
2431 cmd->cklen = csp->csp_cipher_klen;
2432 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2433
2434 /*
2435 * Need to specify the size for the AES key in the masks.
2436 */
2437 if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) ==
2438 HIFN_CRYPT_CMD_ALG_AES) {
2439 switch (cmd->cklen) {
2440 case 16:
2441 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128;
2442 break;
2443 case 24:
2444 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192;
2445 break;
2446 case 32:
2447 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256;
2448 break;
2449 default:
2450 err = EINVAL;
2451 goto errout;
2452 }
2453 }
2454 break;
2455 }
2456
2457 switch (csp->csp_mode) {
2458 case CSP_MODE_DIGEST:
2459 case CSP_MODE_ETA:
2460 cmd->base_masks |= HIFN_BASE_CMD_MAC;
2461
2462 switch (csp->csp_auth_alg) {
2463 case CRYPTO_SHA1:
2464 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2465 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2466 HIFN_MAC_CMD_POS_IPSEC;
2467 break;
2468 case CRYPTO_SHA1_HMAC:
2469 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2470 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2471 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2472 break;
2473 }
2474
2475 if (csp->csp_auth_alg == CRYPTO_SHA1_HMAC) {
2476 cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY;
2477 if (crp->crp_auth_key != NULL)
2478 mackey = crp->crp_auth_key;
2479 else
2480 mackey = csp->csp_auth_key;
2481 keylen = csp->csp_auth_klen;
2482 bcopy(mackey, cmd->mac, keylen);
2483 bzero(cmd->mac + keylen, HIFN_MAC_KEY_LENGTH - keylen);
2484 }
2485 }
2486
2487 cmd->crp = crp;
2488 cmd->session = ses;
2489 cmd->softc = sc;
2490
2491 err = hifn_crypto(sc, cmd, crp, hint);
2492 if (!err) {
2493 return 0;
2494 } else if (err == ERESTART) {
2495 /*
2496 * There weren't enough resources to dispatch the request
2497 * to the part. Notify the caller so they'll requeue this
2498 * request and resubmit it again soon.
2499 */
2500 #ifdef HIFN_DEBUG
2501 if (hifn_debug)
2502 device_printf(sc->sc_dev, "requeue request\n");
2503 #endif
2504 free(cmd, M_DEVBUF);
2505 sc->sc_needwakeup |= CRYPTO_SYMQ;
2506 return (err);
2507 }
2508
2509 errout:
2510 if (cmd != NULL)
2511 free(cmd, M_DEVBUF);
2512 if (err == EINVAL)
2513 hifnstats.hst_invalid++;
2514 else
2515 hifnstats.hst_nomem++;
2516 crp->crp_etype = err;
2517 crypto_done(crp);
2518 return (0);
2519 }
2520
2521 static void
hifn_abort(struct hifn_softc * sc)2522 hifn_abort(struct hifn_softc *sc)
2523 {
2524 struct hifn_dma *dma = sc->sc_dma;
2525 struct hifn_command *cmd;
2526 struct cryptop *crp;
2527 int i, u;
2528
2529 i = sc->sc_resk; u = sc->sc_resu;
2530 while (u != 0) {
2531 cmd = sc->sc_hifn_commands[i];
2532 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i));
2533 sc->sc_hifn_commands[i] = NULL;
2534 crp = cmd->crp;
2535
2536 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) {
2537 /* Salvage what we can. */
2538 u_int8_t *macbuf;
2539
2540 if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2541 macbuf = dma->result_bufs[i];
2542 macbuf += 12;
2543 } else
2544 macbuf = NULL;
2545 hifnstats.hst_opackets++;
2546 hifn_callback(sc, cmd, macbuf);
2547 } else {
2548 if (cmd->src_map == cmd->dst_map) {
2549 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2550 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2551 } else {
2552 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2553 BUS_DMASYNC_POSTWRITE);
2554 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2555 BUS_DMASYNC_POSTREAD);
2556 }
2557
2558 if (cmd->dst_m != NULL) {
2559 m_freem(cmd->dst_m);
2560 }
2561
2562 /* non-shared buffers cannot be restarted */
2563 if (cmd->src_map != cmd->dst_map) {
2564 /*
2565 * XXX should be EAGAIN, delayed until
2566 * after the reset.
2567 */
2568 crp->crp_etype = ENOMEM;
2569 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2570 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2571 } else
2572 crp->crp_etype = ENOMEM;
2573
2574 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2575 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2576
2577 free(cmd, M_DEVBUF);
2578 if (crp->crp_etype != EAGAIN)
2579 crypto_done(crp);
2580 }
2581
2582 if (++i == HIFN_D_RES_RSIZE)
2583 i = 0;
2584 u--;
2585 }
2586 sc->sc_resk = i; sc->sc_resu = u;
2587
2588 hifn_reset_board(sc, 1);
2589 hifn_init_dma(sc);
2590 hifn_init_pci_registers(sc);
2591 }
2592
2593 static void
hifn_callback(struct hifn_softc * sc,struct hifn_command * cmd,u_int8_t * macbuf)2594 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
2595 {
2596 struct hifn_dma *dma = sc->sc_dma;
2597 struct cryptop *crp = cmd->crp;
2598 uint8_t macbuf2[SHA1_HASH_LEN];
2599 struct mbuf *m;
2600 int totlen, i, u;
2601
2602 if (cmd->src_map == cmd->dst_map) {
2603 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2604 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2605 } else {
2606 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2607 BUS_DMASYNC_POSTWRITE);
2608 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2609 BUS_DMASYNC_POSTREAD);
2610 }
2611
2612 if (crp->crp_buf.cb_type == CRYPTO_BUF_MBUF) {
2613 if (cmd->dst_m != NULL) {
2614 totlen = cmd->src_mapsize;
2615 for (m = cmd->dst_m; m != NULL; m = m->m_next) {
2616 if (totlen < m->m_len) {
2617 m->m_len = totlen;
2618 totlen = 0;
2619 } else
2620 totlen -= m->m_len;
2621 }
2622 cmd->dst_m->m_pkthdr.len =
2623 crp->crp_buf.cb_mbuf->m_pkthdr.len;
2624 m_freem(crp->crp_buf.cb_mbuf);
2625 crp->crp_buf.cb_mbuf = cmd->dst_m;
2626 }
2627 }
2628
2629 if (cmd->sloplen != 0) {
2630 crypto_copyback(crp, cmd->src_mapsize - cmd->sloplen,
2631 cmd->sloplen, &dma->slop[cmd->slopidx]);
2632 }
2633
2634 i = sc->sc_dstk; u = sc->sc_dstu;
2635 while (u != 0) {
2636 if (i == HIFN_D_DST_RSIZE)
2637 i = 0;
2638 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2639 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2640 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) {
2641 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2642 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2643 break;
2644 }
2645 i++, u--;
2646 }
2647 sc->sc_dstk = i; sc->sc_dstu = u;
2648
2649 hifnstats.hst_obytes += cmd->dst_mapsize;
2650
2651 if (macbuf != NULL) {
2652 if (crp->crp_op & CRYPTO_OP_VERIFY_DIGEST) {
2653 crypto_copydata(crp, crp->crp_digest_start,
2654 cmd->session->hs_mlen, macbuf2);
2655 if (timingsafe_bcmp(macbuf, macbuf2,
2656 cmd->session->hs_mlen) != 0)
2657 crp->crp_etype = EBADMSG;
2658 } else
2659 crypto_copyback(crp, crp->crp_digest_start,
2660 cmd->session->hs_mlen, macbuf);
2661 }
2662
2663 if (cmd->src_map != cmd->dst_map) {
2664 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2665 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2666 }
2667 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2668 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2669 free(cmd, M_DEVBUF);
2670 crypto_done(crp);
2671 }
2672
2673 /*
2674 * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0
2675 * and Group 1 registers; avoid conditions that could create
2676 * burst writes by doing a read in between the writes.
2677 *
2678 * NB: The read we interpose is always to the same register;
2679 * we do this because reading from an arbitrary (e.g. last)
2680 * register may not always work.
2681 */
2682 static void
hifn_write_reg_0(struct hifn_softc * sc,bus_size_t reg,u_int32_t val)2683 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2684 {
2685 if (sc->sc_flags & HIFN_IS_7811) {
2686 if (sc->sc_bar0_lastreg == reg - 4)
2687 bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG);
2688 sc->sc_bar0_lastreg = reg;
2689 }
2690 bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
2691 }
2692
2693 static void
hifn_write_reg_1(struct hifn_softc * sc,bus_size_t reg,u_int32_t val)2694 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2695 {
2696 if (sc->sc_flags & HIFN_IS_7811) {
2697 if (sc->sc_bar1_lastreg == reg - 4)
2698 bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID);
2699 sc->sc_bar1_lastreg = reg;
2700 }
2701 bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);
2702 }
2703
2704 #ifdef HIFN_VULCANDEV
2705 /*
2706 * this code provides support for mapping the PK engine's register
2707 * into a userspace program.
2708 *
2709 */
2710 static int
vulcanpk_mmap(struct cdev * dev,vm_ooffset_t offset,vm_paddr_t * paddr,int nprot,vm_memattr_t * memattr)2711 vulcanpk_mmap(struct cdev *dev, vm_ooffset_t offset,
2712 vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr)
2713 {
2714 struct hifn_softc *sc;
2715 vm_paddr_t pd;
2716 void *b;
2717
2718 sc = dev->si_drv1;
2719
2720 pd = rman_get_start(sc->sc_bar1res);
2721 b = rman_get_virtual(sc->sc_bar1res);
2722
2723 #if 0
2724 printf("vpk mmap: %p(%016llx) offset=%lld\n", b,
2725 (unsigned long long)pd, offset);
2726 hexdump(b, HIFN_1_PUB_MEMEND, "vpk", 0);
2727 #endif
2728
2729 if (offset == 0) {
2730 *paddr = pd;
2731 return (0);
2732 }
2733 return (-1);
2734 }
2735
2736 static struct cdevsw vulcanpk_cdevsw = {
2737 .d_version = D_VERSION,
2738 .d_mmap = vulcanpk_mmap,
2739 .d_name = "vulcanpk",
2740 };
2741 #endif /* HIFN_VULCANDEV */
2742