1/* 2 * Copyright 2016 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23#include <dt-bindings/interrupt-controller/irq.h> 24#include <dt-bindings/gpio/gpio.h> 25 26/ { 27 #address-cells = <1>; 28 #size-cells = <1>; 29 compatible = "arm,realview-eb"; 30 31 chosen { }; 32 33 aliases { 34 serial0 = &serial0; 35 serial1 = &serial1; 36 serial2 = &serial2; 37 serial3 = &serial3; 38 i2c0 = &i2c; 39 }; 40 41 memory { 42 device_type = "memory"; 43 /* 128 MiB memory @ 0x0 */ 44 reg = <0x00000000 0x08000000>; 45 }; 46 47 /* The voltage to the MMC card is hardwired at 3.3V */ 48 vmmc: fixedregulator@0 { 49 compatible = "regulator-fixed"; 50 regulator-name = "vmmc"; 51 regulator-min-microvolt = <3300000>; 52 regulator-max-microvolt = <3300000>; 53 regulator-boot-on; 54 }; 55 56 xtal24mhz: xtal24mhz@24M { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <24000000>; 60 }; 61 62 timclk: timclk@1M { 63 #clock-cells = <0>; 64 compatible = "fixed-factor-clock"; 65 clock-div = <24>; 66 clock-mult = <1>; 67 clocks = <&xtal24mhz>; 68 }; 69 70 mclk: mclk@24M { 71 #clock-cells = <0>; 72 compatible = "fixed-factor-clock"; 73 clock-div = <1>; 74 clock-mult = <1>; 75 clocks = <&xtal24mhz>; 76 }; 77 78 kmiclk: kmiclk@24M { 79 #clock-cells = <0>; 80 compatible = "fixed-factor-clock"; 81 clock-div = <1>; 82 clock-mult = <1>; 83 clocks = <&xtal24mhz>; 84 }; 85 86 sspclk: sspclk@24M { 87 #clock-cells = <0>; 88 compatible = "fixed-factor-clock"; 89 clock-div = <1>; 90 clock-mult = <1>; 91 clocks = <&xtal24mhz>; 92 }; 93 94 uartclk: uartclk@24M { 95 #clock-cells = <0>; 96 compatible = "fixed-factor-clock"; 97 clock-div = <1>; 98 clock-mult = <1>; 99 clocks = <&xtal24mhz>; 100 }; 101 102 wdogclk: wdogclk@24M { 103 #clock-cells = <0>; 104 compatible = "fixed-factor-clock"; 105 clock-div = <1>; 106 clock-mult = <1>; 107 clocks = <&xtal24mhz>; 108 }; 109 110 /* FIXME: this actually hangs off the PLL clocks */ 111 pclk: pclk@0 { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <0>; 115 }; 116 117 flash0@40000000 { 118 /* 2 * 32MiB NOR Flash memory */ 119 compatible = "arm,versatile-flash", "cfi-flash"; 120 reg = <0x40000000 0x04000000>; 121 bank-width = <4>; 122 }; 123 124 flash1@44000000 { 125 /* 2 * 32MiB NOR Flash memory */ 126 compatible = "arm,versatile-flash", "cfi-flash"; 127 reg = <0x44000000 0x04000000>; 128 bank-width = <4>; 129 }; 130 131 /* SMSC LAN91C111 ethernet with PHY and EEPROM */ 132 ethernet: ethernet@4e000000 { 133 compatible = "smsc,lan91c111"; 134 reg = <0x4e000000 0x10000>; 135 /* 136 * This means the adapter can be accessed with 8, 16 or 137 * 32 bit reads/writes. 138 */ 139 reg-io-width = <7>; 140 }; 141 142 usb: usb@4f000000 { 143 compatible = "nxp,usb-isp1761"; 144 reg = <0x4f000000 0x20000>; 145 port1-otg; 146 }; 147 148 bridge { 149 compatible = "ti,ths8134a", "ti,ths8134"; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 153 ports { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 port@0 { 158 reg = <0>; 159 160 vga_bridge_in: endpoint { 161 remote-endpoint = <&clcd_pads>; 162 }; 163 }; 164 165 port@1 { 166 reg = <1>; 167 168 vga_bridge_out: endpoint { 169 remote-endpoint = <&vga_con_in>; 170 }; 171 }; 172 }; 173 }; 174 175 vga { 176 compatible = "vga-connector"; 177 178 port { 179 vga_con_in: endpoint { 180 remote-endpoint = <&vga_bridge_out>; 181 }; 182 }; 183 }; 184 185 /* These peripherals are inside the FPGA */ 186 fpga { 187 #address-cells = <1>; 188 #size-cells = <1>; 189 compatible = "simple-bus"; 190 ranges; 191 192 syscon: syscon@10000000 { 193 compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd"; 194 reg = <0x10000000 0x1000>; 195 196 [email protected] { 197 compatible = "register-bit-led"; 198 offset = <0x08>; 199 mask = <0x01>; 200 label = "versatile:0"; 201 linux,default-trigger = "heartbeat"; 202 default-state = "on"; 203 }; 204 [email protected] { 205 compatible = "register-bit-led"; 206 offset = <0x08>; 207 mask = <0x02>; 208 label = "versatile:1"; 209 linux,default-trigger = "mmc0"; 210 default-state = "off"; 211 }; 212 [email protected] { 213 compatible = "register-bit-led"; 214 offset = <0x08>; 215 mask = <0x04>; 216 label = "versatile:2"; 217 linux,default-trigger = "cpu0"; 218 default-state = "off"; 219 }; 220 [email protected] { 221 compatible = "register-bit-led"; 222 offset = <0x08>; 223 mask = <0x08>; 224 label = "versatile:3"; 225 default-state = "off"; 226 }; 227 [email protected] { 228 compatible = "register-bit-led"; 229 offset = <0x08>; 230 mask = <0x10>; 231 label = "versatile:4"; 232 default-state = "off"; 233 }; 234 [email protected] { 235 compatible = "register-bit-led"; 236 offset = <0x08>; 237 mask = <0x20>; 238 label = "versatile:5"; 239 default-state = "off"; 240 }; 241 [email protected] { 242 compatible = "register-bit-led"; 243 offset = <0x08>; 244 mask = <0x40>; 245 label = "versatile:6"; 246 default-state = "off"; 247 }; 248 [email protected] { 249 compatible = "register-bit-led"; 250 offset = <0x08>; 251 mask = <0x80>; 252 label = "versatile:7"; 253 default-state = "off"; 254 }; 255 oscclk0: osc0@0c { 256 compatible = "arm,syscon-icst307"; 257 #clock-cells = <0>; 258 lock-offset = <0x20>; 259 vco-offset = <0x0C>; 260 clocks = <&xtal24mhz>; 261 }; 262 oscclk1: osc1@10 { 263 compatible = "arm,syscon-icst307"; 264 #clock-cells = <0>; 265 lock-offset = <0x20>; 266 vco-offset = <0x10>; 267 clocks = <&xtal24mhz>; 268 }; 269 oscclk2: osc2@14 { 270 compatible = "arm,syscon-icst307"; 271 #clock-cells = <0>; 272 lock-offset = <0x20>; 273 vco-offset = <0x14>; 274 clocks = <&xtal24mhz>; 275 }; 276 oscclk3: osc3@18 { 277 compatible = "arm,syscon-icst307"; 278 #clock-cells = <0>; 279 lock-offset = <0x20>; 280 vco-offset = <0x18>; 281 clocks = <&xtal24mhz>; 282 }; 283 oscclk4: osc4@1c { 284 compatible = "arm,syscon-icst307"; 285 #clock-cells = <0>; 286 lock-offset = <0x20>; 287 vco-offset = <0x1c>; 288 clocks = <&xtal24mhz>; 289 }; 290 }; 291 292 i2c: i2c@10002000 { 293 #address-cells = <1>; 294 #size-cells = <0>; 295 compatible = "arm,versatile-i2c"; 296 reg = <0x10002000 0x1000>; 297 298 rtc@68 { 299 compatible = "dallas,ds1338"; 300 reg = <0x68>; 301 }; 302 }; 303 304 aaci: aaci@10004000 { 305 compatible = "arm,pl041", "arm,primecell"; 306 reg = <0x10004000 0x1000>; 307 clocks = <&pclk>; 308 clock-names = "apb_pclk"; 309 }; 310 311 mmc: mmcsd@10005000 { 312 compatible = "arm,pl18x", "arm,primecell"; 313 reg = <0x10005000 0x1000>; 314 315 /* Due to frequent FIFO overruns, use just 500 kHz */ 316 max-frequency = <500000>; 317 bus-width = <4>; 318 cap-sd-highspeed; 319 cap-mmc-highspeed; 320 clocks = <&mclk>, <&pclk>; 321 clock-names = "mclk", "apb_pclk"; 322 vmmc-supply = <&vmmc>; 323 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 324 wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 325 }; 326 327 kmi0: kmi@10006000 { 328 compatible = "arm,pl050", "arm,primecell"; 329 reg = <0x10006000 0x1000>; 330 clocks = <&kmiclk>, <&pclk>; 331 clock-names = "KMIREFCLK", "apb_pclk"; 332 }; 333 334 kmi1: kmi@10007000 { 335 compatible = "arm,pl050", "arm,primecell"; 336 reg = <0x10007000 0x1000>; 337 clocks = <&kmiclk>, <&pclk>; 338 clock-names = "KMIREFCLK", "apb_pclk"; 339 }; 340 341 charlcd: fpga_charlcd: charlcd@10008000 { 342 compatible = "arm,versatile-lcd"; 343 reg = <0x10008000 0x1000>; 344 clocks = <&pclk>; 345 clock-names = "apb_pclk"; 346 }; 347 348 serial0: serial@10009000 { 349 compatible = "arm,pl011", "arm,primecell"; 350 reg = <0x10009000 0x1000>; 351 clocks = <&uartclk>, <&pclk>; 352 clock-names = "uartclk", "apb_pclk"; 353 }; 354 355 serial1: serial@1000a000 { 356 compatible = "arm,pl011", "arm,primecell"; 357 reg = <0x1000a000 0x1000>; 358 clocks = <&uartclk>, <&pclk>; 359 clock-names = "uartclk", "apb_pclk"; 360 }; 361 362 serial2: serial@1000b000 { 363 compatible = "arm,pl011", "arm,primecell"; 364 reg = <0x1000b000 0x1000>; 365 clocks = <&uartclk>, <&pclk>; 366 clock-names = "uartclk", "apb_pclk"; 367 }; 368 369 serial3: serial@1000c000 { 370 compatible = "arm,pl011", "arm,primecell"; 371 reg = <0x1000c000 0x1000>; 372 clocks = <&uartclk>, <&pclk>; 373 clock-names = "uartclk", "apb_pclk"; 374 }; 375 376 ssp: spi@1000d000 { 377 compatible = "arm,pl022", "arm,primecell"; 378 reg = <0x1000d000 0x1000>; 379 clocks = <&sspclk>, <&pclk>; 380 clock-names = "SSPCLK", "apb_pclk"; 381 }; 382 383 wdog: watchdog@10010000 { 384 compatible = "arm,sp805", "arm,primecell"; 385 reg = <0x10010000 0x1000>; 386 clocks = <&wdogclk>, <&pclk>; 387 clock-names = "wdogclk", "apb_pclk"; 388 status = "disabled"; 389 }; 390 391 timer01: timer@10011000 { 392 compatible = "arm,sp804", "arm,primecell"; 393 reg = <0x10011000 0x1000>; 394 clocks = <&timclk>, <&timclk>, <&pclk>; 395 clock-names = "timer1", "timer2", "apb_pclk"; 396 }; 397 398 timer23: timer@10012000 { 399 compatible = "arm,sp804", "arm,primecell"; 400 reg = <0x10012000 0x1000>; 401 clocks = <&timclk>, <&timclk>, <&pclk>; 402 clock-names = "timer1", "timer2", "apb_pclk"; 403 }; 404 405 gpio0: gpio@10013000 { 406 compatible = "arm,pl061", "arm,primecell"; 407 reg = <0x10013000 0x1000>; 408 gpio-controller; 409 #gpio-cells = <2>; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 clocks = <&pclk>; 413 clock-names = "apb_pclk"; 414 }; 415 416 gpio1: gpio@10014000 { 417 compatible = "arm,pl061", "arm,primecell"; 418 reg = <0x10014000 0x1000>; 419 gpio-controller; 420 #gpio-cells = <2>; 421 interrupt-controller; 422 #interrupt-cells = <2>; 423 clocks = <&pclk>; 424 clock-names = "apb_pclk"; 425 }; 426 427 gpio2: gpio@10015000 { 428 compatible = "arm,pl061", "arm,primecell"; 429 reg = <0x10015000 0x1000>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 interrupt-controller; 433 #interrupt-cells = <2>; 434 clocks = <&pclk>; 435 clock-names = "apb_pclk"; 436 }; 437 438 rtc: rtc@10017000 { 439 compatible = "arm,pl031", "arm,primecell"; 440 reg = <0x10017000 0x1000>; 441 clocks = <&pclk>; 442 clock-names = "apb_pclk"; 443 }; 444 445 clcd: clcd@10020000 { 446 compatible = "arm,pl111", "arm,primecell"; 447 reg = <0x10020000 0x1000>; 448 interrupt-names = "combined"; 449 clocks = <&oscclk0>, <&pclk>; 450 clock-names = "clcdclk", "apb_pclk"; 451 /* 1024x768 16bpp @65MHz works fine */ 452 max-memory-bandwidth = <95000000>; 453 454 port { 455 clcd_pads: endpoint { 456 remote-endpoint = <&vga_bridge_in>; 457 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 458 }; 459 }; 460 }; 461 }; 462}; 463