1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Michal Meloun <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 /*
29 * Rockchip PHY TYPEC
30 */
31
32 #include <sys/cdefs.h>
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/rman.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
40 #include <sys/gpio.h>
41 #include <machine/bus.h>
42
43 #include <dev/fdt/fdt_common.h>
44 #include <dev/ofw/ofw_bus.h>
45 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/ofw/ofw_subr.h>
47
48 #include <dev/extres/clk/clk.h>
49 #include <dev/extres/phy/phy.h>
50 #include <dev/extres/phy/phy_internal.h>
51 #include <dev/extres/syscon/syscon.h>
52 #include <dev/extres/hwreset/hwreset.h>
53
54 #include "syscon_if.h"
55
56 #define GRF_HIWORD_SHIFT 16
57 #define GRF_SOC_CON_5_PCIE 0xE214
58 #define CON_5_PCIE_IDLE_OFF(x) (1 <<(((x) & 0x3) + 3))
59 #define GRF_SOC_CON8 0xE220
60 #define GRF_SOC_STATUS1 0xE2A4
61
62 /* PHY config registers - write */
63 #define PHY_CFG_CLK_TEST 0x10
64 #define CLK_TEST_SEPE_RATE (1 << 3)
65 #define PHY_CFG_CLK_SCC 0x12
66 #define CLK_SCC_PLL_100M (1 << 3)
67
68 /* PHY config registers - read */
69 #define PHY_CFG_PLL_LOCK 0x10
70 #define CLK_PLL_LOCKED (1 << 1)
71 #define PHY_CFG_SCC_LOCK 0x12
72 #define CLK_SCC_100M_GATE (1 << 2)
73
74 #define STATUS1_PLL_LOCKED (1 << 9)
75
76 static struct ofw_compat_data compat_data[] = {
77 {"rockchip,rk3399-pcie-phy", 1},
78 {NULL, 0}
79 };
80
81 struct rk_pcie_phy_softc {
82 device_t dev;
83 struct syscon *syscon;
84 struct mtx mtx;
85 clk_t clk_ref;
86 hwreset_t hwreset_phy;
87 int enable_count;
88 };
89
90 #define PHY_LOCK(_sc) mtx_lock(&(_sc)->mtx)
91 #define PHY_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
92 #define PHY_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
93 device_get_nameunit(_sc->dev), "rk_pcie_phyc", MTX_DEF)
94 #define PHY_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx);
95 #define PHY_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
96 #define PHY_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
97
98 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg))
99 #define WR4(sc, reg, mask, val) \
100 SYSCON_WRITE_4((sc)->syscon, (reg), ((mask) << GRF_HIWORD_SHIFT) | (val))
101
102 #define MAX_LANE 4
103
104 static void
cfg_write(struct rk_pcie_phy_softc * sc,uint32_t reg,uint32_t data)105 cfg_write(struct rk_pcie_phy_softc *sc, uint32_t reg, uint32_t data)
106 {
107 /* setup register address and data first */
108 WR4(sc, GRF_SOC_CON8, 0x7FF,
109 (reg & 0x3F) << 1 | (data & 0x0F) << 7);
110 /* dummy readback for sync */
111 RD4(sc, GRF_SOC_CON8);
112
113 /* Do write pulse */
114 WR4(sc, GRF_SOC_CON8, 1, 1);
115 RD4(sc, GRF_SOC_CON8);
116 DELAY(10);
117 WR4(sc, GRF_SOC_CON8, 1, 0);
118 RD4(sc, GRF_SOC_CON8);
119 DELAY(10);
120 }
121
122 static uint32_t
cfg_read(struct rk_pcie_phy_softc * sc,uint32_t reg)123 cfg_read(struct rk_pcie_phy_softc *sc, uint32_t reg)
124 {
125 uint32_t val;
126
127 WR4(sc, GRF_SOC_CON8, 0x3FF, reg << 1);
128 RD4(sc, GRF_SOC_CON8);
129 DELAY(10);
130 val = RD4(sc, GRF_SOC_STATUS1);
131 return ((val >> 8) & 0x0f);
132 }
133
134 static int
rk_pcie_phy_up(struct rk_pcie_phy_softc * sc,int id)135 rk_pcie_phy_up(struct rk_pcie_phy_softc *sc, int id)
136 {
137 uint32_t val;
138 int i, rv;
139
140 PHY_LOCK(sc);
141
142 sc->enable_count++;
143 if (sc->enable_count != 1) {
144 PHY_UNLOCK(sc);
145 return (0);
146 }
147
148 rv = hwreset_deassert(sc->hwreset_phy);
149 if (rv != 0) {
150 device_printf(sc->dev, "Cannot deassert 'phy' reset\n");
151 PHY_UNLOCK(sc);
152 return (rv);
153 }
154 /* Un-idle all lanes */
155 for (i = 0; i < MAX_LANE; i++)
156 WR4(sc, GRF_SOC_CON_5_PCIE, CON_5_PCIE_IDLE_OFF(i), 0);
157
158 /* Wait for PLL lock */
159 for (i = 100; i > 0; i--) {
160 val = cfg_read(sc, PHY_CFG_PLL_LOCK);
161 if (val & CLK_PLL_LOCKED)
162 break;
163 DELAY(1000);
164 }
165 if (i <= 0) {
166 device_printf(sc->dev, "PLL lock timeouted, 0x%02X\n", val);
167 PHY_UNLOCK(sc);
168 return (ETIMEDOUT);
169 }
170 /* Switch PLL to stable 5GHz, rate adjustment is done by divider */
171 cfg_write(sc, PHY_CFG_CLK_TEST, CLK_TEST_SEPE_RATE);
172 /* Enable 100MHz output for PCIe ref clock */
173 cfg_write(sc, PHY_CFG_CLK_SCC, CLK_SCC_PLL_100M);
174
175 /* Wait for ungating of ref clock */
176 for (i = 100; i > 0; i--) {
177 val = cfg_read(sc, PHY_CFG_SCC_LOCK);
178 if ((val & CLK_SCC_100M_GATE) == 0)
179 break;
180 DELAY(1000);
181 }
182 if (i <= 0) {
183 device_printf(sc->dev, "PLL output enable timeouted\n");
184 PHY_UNLOCK(sc);
185 return (ETIMEDOUT);
186 }
187
188 /* Wait for PLL relock (to 5GHz) */
189 for (i = 100; i > 0; i--) {
190 val = cfg_read(sc, PHY_CFG_PLL_LOCK);
191 if (val & CLK_PLL_LOCKED)
192 break;
193 DELAY(1000);
194 }
195 if (i <= 0) {
196 device_printf(sc->dev, "PLL relock timeouted\n");
197 PHY_UNLOCK(sc);
198 return (ETIMEDOUT);
199 }
200
201 PHY_UNLOCK(sc);
202 return (rv);
203 }
204
205 static int
rk_pcie_phy_down(struct rk_pcie_phy_softc * sc,int id)206 rk_pcie_phy_down(struct rk_pcie_phy_softc *sc, int id)
207 {
208 int rv;
209
210 PHY_LOCK(sc);
211
212 rv = 0;
213 if (sc->enable_count <= 0)
214 panic("unpaired enable/disable");
215
216 sc->enable_count--;
217
218 /* Idle given lane */
219 WR4(sc, GRF_SOC_CON_5_PCIE,
220 CON_5_PCIE_IDLE_OFF(id),
221 CON_5_PCIE_IDLE_OFF(id));
222
223 if (sc->enable_count == 0) {
224 rv = hwreset_assert(sc->hwreset_phy);
225 if (rv != 0)
226 device_printf(sc->dev, "Cannot assert 'phy' reset\n");
227 }
228 PHY_UNLOCK(sc);
229 return (rv);
230 }
231
232 static int
rk_pcie_phy_enable(struct phynode * phynode,bool enable)233 rk_pcie_phy_enable(struct phynode *phynode, bool enable)
234 {
235 struct rk_pcie_phy_softc *sc;
236 device_t dev;
237 intptr_t phy;
238 int rv;
239
240 dev = phynode_get_device(phynode);
241 phy = phynode_get_id(phynode);
242 sc = device_get_softc(dev);
243
244 if (enable)
245 rv = rk_pcie_phy_up(sc, (int)phy);
246 else
247 rv = rk_pcie_phy_down(sc, (int) phy);
248
249 return (rv);
250 }
251
252 /* Phy class and methods. */
253 static phynode_method_t rk_pcie_phy_phynode_methods[] = {
254 PHYNODEMETHOD(phynode_enable, rk_pcie_phy_enable),
255
256 PHYNODEMETHOD_END
257 };
258
259 DEFINE_CLASS_1( rk_pcie_phy_phynode, rk_pcie_phy_phynode_class,
260 rk_pcie_phy_phynode_methods, 0, phynode_class);
261
262 static int
rk_pcie_phy_probe(device_t dev)263 rk_pcie_phy_probe(device_t dev)
264 {
265
266 if (!ofw_bus_status_okay(dev))
267 return (ENXIO);
268
269 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
270 return (ENXIO);
271
272 device_set_desc(dev, "Rockchip RK3399 PCIe PHY");
273 return (BUS_PROBE_DEFAULT);
274 }
275
276 static int
rk_pcie_phy_attach(device_t dev)277 rk_pcie_phy_attach(device_t dev)
278 {
279 struct rk_pcie_phy_softc *sc;
280 struct phynode_init_def phy_init;
281 struct phynode *phynode;
282 phandle_t node;
283 int i, rv;
284
285 sc = device_get_softc(dev);
286 sc->dev = dev;
287 node = ofw_bus_get_node(dev);
288 PHY_LOCK_INIT(sc);
289
290 if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 ||
291 sc->syscon == NULL) {
292 device_printf(dev, "cannot get syscon for device\n");
293 rv = ENXIO;
294 goto fail;
295 }
296
297 rv = clk_set_assigned(dev, ofw_bus_get_node(dev));
298 if (rv != 0 && rv != ENOENT) {
299 device_printf(dev, "clk_set_assigned failed: %d\n", rv);
300 rv = ENXIO;
301 goto fail;
302 }
303
304 rv = clk_get_by_ofw_name(sc->dev, 0, "refclk", &sc->clk_ref);
305 if (rv != 0) {
306 device_printf(sc->dev, "Cannot get 'refclk' clock\n");
307 rv = ENXIO;
308 goto fail;
309 }
310 rv = hwreset_get_by_ofw_name(sc->dev, 0, "phy", &sc->hwreset_phy);
311 if (rv != 0) {
312 device_printf(sc->dev, "Cannot get 'phy' reset\n");
313 rv = ENXIO;
314 goto fail;
315 }
316
317 rv = hwreset_assert(sc->hwreset_phy);
318 if (rv != 0) {
319 device_printf(sc->dev, "Cannot assert 'phy' reset\n");
320 rv = ENXIO;
321 goto fail;
322 }
323
324 rv = clk_enable(sc->clk_ref);
325 if (rv != 0) {
326 device_printf(sc->dev, "Cannot enable 'ref' clock\n");
327 rv = ENXIO;
328 goto fail;
329 }
330
331 for (i = 0; i < MAX_LANE; i++) {
332 phy_init.id = i;
333 phy_init.ofw_node = node;
334 phynode = phynode_create(dev, &rk_pcie_phy_phynode_class,
335 &phy_init);
336 if (phynode == NULL) {
337 device_printf(dev, "Cannot create phy[%d]\n", i);
338 rv = ENXIO;
339 goto fail;
340 }
341 if (phynode_register(phynode) == NULL) {
342 device_printf(dev, "Cannot register phy[%d]\n", i);
343 rv = ENXIO;
344 goto fail;
345 }
346 }
347
348 return (0);
349
350 fail:
351 return (rv);
352 }
353
354 static device_method_t rk_pcie_phy_methods[] = {
355 /* Device interface */
356 DEVMETHOD(device_probe, rk_pcie_phy_probe),
357 DEVMETHOD(device_attach, rk_pcie_phy_attach),
358
359 DEVMETHOD_END
360 };
361
362 DEFINE_CLASS_0(rk_pcie_phy, rk_pcie_phy_driver, rk_pcie_phy_methods,
363 sizeof(struct rk_pcie_phy_softc));
364
365 EARLY_DRIVER_MODULE(rk_pcie_phy, simplebus, rk_pcie_phy_driver, NULL, NULL,
366 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
367