1 /*-
2 * Copyright (c) 2017 Chelsio Communications, Inc.
3 * Copyright (c) 2021 The FreeBSD Foundation
4 * All rights reserved.
5 * Written by: John Baldwin <[email protected]>
6 *
7 * Portions of this software were developed by Ararat River
8 * Consulting, LLC under sponsorship of the FreeBSD Foundation.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 #include <sys/types.h>
36 #include <sys/bus.h>
37 #include <sys/lock.h>
38 #include <sys/malloc.h>
39 #include <sys/mutex.h>
40 #include <sys/module.h>
41 #include <sys/sglist.h>
42
43 #include <opencrypto/cryptodev.h>
44 #include <opencrypto/xform.h>
45
46 #include "cryptodev_if.h"
47
48 #include "common/common.h"
49 #include "crypto/t4_crypto.h"
50
51 /*
52 * Requests consist of:
53 *
54 * +-------------------------------+
55 * | struct fw_crypto_lookaside_wr |
56 * +-------------------------------+
57 * | struct ulp_txpkt |
58 * +-------------------------------+
59 * | struct ulptx_idata |
60 * +-------------------------------+
61 * | struct cpl_tx_sec_pdu |
62 * +-------------------------------+
63 * | struct cpl_tls_tx_scmd_fmt |
64 * +-------------------------------+
65 * | key context header |
66 * +-------------------------------+
67 * | AES key | ----- For requests with AES
68 * +-------------------------------+
69 * | Hash state | ----- For hash-only requests
70 * +-------------------------------+ -
71 * | IPAD (16-byte aligned) | \
72 * +-------------------------------+ +---- For requests with HMAC
73 * | OPAD (16-byte aligned) | /
74 * +-------------------------------+ -
75 * | GMAC H | ----- For AES-GCM
76 * +-------------------------------+ -
77 * | struct cpl_rx_phys_dsgl | \
78 * +-------------------------------+ +---- Destination buffer for
79 * | PHYS_DSGL entries | / non-hash-only requests
80 * +-------------------------------+ -
81 * | 16 dummy bytes | ----- Only for HMAC/hash-only requests
82 * +-------------------------------+
83 * | IV | ----- If immediate IV
84 * +-------------------------------+
85 * | Payload | ----- If immediate Payload
86 * +-------------------------------+ -
87 * | struct ulptx_sgl | \
88 * +-------------------------------+ +---- If payload via SGL
89 * | SGL entries | /
90 * +-------------------------------+ -
91 *
92 * Note that the key context must be padded to ensure 16-byte alignment.
93 * For HMAC requests, the key consists of the partial hash of the IPAD
94 * followed by the partial hash of the OPAD.
95 *
96 * Replies consist of:
97 *
98 * +-------------------------------+
99 * | struct cpl_fw6_pld |
100 * +-------------------------------+
101 * | hash digest | ----- For HMAC request with
102 * +-------------------------------+ 'hash_size' set in work request
103 *
104 * A 32-bit big-endian error status word is supplied in the last 4
105 * bytes of data[0] in the CPL_FW6_PLD message. bit 0 indicates a
106 * "MAC" error and bit 1 indicates a "PAD" error.
107 *
108 * The 64-bit 'cookie' field from the fw_crypto_lookaside_wr message
109 * in the request is returned in data[1] of the CPL_FW6_PLD message.
110 *
111 * For block cipher replies, the updated IV is supplied in data[2] and
112 * data[3] of the CPL_FW6_PLD message.
113 *
114 * For hash replies where the work request set 'hash_size' to request
115 * a copy of the hash in the reply, the hash digest is supplied
116 * immediately following the CPL_FW6_PLD message.
117 */
118
119 /*
120 * The crypto engine supports a maximum AAD size of 511 bytes.
121 */
122 #define MAX_AAD_LEN 511
123
124 /*
125 * The documentation for CPL_RX_PHYS_DSGL claims a maximum of 32 SG
126 * entries. While the CPL includes a 16-bit length field, the T6 can
127 * sometimes hang if an error occurs while processing a request with a
128 * single DSGL entry larger than 2k.
129 */
130 #define MAX_RX_PHYS_DSGL_SGE 32
131 #define DSGL_SGE_MAXLEN 2048
132
133 /*
134 * The adapter only supports requests with a total input or output
135 * length of 64k-1 or smaller. Longer requests either result in hung
136 * requests or incorrect results.
137 */
138 #define MAX_REQUEST_SIZE 65535
139
140 static MALLOC_DEFINE(M_CCR, "ccr", "Chelsio T6 crypto");
141
142 struct ccr_session_hmac {
143 struct auth_hash *auth_hash;
144 int hash_len;
145 unsigned int partial_digest_len;
146 unsigned int auth_mode;
147 unsigned int mk_size;
148 char pads[CHCR_HASH_MAX_BLOCK_SIZE_128 * 2];
149 };
150
151 struct ccr_session_gmac {
152 int hash_len;
153 char ghash_h[GMAC_BLOCK_LEN];
154 };
155
156 struct ccr_session_ccm_mac {
157 int hash_len;
158 };
159
160 struct ccr_session_blkcipher {
161 unsigned int cipher_mode;
162 unsigned int key_len;
163 unsigned int iv_len;
164 __be32 key_ctx_hdr;
165 char enckey[CHCR_AES_MAX_KEY_LEN];
166 char deckey[CHCR_AES_MAX_KEY_LEN];
167 };
168
169 struct ccr_port {
170 struct sge_wrq *txq;
171 struct sge_rxq *rxq;
172 int rx_channel_id;
173 int tx_channel_id;
174 u_int active_sessions;
175
176 counter_u64_t stats_queued;
177 counter_u64_t stats_completed;
178 };
179
180 struct ccr_session {
181 #ifdef INVARIANTS
182 int pending;
183 #endif
184 enum { HASH, HMAC, BLKCIPHER, ETA, GCM, CCM } mode;
185 struct ccr_port *port;
186 union {
187 struct ccr_session_hmac hmac;
188 struct ccr_session_gmac gmac;
189 struct ccr_session_ccm_mac ccm_mac;
190 };
191 struct ccr_session_blkcipher blkcipher;
192 struct mtx lock;
193
194 /*
195 * Pre-allocate S/G lists used when preparing a work request.
196 * 'sg_input' contains an sglist describing the entire input
197 * buffer for a 'struct cryptop'. 'sg_output' contains an
198 * sglist describing the entire output buffer. 'sg_ulptx' is
199 * used to describe the data the engine should DMA as input
200 * via ULPTX_SGL. 'sg_dsgl' is used to describe the
201 * destination that cipher text and a tag should be written
202 * to.
203 */
204 struct sglist *sg_input;
205 struct sglist *sg_output;
206 struct sglist *sg_ulptx;
207 struct sglist *sg_dsgl;
208 };
209
210 struct ccr_softc {
211 struct adapter *adapter;
212 device_t dev;
213 uint32_t cid;
214 struct mtx lock;
215 bool detaching;
216 struct ccr_port ports[MAX_NPORTS];
217 u_int port_mask;
218 int first_rxq_id;
219
220 /*
221 * Pre-allocate a dummy output buffer for the IV and AAD for
222 * AEAD requests.
223 */
224 char *iv_aad_buf;
225 struct sglist *sg_iv_aad;
226
227 /* Statistics. */
228 counter_u64_t stats_blkcipher_encrypt;
229 counter_u64_t stats_blkcipher_decrypt;
230 counter_u64_t stats_hash;
231 counter_u64_t stats_hmac;
232 counter_u64_t stats_eta_encrypt;
233 counter_u64_t stats_eta_decrypt;
234 counter_u64_t stats_gcm_encrypt;
235 counter_u64_t stats_gcm_decrypt;
236 counter_u64_t stats_ccm_encrypt;
237 counter_u64_t stats_ccm_decrypt;
238 counter_u64_t stats_wr_nomem;
239 counter_u64_t stats_inflight;
240 counter_u64_t stats_mac_error;
241 counter_u64_t stats_pad_error;
242 counter_u64_t stats_sglist_error;
243 counter_u64_t stats_process_error;
244 counter_u64_t stats_sw_fallback;
245
246 struct sysctl_ctx_list ctx;
247 };
248
249 /*
250 * Crypto requests involve two kind of scatter/gather lists.
251 *
252 * Non-hash-only requests require a PHYS_DSGL that describes the
253 * location to store the results of the encryption or decryption
254 * operation. This SGL uses a different format (PHYS_DSGL) and should
255 * exclude the skip bytes at the start of the data as well as any AAD
256 * or IV. For authenticated encryption requests it should include the
257 * destination of the hash or tag.
258 *
259 * The input payload may either be supplied inline as immediate data,
260 * or via a standard ULP_TX SGL. This SGL should include AAD,
261 * ciphertext, and the hash or tag for authenticated decryption
262 * requests.
263 *
264 * These scatter/gather lists can describe different subsets of the
265 * buffers described by the crypto operation. ccr_populate_sglist()
266 * generates a scatter/gather list that covers an entire crypto
267 * operation buffer that is then used to construct the other
268 * scatter/gather lists.
269 */
270 static int
ccr_populate_sglist(struct sglist * sg,struct crypto_buffer * cb)271 ccr_populate_sglist(struct sglist *sg, struct crypto_buffer *cb)
272 {
273 int error;
274
275 sglist_reset(sg);
276 switch (cb->cb_type) {
277 case CRYPTO_BUF_MBUF:
278 error = sglist_append_mbuf(sg, cb->cb_mbuf);
279 break;
280 case CRYPTO_BUF_SINGLE_MBUF:
281 error = sglist_append_single_mbuf(sg, cb->cb_mbuf);
282 break;
283 case CRYPTO_BUF_UIO:
284 error = sglist_append_uio(sg, cb->cb_uio);
285 break;
286 case CRYPTO_BUF_CONTIG:
287 error = sglist_append(sg, cb->cb_buf, cb->cb_buf_len);
288 break;
289 case CRYPTO_BUF_VMPAGE:
290 error = sglist_append_vmpages(sg, cb->cb_vm_page,
291 cb->cb_vm_page_len, cb->cb_vm_page_offset);
292 break;
293 default:
294 error = EINVAL;
295 }
296 return (error);
297 }
298
299 /*
300 * Segments in 'sg' larger than 'maxsegsize' are counted as multiple
301 * segments.
302 */
303 static int
ccr_count_sgl(struct sglist * sg,int maxsegsize)304 ccr_count_sgl(struct sglist *sg, int maxsegsize)
305 {
306 int i, nsegs;
307
308 nsegs = 0;
309 for (i = 0; i < sg->sg_nseg; i++)
310 nsegs += howmany(sg->sg_segs[i].ss_len, maxsegsize);
311 return (nsegs);
312 }
313
314 /* These functions deal with PHYS_DSGL for the reply buffer. */
315 static inline int
ccr_phys_dsgl_len(int nsegs)316 ccr_phys_dsgl_len(int nsegs)
317 {
318 int len;
319
320 len = (nsegs / 8) * sizeof(struct phys_sge_pairs);
321 if ((nsegs % 8) != 0) {
322 len += sizeof(uint16_t) * 8;
323 len += roundup2(nsegs % 8, 2) * sizeof(uint64_t);
324 }
325 return (len);
326 }
327
328 static void
ccr_write_phys_dsgl(struct ccr_session * s,void * dst,int nsegs)329 ccr_write_phys_dsgl(struct ccr_session *s, void *dst, int nsegs)
330 {
331 struct sglist *sg;
332 struct cpl_rx_phys_dsgl *cpl;
333 struct phys_sge_pairs *sgl;
334 vm_paddr_t paddr;
335 size_t seglen;
336 u_int i, j;
337
338 sg = s->sg_dsgl;
339 cpl = dst;
340 cpl->op_to_tid = htobe32(V_CPL_RX_PHYS_DSGL_OPCODE(CPL_RX_PHYS_DSGL) |
341 V_CPL_RX_PHYS_DSGL_ISRDMA(0));
342 cpl->pcirlxorder_to_noofsgentr = htobe32(
343 V_CPL_RX_PHYS_DSGL_PCIRLXORDER(0) |
344 V_CPL_RX_PHYS_DSGL_PCINOSNOOP(0) |
345 V_CPL_RX_PHYS_DSGL_PCITPHNTENB(0) | V_CPL_RX_PHYS_DSGL_DCAID(0) |
346 V_CPL_RX_PHYS_DSGL_NOOFSGENTR(nsegs));
347 cpl->rss_hdr_int.opcode = CPL_RX_PHYS_ADDR;
348 cpl->rss_hdr_int.qid = htobe16(s->port->rxq->iq.abs_id);
349 cpl->rss_hdr_int.hash_val = 0;
350 cpl->rss_hdr_int.channel = s->port->rx_channel_id;
351 sgl = (struct phys_sge_pairs *)(cpl + 1);
352 j = 0;
353 for (i = 0; i < sg->sg_nseg; i++) {
354 seglen = sg->sg_segs[i].ss_len;
355 paddr = sg->sg_segs[i].ss_paddr;
356 do {
357 sgl->addr[j] = htobe64(paddr);
358 if (seglen > DSGL_SGE_MAXLEN) {
359 sgl->len[j] = htobe16(DSGL_SGE_MAXLEN);
360 paddr += DSGL_SGE_MAXLEN;
361 seglen -= DSGL_SGE_MAXLEN;
362 } else {
363 sgl->len[j] = htobe16(seglen);
364 seglen = 0;
365 }
366 j++;
367 if (j == 8) {
368 sgl++;
369 j = 0;
370 }
371 } while (seglen != 0);
372 }
373 MPASS(j + 8 * (sgl - (struct phys_sge_pairs *)(cpl + 1)) == nsegs);
374 }
375
376 /* These functions deal with the ULPTX_SGL for input payload. */
377 static inline int
ccr_ulptx_sgl_len(int nsegs)378 ccr_ulptx_sgl_len(int nsegs)
379 {
380 u_int n;
381
382 nsegs--; /* first segment is part of ulptx_sgl */
383 n = sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
384 return (roundup2(n, 16));
385 }
386
387 static void
ccr_write_ulptx_sgl(struct ccr_session * s,void * dst,int nsegs)388 ccr_write_ulptx_sgl(struct ccr_session *s, void *dst, int nsegs)
389 {
390 struct ulptx_sgl *usgl;
391 struct sglist *sg;
392 struct sglist_seg *ss;
393 int i;
394
395 sg = s->sg_ulptx;
396 MPASS(nsegs == sg->sg_nseg);
397 ss = &sg->sg_segs[0];
398 usgl = dst;
399 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
400 V_ULPTX_NSGE(nsegs));
401 usgl->len0 = htobe32(ss->ss_len);
402 usgl->addr0 = htobe64(ss->ss_paddr);
403 ss++;
404 for (i = 0; i < sg->sg_nseg - 1; i++) {
405 usgl->sge[i / 2].len[i & 1] = htobe32(ss->ss_len);
406 usgl->sge[i / 2].addr[i & 1] = htobe64(ss->ss_paddr);
407 ss++;
408 }
409 }
410
411 static bool
ccr_use_imm_data(u_int transhdr_len,u_int input_len)412 ccr_use_imm_data(u_int transhdr_len, u_int input_len)
413 {
414
415 if (input_len > CRYPTO_MAX_IMM_TX_PKT_LEN)
416 return (false);
417 if (roundup2(transhdr_len, 16) + roundup2(input_len, 16) >
418 SGE_MAX_WR_LEN)
419 return (false);
420 return (true);
421 }
422
423 static void
ccr_populate_wreq(struct ccr_softc * sc,struct ccr_session * s,struct chcr_wr * crwr,u_int kctx_len,u_int wr_len,u_int imm_len,u_int sgl_len,u_int hash_size,struct cryptop * crp)424 ccr_populate_wreq(struct ccr_softc *sc, struct ccr_session *s,
425 struct chcr_wr *crwr, u_int kctx_len, u_int wr_len, u_int imm_len,
426 u_int sgl_len, u_int hash_size, struct cryptop *crp)
427 {
428 u_int cctx_size, idata_len;
429
430 cctx_size = sizeof(struct _key_ctx) + kctx_len;
431 crwr->wreq.op_to_cctx_size = htobe32(
432 V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(FW_CRYPTO_LOOKASIDE_WR) |
433 V_FW_CRYPTO_LOOKASIDE_WR_COMPL(0) |
434 V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(imm_len) |
435 V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(1) |
436 V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(cctx_size >> 4));
437 crwr->wreq.len16_pkd = htobe32(
438 V_FW_CRYPTO_LOOKASIDE_WR_LEN16(wr_len / 16));
439 crwr->wreq.session_id = 0;
440 crwr->wreq.rx_chid_to_rx_q_id = htobe32(
441 V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(s->port->rx_channel_id) |
442 V_FW_CRYPTO_LOOKASIDE_WR_LCB(0) |
443 V_FW_CRYPTO_LOOKASIDE_WR_PHASH(0) |
444 V_FW_CRYPTO_LOOKASIDE_WR_IV(IV_NOP) |
445 V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(0) |
446 V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(0) | /* unused in firmware */
447 V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(s->port->rxq->iq.abs_id));
448 crwr->wreq.key_addr = 0;
449 crwr->wreq.pld_size_hash_size = htobe32(
450 V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(sgl_len) |
451 V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(hash_size));
452 crwr->wreq.cookie = htobe64((uintptr_t)crp);
453
454 crwr->ulptx.cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
455 V_ULP_TXPKT_DATAMODIFY(0) |
456 V_ULP_TXPKT_CHANNELID(s->port->tx_channel_id) |
457 V_ULP_TXPKT_DEST(0) |
458 V_ULP_TXPKT_FID(sc->first_rxq_id) | V_ULP_TXPKT_RO(1));
459 crwr->ulptx.len = htobe32(
460 ((wr_len - sizeof(struct fw_crypto_lookaside_wr)) / 16));
461
462 crwr->sc_imm.cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
463 V_ULP_TX_SC_MORE(sgl_len != 0 ? 1 : 0));
464 idata_len = wr_len - offsetof(struct chcr_wr, sec_cpl) - sgl_len;
465 if (imm_len % 16 != 0)
466 idata_len -= 16 - imm_len % 16;
467 crwr->sc_imm.len = htobe32(idata_len);
468 }
469
470 static int
ccr_hash(struct ccr_softc * sc,struct ccr_session * s,struct cryptop * crp)471 ccr_hash(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp)
472 {
473 struct chcr_wr *crwr;
474 struct wrqe *wr;
475 struct auth_hash *axf;
476 char *dst;
477 u_int hash_size_in_response, kctx_flits, kctx_len, transhdr_len, wr_len;
478 u_int hmac_ctrl, imm_len, iopad_size;
479 int error, sgl_nsegs, sgl_len, use_opad;
480
481 /* Reject requests with too large of an input buffer. */
482 if (crp->crp_payload_length > MAX_REQUEST_SIZE)
483 return (EFBIG);
484
485 axf = s->hmac.auth_hash;
486
487 if (s->mode == HMAC) {
488 use_opad = 1;
489 hmac_ctrl = SCMD_HMAC_CTRL_NO_TRUNC;
490 } else {
491 use_opad = 0;
492 hmac_ctrl = SCMD_HMAC_CTRL_NOP;
493 }
494
495 /* PADs must be 128-bit aligned. */
496 iopad_size = roundup2(s->hmac.partial_digest_len, 16);
497
498 /*
499 * The 'key' part of the context includes the aligned IPAD and
500 * OPAD.
501 */
502 kctx_len = iopad_size;
503 if (use_opad)
504 kctx_len += iopad_size;
505 hash_size_in_response = axf->hashsize;
506 transhdr_len = HASH_TRANSHDR_SIZE(kctx_len);
507
508 if (crp->crp_payload_length == 0) {
509 imm_len = axf->blocksize;
510 sgl_nsegs = 0;
511 sgl_len = 0;
512 } else if (ccr_use_imm_data(transhdr_len, crp->crp_payload_length)) {
513 imm_len = crp->crp_payload_length;
514 sgl_nsegs = 0;
515 sgl_len = 0;
516 } else {
517 imm_len = 0;
518 sglist_reset(s->sg_ulptx);
519 error = sglist_append_sglist(s->sg_ulptx, s->sg_input,
520 crp->crp_payload_start, crp->crp_payload_length);
521 if (error)
522 return (error);
523 sgl_nsegs = s->sg_ulptx->sg_nseg;
524 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs);
525 }
526
527 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len;
528 if (wr_len > SGE_MAX_WR_LEN)
529 return (EFBIG);
530 wr = alloc_wrqe(wr_len, s->port->txq);
531 if (wr == NULL) {
532 counter_u64_add(sc->stats_wr_nomem, 1);
533 return (ENOMEM);
534 }
535 crwr = wrtod(wr);
536 memset(crwr, 0, wr_len);
537
538 ccr_populate_wreq(sc, s, crwr, kctx_len, wr_len, imm_len, sgl_len,
539 hash_size_in_response, crp);
540
541 crwr->sec_cpl.op_ivinsrtofst = htobe32(
542 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
543 V_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
544 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
545 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
546 V_CPL_TX_SEC_PDU_IVINSRTOFST(0));
547
548 crwr->sec_cpl.pldlen = htobe32(crp->crp_payload_length == 0 ?
549 axf->blocksize : crp->crp_payload_length);
550
551 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32(
552 V_CPL_TX_SEC_PDU_AUTHSTART(1) | V_CPL_TX_SEC_PDU_AUTHSTOP(0));
553
554 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
555 crwr->sec_cpl.seqno_numivs = htobe32(
556 V_SCMD_SEQ_NO_CTRL(0) |
557 V_SCMD_PROTO_VERSION(SCMD_PROTO_VERSION_GENERIC) |
558 V_SCMD_CIPH_MODE(SCMD_CIPH_MODE_NOP) |
559 V_SCMD_AUTH_MODE(s->hmac.auth_mode) |
560 V_SCMD_HMAC_CTRL(hmac_ctrl));
561 crwr->sec_cpl.ivgen_hdrlen = htobe32(
562 V_SCMD_LAST_FRAG(0) |
563 V_SCMD_MORE_FRAGS(crp->crp_payload_length == 0 ? 1 : 0) |
564 V_SCMD_MAC_ONLY(1));
565
566 memcpy(crwr->key_ctx.key, s->hmac.pads, kctx_len);
567
568 /* XXX: F_KEY_CONTEXT_SALT_PRESENT set, but 'salt' not set. */
569 kctx_flits = (sizeof(struct _key_ctx) + kctx_len) / 16;
570 crwr->key_ctx.ctx_hdr = htobe32(V_KEY_CONTEXT_CTX_LEN(kctx_flits) |
571 V_KEY_CONTEXT_OPAD_PRESENT(use_opad) |
572 V_KEY_CONTEXT_SALT_PRESENT(1) |
573 V_KEY_CONTEXT_CK_SIZE(CHCR_KEYCTX_NO_KEY) |
574 V_KEY_CONTEXT_MK_SIZE(s->hmac.mk_size) | V_KEY_CONTEXT_VALID(1));
575
576 dst = (char *)(crwr + 1) + kctx_len + DUMMY_BYTES;
577 if (crp->crp_payload_length == 0) {
578 dst[0] = 0x80;
579 if (s->mode == HMAC)
580 *(uint64_t *)(dst + axf->blocksize - sizeof(uint64_t)) =
581 htobe64(axf->blocksize << 3);
582 } else if (imm_len != 0)
583 crypto_copydata(crp, crp->crp_payload_start,
584 crp->crp_payload_length, dst);
585 else
586 ccr_write_ulptx_sgl(s, dst, sgl_nsegs);
587
588 /* XXX: TODO backpressure */
589 t4_wrq_tx(sc->adapter, wr);
590
591 return (0);
592 }
593
594 static int
ccr_hash_done(struct ccr_softc * sc,struct ccr_session * s,struct cryptop * crp,const struct cpl_fw6_pld * cpl,int error)595 ccr_hash_done(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp,
596 const struct cpl_fw6_pld *cpl, int error)
597 {
598 uint8_t hash[HASH_MAX_LEN];
599
600 if (error)
601 return (error);
602
603 if (crp->crp_op & CRYPTO_OP_VERIFY_DIGEST) {
604 crypto_copydata(crp, crp->crp_digest_start, s->hmac.hash_len,
605 hash);
606 if (timingsafe_bcmp((cpl + 1), hash, s->hmac.hash_len) != 0)
607 return (EBADMSG);
608 } else
609 crypto_copyback(crp, crp->crp_digest_start, s->hmac.hash_len,
610 (cpl + 1));
611 return (0);
612 }
613
614 static int
ccr_blkcipher(struct ccr_softc * sc,struct ccr_session * s,struct cryptop * crp)615 ccr_blkcipher(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp)
616 {
617 char iv[CHCR_MAX_CRYPTO_IV_LEN];
618 struct chcr_wr *crwr;
619 struct wrqe *wr;
620 char *dst;
621 u_int kctx_len, key_half, op_type, transhdr_len, wr_len;
622 u_int imm_len, iv_len;
623 int dsgl_nsegs, dsgl_len;
624 int sgl_nsegs, sgl_len;
625 int error;
626
627 if (s->blkcipher.key_len == 0 || crp->crp_payload_length == 0)
628 return (EINVAL);
629 if (s->blkcipher.cipher_mode == SCMD_CIPH_MODE_AES_CBC &&
630 (crp->crp_payload_length % AES_BLOCK_LEN) != 0)
631 return (EINVAL);
632
633 /* Reject requests with too large of an input buffer. */
634 if (crp->crp_payload_length > MAX_REQUEST_SIZE)
635 return (EFBIG);
636
637 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
638 op_type = CHCR_ENCRYPT_OP;
639 else
640 op_type = CHCR_DECRYPT_OP;
641
642 sglist_reset(s->sg_dsgl);
643 if (CRYPTO_HAS_OUTPUT_BUFFER(crp))
644 error = sglist_append_sglist(s->sg_dsgl, s->sg_output,
645 crp->crp_payload_output_start, crp->crp_payload_length);
646 else
647 error = sglist_append_sglist(s->sg_dsgl, s->sg_input,
648 crp->crp_payload_start, crp->crp_payload_length);
649 if (error)
650 return (error);
651 dsgl_nsegs = ccr_count_sgl(s->sg_dsgl, DSGL_SGE_MAXLEN);
652 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE)
653 return (EFBIG);
654 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs);
655
656 /* The 'key' must be 128-bit aligned. */
657 kctx_len = roundup2(s->blkcipher.key_len, 16);
658 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len);
659
660 /* For AES-XTS we send a 16-byte IV in the work request. */
661 if (s->blkcipher.cipher_mode == SCMD_CIPH_MODE_AES_XTS)
662 iv_len = AES_BLOCK_LEN;
663 else
664 iv_len = s->blkcipher.iv_len;
665
666 if (ccr_use_imm_data(transhdr_len, crp->crp_payload_length + iv_len)) {
667 imm_len = crp->crp_payload_length;
668 sgl_nsegs = 0;
669 sgl_len = 0;
670 } else {
671 imm_len = 0;
672 sglist_reset(s->sg_ulptx);
673 error = sglist_append_sglist(s->sg_ulptx, s->sg_input,
674 crp->crp_payload_start, crp->crp_payload_length);
675 if (error)
676 return (error);
677 sgl_nsegs = s->sg_ulptx->sg_nseg;
678 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs);
679 }
680
681 wr_len = roundup2(transhdr_len, 16) + iv_len +
682 roundup2(imm_len, 16) + sgl_len;
683 if (wr_len > SGE_MAX_WR_LEN)
684 return (EFBIG);
685 wr = alloc_wrqe(wr_len, s->port->txq);
686 if (wr == NULL) {
687 counter_u64_add(sc->stats_wr_nomem, 1);
688 return (ENOMEM);
689 }
690 crwr = wrtod(wr);
691 memset(crwr, 0, wr_len);
692
693 crypto_read_iv(crp, iv);
694
695 /* Zero the remainder of the IV for AES-XTS. */
696 memset(iv + s->blkcipher.iv_len, 0, iv_len - s->blkcipher.iv_len);
697
698 ccr_populate_wreq(sc, s, crwr, kctx_len, wr_len, imm_len, sgl_len, 0,
699 crp);
700
701 crwr->sec_cpl.op_ivinsrtofst = htobe32(
702 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
703 V_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
704 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
705 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
706 V_CPL_TX_SEC_PDU_IVINSRTOFST(1));
707
708 crwr->sec_cpl.pldlen = htobe32(iv_len + crp->crp_payload_length);
709
710 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32(
711 V_CPL_TX_SEC_PDU_CIPHERSTART(iv_len + 1) |
712 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(0));
713 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32(
714 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(0));
715
716 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
717 crwr->sec_cpl.seqno_numivs = htobe32(
718 V_SCMD_SEQ_NO_CTRL(0) |
719 V_SCMD_PROTO_VERSION(SCMD_PROTO_VERSION_GENERIC) |
720 V_SCMD_ENC_DEC_CTRL(op_type) |
721 V_SCMD_CIPH_MODE(s->blkcipher.cipher_mode) |
722 V_SCMD_AUTH_MODE(SCMD_AUTH_MODE_NOP) |
723 V_SCMD_HMAC_CTRL(SCMD_HMAC_CTRL_NOP) |
724 V_SCMD_IV_SIZE(iv_len / 2) |
725 V_SCMD_NUM_IVS(0));
726 crwr->sec_cpl.ivgen_hdrlen = htobe32(
727 V_SCMD_IV_GEN_CTRL(0) |
728 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) |
729 V_SCMD_AADIVDROP(1) | V_SCMD_HDR_LEN(dsgl_len));
730
731 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr;
732 switch (s->blkcipher.cipher_mode) {
733 case SCMD_CIPH_MODE_AES_CBC:
734 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
735 memcpy(crwr->key_ctx.key, s->blkcipher.enckey,
736 s->blkcipher.key_len);
737 else
738 memcpy(crwr->key_ctx.key, s->blkcipher.deckey,
739 s->blkcipher.key_len);
740 break;
741 case SCMD_CIPH_MODE_AES_CTR:
742 memcpy(crwr->key_ctx.key, s->blkcipher.enckey,
743 s->blkcipher.key_len);
744 break;
745 case SCMD_CIPH_MODE_AES_XTS:
746 key_half = s->blkcipher.key_len / 2;
747 memcpy(crwr->key_ctx.key, s->blkcipher.enckey + key_half,
748 key_half);
749 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
750 memcpy(crwr->key_ctx.key + key_half,
751 s->blkcipher.enckey, key_half);
752 else
753 memcpy(crwr->key_ctx.key + key_half,
754 s->blkcipher.deckey, key_half);
755 break;
756 }
757
758 dst = (char *)(crwr + 1) + kctx_len;
759 ccr_write_phys_dsgl(s, dst, dsgl_nsegs);
760 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len;
761 memcpy(dst, iv, iv_len);
762 dst += iv_len;
763 if (imm_len != 0)
764 crypto_copydata(crp, crp->crp_payload_start,
765 crp->crp_payload_length, dst);
766 else
767 ccr_write_ulptx_sgl(s, dst, sgl_nsegs);
768
769 /* XXX: TODO backpressure */
770 t4_wrq_tx(sc->adapter, wr);
771
772 explicit_bzero(iv, sizeof(iv));
773 return (0);
774 }
775
776 static int
ccr_blkcipher_done(struct ccr_softc * sc,struct ccr_session * s,struct cryptop * crp,const struct cpl_fw6_pld * cpl,int error)777 ccr_blkcipher_done(struct ccr_softc *sc, struct ccr_session *s,
778 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error)
779 {
780
781 /*
782 * The updated IV to permit chained requests is at
783 * cpl->data[2], but OCF doesn't permit chained requests.
784 */
785 return (error);
786 }
787
788 /*
789 * 'hashsize' is the length of a full digest. 'authsize' is the
790 * requested digest length for this operation which may be less
791 * than 'hashsize'.
792 */
793 static int
ccr_hmac_ctrl(unsigned int hashsize,unsigned int authsize)794 ccr_hmac_ctrl(unsigned int hashsize, unsigned int authsize)
795 {
796
797 if (authsize == 10)
798 return (SCMD_HMAC_CTRL_TRUNC_RFC4366);
799 if (authsize == 12)
800 return (SCMD_HMAC_CTRL_IPSEC_96BIT);
801 if (authsize == hashsize / 2)
802 return (SCMD_HMAC_CTRL_DIV2);
803 return (SCMD_HMAC_CTRL_NO_TRUNC);
804 }
805
806 static int
ccr_eta(struct ccr_softc * sc,struct ccr_session * s,struct cryptop * crp)807 ccr_eta(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp)
808 {
809 char iv[CHCR_MAX_CRYPTO_IV_LEN];
810 struct chcr_wr *crwr;
811 struct wrqe *wr;
812 struct auth_hash *axf;
813 char *dst;
814 u_int kctx_len, key_half, op_type, transhdr_len, wr_len;
815 u_int hash_size_in_response, imm_len, iopad_size, iv_len;
816 u_int aad_start, aad_stop;
817 u_int auth_insert;
818 u_int cipher_start, cipher_stop;
819 u_int hmac_ctrl, input_len;
820 int dsgl_nsegs, dsgl_len;
821 int sgl_nsegs, sgl_len;
822 int error;
823
824 /*
825 * If there is a need in the future, requests with an empty
826 * payload could be supported as HMAC-only requests.
827 */
828 if (s->blkcipher.key_len == 0 || crp->crp_payload_length == 0)
829 return (EINVAL);
830 if (s->blkcipher.cipher_mode == SCMD_CIPH_MODE_AES_CBC &&
831 (crp->crp_payload_length % AES_BLOCK_LEN) != 0)
832 return (EINVAL);
833
834 /* For AES-XTS we send a 16-byte IV in the work request. */
835 if (s->blkcipher.cipher_mode == SCMD_CIPH_MODE_AES_XTS)
836 iv_len = AES_BLOCK_LEN;
837 else
838 iv_len = s->blkcipher.iv_len;
839
840 if (crp->crp_aad_length + iv_len > MAX_AAD_LEN)
841 return (EINVAL);
842
843 axf = s->hmac.auth_hash;
844 hash_size_in_response = s->hmac.hash_len;
845 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
846 op_type = CHCR_ENCRYPT_OP;
847 else
848 op_type = CHCR_DECRYPT_OP;
849
850 /*
851 * The output buffer consists of the cipher text followed by
852 * the hash when encrypting. For decryption it only contains
853 * the plain text.
854 *
855 * Due to a firmware bug, the output buffer must include a
856 * dummy output buffer for the IV and AAD prior to the real
857 * output buffer.
858 */
859 if (op_type == CHCR_ENCRYPT_OP) {
860 if (iv_len + crp->crp_aad_length + crp->crp_payload_length +
861 hash_size_in_response > MAX_REQUEST_SIZE)
862 return (EFBIG);
863 } else {
864 if (iv_len + crp->crp_aad_length + crp->crp_payload_length >
865 MAX_REQUEST_SIZE)
866 return (EFBIG);
867 }
868 sglist_reset(s->sg_dsgl);
869 error = sglist_append_sglist(s->sg_dsgl, sc->sg_iv_aad, 0,
870 iv_len + crp->crp_aad_length);
871 if (error)
872 return (error);
873 if (CRYPTO_HAS_OUTPUT_BUFFER(crp))
874 error = sglist_append_sglist(s->sg_dsgl, s->sg_output,
875 crp->crp_payload_output_start, crp->crp_payload_length);
876 else
877 error = sglist_append_sglist(s->sg_dsgl, s->sg_input,
878 crp->crp_payload_start, crp->crp_payload_length);
879 if (error)
880 return (error);
881 if (op_type == CHCR_ENCRYPT_OP) {
882 if (CRYPTO_HAS_OUTPUT_BUFFER(crp))
883 error = sglist_append_sglist(s->sg_dsgl, s->sg_output,
884 crp->crp_digest_start, hash_size_in_response);
885 else
886 error = sglist_append_sglist(s->sg_dsgl, s->sg_input,
887 crp->crp_digest_start, hash_size_in_response);
888 if (error)
889 return (error);
890 }
891 dsgl_nsegs = ccr_count_sgl(s->sg_dsgl, DSGL_SGE_MAXLEN);
892 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE)
893 return (EFBIG);
894 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs);
895
896 /* PADs must be 128-bit aligned. */
897 iopad_size = roundup2(s->hmac.partial_digest_len, 16);
898
899 /*
900 * The 'key' part of the key context consists of the key followed
901 * by the IPAD and OPAD.
902 */
903 kctx_len = roundup2(s->blkcipher.key_len, 16) + iopad_size * 2;
904 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len);
905
906 /*
907 * The input buffer consists of the IV, any AAD, and then the
908 * cipher/plain text. For decryption requests the hash is
909 * appended after the cipher text.
910 *
911 * The IV is always stored at the start of the input buffer
912 * even though it may be duplicated in the payload. The
913 * crypto engine doesn't work properly if the IV offset points
914 * inside of the AAD region, so a second copy is always
915 * required.
916 */
917 input_len = crp->crp_aad_length + crp->crp_payload_length;
918
919 /*
920 * The firmware hangs if sent a request which is a
921 * bit smaller than MAX_REQUEST_SIZE. In particular, the
922 * firmware appears to require 512 - 16 bytes of spare room
923 * along with the size of the hash even if the hash isn't
924 * included in the input buffer.
925 */
926 if (input_len + roundup2(axf->hashsize, 16) + (512 - 16) >
927 MAX_REQUEST_SIZE)
928 return (EFBIG);
929 if (op_type == CHCR_DECRYPT_OP)
930 input_len += hash_size_in_response;
931
932 if (ccr_use_imm_data(transhdr_len, iv_len + input_len)) {
933 imm_len = input_len;
934 sgl_nsegs = 0;
935 sgl_len = 0;
936 } else {
937 imm_len = 0;
938 sglist_reset(s->sg_ulptx);
939 if (crp->crp_aad_length != 0) {
940 if (crp->crp_aad != NULL)
941 error = sglist_append(s->sg_ulptx,
942 crp->crp_aad, crp->crp_aad_length);
943 else
944 error = sglist_append_sglist(s->sg_ulptx,
945 s->sg_input, crp->crp_aad_start,
946 crp->crp_aad_length);
947 if (error)
948 return (error);
949 }
950 error = sglist_append_sglist(s->sg_ulptx, s->sg_input,
951 crp->crp_payload_start, crp->crp_payload_length);
952 if (error)
953 return (error);
954 if (op_type == CHCR_DECRYPT_OP) {
955 error = sglist_append_sglist(s->sg_ulptx, s->sg_input,
956 crp->crp_digest_start, hash_size_in_response);
957 if (error)
958 return (error);
959 }
960 sgl_nsegs = s->sg_ulptx->sg_nseg;
961 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs);
962 }
963
964 /* Any AAD comes after the IV. */
965 if (crp->crp_aad_length != 0) {
966 aad_start = iv_len + 1;
967 aad_stop = aad_start + crp->crp_aad_length - 1;
968 } else {
969 aad_start = 0;
970 aad_stop = 0;
971 }
972 cipher_start = iv_len + crp->crp_aad_length + 1;
973 if (op_type == CHCR_DECRYPT_OP)
974 cipher_stop = hash_size_in_response;
975 else
976 cipher_stop = 0;
977 if (op_type == CHCR_DECRYPT_OP)
978 auth_insert = hash_size_in_response;
979 else
980 auth_insert = 0;
981
982 wr_len = roundup2(transhdr_len, 16) + iv_len + roundup2(imm_len, 16) +
983 sgl_len;
984 if (wr_len > SGE_MAX_WR_LEN)
985 return (EFBIG);
986 wr = alloc_wrqe(wr_len, s->port->txq);
987 if (wr == NULL) {
988 counter_u64_add(sc->stats_wr_nomem, 1);
989 return (ENOMEM);
990 }
991 crwr = wrtod(wr);
992 memset(crwr, 0, wr_len);
993
994 crypto_read_iv(crp, iv);
995
996 /* Zero the remainder of the IV for AES-XTS. */
997 memset(iv + s->blkcipher.iv_len, 0, iv_len - s->blkcipher.iv_len);
998
999 ccr_populate_wreq(sc, s, crwr, kctx_len, wr_len, imm_len, sgl_len,
1000 op_type == CHCR_DECRYPT_OP ? hash_size_in_response : 0, crp);
1001
1002 crwr->sec_cpl.op_ivinsrtofst = htobe32(
1003 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
1004 V_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
1005 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
1006 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
1007 V_CPL_TX_SEC_PDU_IVINSRTOFST(1));
1008
1009 crwr->sec_cpl.pldlen = htobe32(iv_len + input_len);
1010
1011 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32(
1012 V_CPL_TX_SEC_PDU_AADSTART(aad_start) |
1013 V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) |
1014 V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) |
1015 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(cipher_stop >> 4));
1016 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32(
1017 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(cipher_stop & 0xf) |
1018 V_CPL_TX_SEC_PDU_AUTHSTART(cipher_start) |
1019 V_CPL_TX_SEC_PDU_AUTHSTOP(cipher_stop) |
1020 V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert));
1021
1022 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
1023 hmac_ctrl = ccr_hmac_ctrl(axf->hashsize, hash_size_in_response);
1024 crwr->sec_cpl.seqno_numivs = htobe32(
1025 V_SCMD_SEQ_NO_CTRL(0) |
1026 V_SCMD_PROTO_VERSION(SCMD_PROTO_VERSION_GENERIC) |
1027 V_SCMD_ENC_DEC_CTRL(op_type) |
1028 V_SCMD_CIPH_AUTH_SEQ_CTRL(op_type == CHCR_ENCRYPT_OP ? 1 : 0) |
1029 V_SCMD_CIPH_MODE(s->blkcipher.cipher_mode) |
1030 V_SCMD_AUTH_MODE(s->hmac.auth_mode) |
1031 V_SCMD_HMAC_CTRL(hmac_ctrl) |
1032 V_SCMD_IV_SIZE(iv_len / 2) |
1033 V_SCMD_NUM_IVS(0));
1034 crwr->sec_cpl.ivgen_hdrlen = htobe32(
1035 V_SCMD_IV_GEN_CTRL(0) |
1036 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) |
1037 V_SCMD_AADIVDROP(0) | V_SCMD_HDR_LEN(dsgl_len));
1038
1039 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr;
1040 switch (s->blkcipher.cipher_mode) {
1041 case SCMD_CIPH_MODE_AES_CBC:
1042 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
1043 memcpy(crwr->key_ctx.key, s->blkcipher.enckey,
1044 s->blkcipher.key_len);
1045 else
1046 memcpy(crwr->key_ctx.key, s->blkcipher.deckey,
1047 s->blkcipher.key_len);
1048 break;
1049 case SCMD_CIPH_MODE_AES_CTR:
1050 memcpy(crwr->key_ctx.key, s->blkcipher.enckey,
1051 s->blkcipher.key_len);
1052 break;
1053 case SCMD_CIPH_MODE_AES_XTS:
1054 key_half = s->blkcipher.key_len / 2;
1055 memcpy(crwr->key_ctx.key, s->blkcipher.enckey + key_half,
1056 key_half);
1057 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
1058 memcpy(crwr->key_ctx.key + key_half,
1059 s->blkcipher.enckey, key_half);
1060 else
1061 memcpy(crwr->key_ctx.key + key_half,
1062 s->blkcipher.deckey, key_half);
1063 break;
1064 }
1065
1066 dst = crwr->key_ctx.key + roundup2(s->blkcipher.key_len, 16);
1067 memcpy(dst, s->hmac.pads, iopad_size * 2);
1068
1069 dst = (char *)(crwr + 1) + kctx_len;
1070 ccr_write_phys_dsgl(s, dst, dsgl_nsegs);
1071 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len;
1072 memcpy(dst, iv, iv_len);
1073 dst += iv_len;
1074 if (imm_len != 0) {
1075 if (crp->crp_aad_length != 0) {
1076 if (crp->crp_aad != NULL)
1077 memcpy(dst, crp->crp_aad, crp->crp_aad_length);
1078 else
1079 crypto_copydata(crp, crp->crp_aad_start,
1080 crp->crp_aad_length, dst);
1081 dst += crp->crp_aad_length;
1082 }
1083 crypto_copydata(crp, crp->crp_payload_start,
1084 crp->crp_payload_length, dst);
1085 dst += crp->crp_payload_length;
1086 if (op_type == CHCR_DECRYPT_OP)
1087 crypto_copydata(crp, crp->crp_digest_start,
1088 hash_size_in_response, dst);
1089 } else
1090 ccr_write_ulptx_sgl(s, dst, sgl_nsegs);
1091
1092 /* XXX: TODO backpressure */
1093 t4_wrq_tx(sc->adapter, wr);
1094
1095 explicit_bzero(iv, sizeof(iv));
1096 return (0);
1097 }
1098
1099 static int
ccr_eta_done(struct ccr_softc * sc,struct ccr_session * s,struct cryptop * crp,const struct cpl_fw6_pld * cpl,int error)1100 ccr_eta_done(struct ccr_softc *sc, struct ccr_session *s,
1101 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error)
1102 {
1103
1104 /*
1105 * The updated IV to permit chained requests is at
1106 * cpl->data[2], but OCF doesn't permit chained requests.
1107 */
1108 return (error);
1109 }
1110
1111 static int
ccr_gcm(struct ccr_softc * sc,struct ccr_session * s,struct cryptop * crp)1112 ccr_gcm(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp)
1113 {
1114 char iv[CHCR_MAX_CRYPTO_IV_LEN];
1115 struct chcr_wr *crwr;
1116 struct wrqe *wr;
1117 char *dst;
1118 u_int iv_len, kctx_len, op_type, transhdr_len, wr_len;
1119 u_int hash_size_in_response, imm_len;
1120 u_int aad_start, aad_stop, cipher_start, cipher_stop, auth_insert;
1121 u_int hmac_ctrl, input_len;
1122 int dsgl_nsegs, dsgl_len;
1123 int sgl_nsegs, sgl_len;
1124 int error;
1125
1126 if (s->blkcipher.key_len == 0)
1127 return (EINVAL);
1128
1129 /*
1130 * The crypto engine doesn't handle GCM requests with an empty
1131 * payload, so handle those in software instead.
1132 */
1133 if (crp->crp_payload_length == 0)
1134 return (EMSGSIZE);
1135
1136 if (crp->crp_aad_length + AES_BLOCK_LEN > MAX_AAD_LEN)
1137 return (EMSGSIZE);
1138
1139 hash_size_in_response = s->gmac.hash_len;
1140 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
1141 op_type = CHCR_ENCRYPT_OP;
1142 else
1143 op_type = CHCR_DECRYPT_OP;
1144
1145 iv_len = AES_BLOCK_LEN;
1146
1147 /*
1148 * GCM requests should always provide an explicit IV.
1149 */
1150 if ((crp->crp_flags & CRYPTO_F_IV_SEPARATE) == 0)
1151 return (EINVAL);
1152
1153 /*
1154 * The output buffer consists of the cipher text followed by
1155 * the tag when encrypting. For decryption it only contains
1156 * the plain text.
1157 *
1158 * Due to a firmware bug, the output buffer must include a
1159 * dummy output buffer for the IV and AAD prior to the real
1160 * output buffer.
1161 */
1162 if (op_type == CHCR_ENCRYPT_OP) {
1163 if (iv_len + crp->crp_aad_length + crp->crp_payload_length +
1164 hash_size_in_response > MAX_REQUEST_SIZE)
1165 return (EFBIG);
1166 } else {
1167 if (iv_len + crp->crp_aad_length + crp->crp_payload_length >
1168 MAX_REQUEST_SIZE)
1169 return (EFBIG);
1170 }
1171 sglist_reset(s->sg_dsgl);
1172 error = sglist_append_sglist(s->sg_dsgl, sc->sg_iv_aad, 0, iv_len +
1173 crp->crp_aad_length);
1174 if (error)
1175 return (error);
1176 if (CRYPTO_HAS_OUTPUT_BUFFER(crp))
1177 error = sglist_append_sglist(s->sg_dsgl, s->sg_output,
1178 crp->crp_payload_output_start, crp->crp_payload_length);
1179 else
1180 error = sglist_append_sglist(s->sg_dsgl, s->sg_input,
1181 crp->crp_payload_start, crp->crp_payload_length);
1182 if (error)
1183 return (error);
1184 if (op_type == CHCR_ENCRYPT_OP) {
1185 if (CRYPTO_HAS_OUTPUT_BUFFER(crp))
1186 error = sglist_append_sglist(s->sg_dsgl, s->sg_output,
1187 crp->crp_digest_start, hash_size_in_response);
1188 else
1189 error = sglist_append_sglist(s->sg_dsgl, s->sg_input,
1190 crp->crp_digest_start, hash_size_in_response);
1191 if (error)
1192 return (error);
1193 }
1194 dsgl_nsegs = ccr_count_sgl(s->sg_dsgl, DSGL_SGE_MAXLEN);
1195 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE)
1196 return (EFBIG);
1197 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs);
1198
1199 /*
1200 * The 'key' part of the key context consists of the key followed
1201 * by the Galois hash key.
1202 */
1203 kctx_len = roundup2(s->blkcipher.key_len, 16) + GMAC_BLOCK_LEN;
1204 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len);
1205
1206 /*
1207 * The input buffer consists of the IV, any AAD, and then the
1208 * cipher/plain text. For decryption requests the hash is
1209 * appended after the cipher text.
1210 *
1211 * The IV is always stored at the start of the input buffer
1212 * even though it may be duplicated in the payload. The
1213 * crypto engine doesn't work properly if the IV offset points
1214 * inside of the AAD region, so a second copy is always
1215 * required.
1216 */
1217 input_len = crp->crp_aad_length + crp->crp_payload_length;
1218 if (op_type == CHCR_DECRYPT_OP)
1219 input_len += hash_size_in_response;
1220 if (input_len > MAX_REQUEST_SIZE)
1221 return (EFBIG);
1222 if (ccr_use_imm_data(transhdr_len, iv_len + input_len)) {
1223 imm_len = input_len;
1224 sgl_nsegs = 0;
1225 sgl_len = 0;
1226 } else {
1227 imm_len = 0;
1228 sglist_reset(s->sg_ulptx);
1229 if (crp->crp_aad_length != 0) {
1230 if (crp->crp_aad != NULL)
1231 error = sglist_append(s->sg_ulptx,
1232 crp->crp_aad, crp->crp_aad_length);
1233 else
1234 error = sglist_append_sglist(s->sg_ulptx,
1235 s->sg_input, crp->crp_aad_start,
1236 crp->crp_aad_length);
1237 if (error)
1238 return (error);
1239 }
1240 error = sglist_append_sglist(s->sg_ulptx, s->sg_input,
1241 crp->crp_payload_start, crp->crp_payload_length);
1242 if (error)
1243 return (error);
1244 if (op_type == CHCR_DECRYPT_OP) {
1245 error = sglist_append_sglist(s->sg_ulptx, s->sg_input,
1246 crp->crp_digest_start, hash_size_in_response);
1247 if (error)
1248 return (error);
1249 }
1250 sgl_nsegs = s->sg_ulptx->sg_nseg;
1251 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs);
1252 }
1253
1254 if (crp->crp_aad_length != 0) {
1255 aad_start = iv_len + 1;
1256 aad_stop = aad_start + crp->crp_aad_length - 1;
1257 } else {
1258 aad_start = 0;
1259 aad_stop = 0;
1260 }
1261 cipher_start = iv_len + crp->crp_aad_length + 1;
1262 if (op_type == CHCR_DECRYPT_OP)
1263 cipher_stop = hash_size_in_response;
1264 else
1265 cipher_stop = 0;
1266 if (op_type == CHCR_DECRYPT_OP)
1267 auth_insert = hash_size_in_response;
1268 else
1269 auth_insert = 0;
1270
1271 wr_len = roundup2(transhdr_len, 16) + iv_len + roundup2(imm_len, 16) +
1272 sgl_len;
1273 if (wr_len > SGE_MAX_WR_LEN)
1274 return (EFBIG);
1275 wr = alloc_wrqe(wr_len, s->port->txq);
1276 if (wr == NULL) {
1277 counter_u64_add(sc->stats_wr_nomem, 1);
1278 return (ENOMEM);
1279 }
1280 crwr = wrtod(wr);
1281 memset(crwr, 0, wr_len);
1282
1283 crypto_read_iv(crp, iv);
1284 *(uint32_t *)&iv[12] = htobe32(1);
1285
1286 ccr_populate_wreq(sc, s, crwr, kctx_len, wr_len, imm_len, sgl_len, 0,
1287 crp);
1288
1289 crwr->sec_cpl.op_ivinsrtofst = htobe32(
1290 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
1291 V_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
1292 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
1293 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
1294 V_CPL_TX_SEC_PDU_IVINSRTOFST(1));
1295
1296 crwr->sec_cpl.pldlen = htobe32(iv_len + input_len);
1297
1298 /*
1299 * NB: cipherstop is explicitly set to 0. On encrypt it
1300 * should normally be set to 0 anyway. However, for decrypt
1301 * the cipher ends before the tag in the ETA case (and
1302 * authstop is set to stop before the tag), but for GCM the
1303 * cipher still runs to the end of the buffer. Not sure if
1304 * this is intentional or a firmware quirk, but it is required
1305 * for working tag validation with GCM decryption.
1306 */
1307 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32(
1308 V_CPL_TX_SEC_PDU_AADSTART(aad_start) |
1309 V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) |
1310 V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) |
1311 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(0));
1312 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32(
1313 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(0) |
1314 V_CPL_TX_SEC_PDU_AUTHSTART(cipher_start) |
1315 V_CPL_TX_SEC_PDU_AUTHSTOP(cipher_stop) |
1316 V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert));
1317
1318 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
1319 hmac_ctrl = ccr_hmac_ctrl(AES_GMAC_HASH_LEN, hash_size_in_response);
1320 crwr->sec_cpl.seqno_numivs = htobe32(
1321 V_SCMD_SEQ_NO_CTRL(0) |
1322 V_SCMD_PROTO_VERSION(SCMD_PROTO_VERSION_GENERIC) |
1323 V_SCMD_ENC_DEC_CTRL(op_type) |
1324 V_SCMD_CIPH_AUTH_SEQ_CTRL(op_type == CHCR_ENCRYPT_OP ? 1 : 0) |
1325 V_SCMD_CIPH_MODE(SCMD_CIPH_MODE_AES_GCM) |
1326 V_SCMD_AUTH_MODE(SCMD_AUTH_MODE_GHASH) |
1327 V_SCMD_HMAC_CTRL(hmac_ctrl) |
1328 V_SCMD_IV_SIZE(iv_len / 2) |
1329 V_SCMD_NUM_IVS(0));
1330 crwr->sec_cpl.ivgen_hdrlen = htobe32(
1331 V_SCMD_IV_GEN_CTRL(0) |
1332 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) |
1333 V_SCMD_AADIVDROP(0) | V_SCMD_HDR_LEN(dsgl_len));
1334
1335 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr;
1336 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, s->blkcipher.key_len);
1337 dst = crwr->key_ctx.key + roundup2(s->blkcipher.key_len, 16);
1338 memcpy(dst, s->gmac.ghash_h, GMAC_BLOCK_LEN);
1339
1340 dst = (char *)(crwr + 1) + kctx_len;
1341 ccr_write_phys_dsgl(s, dst, dsgl_nsegs);
1342 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len;
1343 memcpy(dst, iv, iv_len);
1344 dst += iv_len;
1345 if (imm_len != 0) {
1346 if (crp->crp_aad_length != 0) {
1347 if (crp->crp_aad != NULL)
1348 memcpy(dst, crp->crp_aad, crp->crp_aad_length);
1349 else
1350 crypto_copydata(crp, crp->crp_aad_start,
1351 crp->crp_aad_length, dst);
1352 dst += crp->crp_aad_length;
1353 }
1354 crypto_copydata(crp, crp->crp_payload_start,
1355 crp->crp_payload_length, dst);
1356 dst += crp->crp_payload_length;
1357 if (op_type == CHCR_DECRYPT_OP)
1358 crypto_copydata(crp, crp->crp_digest_start,
1359 hash_size_in_response, dst);
1360 } else
1361 ccr_write_ulptx_sgl(s, dst, sgl_nsegs);
1362
1363 /* XXX: TODO backpressure */
1364 t4_wrq_tx(sc->adapter, wr);
1365
1366 explicit_bzero(iv, sizeof(iv));
1367 return (0);
1368 }
1369
1370 static int
ccr_gcm_done(struct ccr_softc * sc,struct ccr_session * s,struct cryptop * crp,const struct cpl_fw6_pld * cpl,int error)1371 ccr_gcm_done(struct ccr_softc *sc, struct ccr_session *s,
1372 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error)
1373 {
1374
1375 /*
1376 * The updated IV to permit chained requests is at
1377 * cpl->data[2], but OCF doesn't permit chained requests.
1378 *
1379 * Note that the hardware should always verify the GMAC hash.
1380 */
1381 return (error);
1382 }
1383
1384 /*
1385 * Handle a GCM request that is not supported by the crypto engine by
1386 * performing the operation in software. Derived from swcr_authenc().
1387 */
1388 static void
ccr_gcm_soft(struct ccr_session * s,struct cryptop * crp)1389 ccr_gcm_soft(struct ccr_session *s, struct cryptop *crp)
1390 {
1391 struct auth_hash *axf;
1392 struct enc_xform *exf;
1393 void *auth_ctx, *kschedule;
1394 char block[GMAC_BLOCK_LEN];
1395 char digest[GMAC_DIGEST_LEN];
1396 int error, i, len;
1397
1398 auth_ctx = NULL;
1399 kschedule = NULL;
1400
1401 /* Initialize the MAC. */
1402 switch (s->blkcipher.key_len) {
1403 case 16:
1404 axf = &auth_hash_nist_gmac_aes_128;
1405 break;
1406 case 24:
1407 axf = &auth_hash_nist_gmac_aes_192;
1408 break;
1409 case 32:
1410 axf = &auth_hash_nist_gmac_aes_256;
1411 break;
1412 default:
1413 error = EINVAL;
1414 goto out;
1415 }
1416 auth_ctx = malloc(axf->ctxsize, M_CCR, M_NOWAIT);
1417 if (auth_ctx == NULL) {
1418 error = ENOMEM;
1419 goto out;
1420 }
1421 axf->Init(auth_ctx);
1422 axf->Setkey(auth_ctx, s->blkcipher.enckey, s->blkcipher.key_len);
1423
1424 /* Initialize the cipher. */
1425 exf = &enc_xform_aes_nist_gcm;
1426 kschedule = malloc(exf->ctxsize, M_CCR, M_NOWAIT);
1427 if (kschedule == NULL) {
1428 error = ENOMEM;
1429 goto out;
1430 }
1431 error = exf->setkey(kschedule, s->blkcipher.enckey,
1432 s->blkcipher.key_len);
1433 if (error)
1434 goto out;
1435
1436 if ((crp->crp_flags & CRYPTO_F_IV_SEPARATE) == 0) {
1437 error = EINVAL;
1438 goto out;
1439 }
1440
1441 axf->Reinit(auth_ctx, crp->crp_iv, AES_GCM_IV_LEN);
1442
1443 /* MAC the AAD. */
1444 if (crp->crp_aad != NULL) {
1445 len = rounddown(crp->crp_aad_length, sizeof(block));
1446 if (len != 0)
1447 axf->Update(auth_ctx, crp->crp_aad, len);
1448 if (crp->crp_aad_length != len) {
1449 memset(block, 0, sizeof(block));
1450 memcpy(block, (char *)crp->crp_aad + len,
1451 crp->crp_aad_length - len);
1452 axf->Update(auth_ctx, block, sizeof(block));
1453 }
1454 } else {
1455 for (i = 0; i < crp->crp_aad_length; i += sizeof(block)) {
1456 len = imin(crp->crp_aad_length - i, sizeof(block));
1457 crypto_copydata(crp, crp->crp_aad_start + i, len,
1458 block);
1459 bzero(block + len, sizeof(block) - len);
1460 axf->Update(auth_ctx, block, sizeof(block));
1461 }
1462 }
1463
1464 exf->reinit(kschedule, crp->crp_iv, AES_GCM_IV_LEN);
1465
1466 /* Do encryption with MAC */
1467 for (i = 0; i < crp->crp_payload_length; i += sizeof(block)) {
1468 len = imin(crp->crp_payload_length - i, sizeof(block));
1469 crypto_copydata(crp, crp->crp_payload_start + i, len, block);
1470 bzero(block + len, sizeof(block) - len);
1471 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) {
1472 exf->encrypt(kschedule, block, block);
1473 axf->Update(auth_ctx, block, len);
1474 crypto_copyback(crp, crp->crp_payload_start + i, len,
1475 block);
1476 } else {
1477 axf->Update(auth_ctx, block, len);
1478 }
1479 }
1480
1481 /* Length block. */
1482 bzero(block, sizeof(block));
1483 ((uint32_t *)block)[1] = htobe32(crp->crp_aad_length * 8);
1484 ((uint32_t *)block)[3] = htobe32(crp->crp_payload_length * 8);
1485 axf->Update(auth_ctx, block, sizeof(block));
1486
1487 /* Finalize MAC. */
1488 axf->Final(digest, auth_ctx);
1489
1490 /* Inject or validate tag. */
1491 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) {
1492 crypto_copyback(crp, crp->crp_digest_start, sizeof(digest),
1493 digest);
1494 error = 0;
1495 } else {
1496 char digest2[GMAC_DIGEST_LEN];
1497
1498 crypto_copydata(crp, crp->crp_digest_start, sizeof(digest2),
1499 digest2);
1500 if (timingsafe_bcmp(digest, digest2, sizeof(digest)) == 0) {
1501 error = 0;
1502
1503 /* Tag matches, decrypt data. */
1504 for (i = 0; i < crp->crp_payload_length;
1505 i += sizeof(block)) {
1506 len = imin(crp->crp_payload_length - i,
1507 sizeof(block));
1508 crypto_copydata(crp, crp->crp_payload_start + i,
1509 len, block);
1510 bzero(block + len, sizeof(block) - len);
1511 exf->decrypt(kschedule, block, block);
1512 crypto_copyback(crp, crp->crp_payload_start + i,
1513 len, block);
1514 }
1515 } else
1516 error = EBADMSG;
1517 explicit_bzero(digest2, sizeof(digest2));
1518 }
1519
1520 out:
1521 zfree(kschedule, M_CCR);
1522 zfree(auth_ctx, M_CCR);
1523 explicit_bzero(block, sizeof(block));
1524 explicit_bzero(digest, sizeof(digest));
1525 crp->crp_etype = error;
1526 crypto_done(crp);
1527 }
1528
1529 static int
ccr_ccm_hmac_ctrl(unsigned int authsize)1530 ccr_ccm_hmac_ctrl(unsigned int authsize)
1531 {
1532 switch (authsize) {
1533 case 4:
1534 return (SCMD_HMAC_CTRL_PL1);
1535 case 6:
1536 return (SCMD_HMAC_CTRL_PL2);
1537 case 8:
1538 return (SCMD_HMAC_CTRL_DIV2);
1539 case 10:
1540 return (SCMD_HMAC_CTRL_TRUNC_RFC4366);
1541 case 12:
1542 return (SCMD_HMAC_CTRL_IPSEC_96BIT);
1543 case 14:
1544 return (SCMD_HMAC_CTRL_PL3);
1545 case 16:
1546 return (SCMD_HMAC_CTRL_NO_TRUNC);
1547 default:
1548 __assert_unreachable();
1549 }
1550 }
1551
1552 static void
generate_ccm_b0(struct cryptop * crp,u_int hash_size_in_response,const char * iv,char * b0)1553 generate_ccm_b0(struct cryptop *crp, u_int hash_size_in_response,
1554 const char *iv, char *b0)
1555 {
1556 u_int i, payload_len, L;
1557
1558 /* NB: L is already set in the first byte of the IV. */
1559 memcpy(b0, iv, CCM_B0_SIZE);
1560 L = iv[0] + 1;
1561
1562 /* Set length of hash in bits 3 - 5. */
1563 b0[0] |= (((hash_size_in_response - 2) / 2) << 3);
1564
1565 /* Store the payload length as a big-endian value. */
1566 payload_len = crp->crp_payload_length;
1567 for (i = 0; i < L; i++) {
1568 b0[CCM_CBC_BLOCK_LEN - 1 - i] = payload_len;
1569 payload_len >>= 8;
1570 }
1571
1572 /*
1573 * If there is AAD in the request, set bit 6 in the flags
1574 * field and store the AAD length as a big-endian value at the
1575 * start of block 1. This only assumes a 16-bit AAD length
1576 * since T6 doesn't support large AAD sizes.
1577 */
1578 if (crp->crp_aad_length != 0) {
1579 b0[0] |= (1 << 6);
1580 *(uint16_t *)(b0 + CCM_B0_SIZE) = htobe16(crp->crp_aad_length);
1581 }
1582 }
1583
1584 static int
ccr_ccm(struct ccr_softc * sc,struct ccr_session * s,struct cryptop * crp)1585 ccr_ccm(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp)
1586 {
1587 char iv[CHCR_MAX_CRYPTO_IV_LEN];
1588 const struct crypto_session_params *csp;
1589 struct ulptx_idata *idata;
1590 struct chcr_wr *crwr;
1591 struct wrqe *wr;
1592 char *dst;
1593 u_int iv_len, kctx_len, op_type, transhdr_len, wr_len;
1594 u_int aad_len, b0_len, hash_size_in_response, imm_len;
1595 u_int aad_start, aad_stop, cipher_start, cipher_stop, auth_insert;
1596 u_int hmac_ctrl, input_len;
1597 int dsgl_nsegs, dsgl_len;
1598 int sgl_nsegs, sgl_len;
1599 int error;
1600
1601 csp = crypto_get_params(crp->crp_session);
1602
1603 if (s->blkcipher.key_len == 0)
1604 return (EINVAL);
1605
1606 /*
1607 * The crypto engine doesn't handle CCM requests with an empty
1608 * payload, so handle those in software instead.
1609 */
1610 if (crp->crp_payload_length == 0)
1611 return (EMSGSIZE);
1612
1613 /* The length has to fit within the length field in block 0. */
1614 if (crp->crp_payload_length > ccm_max_payload_length(csp))
1615 return (EMSGSIZE);
1616
1617 /*
1618 * CCM always includes block 0 in the AAD before AAD from the
1619 * request.
1620 */
1621 b0_len = CCM_B0_SIZE;
1622 if (crp->crp_aad_length != 0)
1623 b0_len += CCM_AAD_FIELD_SIZE;
1624 aad_len = b0_len + crp->crp_aad_length;
1625
1626 /*
1627 * CCM requests should always provide an explicit IV (really
1628 * the nonce).
1629 */
1630 if ((crp->crp_flags & CRYPTO_F_IV_SEPARATE) == 0)
1631 return (EINVAL);
1632
1633 /*
1634 * The IV in the work request is 16 bytes and not just the
1635 * nonce.
1636 */
1637 iv_len = AES_BLOCK_LEN;
1638
1639 if (iv_len + aad_len > MAX_AAD_LEN)
1640 return (EMSGSIZE);
1641
1642 hash_size_in_response = s->ccm_mac.hash_len;
1643 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
1644 op_type = CHCR_ENCRYPT_OP;
1645 else
1646 op_type = CHCR_DECRYPT_OP;
1647
1648 /*
1649 * The output buffer consists of the cipher text followed by
1650 * the tag when encrypting. For decryption it only contains
1651 * the plain text.
1652 *
1653 * Due to a firmware bug, the output buffer must include a
1654 * dummy output buffer for the IV and AAD prior to the real
1655 * output buffer.
1656 */
1657 if (op_type == CHCR_ENCRYPT_OP) {
1658 if (iv_len + aad_len + crp->crp_payload_length +
1659 hash_size_in_response > MAX_REQUEST_SIZE)
1660 return (EFBIG);
1661 } else {
1662 if (iv_len + aad_len + crp->crp_payload_length >
1663 MAX_REQUEST_SIZE)
1664 return (EFBIG);
1665 }
1666 sglist_reset(s->sg_dsgl);
1667 error = sglist_append_sglist(s->sg_dsgl, sc->sg_iv_aad, 0, iv_len +
1668 aad_len);
1669 if (error)
1670 return (error);
1671 if (CRYPTO_HAS_OUTPUT_BUFFER(crp))
1672 error = sglist_append_sglist(s->sg_dsgl, s->sg_output,
1673 crp->crp_payload_output_start, crp->crp_payload_length);
1674 else
1675 error = sglist_append_sglist(s->sg_dsgl, s->sg_input,
1676 crp->crp_payload_start, crp->crp_payload_length);
1677 if (error)
1678 return (error);
1679 if (op_type == CHCR_ENCRYPT_OP) {
1680 if (CRYPTO_HAS_OUTPUT_BUFFER(crp))
1681 error = sglist_append_sglist(s->sg_dsgl, s->sg_output,
1682 crp->crp_digest_start, hash_size_in_response);
1683 else
1684 error = sglist_append_sglist(s->sg_dsgl, s->sg_input,
1685 crp->crp_digest_start, hash_size_in_response);
1686 if (error)
1687 return (error);
1688 }
1689 dsgl_nsegs = ccr_count_sgl(s->sg_dsgl, DSGL_SGE_MAXLEN);
1690 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE)
1691 return (EFBIG);
1692 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs);
1693
1694 /*
1695 * The 'key' part of the key context consists of two copies of
1696 * the AES key.
1697 */
1698 kctx_len = roundup2(s->blkcipher.key_len, 16) * 2;
1699 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len);
1700
1701 /*
1702 * The input buffer consists of the IV, AAD (including block
1703 * 0), and then the cipher/plain text. For decryption
1704 * requests the hash is appended after the cipher text.
1705 *
1706 * The IV is always stored at the start of the input buffer
1707 * even though it may be duplicated in the payload. The
1708 * crypto engine doesn't work properly if the IV offset points
1709 * inside of the AAD region, so a second copy is always
1710 * required.
1711 */
1712 input_len = aad_len + crp->crp_payload_length;
1713 if (op_type == CHCR_DECRYPT_OP)
1714 input_len += hash_size_in_response;
1715 if (input_len > MAX_REQUEST_SIZE)
1716 return (EFBIG);
1717 if (ccr_use_imm_data(transhdr_len, iv_len + input_len)) {
1718 imm_len = input_len;
1719 sgl_nsegs = 0;
1720 sgl_len = 0;
1721 } else {
1722 /* Block 0 is passed as immediate data. */
1723 imm_len = b0_len;
1724
1725 sglist_reset(s->sg_ulptx);
1726 if (crp->crp_aad_length != 0) {
1727 if (crp->crp_aad != NULL)
1728 error = sglist_append(s->sg_ulptx,
1729 crp->crp_aad, crp->crp_aad_length);
1730 else
1731 error = sglist_append_sglist(s->sg_ulptx,
1732 s->sg_input, crp->crp_aad_start,
1733 crp->crp_aad_length);
1734 if (error)
1735 return (error);
1736 }
1737 error = sglist_append_sglist(s->sg_ulptx, s->sg_input,
1738 crp->crp_payload_start, crp->crp_payload_length);
1739 if (error)
1740 return (error);
1741 if (op_type == CHCR_DECRYPT_OP) {
1742 error = sglist_append_sglist(s->sg_ulptx, s->sg_input,
1743 crp->crp_digest_start, hash_size_in_response);
1744 if (error)
1745 return (error);
1746 }
1747 sgl_nsegs = s->sg_ulptx->sg_nseg;
1748 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs);
1749 }
1750
1751 aad_start = iv_len + 1;
1752 aad_stop = aad_start + aad_len - 1;
1753 cipher_start = aad_stop + 1;
1754 if (op_type == CHCR_DECRYPT_OP)
1755 cipher_stop = hash_size_in_response;
1756 else
1757 cipher_stop = 0;
1758 if (op_type == CHCR_DECRYPT_OP)
1759 auth_insert = hash_size_in_response;
1760 else
1761 auth_insert = 0;
1762
1763 wr_len = roundup2(transhdr_len, 16) + iv_len + roundup2(imm_len, 16) +
1764 sgl_len;
1765 if (wr_len > SGE_MAX_WR_LEN)
1766 return (EFBIG);
1767 wr = alloc_wrqe(wr_len, s->port->txq);
1768 if (wr == NULL) {
1769 counter_u64_add(sc->stats_wr_nomem, 1);
1770 return (ENOMEM);
1771 }
1772 crwr = wrtod(wr);
1773 memset(crwr, 0, wr_len);
1774
1775 /*
1776 * Read the nonce from the request. Use the nonce to generate
1777 * the full IV with the counter set to 0.
1778 */
1779 memset(iv, 0, iv_len);
1780 iv[0] = (15 - csp->csp_ivlen) - 1;
1781 crypto_read_iv(crp, iv + 1);
1782
1783 ccr_populate_wreq(sc, s, crwr, kctx_len, wr_len, imm_len, sgl_len, 0,
1784 crp);
1785
1786 crwr->sec_cpl.op_ivinsrtofst = htobe32(
1787 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) |
1788 V_CPL_TX_SEC_PDU_RXCHID(s->port->rx_channel_id) |
1789 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) |
1790 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) |
1791 V_CPL_TX_SEC_PDU_IVINSRTOFST(1));
1792
1793 crwr->sec_cpl.pldlen = htobe32(iv_len + input_len);
1794
1795 /*
1796 * NB: cipherstop is explicitly set to 0. See comments above
1797 * in ccr_gcm().
1798 */
1799 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32(
1800 V_CPL_TX_SEC_PDU_AADSTART(aad_start) |
1801 V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) |
1802 V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) |
1803 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(0));
1804 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32(
1805 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(0) |
1806 V_CPL_TX_SEC_PDU_AUTHSTART(cipher_start) |
1807 V_CPL_TX_SEC_PDU_AUTHSTOP(cipher_stop) |
1808 V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert));
1809
1810 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */
1811 hmac_ctrl = ccr_ccm_hmac_ctrl(hash_size_in_response);
1812 crwr->sec_cpl.seqno_numivs = htobe32(
1813 V_SCMD_SEQ_NO_CTRL(0) |
1814 V_SCMD_PROTO_VERSION(SCMD_PROTO_VERSION_GENERIC) |
1815 V_SCMD_ENC_DEC_CTRL(op_type) |
1816 V_SCMD_CIPH_AUTH_SEQ_CTRL(op_type == CHCR_ENCRYPT_OP ? 0 : 1) |
1817 V_SCMD_CIPH_MODE(SCMD_CIPH_MODE_AES_CCM) |
1818 V_SCMD_AUTH_MODE(SCMD_AUTH_MODE_CBCMAC) |
1819 V_SCMD_HMAC_CTRL(hmac_ctrl) |
1820 V_SCMD_IV_SIZE(iv_len / 2) |
1821 V_SCMD_NUM_IVS(0));
1822 crwr->sec_cpl.ivgen_hdrlen = htobe32(
1823 V_SCMD_IV_GEN_CTRL(0) |
1824 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) |
1825 V_SCMD_AADIVDROP(0) | V_SCMD_HDR_LEN(dsgl_len));
1826
1827 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr;
1828 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, s->blkcipher.key_len);
1829 memcpy(crwr->key_ctx.key + roundup(s->blkcipher.key_len, 16),
1830 s->blkcipher.enckey, s->blkcipher.key_len);
1831
1832 dst = (char *)(crwr + 1) + kctx_len;
1833 ccr_write_phys_dsgl(s, dst, dsgl_nsegs);
1834 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len;
1835 memcpy(dst, iv, iv_len);
1836 dst += iv_len;
1837 generate_ccm_b0(crp, hash_size_in_response, iv, dst);
1838 if (sgl_nsegs == 0) {
1839 dst += b0_len;
1840 if (crp->crp_aad_length != 0) {
1841 if (crp->crp_aad != NULL)
1842 memcpy(dst, crp->crp_aad, crp->crp_aad_length);
1843 else
1844 crypto_copydata(crp, crp->crp_aad_start,
1845 crp->crp_aad_length, dst);
1846 dst += crp->crp_aad_length;
1847 }
1848 crypto_copydata(crp, crp->crp_payload_start,
1849 crp->crp_payload_length, dst);
1850 dst += crp->crp_payload_length;
1851 if (op_type == CHCR_DECRYPT_OP)
1852 crypto_copydata(crp, crp->crp_digest_start,
1853 hash_size_in_response, dst);
1854 } else {
1855 dst += CCM_B0_SIZE;
1856 if (b0_len > CCM_B0_SIZE) {
1857 /*
1858 * If there is AAD, insert padding including a
1859 * ULP_TX_SC_NOOP so that the ULP_TX_SC_DSGL
1860 * is 16-byte aligned.
1861 */
1862 KASSERT(b0_len - CCM_B0_SIZE == CCM_AAD_FIELD_SIZE,
1863 ("b0_len mismatch"));
1864 memset(dst + CCM_AAD_FIELD_SIZE, 0,
1865 8 - CCM_AAD_FIELD_SIZE);
1866 idata = (void *)(dst + 8);
1867 idata->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
1868 idata->len = htobe32(0);
1869 dst = (void *)(idata + 1);
1870 }
1871 ccr_write_ulptx_sgl(s, dst, sgl_nsegs);
1872 }
1873
1874 /* XXX: TODO backpressure */
1875 t4_wrq_tx(sc->adapter, wr);
1876
1877 explicit_bzero(iv, sizeof(iv));
1878 return (0);
1879 }
1880
1881 static int
ccr_ccm_done(struct ccr_softc * sc,struct ccr_session * s,struct cryptop * crp,const struct cpl_fw6_pld * cpl,int error)1882 ccr_ccm_done(struct ccr_softc *sc, struct ccr_session *s,
1883 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error)
1884 {
1885
1886 /*
1887 * The updated IV to permit chained requests is at
1888 * cpl->data[2], but OCF doesn't permit chained requests.
1889 *
1890 * Note that the hardware should always verify the CBC MAC
1891 * hash.
1892 */
1893 return (error);
1894 }
1895
1896 /*
1897 * Handle a CCM request that is not supported by the crypto engine by
1898 * performing the operation in software. Derived from swcr_ccm().
1899 */
1900 static void
build_ccm_b0(const char * nonce,u_int nonce_length,u_int aad_length,u_int data_length,u_int tag_length,uint8_t * b0)1901 build_ccm_b0(const char *nonce, u_int nonce_length, u_int aad_length,
1902 u_int data_length, u_int tag_length, uint8_t *b0)
1903 {
1904 uint8_t *bp;
1905 uint8_t flags, L;
1906
1907 KASSERT(nonce_length >= 7 && nonce_length <= 13,
1908 ("nonce_length must be between 7 and 13 bytes"));
1909
1910 /*
1911 * Need to determine the L field value. This is the number of
1912 * bytes needed to specify the length of the message; the length
1913 * is whatever is left in the 16 bytes after specifying flags and
1914 * the nonce.
1915 */
1916 L = 15 - nonce_length;
1917
1918 flags = ((aad_length > 0) << 6) +
1919 (((tag_length - 2) / 2) << 3) +
1920 L - 1;
1921
1922 /*
1923 * Now we need to set up the first block, which has flags, nonce,
1924 * and the message length.
1925 */
1926 b0[0] = flags;
1927 memcpy(b0 + 1, nonce, nonce_length);
1928 bp = b0 + 1 + nonce_length;
1929
1930 /* Need to copy L' [aka L-1] bytes of data_length */
1931 for (uint8_t *dst = b0 + CCM_CBC_BLOCK_LEN - 1; dst >= bp; dst--) {
1932 *dst = data_length;
1933 data_length >>= 8;
1934 }
1935 }
1936
1937 /* NB: OCF only supports AAD lengths < 2^32. */
1938 static int
build_ccm_aad_length(u_int aad_length,uint8_t * blk)1939 build_ccm_aad_length(u_int aad_length, uint8_t *blk)
1940 {
1941 if (aad_length < ((1 << 16) - (1 << 8))) {
1942 be16enc(blk, aad_length);
1943 return (sizeof(uint16_t));
1944 } else {
1945 blk[0] = 0xff;
1946 blk[1] = 0xfe;
1947 be32enc(blk + 2, aad_length);
1948 return (2 + sizeof(uint32_t));
1949 }
1950 }
1951
1952 static void
ccr_ccm_soft(struct ccr_session * s,struct cryptop * crp)1953 ccr_ccm_soft(struct ccr_session *s, struct cryptop *crp)
1954 {
1955 const struct crypto_session_params *csp;
1956 struct auth_hash *axf;
1957 struct enc_xform *exf;
1958 union authctx *auth_ctx;
1959 void *kschedule;
1960 char block[CCM_CBC_BLOCK_LEN];
1961 char tag[AES_CBC_MAC_HASH_LEN];
1962 u_int taglen;
1963 int error, i, len;
1964
1965 auth_ctx = NULL;
1966 kschedule = NULL;
1967 taglen = s->ccm_mac.hash_len;
1968
1969 csp = crypto_get_params(crp->crp_session);
1970 if (crp->crp_payload_length > ccm_max_payload_length(csp)) {
1971 error = EMSGSIZE;
1972 goto out;
1973 }
1974
1975 /* Initialize the MAC. */
1976 switch (s->blkcipher.key_len) {
1977 case 16:
1978 axf = &auth_hash_ccm_cbc_mac_128;
1979 break;
1980 case 24:
1981 axf = &auth_hash_ccm_cbc_mac_192;
1982 break;
1983 case 32:
1984 axf = &auth_hash_ccm_cbc_mac_256;
1985 break;
1986 default:
1987 error = EINVAL;
1988 goto out;
1989 }
1990 auth_ctx = malloc(axf->ctxsize, M_CCR, M_NOWAIT);
1991 if (auth_ctx == NULL) {
1992 error = ENOMEM;
1993 goto out;
1994 }
1995 axf->Init(auth_ctx);
1996 axf->Setkey(auth_ctx, s->blkcipher.enckey, s->blkcipher.key_len);
1997
1998 /* Initialize the cipher. */
1999 exf = &enc_xform_ccm;
2000 kschedule = malloc(exf->ctxsize, M_CCR, M_NOWAIT);
2001 if (kschedule == NULL) {
2002 error = ENOMEM;
2003 goto out;
2004 }
2005 error = exf->setkey(kschedule, s->blkcipher.enckey,
2006 s->blkcipher.key_len);
2007 if (error)
2008 goto out;
2009
2010 if ((crp->crp_flags & CRYPTO_F_IV_SEPARATE) == 0) {
2011 error = EINVAL;
2012 goto out;
2013 }
2014
2015 axf->Reinit(auth_ctx, crp->crp_iv, csp->csp_ivlen);
2016
2017 /* Supply MAC with b0. */
2018 build_ccm_b0(crp->crp_iv, csp->csp_ivlen, crp->crp_aad_length,
2019 crp->crp_payload_length, taglen, block);
2020 axf->Update(auth_ctx, block, CCM_CBC_BLOCK_LEN);
2021
2022 /* MAC the AAD. */
2023 if (crp->crp_aad_length != 0) {
2024 len = build_ccm_aad_length(crp->crp_aad_length, block);
2025 axf->Update(auth_ctx, block, len);
2026 if (crp->crp_aad != NULL)
2027 axf->Update(auth_ctx, crp->crp_aad,
2028 crp->crp_aad_length);
2029 else
2030 crypto_apply(crp, crp->crp_aad_start,
2031 crp->crp_aad_length, axf->Update, auth_ctx);
2032
2033 /* Pad the AAD (including length field) to a full block. */
2034 len = (len + crp->crp_aad_length) % CCM_CBC_BLOCK_LEN;
2035 if (len != 0) {
2036 len = CCM_CBC_BLOCK_LEN - len;
2037 memset(block, 0, CCM_CBC_BLOCK_LEN);
2038 axf->Update(auth_ctx, block, len);
2039 }
2040 }
2041
2042 exf->reinit(kschedule, crp->crp_iv, csp->csp_ivlen);
2043
2044 /* Do encryption/decryption with MAC */
2045 for (i = 0; i < crp->crp_payload_length; i += sizeof(block)) {
2046 len = imin(crp->crp_payload_length - i, sizeof(block));
2047 crypto_copydata(crp, crp->crp_payload_start + i, len, block);
2048 bzero(block + len, sizeof(block) - len);
2049 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) {
2050 axf->Update(auth_ctx, block, len);
2051 exf->encrypt(kschedule, block, block);
2052 crypto_copyback(crp, crp->crp_payload_start + i, len,
2053 block);
2054 } else {
2055 exf->decrypt(kschedule, block, block);
2056 axf->Update(auth_ctx, block, len);
2057 }
2058 }
2059
2060 /* Finalize MAC. */
2061 axf->Final(tag, auth_ctx);
2062
2063 /* Inject or validate tag. */
2064 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) {
2065 crypto_copyback(crp, crp->crp_digest_start, taglen, tag);
2066 error = 0;
2067 } else {
2068 char tag2[AES_CBC_MAC_HASH_LEN];
2069
2070 crypto_copydata(crp, crp->crp_digest_start, taglen, tag2);
2071 if (timingsafe_bcmp(tag, tag2, taglen) == 0) {
2072 error = 0;
2073
2074 /* Tag matches, decrypt data. */
2075 exf->reinit(kschedule, crp->crp_iv, csp->csp_ivlen);
2076 for (i = 0; i < crp->crp_payload_length;
2077 i += sizeof(block)) {
2078 len = imin(crp->crp_payload_length - i,
2079 sizeof(block));
2080 crypto_copydata(crp, crp->crp_payload_start + i,
2081 len, block);
2082 bzero(block + len, sizeof(block) - len);
2083 exf->decrypt(kschedule, block, block);
2084 crypto_copyback(crp, crp->crp_payload_start + i,
2085 len, block);
2086 }
2087 } else
2088 error = EBADMSG;
2089 explicit_bzero(tag2, sizeof(tag2));
2090 }
2091
2092 out:
2093 zfree(kschedule, M_CCR);
2094 zfree(auth_ctx, M_CCR);
2095 explicit_bzero(block, sizeof(block));
2096 explicit_bzero(tag, sizeof(tag));
2097 crp->crp_etype = error;
2098 crypto_done(crp);
2099 }
2100
2101 static void
ccr_identify(driver_t * driver,device_t parent)2102 ccr_identify(driver_t *driver, device_t parent)
2103 {
2104 struct adapter *sc;
2105
2106 sc = device_get_softc(parent);
2107 if (sc->cryptocaps & FW_CAPS_CONFIG_CRYPTO_LOOKASIDE &&
2108 device_find_child(parent, "ccr", -1) == NULL)
2109 device_add_child(parent, "ccr", -1);
2110 }
2111
2112 static int
ccr_probe(device_t dev)2113 ccr_probe(device_t dev)
2114 {
2115
2116 device_set_desc(dev, "Chelsio Crypto Accelerator");
2117 return (BUS_PROBE_DEFAULT);
2118 }
2119
2120 static void
ccr_sysctls(struct ccr_softc * sc)2121 ccr_sysctls(struct ccr_softc *sc)
2122 {
2123 struct sysctl_ctx_list *ctx = &sc->ctx;
2124 struct sysctl_oid *oid, *port_oid;
2125 struct sysctl_oid_list *children;
2126 char buf[16];
2127 int i;
2128
2129 /*
2130 * dev.ccr.X.
2131 */
2132 oid = device_get_sysctl_tree(sc->dev);
2133 children = SYSCTL_CHILDREN(oid);
2134
2135 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "port_mask", CTLFLAG_RW,
2136 &sc->port_mask, 0, "Mask of enabled ports");
2137
2138 /*
2139 * dev.ccr.X.stats.
2140 */
2141 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats",
2142 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "statistics");
2143 children = SYSCTL_CHILDREN(oid);
2144
2145 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "hash", CTLFLAG_RD,
2146 &sc->stats_hash, "Hash requests submitted");
2147 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "hmac", CTLFLAG_RD,
2148 &sc->stats_hmac, "HMAC requests submitted");
2149 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "cipher_encrypt",
2150 CTLFLAG_RD, &sc->stats_blkcipher_encrypt,
2151 "Cipher encryption requests submitted");
2152 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "cipher_decrypt",
2153 CTLFLAG_RD, &sc->stats_blkcipher_decrypt,
2154 "Cipher decryption requests submitted");
2155 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "eta_encrypt",
2156 CTLFLAG_RD, &sc->stats_eta_encrypt,
2157 "Combined AES+HMAC encryption requests submitted");
2158 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "eta_decrypt",
2159 CTLFLAG_RD, &sc->stats_eta_decrypt,
2160 "Combined AES+HMAC decryption requests submitted");
2161 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "gcm_encrypt",
2162 CTLFLAG_RD, &sc->stats_gcm_encrypt,
2163 "AES-GCM encryption requests submitted");
2164 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "gcm_decrypt",
2165 CTLFLAG_RD, &sc->stats_gcm_decrypt,
2166 "AES-GCM decryption requests submitted");
2167 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ccm_encrypt",
2168 CTLFLAG_RD, &sc->stats_ccm_encrypt,
2169 "AES-CCM encryption requests submitted");
2170 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ccm_decrypt",
2171 CTLFLAG_RD, &sc->stats_ccm_decrypt,
2172 "AES-CCM decryption requests submitted");
2173 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "wr_nomem", CTLFLAG_RD,
2174 &sc->stats_wr_nomem, "Work request memory allocation failures");
2175 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "inflight", CTLFLAG_RD,
2176 &sc->stats_inflight, "Requests currently pending");
2177 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "mac_error", CTLFLAG_RD,
2178 &sc->stats_mac_error, "MAC errors");
2179 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "pad_error", CTLFLAG_RD,
2180 &sc->stats_pad_error, "Padding errors");
2181 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "sglist_error",
2182 CTLFLAG_RD, &sc->stats_sglist_error,
2183 "Requests for which DMA mapping failed");
2184 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "process_error",
2185 CTLFLAG_RD, &sc->stats_process_error,
2186 "Requests failed during queueing");
2187 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "sw_fallback",
2188 CTLFLAG_RD, &sc->stats_sw_fallback,
2189 "Requests processed by falling back to software");
2190
2191 /*
2192 * dev.ccr.X.stats.port
2193 */
2194 port_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "port",
2195 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Per-port statistics");
2196
2197 for (i = 0; i < nitems(sc->ports); i++) {
2198 if (sc->ports[i].rxq == NULL)
2199 continue;
2200
2201 /*
2202 * dev.ccr.X.stats.port.Y
2203 */
2204 snprintf(buf, sizeof(buf), "%d", i);
2205 oid = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(port_oid), OID_AUTO,
2206 buf, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, buf);
2207 children = SYSCTL_CHILDREN(oid);
2208
2209 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "active_sessions",
2210 CTLFLAG_RD, &sc->ports[i].active_sessions, 0,
2211 "Count of active sessions");
2212 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "queued",
2213 CTLFLAG_RD, &sc->ports[i].stats_queued, "Requests queued");
2214 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "completed",
2215 CTLFLAG_RD, &sc->ports[i].stats_completed,
2216 "Requests completed");
2217 }
2218 }
2219
2220 static void
ccr_init_port(struct ccr_softc * sc,int port)2221 ccr_init_port(struct ccr_softc *sc, int port)
2222 {
2223 struct port_info *pi;
2224
2225 pi = sc->adapter->port[port];
2226 sc->ports[port].txq = &sc->adapter->sge.ctrlq[port];
2227 sc->ports[port].rxq = &sc->adapter->sge.rxq[pi->vi->first_rxq];
2228 sc->ports[port].rx_channel_id = pi->rx_c_chan;
2229 sc->ports[port].tx_channel_id = pi->tx_chan;
2230 sc->ports[port].stats_queued = counter_u64_alloc(M_WAITOK);
2231 sc->ports[port].stats_completed = counter_u64_alloc(M_WAITOK);
2232 _Static_assert(sizeof(sc->port_mask) * NBBY >= MAX_NPORTS - 1,
2233 "Too many ports to fit in port_mask");
2234
2235 /*
2236 * Completions for crypto requests on port 1 can sometimes
2237 * return a stale cookie value due to a firmware bug. Disable
2238 * requests on port 1 by default on affected firmware.
2239 */
2240 if (sc->adapter->params.fw_vers >= FW_VERSION32(1, 25, 4, 0) ||
2241 port == 0)
2242 sc->port_mask |= 1u << port;
2243 }
2244
2245 static int
ccr_attach(device_t dev)2246 ccr_attach(device_t dev)
2247 {
2248 struct ccr_softc *sc;
2249 int32_t cid;
2250 int i;
2251
2252 sc = device_get_softc(dev);
2253 sc->dev = dev;
2254 sysctl_ctx_init(&sc->ctx);
2255 sc->adapter = device_get_softc(device_get_parent(dev));
2256 for_each_port(sc->adapter, i) {
2257 ccr_init_port(sc, i);
2258 }
2259 cid = crypto_get_driverid(dev, sizeof(struct ccr_session),
2260 CRYPTOCAP_F_HARDWARE);
2261 if (cid < 0) {
2262 device_printf(dev, "could not get crypto driver id\n");
2263 return (ENXIO);
2264 }
2265 sc->cid = cid;
2266 sc->adapter->ccr_softc = sc;
2267
2268 /*
2269 * The FID must be the first RXQ for port 0 regardless of
2270 * which port is used to service the request.
2271 */
2272 sc->first_rxq_id = sc->adapter->sge.rxq[0].iq.abs_id;
2273
2274 mtx_init(&sc->lock, "ccr", NULL, MTX_DEF);
2275 sc->iv_aad_buf = malloc(MAX_AAD_LEN, M_CCR, M_WAITOK);
2276 sc->sg_iv_aad = sglist_build(sc->iv_aad_buf, MAX_AAD_LEN, M_WAITOK);
2277 sc->stats_blkcipher_encrypt = counter_u64_alloc(M_WAITOK);
2278 sc->stats_blkcipher_decrypt = counter_u64_alloc(M_WAITOK);
2279 sc->stats_hash = counter_u64_alloc(M_WAITOK);
2280 sc->stats_hmac = counter_u64_alloc(M_WAITOK);
2281 sc->stats_eta_encrypt = counter_u64_alloc(M_WAITOK);
2282 sc->stats_eta_decrypt = counter_u64_alloc(M_WAITOK);
2283 sc->stats_gcm_encrypt = counter_u64_alloc(M_WAITOK);
2284 sc->stats_gcm_decrypt = counter_u64_alloc(M_WAITOK);
2285 sc->stats_ccm_encrypt = counter_u64_alloc(M_WAITOK);
2286 sc->stats_ccm_decrypt = counter_u64_alloc(M_WAITOK);
2287 sc->stats_wr_nomem = counter_u64_alloc(M_WAITOK);
2288 sc->stats_inflight = counter_u64_alloc(M_WAITOK);
2289 sc->stats_mac_error = counter_u64_alloc(M_WAITOK);
2290 sc->stats_pad_error = counter_u64_alloc(M_WAITOK);
2291 sc->stats_sglist_error = counter_u64_alloc(M_WAITOK);
2292 sc->stats_process_error = counter_u64_alloc(M_WAITOK);
2293 sc->stats_sw_fallback = counter_u64_alloc(M_WAITOK);
2294 ccr_sysctls(sc);
2295
2296 return (0);
2297 }
2298
2299 static void
ccr_free_port(struct ccr_softc * sc,int port)2300 ccr_free_port(struct ccr_softc *sc, int port)
2301 {
2302
2303 counter_u64_free(sc->ports[port].stats_queued);
2304 counter_u64_free(sc->ports[port].stats_completed);
2305 }
2306
2307 static int
ccr_detach(device_t dev)2308 ccr_detach(device_t dev)
2309 {
2310 struct ccr_softc *sc;
2311 int i;
2312
2313 sc = device_get_softc(dev);
2314
2315 mtx_lock(&sc->lock);
2316 sc->detaching = true;
2317 mtx_unlock(&sc->lock);
2318
2319 crypto_unregister_all(sc->cid);
2320
2321 sysctl_ctx_free(&sc->ctx);
2322 mtx_destroy(&sc->lock);
2323 counter_u64_free(sc->stats_blkcipher_encrypt);
2324 counter_u64_free(sc->stats_blkcipher_decrypt);
2325 counter_u64_free(sc->stats_hash);
2326 counter_u64_free(sc->stats_hmac);
2327 counter_u64_free(sc->stats_eta_encrypt);
2328 counter_u64_free(sc->stats_eta_decrypt);
2329 counter_u64_free(sc->stats_gcm_encrypt);
2330 counter_u64_free(sc->stats_gcm_decrypt);
2331 counter_u64_free(sc->stats_ccm_encrypt);
2332 counter_u64_free(sc->stats_ccm_decrypt);
2333 counter_u64_free(sc->stats_wr_nomem);
2334 counter_u64_free(sc->stats_inflight);
2335 counter_u64_free(sc->stats_mac_error);
2336 counter_u64_free(sc->stats_pad_error);
2337 counter_u64_free(sc->stats_sglist_error);
2338 counter_u64_free(sc->stats_process_error);
2339 counter_u64_free(sc->stats_sw_fallback);
2340 for_each_port(sc->adapter, i) {
2341 ccr_free_port(sc, i);
2342 }
2343 sglist_free(sc->sg_iv_aad);
2344 free(sc->iv_aad_buf, M_CCR);
2345 sc->adapter->ccr_softc = NULL;
2346 return (0);
2347 }
2348
2349 static void
ccr_init_hash_digest(struct ccr_session * s)2350 ccr_init_hash_digest(struct ccr_session *s)
2351 {
2352 union authctx auth_ctx;
2353 struct auth_hash *axf;
2354
2355 axf = s->hmac.auth_hash;
2356 axf->Init(&auth_ctx);
2357 t4_copy_partial_hash(axf->type, &auth_ctx, s->hmac.pads);
2358 }
2359
2360 static bool
ccr_aes_check_keylen(int alg,int klen)2361 ccr_aes_check_keylen(int alg, int klen)
2362 {
2363
2364 switch (klen * 8) {
2365 case 128:
2366 case 192:
2367 if (alg == CRYPTO_AES_XTS)
2368 return (false);
2369 break;
2370 case 256:
2371 break;
2372 case 512:
2373 if (alg != CRYPTO_AES_XTS)
2374 return (false);
2375 break;
2376 default:
2377 return (false);
2378 }
2379 return (true);
2380 }
2381
2382 static void
ccr_aes_setkey(struct ccr_session * s,const void * key,int klen)2383 ccr_aes_setkey(struct ccr_session *s, const void *key, int klen)
2384 {
2385 unsigned int ck_size, iopad_size, kctx_flits, kctx_len, kbits, mk_size;
2386 unsigned int opad_present;
2387
2388 if (s->blkcipher.cipher_mode == SCMD_CIPH_MODE_AES_XTS)
2389 kbits = (klen / 2) * 8;
2390 else
2391 kbits = klen * 8;
2392 switch (kbits) {
2393 case 128:
2394 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128;
2395 break;
2396 case 192:
2397 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192;
2398 break;
2399 case 256:
2400 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256;
2401 break;
2402 default:
2403 panic("should not get here");
2404 }
2405
2406 s->blkcipher.key_len = klen;
2407 memcpy(s->blkcipher.enckey, key, s->blkcipher.key_len);
2408 switch (s->blkcipher.cipher_mode) {
2409 case SCMD_CIPH_MODE_AES_CBC:
2410 case SCMD_CIPH_MODE_AES_XTS:
2411 t4_aes_getdeckey(s->blkcipher.deckey, key, kbits);
2412 break;
2413 }
2414
2415 kctx_len = roundup2(s->blkcipher.key_len, 16);
2416 switch (s->mode) {
2417 case ETA:
2418 mk_size = s->hmac.mk_size;
2419 opad_present = 1;
2420 iopad_size = roundup2(s->hmac.partial_digest_len, 16);
2421 kctx_len += iopad_size * 2;
2422 break;
2423 case GCM:
2424 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_128;
2425 opad_present = 0;
2426 kctx_len += GMAC_BLOCK_LEN;
2427 break;
2428 case CCM:
2429 switch (kbits) {
2430 case 128:
2431 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_128;
2432 break;
2433 case 192:
2434 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_192;
2435 break;
2436 case 256:
2437 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256;
2438 break;
2439 default:
2440 panic("should not get here");
2441 }
2442 opad_present = 0;
2443 kctx_len *= 2;
2444 break;
2445 default:
2446 mk_size = CHCR_KEYCTX_NO_KEY;
2447 opad_present = 0;
2448 break;
2449 }
2450 kctx_flits = (sizeof(struct _key_ctx) + kctx_len) / 16;
2451 s->blkcipher.key_ctx_hdr = htobe32(V_KEY_CONTEXT_CTX_LEN(kctx_flits) |
2452 V_KEY_CONTEXT_DUAL_CK(s->blkcipher.cipher_mode ==
2453 SCMD_CIPH_MODE_AES_XTS) |
2454 V_KEY_CONTEXT_OPAD_PRESENT(opad_present) |
2455 V_KEY_CONTEXT_SALT_PRESENT(1) | V_KEY_CONTEXT_CK_SIZE(ck_size) |
2456 V_KEY_CONTEXT_MK_SIZE(mk_size) | V_KEY_CONTEXT_VALID(1));
2457 }
2458
2459 static bool
ccr_auth_supported(const struct crypto_session_params * csp)2460 ccr_auth_supported(const struct crypto_session_params *csp)
2461 {
2462
2463 switch (csp->csp_auth_alg) {
2464 case CRYPTO_SHA1:
2465 case CRYPTO_SHA2_224:
2466 case CRYPTO_SHA2_256:
2467 case CRYPTO_SHA2_384:
2468 case CRYPTO_SHA2_512:
2469 case CRYPTO_SHA1_HMAC:
2470 case CRYPTO_SHA2_224_HMAC:
2471 case CRYPTO_SHA2_256_HMAC:
2472 case CRYPTO_SHA2_384_HMAC:
2473 case CRYPTO_SHA2_512_HMAC:
2474 break;
2475 default:
2476 return (false);
2477 }
2478 return (true);
2479 }
2480
2481 static bool
ccr_cipher_supported(const struct crypto_session_params * csp)2482 ccr_cipher_supported(const struct crypto_session_params *csp)
2483 {
2484
2485 switch (csp->csp_cipher_alg) {
2486 case CRYPTO_AES_CBC:
2487 if (csp->csp_ivlen != AES_BLOCK_LEN)
2488 return (false);
2489 break;
2490 case CRYPTO_AES_ICM:
2491 if (csp->csp_ivlen != AES_BLOCK_LEN)
2492 return (false);
2493 break;
2494 case CRYPTO_AES_XTS:
2495 if (csp->csp_ivlen != AES_XTS_IV_LEN)
2496 return (false);
2497 break;
2498 default:
2499 return (false);
2500 }
2501 return (ccr_aes_check_keylen(csp->csp_cipher_alg,
2502 csp->csp_cipher_klen));
2503 }
2504
2505 static int
ccr_cipher_mode(const struct crypto_session_params * csp)2506 ccr_cipher_mode(const struct crypto_session_params *csp)
2507 {
2508
2509 switch (csp->csp_cipher_alg) {
2510 case CRYPTO_AES_CBC:
2511 return (SCMD_CIPH_MODE_AES_CBC);
2512 case CRYPTO_AES_ICM:
2513 return (SCMD_CIPH_MODE_AES_CTR);
2514 case CRYPTO_AES_NIST_GCM_16:
2515 return (SCMD_CIPH_MODE_AES_GCM);
2516 case CRYPTO_AES_XTS:
2517 return (SCMD_CIPH_MODE_AES_XTS);
2518 case CRYPTO_AES_CCM_16:
2519 return (SCMD_CIPH_MODE_AES_CCM);
2520 default:
2521 return (SCMD_CIPH_MODE_NOP);
2522 }
2523 }
2524
2525 static int
ccr_probesession(device_t dev,const struct crypto_session_params * csp)2526 ccr_probesession(device_t dev, const struct crypto_session_params *csp)
2527 {
2528 unsigned int cipher_mode;
2529
2530 if ((csp->csp_flags & ~(CSP_F_SEPARATE_OUTPUT | CSP_F_SEPARATE_AAD)) !=
2531 0)
2532 return (EINVAL);
2533 switch (csp->csp_mode) {
2534 case CSP_MODE_DIGEST:
2535 if (!ccr_auth_supported(csp))
2536 return (EINVAL);
2537 break;
2538 case CSP_MODE_CIPHER:
2539 if (!ccr_cipher_supported(csp))
2540 return (EINVAL);
2541 break;
2542 case CSP_MODE_AEAD:
2543 switch (csp->csp_cipher_alg) {
2544 case CRYPTO_AES_NIST_GCM_16:
2545 if (csp->csp_ivlen != AES_GCM_IV_LEN)
2546 return (EINVAL);
2547 if (csp->csp_auth_mlen < 0 ||
2548 csp->csp_auth_mlen > AES_GMAC_HASH_LEN)
2549 return (EINVAL);
2550 break;
2551 case CRYPTO_AES_CCM_16:
2552 break;
2553 default:
2554 return (EINVAL);
2555 }
2556 break;
2557 case CSP_MODE_ETA:
2558 if (!ccr_auth_supported(csp) || !ccr_cipher_supported(csp))
2559 return (EINVAL);
2560 break;
2561 default:
2562 return (EINVAL);
2563 }
2564
2565 if (csp->csp_cipher_klen != 0) {
2566 cipher_mode = ccr_cipher_mode(csp);
2567 if (cipher_mode == SCMD_CIPH_MODE_NOP)
2568 return (EINVAL);
2569 }
2570
2571 return (CRYPTODEV_PROBE_HARDWARE);
2572 }
2573
2574 /*
2575 * Select an available port with the lowest number of active sessions.
2576 */
2577 static struct ccr_port *
ccr_choose_port(struct ccr_softc * sc)2578 ccr_choose_port(struct ccr_softc *sc)
2579 {
2580 struct ccr_port *best, *p;
2581 int i;
2582
2583 mtx_assert(&sc->lock, MA_OWNED);
2584 best = NULL;
2585 for (i = 0; i < nitems(sc->ports); i++) {
2586 p = &sc->ports[i];
2587
2588 /* Ignore non-existent ports. */
2589 if (p->rxq == NULL)
2590 continue;
2591
2592 /*
2593 * XXX: Ignore ports whose queues aren't initialized.
2594 * This is racy as the rxq can be destroyed by the
2595 * associated VI detaching. Eventually ccr should use
2596 * dedicated queues.
2597 */
2598 if (p->rxq->iq.adapter == NULL || p->txq->adapter == NULL)
2599 continue;
2600
2601 if ((sc->port_mask & (1u << i)) == 0)
2602 continue;
2603
2604 if (best == NULL ||
2605 p->active_sessions < best->active_sessions)
2606 best = p;
2607 }
2608 return (best);
2609 }
2610
2611 static void
ccr_delete_session(struct ccr_session * s)2612 ccr_delete_session(struct ccr_session *s)
2613 {
2614 sglist_free(s->sg_input);
2615 sglist_free(s->sg_output);
2616 sglist_free(s->sg_ulptx);
2617 sglist_free(s->sg_dsgl);
2618 mtx_destroy(&s->lock);
2619 }
2620
2621 static int
ccr_newsession(device_t dev,crypto_session_t cses,const struct crypto_session_params * csp)2622 ccr_newsession(device_t dev, crypto_session_t cses,
2623 const struct crypto_session_params *csp)
2624 {
2625 struct ccr_softc *sc;
2626 struct ccr_session *s;
2627 struct auth_hash *auth_hash;
2628 unsigned int auth_mode, cipher_mode, mk_size;
2629 unsigned int partial_digest_len;
2630
2631 switch (csp->csp_auth_alg) {
2632 case CRYPTO_SHA1:
2633 case CRYPTO_SHA1_HMAC:
2634 auth_hash = &auth_hash_hmac_sha1;
2635 auth_mode = SCMD_AUTH_MODE_SHA1;
2636 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_160;
2637 partial_digest_len = SHA1_HASH_LEN;
2638 break;
2639 case CRYPTO_SHA2_224:
2640 case CRYPTO_SHA2_224_HMAC:
2641 auth_hash = &auth_hash_hmac_sha2_224;
2642 auth_mode = SCMD_AUTH_MODE_SHA224;
2643 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256;
2644 partial_digest_len = SHA2_256_HASH_LEN;
2645 break;
2646 case CRYPTO_SHA2_256:
2647 case CRYPTO_SHA2_256_HMAC:
2648 auth_hash = &auth_hash_hmac_sha2_256;
2649 auth_mode = SCMD_AUTH_MODE_SHA256;
2650 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256;
2651 partial_digest_len = SHA2_256_HASH_LEN;
2652 break;
2653 case CRYPTO_SHA2_384:
2654 case CRYPTO_SHA2_384_HMAC:
2655 auth_hash = &auth_hash_hmac_sha2_384;
2656 auth_mode = SCMD_AUTH_MODE_SHA512_384;
2657 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512;
2658 partial_digest_len = SHA2_512_HASH_LEN;
2659 break;
2660 case CRYPTO_SHA2_512:
2661 case CRYPTO_SHA2_512_HMAC:
2662 auth_hash = &auth_hash_hmac_sha2_512;
2663 auth_mode = SCMD_AUTH_MODE_SHA512_512;
2664 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512;
2665 partial_digest_len = SHA2_512_HASH_LEN;
2666 break;
2667 default:
2668 auth_hash = NULL;
2669 auth_mode = SCMD_AUTH_MODE_NOP;
2670 mk_size = 0;
2671 partial_digest_len = 0;
2672 break;
2673 }
2674
2675 cipher_mode = ccr_cipher_mode(csp);
2676
2677 #ifdef INVARIANTS
2678 switch (csp->csp_mode) {
2679 case CSP_MODE_CIPHER:
2680 if (cipher_mode == SCMD_CIPH_MODE_NOP ||
2681 cipher_mode == SCMD_CIPH_MODE_AES_GCM ||
2682 cipher_mode == SCMD_CIPH_MODE_AES_CCM)
2683 panic("invalid cipher algo");
2684 break;
2685 case CSP_MODE_DIGEST:
2686 if (auth_mode == SCMD_AUTH_MODE_NOP)
2687 panic("invalid auth algo");
2688 break;
2689 case CSP_MODE_AEAD:
2690 if (cipher_mode != SCMD_CIPH_MODE_AES_GCM &&
2691 cipher_mode != SCMD_CIPH_MODE_AES_CCM)
2692 panic("invalid aead cipher algo");
2693 if (auth_mode != SCMD_AUTH_MODE_NOP)
2694 panic("invalid aead auth aglo");
2695 break;
2696 case CSP_MODE_ETA:
2697 if (cipher_mode == SCMD_CIPH_MODE_NOP ||
2698 cipher_mode == SCMD_CIPH_MODE_AES_GCM ||
2699 cipher_mode == SCMD_CIPH_MODE_AES_CCM)
2700 panic("invalid cipher algo");
2701 if (auth_mode == SCMD_AUTH_MODE_NOP)
2702 panic("invalid auth algo");
2703 break;
2704 default:
2705 panic("invalid csp mode");
2706 }
2707 #endif
2708
2709 s = crypto_get_driver_session(cses);
2710 mtx_init(&s->lock, "ccr session", NULL, MTX_DEF);
2711 s->sg_input = sglist_alloc(TX_SGL_SEGS, M_NOWAIT);
2712 s->sg_output = sglist_alloc(TX_SGL_SEGS, M_NOWAIT);
2713 s->sg_ulptx = sglist_alloc(TX_SGL_SEGS, M_NOWAIT);
2714 s->sg_dsgl = sglist_alloc(MAX_RX_PHYS_DSGL_SGE, M_NOWAIT);
2715 if (s->sg_input == NULL || s->sg_output == NULL ||
2716 s->sg_ulptx == NULL || s->sg_dsgl == NULL) {
2717 ccr_delete_session(s);
2718 return (ENOMEM);
2719 }
2720
2721 sc = device_get_softc(dev);
2722
2723 mtx_lock(&sc->lock);
2724 if (sc->detaching) {
2725 mtx_unlock(&sc->lock);
2726 ccr_delete_session(s);
2727 return (ENXIO);
2728 }
2729
2730 s->port = ccr_choose_port(sc);
2731 if (s->port == NULL) {
2732 mtx_unlock(&sc->lock);
2733 ccr_delete_session(s);
2734 return (ENXIO);
2735 }
2736
2737 switch (csp->csp_mode) {
2738 case CSP_MODE_AEAD:
2739 if (cipher_mode == SCMD_CIPH_MODE_AES_CCM)
2740 s->mode = CCM;
2741 else
2742 s->mode = GCM;
2743 break;
2744 case CSP_MODE_ETA:
2745 s->mode = ETA;
2746 break;
2747 case CSP_MODE_DIGEST:
2748 if (csp->csp_auth_klen != 0)
2749 s->mode = HMAC;
2750 else
2751 s->mode = HASH;
2752 break;
2753 case CSP_MODE_CIPHER:
2754 s->mode = BLKCIPHER;
2755 break;
2756 }
2757
2758 if (s->mode == GCM) {
2759 if (csp->csp_auth_mlen == 0)
2760 s->gmac.hash_len = AES_GMAC_HASH_LEN;
2761 else
2762 s->gmac.hash_len = csp->csp_auth_mlen;
2763 t4_init_gmac_hash(csp->csp_cipher_key, csp->csp_cipher_klen,
2764 s->gmac.ghash_h);
2765 } else if (s->mode == CCM) {
2766 if (csp->csp_auth_mlen == 0)
2767 s->ccm_mac.hash_len = AES_CBC_MAC_HASH_LEN;
2768 else
2769 s->ccm_mac.hash_len = csp->csp_auth_mlen;
2770 } else if (auth_mode != SCMD_AUTH_MODE_NOP) {
2771 s->hmac.auth_hash = auth_hash;
2772 s->hmac.auth_mode = auth_mode;
2773 s->hmac.mk_size = mk_size;
2774 s->hmac.partial_digest_len = partial_digest_len;
2775 if (csp->csp_auth_mlen == 0)
2776 s->hmac.hash_len = auth_hash->hashsize;
2777 else
2778 s->hmac.hash_len = csp->csp_auth_mlen;
2779 if (csp->csp_auth_key != NULL)
2780 t4_init_hmac_digest(auth_hash, partial_digest_len,
2781 csp->csp_auth_key, csp->csp_auth_klen,
2782 s->hmac.pads);
2783 else
2784 ccr_init_hash_digest(s);
2785 }
2786 if (cipher_mode != SCMD_CIPH_MODE_NOP) {
2787 s->blkcipher.cipher_mode = cipher_mode;
2788 s->blkcipher.iv_len = csp->csp_ivlen;
2789 if (csp->csp_cipher_key != NULL)
2790 ccr_aes_setkey(s, csp->csp_cipher_key,
2791 csp->csp_cipher_klen);
2792 }
2793
2794 s->port->active_sessions++;
2795 mtx_unlock(&sc->lock);
2796 return (0);
2797 }
2798
2799 static void
ccr_freesession(device_t dev,crypto_session_t cses)2800 ccr_freesession(device_t dev, crypto_session_t cses)
2801 {
2802 struct ccr_softc *sc;
2803 struct ccr_session *s;
2804
2805 sc = device_get_softc(dev);
2806 s = crypto_get_driver_session(cses);
2807 #ifdef INVARIANTS
2808 if (s->pending != 0)
2809 device_printf(dev,
2810 "session %p freed with %d pending requests\n", s,
2811 s->pending);
2812 #endif
2813 mtx_lock(&sc->lock);
2814 s->port->active_sessions--;
2815 mtx_unlock(&sc->lock);
2816 ccr_delete_session(s);
2817 }
2818
2819 static int
ccr_process(device_t dev,struct cryptop * crp,int hint)2820 ccr_process(device_t dev, struct cryptop *crp, int hint)
2821 {
2822 const struct crypto_session_params *csp;
2823 struct ccr_softc *sc;
2824 struct ccr_session *s;
2825 int error;
2826
2827 csp = crypto_get_params(crp->crp_session);
2828 s = crypto_get_driver_session(crp->crp_session);
2829 sc = device_get_softc(dev);
2830
2831 mtx_lock(&s->lock);
2832 error = ccr_populate_sglist(s->sg_input, &crp->crp_buf);
2833 if (error == 0 && CRYPTO_HAS_OUTPUT_BUFFER(crp))
2834 error = ccr_populate_sglist(s->sg_output, &crp->crp_obuf);
2835 if (error) {
2836 counter_u64_add(sc->stats_sglist_error, 1);
2837 goto out;
2838 }
2839
2840 switch (s->mode) {
2841 case HASH:
2842 error = ccr_hash(sc, s, crp);
2843 if (error == 0)
2844 counter_u64_add(sc->stats_hash, 1);
2845 break;
2846 case HMAC:
2847 if (crp->crp_auth_key != NULL)
2848 t4_init_hmac_digest(s->hmac.auth_hash,
2849 s->hmac.partial_digest_len, crp->crp_auth_key,
2850 csp->csp_auth_klen, s->hmac.pads);
2851 error = ccr_hash(sc, s, crp);
2852 if (error == 0)
2853 counter_u64_add(sc->stats_hmac, 1);
2854 break;
2855 case BLKCIPHER:
2856 if (crp->crp_cipher_key != NULL)
2857 ccr_aes_setkey(s, crp->crp_cipher_key,
2858 csp->csp_cipher_klen);
2859 error = ccr_blkcipher(sc, s, crp);
2860 if (error == 0) {
2861 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
2862 counter_u64_add(sc->stats_blkcipher_encrypt, 1);
2863 else
2864 counter_u64_add(sc->stats_blkcipher_decrypt, 1);
2865 }
2866 break;
2867 case ETA:
2868 if (crp->crp_auth_key != NULL)
2869 t4_init_hmac_digest(s->hmac.auth_hash,
2870 s->hmac.partial_digest_len, crp->crp_auth_key,
2871 csp->csp_auth_klen, s->hmac.pads);
2872 if (crp->crp_cipher_key != NULL)
2873 ccr_aes_setkey(s, crp->crp_cipher_key,
2874 csp->csp_cipher_klen);
2875 error = ccr_eta(sc, s, crp);
2876 if (error == 0) {
2877 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
2878 counter_u64_add(sc->stats_eta_encrypt, 1);
2879 else
2880 counter_u64_add(sc->stats_eta_decrypt, 1);
2881 }
2882 break;
2883 case GCM:
2884 if (crp->crp_cipher_key != NULL) {
2885 t4_init_gmac_hash(crp->crp_cipher_key,
2886 csp->csp_cipher_klen, s->gmac.ghash_h);
2887 ccr_aes_setkey(s, crp->crp_cipher_key,
2888 csp->csp_cipher_klen);
2889 }
2890 if (crp->crp_payload_length == 0) {
2891 mtx_unlock(&s->lock);
2892 ccr_gcm_soft(s, crp);
2893 return (0);
2894 }
2895 error = ccr_gcm(sc, s, crp);
2896 if (error == EMSGSIZE || error == EFBIG) {
2897 counter_u64_add(sc->stats_sw_fallback, 1);
2898 mtx_unlock(&s->lock);
2899 ccr_gcm_soft(s, crp);
2900 return (0);
2901 }
2902 if (error == 0) {
2903 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
2904 counter_u64_add(sc->stats_gcm_encrypt, 1);
2905 else
2906 counter_u64_add(sc->stats_gcm_decrypt, 1);
2907 }
2908 break;
2909 case CCM:
2910 if (crp->crp_cipher_key != NULL) {
2911 ccr_aes_setkey(s, crp->crp_cipher_key,
2912 csp->csp_cipher_klen);
2913 }
2914 error = ccr_ccm(sc, s, crp);
2915 if (error == EMSGSIZE || error == EFBIG) {
2916 counter_u64_add(sc->stats_sw_fallback, 1);
2917 mtx_unlock(&s->lock);
2918 ccr_ccm_soft(s, crp);
2919 return (0);
2920 }
2921 if (error == 0) {
2922 if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op))
2923 counter_u64_add(sc->stats_ccm_encrypt, 1);
2924 else
2925 counter_u64_add(sc->stats_ccm_decrypt, 1);
2926 }
2927 break;
2928 }
2929
2930 if (error == 0) {
2931 #ifdef INVARIANTS
2932 s->pending++;
2933 #endif
2934 counter_u64_add(sc->stats_inflight, 1);
2935 counter_u64_add(s->port->stats_queued, 1);
2936 } else
2937 counter_u64_add(sc->stats_process_error, 1);
2938
2939 out:
2940 mtx_unlock(&s->lock);
2941
2942 if (error) {
2943 crp->crp_etype = error;
2944 crypto_done(crp);
2945 }
2946
2947 return (0);
2948 }
2949
2950 static int
do_cpl6_fw_pld(struct sge_iq * iq,const struct rss_header * rss,struct mbuf * m)2951 do_cpl6_fw_pld(struct sge_iq *iq, const struct rss_header *rss,
2952 struct mbuf *m)
2953 {
2954 struct ccr_softc *sc = iq->adapter->ccr_softc;
2955 struct ccr_session *s;
2956 const struct cpl_fw6_pld *cpl;
2957 struct cryptop *crp;
2958 uint32_t status;
2959 int error;
2960
2961 if (m != NULL)
2962 cpl = mtod(m, const void *);
2963 else
2964 cpl = (const void *)(rss + 1);
2965
2966 crp = (struct cryptop *)(uintptr_t)be64toh(cpl->data[1]);
2967 s = crypto_get_driver_session(crp->crp_session);
2968 status = be64toh(cpl->data[0]);
2969 if (CHK_MAC_ERR_BIT(status) || CHK_PAD_ERR_BIT(status))
2970 error = EBADMSG;
2971 else
2972 error = 0;
2973
2974 #ifdef INVARIANTS
2975 mtx_lock(&s->lock);
2976 s->pending--;
2977 mtx_unlock(&s->lock);
2978 #endif
2979 counter_u64_add(sc->stats_inflight, -1);
2980 counter_u64_add(s->port->stats_completed, 1);
2981
2982 switch (s->mode) {
2983 case HASH:
2984 case HMAC:
2985 error = ccr_hash_done(sc, s, crp, cpl, error);
2986 break;
2987 case BLKCIPHER:
2988 error = ccr_blkcipher_done(sc, s, crp, cpl, error);
2989 break;
2990 case ETA:
2991 error = ccr_eta_done(sc, s, crp, cpl, error);
2992 break;
2993 case GCM:
2994 error = ccr_gcm_done(sc, s, crp, cpl, error);
2995 break;
2996 case CCM:
2997 error = ccr_ccm_done(sc, s, crp, cpl, error);
2998 break;
2999 }
3000
3001 if (error == EBADMSG) {
3002 if (CHK_MAC_ERR_BIT(status))
3003 counter_u64_add(sc->stats_mac_error, 1);
3004 if (CHK_PAD_ERR_BIT(status))
3005 counter_u64_add(sc->stats_pad_error, 1);
3006 }
3007 crp->crp_etype = error;
3008 crypto_done(crp);
3009 m_freem(m);
3010 return (0);
3011 }
3012
3013 static int
ccr_modevent(module_t mod,int cmd,void * arg)3014 ccr_modevent(module_t mod, int cmd, void *arg)
3015 {
3016
3017 switch (cmd) {
3018 case MOD_LOAD:
3019 t4_register_cpl_handler(CPL_FW6_PLD, do_cpl6_fw_pld);
3020 return (0);
3021 case MOD_UNLOAD:
3022 t4_register_cpl_handler(CPL_FW6_PLD, NULL);
3023 return (0);
3024 default:
3025 return (EOPNOTSUPP);
3026 }
3027 }
3028
3029 static device_method_t ccr_methods[] = {
3030 DEVMETHOD(device_identify, ccr_identify),
3031 DEVMETHOD(device_probe, ccr_probe),
3032 DEVMETHOD(device_attach, ccr_attach),
3033 DEVMETHOD(device_detach, ccr_detach),
3034
3035 DEVMETHOD(cryptodev_probesession, ccr_probesession),
3036 DEVMETHOD(cryptodev_newsession, ccr_newsession),
3037 DEVMETHOD(cryptodev_freesession, ccr_freesession),
3038 DEVMETHOD(cryptodev_process, ccr_process),
3039
3040 DEVMETHOD_END
3041 };
3042
3043 static driver_t ccr_driver = {
3044 "ccr",
3045 ccr_methods,
3046 sizeof(struct ccr_softc)
3047 };
3048
3049 static devclass_t ccr_devclass;
3050
3051 DRIVER_MODULE(ccr, t6nex, ccr_driver, ccr_devclass, ccr_modevent, NULL);
3052 MODULE_VERSION(ccr, 1);
3053 MODULE_DEPEND(ccr, crypto, 1, 1, 1);
3054 MODULE_DEPEND(ccr, t6nex, 1, 1, 1);
3055