1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012 Oleksandr Tymoshenko <[email protected]>
5 * Copyright (c) 2012, 2013 The FreeBSD Foundation
6 * All rights reserved.
7 *
8 * Portions of this software were developed by Oleksandr Rybalko
9 * under sponsorship from the FreeBSD Foundation.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 */
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bio.h>
39 #include <sys/bus.h>
40 #include <sys/conf.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/kthread.h>
44 #include <sys/lock.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/queue.h>
49 #include <sys/resource.h>
50 #include <sys/rman.h>
51 #include <sys/time.h>
52 #include <sys/timetc.h>
53 #include <sys/fbio.h>
54 #include <sys/consio.h>
55 #include <sys/eventhandler.h>
56
57 #include <sys/kdb.h>
58
59 #include <machine/bus.h>
60 #include <machine/resource.h>
61 #include <machine/frame.h>
62 #include <machine/intr.h>
63
64 #include <dev/ofw/ofw_bus.h>
65 #include <dev/ofw/ofw_bus_subr.h>
66
67 #include <dev/vt/vt.h>
68 #include <dev/vt/colors/vt_termcolors.h>
69
70 #include <arm/freescale/imx/imx51_ccmvar.h>
71
72 #include <arm/freescale/imx/imx51_ipuv3reg.h>
73
74 #include "fb_if.h"
75
76 #define IMX51_IPU_HSP_CLOCK 665000000
77
78 struct ipu3sc_softc {
79 device_t dev;
80 device_t sc_fbd; /* fbd child */
81 struct fb_info sc_info;
82
83 bus_space_tag_t iot;
84 bus_space_handle_t ioh;
85 bus_space_handle_t cm_ioh;
86 bus_space_handle_t dp_ioh;
87 bus_space_handle_t di0_ioh;
88 bus_space_handle_t di1_ioh;
89 bus_space_handle_t dctmpl_ioh;
90 bus_space_handle_t dc_ioh;
91 bus_space_handle_t dmfc_ioh;
92 bus_space_handle_t idmac_ioh;
93 bus_space_handle_t cpmem_ioh;
94 };
95
96 static struct ipu3sc_softc *ipu3sc_softc;
97
98 #define IPUV3_READ(ipuv3, module, reg) \
99 bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg))
100 #define IPUV3_WRITE(ipuv3, module, reg, val) \
101 bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val))
102
103 #define CPMEM_CHANNEL_OFFSET(_c) ((_c) * 0x40)
104 #define CPMEM_WORD_OFFSET(_w) ((_w) * 0x20)
105 #define CPMEM_DP_OFFSET(_d) ((_d) * 0x10000)
106 #define IMX_IPU_DP0 0
107 #define IMX_IPU_DP1 1
108 #define CPMEM_CHANNEL(_dp, _ch, _w) \
109 (CPMEM_DP_OFFSET(_dp) + CPMEM_CHANNEL_OFFSET(_ch) + \
110 CPMEM_WORD_OFFSET(_w))
111 #define CPMEM_OFFSET(_dp, _ch, _w, _o) \
112 (CPMEM_CHANNEL((_dp), (_ch), (_w)) + (_o))
113
114 static int ipu3_fb_probe(device_t);
115 static int ipu3_fb_attach(device_t);
116
117 static void
ipu3_fb_init(struct ipu3sc_softc * sc)118 ipu3_fb_init(struct ipu3sc_softc *sc)
119 {
120 uint64_t w0sh96;
121 uint32_t w1sh96;
122
123 /* FW W0[137:125] - 96 = [41:29] */
124 /* FH W0[149:138] - 96 = [53:42] */
125 w0sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 16));
126 w0sh96 <<= 32;
127 w0sh96 |= IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 12));
128
129 sc->sc_info.fb_width = ((w0sh96 >> 29) & 0x1fff) + 1;
130 sc->sc_info.fb_height = ((w0sh96 >> 42) & 0x0fff) + 1;
131
132 /* SLY W1[115:102] - 96 = [19:6] */
133 w1sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 12));
134 sc->sc_info.fb_stride = ((w1sh96 >> 6) & 0x3fff) + 1;
135
136 printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height,
137 sc->sc_info.fb_stride);
138 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride;
139
140 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size,
141 M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0);
142 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase);
143
144 /* DP1 + config_ch_23 + word_2 */
145 IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 0),
146 (((uint32_t)sc->sc_info.fb_pbase >> 3) |
147 (((uint32_t)sc->sc_info.fb_pbase >> 3) << 29)) & 0xffffffff);
148
149 IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 4),
150 (((uint32_t)sc->sc_info.fb_pbase >> 3) >> 3) & 0xffffffff);
151
152 /* XXX: fetch or set it from/to IPU. */
153 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = sc->sc_info.fb_stride /
154 sc->sc_info.fb_width * 8;
155 }
156
157 /* Use own color map, because of different RGB offset. */
158 static int
ipu3_fb_init_cmap(uint32_t * cmap,int bytespp)159 ipu3_fb_init_cmap(uint32_t *cmap, int bytespp)
160 {
161
162 switch (bytespp) {
163 case 8:
164 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB,
165 0x7, 5, 0x7, 2, 0x3, 0));
166 case 15:
167 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB,
168 0x1f, 10, 0x1f, 5, 0x1f, 0));
169 case 16:
170 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB,
171 0x1f, 11, 0x3f, 5, 0x1f, 0));
172 case 24:
173 case 32: /* Ignore alpha. */
174 return (vt_generate_cons_palette(cmap, COLOR_FORMAT_RGB,
175 0xff, 0, 0xff, 8, 0xff, 16));
176 default:
177 return (1);
178 }
179 }
180
181 static int
ipu3_fb_probe(device_t dev)182 ipu3_fb_probe(device_t dev)
183 {
184
185 if (!ofw_bus_status_okay(dev))
186 return (ENXIO);
187
188 if (!ofw_bus_is_compatible(dev, "fsl,ipu3"))
189 return (ENXIO);
190
191 device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)");
192
193 return (BUS_PROBE_DEFAULT);
194 }
195
196 static int
ipu3_fb_attach(device_t dev)197 ipu3_fb_attach(device_t dev)
198 {
199 struct ipu3sc_softc *sc = device_get_softc(dev);
200 bus_space_tag_t iot;
201 bus_space_handle_t ioh;
202 phandle_t node;
203 pcell_t reg;
204 int err;
205 uintptr_t base;
206
207 ipu3sc_softc = sc;
208
209 if (bootverbose)
210 device_printf(dev, "clock gate status is %d\n",
211 imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
212
213 sc->dev = dev;
214
215 sc = device_get_softc(dev);
216 sc->iot = iot = fdtbus_bs_tag;
217
218 /*
219 * Retrieve the device address based on the start address in the
220 * DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register
221 * address, so we just subtract IPU_CM_BASE to get the offset at which
222 * the IPU device was memory mapped.
223 * On i.MX53, the offset is 0.
224 */
225 node = ofw_bus_get_node(dev);
226 if ((OF_getencprop(node, "reg", ®, sizeof(reg))) <= 0)
227 base = 0;
228 else
229 base = reg - IPU_CM_BASE(0);
230 /* map controller registers */
231 err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh);
232 if (err)
233 goto fail_retarn_cm;
234 sc->cm_ioh = ioh;
235
236 /* map Display Multi FIFO Controller registers */
237 err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh);
238 if (err)
239 goto fail_retarn_dmfc;
240 sc->dmfc_ioh = ioh;
241
242 /* map Display Interface 0 registers */
243 err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh);
244 if (err)
245 goto fail_retarn_di0;
246 sc->di0_ioh = ioh;
247
248 /* map Display Interface 1 registers */
249 err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh);
250 if (err)
251 goto fail_retarn_di1;
252 sc->di1_ioh = ioh;
253
254 /* map Display Processor registers */
255 err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh);
256 if (err)
257 goto fail_retarn_dp;
258 sc->dp_ioh = ioh;
259
260 /* map Display Controller registers */
261 err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh);
262 if (err)
263 goto fail_retarn_dc;
264 sc->dc_ioh = ioh;
265
266 /* map Image DMA Controller registers */
267 err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0,
268 &ioh);
269 if (err)
270 goto fail_retarn_idmac;
271 sc->idmac_ioh = ioh;
272
273 /* map CPMEM registers */
274 err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0,
275 &ioh);
276 if (err)
277 goto fail_retarn_cpmem;
278 sc->cpmem_ioh = ioh;
279
280 /* map DCTEMPL registers */
281 err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0,
282 &ioh);
283 if (err)
284 goto fail_retarn_dctmpl;
285 sc->dctmpl_ioh = ioh;
286
287 #ifdef notyet
288 sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO,
289 ipuv3intr, sc);
290 if (sc->ih == NULL) {
291 device_printf(sc->dev,
292 "unable to establish interrupt at irq %d\n",
293 IMX51_INT_IPUV3);
294 return (ENXIO);
295 }
296 #endif
297
298 /*
299 * We have to wait until interrupts are enabled.
300 * Mailbox relies on it to get data from VideoCore
301 */
302 ipu3_fb_init(sc);
303
304 sc->sc_info.fb_name = device_get_nameunit(dev);
305
306 ipu3_fb_init_cmap(sc->sc_info.fb_cmap, sc->sc_info.fb_depth);
307 sc->sc_info.fb_cmsize = 16;
308
309 /* Ask newbus to attach framebuffer device to me. */
310 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev));
311 if (sc->sc_fbd == NULL)
312 device_printf(dev, "Can't attach fbd device\n");
313
314 return (bus_generic_attach(dev));
315
316 fail_retarn_dctmpl:
317 bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE);
318 fail_retarn_cpmem:
319 bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE);
320 fail_retarn_idmac:
321 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE);
322 fail_retarn_dp:
323 bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE);
324 fail_retarn_dc:
325 bus_space_unmap(sc->iot, sc->di1_ioh, IPU_DI1_SIZE);
326 fail_retarn_di1:
327 bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE);
328 fail_retarn_di0:
329 bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE);
330 fail_retarn_dmfc:
331 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE);
332 fail_retarn_cm:
333 device_printf(sc->dev,
334 "failed to map registers (errno=%d)\n", err);
335 return (err);
336 }
337
338 static struct fb_info *
ipu3_fb_getinfo(device_t dev)339 ipu3_fb_getinfo(device_t dev)
340 {
341 struct ipu3sc_softc *sc = device_get_softc(dev);
342
343 return (&sc->sc_info);
344 }
345
346 static device_method_t ipu3_fb_methods[] = {
347 /* Device interface */
348 DEVMETHOD(device_probe, ipu3_fb_probe),
349 DEVMETHOD(device_attach, ipu3_fb_attach),
350
351 /* Framebuffer service methods */
352 DEVMETHOD(fb_getinfo, ipu3_fb_getinfo),
353 { 0, 0 }
354 };
355
356 static devclass_t ipu3_fb_devclass;
357
358 static driver_t ipu3_fb_driver = {
359 "fb",
360 ipu3_fb_methods,
361 sizeof(struct ipu3sc_softc),
362 };
363
364 DRIVER_MODULE(fb, simplebus, ipu3_fb_driver, ipu3_fb_devclass, 0, 0);
365