1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright 2008 Nathan Whitehorn. All rights reserved.
5 * Copyright 2003 by Peter Grehan. All rights reserved.
6 * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * From:
32 * NetBSD: if_bm.c,v 1.9.2.1 2000/11/01 15:02:49 tv Exp
33 */
34
35 /*
36 * BMAC/BMAC+ Macio cell 10/100 ethernet driver
37 * The low-cost, low-feature Apple variant of the Sun HME
38 */
39
40 #include <sys/cdefs.h>
41 __FBSDID("$FreeBSD$");
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sockio.h>
46 #include <sys/endian.h>
47 #include <sys/mbuf.h>
48 #include <sys/module.h>
49 #include <sys/malloc.h>
50 #include <sys/kernel.h>
51 #include <sys/socket.h>
52
53 #include <net/bpf.h>
54 #include <net/if.h>
55 #include <net/if_var.h>
56 #include <net/if_arp.h>
57 #include <net/ethernet.h>
58 #include <net/if_dl.h>
59 #include <net/if_media.h>
60 #include <net/if_types.h>
61
62 #include <machine/pio.h>
63 #include <machine/bus.h>
64 #include <machine/resource.h>
65 #include <sys/bus.h>
66 #include <sys/rman.h>
67
68 #include <dev/mii/mii.h>
69 #include <dev/mii/mii_bitbang.h>
70 #include <dev/mii/miivar.h>
71
72 #include <dev/ofw/ofw_bus.h>
73 #include <dev/ofw/openfirm.h>
74 #include <machine/dbdma.h>
75
76 MODULE_DEPEND(bm, ether, 1, 1, 1);
77 MODULE_DEPEND(bm, miibus, 1, 1, 1);
78
79 /* "controller miibus0" required. See GENERIC if you get errors here. */
80 #include "miibus_if.h"
81
82 #include "if_bmreg.h"
83 #include "if_bmvar.h"
84
85 static int bm_probe (device_t);
86 static int bm_attach (device_t);
87 static int bm_detach (device_t);
88 static int bm_shutdown (device_t);
89
90 static void bm_start (struct ifnet *);
91 static void bm_start_locked (struct ifnet *);
92 static int bm_encap (struct bm_softc *sc, struct mbuf **m_head);
93 static int bm_ioctl (struct ifnet *, u_long, caddr_t);
94 static void bm_init (void *);
95 static void bm_init_locked (struct bm_softc *sc);
96 static void bm_chip_setup (struct bm_softc *sc);
97 static void bm_stop (struct bm_softc *sc);
98 static void bm_setladrf (struct bm_softc *sc);
99 static void bm_dummypacket (struct bm_softc *sc);
100 static void bm_txintr (void *xsc);
101 static void bm_rxintr (void *xsc);
102
103 static int bm_add_rxbuf (struct bm_softc *sc, int i);
104 static int bm_add_rxbuf_dma (struct bm_softc *sc, int i);
105 static void bm_enable_interrupts (struct bm_softc *sc);
106 static void bm_disable_interrupts (struct bm_softc *sc);
107 static void bm_tick (void *xsc);
108
109 static int bm_ifmedia_upd (struct ifnet *);
110 static void bm_ifmedia_sts (struct ifnet *, struct ifmediareq *);
111
112 static int bm_miibus_readreg (device_t, int, int);
113 static int bm_miibus_writereg (device_t, int, int, int);
114 static void bm_miibus_statchg (device_t);
115
116 /*
117 * MII bit-bang glue
118 */
119 static uint32_t bm_mii_bitbang_read(device_t);
120 static void bm_mii_bitbang_write(device_t, uint32_t);
121
122 static const struct mii_bitbang_ops bm_mii_bitbang_ops = {
123 bm_mii_bitbang_read,
124 bm_mii_bitbang_write,
125 {
126 BM_MII_DATAOUT, /* MII_BIT_MDO */
127 BM_MII_DATAIN, /* MII_BIT_MDI */
128 BM_MII_CLK, /* MII_BIT_MDC */
129 BM_MII_OENABLE, /* MII_BIT_DIR_HOST_PHY */
130 0, /* MII_BIT_DIR_PHY_HOST */
131 }
132 };
133
134 static device_method_t bm_methods[] = {
135 /* Device interface */
136 DEVMETHOD(device_probe, bm_probe),
137 DEVMETHOD(device_attach, bm_attach),
138 DEVMETHOD(device_detach, bm_detach),
139 DEVMETHOD(device_shutdown, bm_shutdown),
140
141 /* MII interface */
142 DEVMETHOD(miibus_readreg, bm_miibus_readreg),
143 DEVMETHOD(miibus_writereg, bm_miibus_writereg),
144 DEVMETHOD(miibus_statchg, bm_miibus_statchg),
145
146 DEVMETHOD_END
147 };
148
149 static driver_t bm_macio_driver = {
150 "bm",
151 bm_methods,
152 sizeof(struct bm_softc)
153 };
154
155 static devclass_t bm_devclass;
156
157 DRIVER_MODULE(bm, macio, bm_macio_driver, bm_devclass, 0, 0);
158 DRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0);
159
160 /*
161 * MII internal routines
162 */
163
164 /*
165 * Write the MII serial port for the MII bit-bang module.
166 */
167 static void
bm_mii_bitbang_write(device_t dev,uint32_t val)168 bm_mii_bitbang_write(device_t dev, uint32_t val)
169 {
170 struct bm_softc *sc;
171
172 sc = device_get_softc(dev);
173
174 CSR_WRITE_2(sc, BM_MII_CSR, val);
175 CSR_BARRIER(sc, BM_MII_CSR, 2,
176 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
177 }
178
179 /*
180 * Read the MII serial port for the MII bit-bang module.
181 */
182 static uint32_t
bm_mii_bitbang_read(device_t dev)183 bm_mii_bitbang_read(device_t dev)
184 {
185 struct bm_softc *sc;
186 uint32_t reg;
187
188 sc = device_get_softc(dev);
189
190 reg = CSR_READ_2(sc, BM_MII_CSR);
191 CSR_BARRIER(sc, BM_MII_CSR, 2,
192 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
193
194 return (reg);
195 }
196
197 /*
198 * MII bus i/f
199 */
200 static int
bm_miibus_readreg(device_t dev,int phy,int reg)201 bm_miibus_readreg(device_t dev, int phy, int reg)
202 {
203
204 return (mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg));
205 }
206
207 static int
bm_miibus_writereg(device_t dev,int phy,int reg,int data)208 bm_miibus_writereg(device_t dev, int phy, int reg, int data)
209 {
210
211 mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg);
212
213 return (0);
214 }
215
216 static void
bm_miibus_statchg(device_t dev)217 bm_miibus_statchg(device_t dev)
218 {
219 struct bm_softc *sc = device_get_softc(dev);
220 uint16_t reg;
221 int new_duplex;
222
223 reg = CSR_READ_2(sc, BM_TX_CONFIG);
224 new_duplex = IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX;
225
226 if (new_duplex != sc->sc_duplex) {
227 /* Turn off TX MAC while we fiddle its settings */
228 reg &= ~BM_ENABLE;
229
230 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
231 while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE)
232 DELAY(10);
233 }
234
235 if (new_duplex && !sc->sc_duplex)
236 reg |= BM_TX_IGNORECOLL | BM_TX_FULLDPX;
237 else if (!new_duplex && sc->sc_duplex)
238 reg &= ~(BM_TX_IGNORECOLL | BM_TX_FULLDPX);
239
240 if (new_duplex != sc->sc_duplex) {
241 /* Turn TX MAC back on */
242 reg |= BM_ENABLE;
243
244 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
245 sc->sc_duplex = new_duplex;
246 }
247 }
248
249 /*
250 * ifmedia/mii callbacks
251 */
252 static int
bm_ifmedia_upd(struct ifnet * ifp)253 bm_ifmedia_upd(struct ifnet *ifp)
254 {
255 struct bm_softc *sc = ifp->if_softc;
256 int error;
257
258 BM_LOCK(sc);
259 error = mii_mediachg(sc->sc_mii);
260 BM_UNLOCK(sc);
261 return (error);
262 }
263
264 static void
bm_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifm)265 bm_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifm)
266 {
267 struct bm_softc *sc = ifp->if_softc;
268
269 BM_LOCK(sc);
270 mii_pollstat(sc->sc_mii);
271 ifm->ifm_active = sc->sc_mii->mii_media_active;
272 ifm->ifm_status = sc->sc_mii->mii_media_status;
273 BM_UNLOCK(sc);
274 }
275
276 /*
277 * Macio probe/attach
278 */
279 static int
bm_probe(device_t dev)280 bm_probe(device_t dev)
281 {
282 const char *dname = ofw_bus_get_name(dev);
283 const char *dcompat = ofw_bus_get_compat(dev);
284
285 /*
286 * BMAC+ cells have a name of "ethernet" and
287 * a compatible property of "bmac+"
288 */
289 if (strcmp(dname, "bmac") == 0) {
290 device_set_desc(dev, "Apple BMAC Ethernet Adaptor");
291 } else if (strcmp(dcompat, "bmac+") == 0) {
292 device_set_desc(dev, "Apple BMAC+ Ethernet Adaptor");
293 } else
294 return (ENXIO);
295
296 return (0);
297 }
298
299 static int
bm_attach(device_t dev)300 bm_attach(device_t dev)
301 {
302 phandle_t node;
303 u_char *eaddr;
304 struct ifnet *ifp;
305 int error, cellid, i;
306 struct bm_txsoft *txs;
307 struct bm_softc *sc = device_get_softc(dev);
308
309 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
310 ifp->if_softc = sc;
311 sc->sc_dev = dev;
312 sc->sc_duplex = ~IFM_FDX;
313
314 error = 0;
315 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
316 MTX_DEF);
317 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
318
319 /* Check for an improved version of Paddington */
320 sc->sc_streaming = 0;
321 cellid = -1;
322 node = ofw_bus_get_node(dev);
323
324 OF_getprop(node, "cell-id", &cellid, sizeof(cellid));
325 if (cellid >= 0xc4)
326 sc->sc_streaming = 1;
327
328 sc->sc_memrid = 0;
329 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
330 &sc->sc_memrid, RF_ACTIVE);
331 if (sc->sc_memr == NULL) {
332 device_printf(dev, "Could not alloc chip registers!\n");
333 return (ENXIO);
334 }
335
336 sc->sc_txdmarid = BM_TXDMA_REGISTERS;
337 sc->sc_rxdmarid = BM_RXDMA_REGISTERS;
338
339 sc->sc_txdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
340 &sc->sc_txdmarid, RF_ACTIVE);
341 sc->sc_rxdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
342 &sc->sc_rxdmarid, RF_ACTIVE);
343
344 if (sc->sc_txdmar == NULL || sc->sc_rxdmar == NULL) {
345 device_printf(dev, "Could not map DBDMA registers!\n");
346 return (ENXIO);
347 }
348
349 error = dbdma_allocate_channel(sc->sc_txdmar, 0, bus_get_dma_tag(dev),
350 BM_MAX_DMA_COMMANDS, &sc->sc_txdma);
351 error += dbdma_allocate_channel(sc->sc_rxdmar, 0, bus_get_dma_tag(dev),
352 BM_MAX_DMA_COMMANDS, &sc->sc_rxdma);
353
354 if (error) {
355 device_printf(dev,"Could not allocate DBDMA channel!\n");
356 return (ENXIO);
357 }
358
359 /* alloc DMA tags and buffers */
360 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
361 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
362 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
363 NULL, &sc->sc_pdma_tag);
364
365 if (error) {
366 device_printf(dev,"Could not allocate DMA tag!\n");
367 return (ENXIO);
368 }
369
370 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR,
371 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES,
372 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdma_tag);
373
374 if (error) {
375 device_printf(dev,"Could not allocate RX DMA channel!\n");
376 return (ENXIO);
377 }
378
379 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR,
380 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * BM_NTXSEGS, BM_NTXSEGS,
381 MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdma_tag);
382
383 if (error) {
384 device_printf(dev,"Could not allocate TX DMA tag!\n");
385 return (ENXIO);
386 }
387
388 /* init transmit descriptors */
389 STAILQ_INIT(&sc->sc_txfreeq);
390 STAILQ_INIT(&sc->sc_txdirtyq);
391
392 /* create TX DMA maps */
393 error = ENOMEM;
394 for (i = 0; i < BM_MAX_TX_PACKETS; i++) {
395 txs = &sc->sc_txsoft[i];
396 txs->txs_mbuf = NULL;
397 error = bus_dmamap_create(sc->sc_tdma_tag, 0, &txs->txs_dmamap);
398 if (error) {
399 device_printf(sc->sc_dev,
400 "unable to create TX DMA map %d, error = %d\n",
401 i, error);
402 }
403 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
404 }
405
406 /* Create the receive buffer DMA maps. */
407 for (i = 0; i < BM_MAX_RX_PACKETS; i++) {
408 error = bus_dmamap_create(sc->sc_rdma_tag, 0,
409 &sc->sc_rxsoft[i].rxs_dmamap);
410 if (error) {
411 device_printf(sc->sc_dev,
412 "unable to create RX DMA map %d, error = %d\n",
413 i, error);
414 }
415 sc->sc_rxsoft[i].rxs_mbuf = NULL;
416 }
417
418 /* alloc interrupt */
419 bm_disable_interrupts(sc);
420
421 sc->sc_txdmairqid = BM_TXDMA_INTERRUPT;
422 sc->sc_txdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
423 &sc->sc_txdmairqid, RF_ACTIVE);
424
425 if (error) {
426 device_printf(dev,"Could not allocate TX interrupt!\n");
427 return (ENXIO);
428 }
429
430 bus_setup_intr(dev,sc->sc_txdmairq,
431 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_txintr, sc,
432 &sc->sc_txihtx);
433
434 sc->sc_rxdmairqid = BM_RXDMA_INTERRUPT;
435 sc->sc_rxdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
436 &sc->sc_rxdmairqid, RF_ACTIVE);
437
438 if (error) {
439 device_printf(dev,"Could not allocate RX interrupt!\n");
440 return (ENXIO);
441 }
442
443 bus_setup_intr(dev,sc->sc_rxdmairq,
444 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_rxintr, sc,
445 &sc->sc_rxih);
446
447 /*
448 * Get the ethernet address from OpenFirmware
449 */
450 eaddr = sc->sc_enaddr;
451 OF_getprop(node, "local-mac-address", eaddr, ETHER_ADDR_LEN);
452
453 /*
454 * Setup MII
455 * On Apple BMAC controllers, we end up in a weird state of
456 * partially-completed autonegotiation on boot. So we force
457 * autonegotation to try again.
458 */
459 error = mii_attach(dev, &sc->sc_miibus, ifp, bm_ifmedia_upd,
460 bm_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
461 MIIF_FORCEANEG);
462 if (error != 0) {
463 device_printf(dev, "attaching PHYs failed\n");
464 return (error);
465 }
466
467 /* reset the adapter */
468 bm_chip_setup(sc);
469
470 sc->sc_mii = device_get_softc(sc->sc_miibus);
471
472 if_initname(ifp, device_get_name(sc->sc_dev),
473 device_get_unit(sc->sc_dev));
474 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
475 ifp->if_start = bm_start;
476 ifp->if_ioctl = bm_ioctl;
477 ifp->if_init = bm_init;
478 IFQ_SET_MAXLEN(&ifp->if_snd, BM_MAX_TX_PACKETS);
479 ifp->if_snd.ifq_drv_maxlen = BM_MAX_TX_PACKETS;
480 IFQ_SET_READY(&ifp->if_snd);
481
482 /* Attach the interface. */
483 ether_ifattach(ifp, sc->sc_enaddr);
484 ifp->if_hwassist = 0;
485
486 gone_by_fcp101_dev(dev);
487
488 return (0);
489 }
490
491 static int
bm_detach(device_t dev)492 bm_detach(device_t dev)
493 {
494 struct bm_softc *sc = device_get_softc(dev);
495
496 BM_LOCK(sc);
497 bm_stop(sc);
498 BM_UNLOCK(sc);
499
500 callout_drain(&sc->sc_tick_ch);
501 ether_ifdetach(sc->sc_ifp);
502 bus_teardown_intr(dev, sc->sc_txdmairq, sc->sc_txihtx);
503 bus_teardown_intr(dev, sc->sc_rxdmairq, sc->sc_rxih);
504
505 dbdma_free_channel(sc->sc_txdma);
506 dbdma_free_channel(sc->sc_rxdma);
507
508 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
509 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_txdmarid,
510 sc->sc_txdmar);
511 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rxdmarid,
512 sc->sc_rxdmar);
513
514 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_txdmairqid,
515 sc->sc_txdmairq);
516 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rxdmairqid,
517 sc->sc_rxdmairq);
518
519 mtx_destroy(&sc->sc_mtx);
520 if_free(sc->sc_ifp);
521
522 return (0);
523 }
524
525 static int
bm_shutdown(device_t dev)526 bm_shutdown(device_t dev)
527 {
528 struct bm_softc *sc;
529
530 sc = device_get_softc(dev);
531
532 BM_LOCK(sc);
533 bm_stop(sc);
534 BM_UNLOCK(sc);
535
536 return (0);
537 }
538
539 static void
bm_dummypacket(struct bm_softc * sc)540 bm_dummypacket(struct bm_softc *sc)
541 {
542 struct mbuf *m;
543 struct ifnet *ifp;
544
545 ifp = sc->sc_ifp;
546
547 MGETHDR(m, M_NOWAIT, MT_DATA);
548
549 if (m == NULL)
550 return;
551
552 bcopy(sc->sc_enaddr,
553 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
554 bcopy(sc->sc_enaddr,
555 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
556 mtod(m, struct ether_header *)->ether_type = htons(3);
557 mtod(m, unsigned char *)[14] = 0;
558 mtod(m, unsigned char *)[15] = 0;
559 mtod(m, unsigned char *)[16] = 0xE3;
560 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
561 IF_ENQUEUE(&ifp->if_snd, m);
562 bm_start_locked(ifp);
563 }
564
565 static void
bm_rxintr(void * xsc)566 bm_rxintr(void *xsc)
567 {
568 struct bm_softc *sc = xsc;
569 struct ifnet *ifp = sc->sc_ifp;
570 struct mbuf *m;
571 int i, prev_stop, new_stop;
572 uint16_t status;
573
574 BM_LOCK(sc);
575
576 status = dbdma_get_chan_status(sc->sc_rxdma);
577 if (status & DBDMA_STATUS_DEAD) {
578 dbdma_reset(sc->sc_rxdma);
579 BM_UNLOCK(sc);
580 return;
581 }
582 if (!(status & DBDMA_STATUS_RUN)) {
583 device_printf(sc->sc_dev,"Bad RX Interrupt!\n");
584 BM_UNLOCK(sc);
585 return;
586 }
587
588 prev_stop = sc->next_rxdma_slot - 1;
589 if (prev_stop < 0)
590 prev_stop = sc->rxdma_loop_slot - 1;
591
592 if (prev_stop < 0) {
593 BM_UNLOCK(sc);
594 return;
595 }
596
597 new_stop = -1;
598 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_POSTREAD);
599
600 for (i = sc->next_rxdma_slot; i < BM_MAX_RX_PACKETS; i++) {
601 if (i == sc->rxdma_loop_slot)
602 i = 0;
603
604 if (i == prev_stop)
605 break;
606
607 status = dbdma_get_cmd_status(sc->sc_rxdma, i);
608
609 if (status == 0)
610 break;
611
612 m = sc->sc_rxsoft[i].rxs_mbuf;
613
614 if (bm_add_rxbuf(sc, i)) {
615 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
616 m = NULL;
617 continue;
618 }
619
620 if (m == NULL)
621 continue;
622
623 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
624 m->m_pkthdr.rcvif = ifp;
625 m->m_len -= (dbdma_get_residuals(sc->sc_rxdma, i) + 2);
626 m->m_pkthdr.len = m->m_len;
627
628 /* Send up the stack */
629 BM_UNLOCK(sc);
630 (*ifp->if_input)(ifp, m);
631 BM_LOCK(sc);
632
633 /* Clear all fields on this command */
634 bm_add_rxbuf_dma(sc, i);
635
636 new_stop = i;
637 }
638
639 /* Change the last packet we processed to the ring buffer terminator,
640 * and restore a receive buffer to the old terminator */
641 if (new_stop >= 0) {
642 dbdma_insert_stop(sc->sc_rxdma, new_stop);
643 bm_add_rxbuf_dma(sc, prev_stop);
644 if (i < sc->rxdma_loop_slot)
645 sc->next_rxdma_slot = i;
646 else
647 sc->next_rxdma_slot = 0;
648 }
649 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE);
650
651 dbdma_wake(sc->sc_rxdma);
652
653 BM_UNLOCK(sc);
654 }
655
656 static void
bm_txintr(void * xsc)657 bm_txintr(void *xsc)
658 {
659 struct bm_softc *sc = xsc;
660 struct ifnet *ifp = sc->sc_ifp;
661 struct bm_txsoft *txs;
662 int progress = 0;
663
664 BM_LOCK(sc);
665
666 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
667 if (!dbdma_get_cmd_status(sc->sc_txdma, txs->txs_lastdesc))
668 break;
669
670 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
671 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap);
672
673 if (txs->txs_mbuf != NULL) {
674 m_freem(txs->txs_mbuf);
675 txs->txs_mbuf = NULL;
676 }
677
678 /* Set the first used TXDMA slot to the location of the
679 * STOP/NOP command associated with this packet. */
680
681 sc->first_used_txdma_slot = txs->txs_stopdesc;
682
683 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
684
685 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
686 progress = 1;
687 }
688
689 if (progress) {
690 /*
691 * We freed some descriptors, so reset IFF_DRV_OACTIVE
692 * and restart.
693 */
694 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
695 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5;
696
697 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) &&
698 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
699 bm_start_locked(ifp);
700 }
701
702 BM_UNLOCK(sc);
703 }
704
705 static void
bm_start(struct ifnet * ifp)706 bm_start(struct ifnet *ifp)
707 {
708 struct bm_softc *sc = ifp->if_softc;
709
710 BM_LOCK(sc);
711 bm_start_locked(ifp);
712 BM_UNLOCK(sc);
713 }
714
715 static void
bm_start_locked(struct ifnet * ifp)716 bm_start_locked(struct ifnet *ifp)
717 {
718 struct bm_softc *sc = ifp->if_softc;
719 struct mbuf *mb_head;
720 int prev_stop;
721 int txqueued = 0;
722
723 /*
724 * We lay out our DBDMA program in the following manner:
725 * OUTPUT_MORE
726 * ...
727 * OUTPUT_LAST (+ Interrupt)
728 * STOP
729 *
730 * To extend the channel, we append a new program,
731 * then replace STOP with NOP and wake the channel.
732 * If we stalled on the STOP already, the program proceeds,
733 * if not it will sail through the NOP.
734 */
735
736 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
737 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
738
739 if (mb_head == NULL)
740 break;
741
742 prev_stop = sc->next_txdma_slot - 1;
743
744 if (bm_encap(sc, &mb_head)) {
745 /* Put the packet back and stop */
746 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
747 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
748 break;
749 }
750
751 dbdma_insert_nop(sc->sc_txdma, prev_stop);
752
753 txqueued = 1;
754
755 BPF_MTAP(ifp, mb_head);
756 }
757
758 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE);
759
760 if (txqueued) {
761 dbdma_wake(sc->sc_txdma);
762 sc->sc_wdog_timer = 5;
763 }
764 }
765
766 static int
bm_encap(struct bm_softc * sc,struct mbuf ** m_head)767 bm_encap(struct bm_softc *sc, struct mbuf **m_head)
768 {
769 bus_dma_segment_t segs[BM_NTXSEGS];
770 struct bm_txsoft *txs;
771 struct mbuf *m;
772 int nsegs = BM_NTXSEGS;
773 int error = 0;
774 uint8_t branch_type;
775 int i;
776
777 /* Limit the command size to the number of free DBDMA slots */
778
779 if (sc->next_txdma_slot >= sc->first_used_txdma_slot)
780 nsegs = BM_MAX_DMA_COMMANDS - 2 - sc->next_txdma_slot +
781 sc->first_used_txdma_slot; /* -2 for branch and indexing */
782 else
783 nsegs = sc->first_used_txdma_slot - sc->next_txdma_slot;
784
785 /* Remove one slot for the STOP/NOP terminator */
786 nsegs--;
787
788 if (nsegs > BM_NTXSEGS)
789 nsegs = BM_NTXSEGS;
790
791 /* Get a work queue entry. */
792 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
793 /* Ran out of descriptors. */
794 return (ENOBUFS);
795 }
796
797 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, txs->txs_dmamap,
798 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
799
800 if (error == EFBIG) {
801 m = m_collapse(*m_head, M_NOWAIT, nsegs);
802 if (m == NULL) {
803 m_freem(*m_head);
804 *m_head = NULL;
805 return (ENOBUFS);
806 }
807 *m_head = m;
808
809 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag,
810 txs->txs_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
811 if (error != 0) {
812 m_freem(*m_head);
813 *m_head = NULL;
814 return (error);
815 }
816 } else if (error != 0)
817 return (error);
818
819 if (nsegs == 0) {
820 m_freem(*m_head);
821 *m_head = NULL;
822 return (EIO);
823 }
824
825 txs->txs_ndescs = nsegs;
826 txs->txs_firstdesc = sc->next_txdma_slot;
827
828 for (i = 0; i < nsegs; i++) {
829 /* Loop back to the beginning if this is our last slot */
830 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1))
831 branch_type = DBDMA_ALWAYS;
832 else
833 branch_type = DBDMA_NEVER;
834
835 if (i+1 == nsegs)
836 txs->txs_lastdesc = sc->next_txdma_slot;
837
838 dbdma_insert_command(sc->sc_txdma, sc->next_txdma_slot++,
839 (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE : DBDMA_OUTPUT_LAST,
840 0, segs[i].ds_addr, segs[i].ds_len,
841 (i + 1 < nsegs) ? DBDMA_NEVER : DBDMA_ALWAYS,
842 branch_type, DBDMA_NEVER, 0);
843
844 if (branch_type == DBDMA_ALWAYS)
845 sc->next_txdma_slot = 0;
846 }
847
848 /* We have a corner case where the STOP command is the last slot,
849 * but you can't branch in STOP commands. So add a NOP branch here
850 * and the STOP in slot 0. */
851
852 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) {
853 dbdma_insert_branch(sc->sc_txdma, sc->next_txdma_slot, 0);
854 sc->next_txdma_slot = 0;
855 }
856
857 txs->txs_stopdesc = sc->next_txdma_slot;
858 dbdma_insert_stop(sc->sc_txdma, sc->next_txdma_slot++);
859
860 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
861 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
862 txs->txs_mbuf = *m_head;
863
864 return (0);
865 }
866
867 static int
bm_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)868 bm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
869 {
870 struct bm_softc *sc = ifp->if_softc;
871 struct ifreq *ifr = (struct ifreq *)data;
872 int error;
873
874 error = 0;
875
876 switch(cmd) {
877 case SIOCSIFFLAGS:
878 BM_LOCK(sc);
879 if ((ifp->if_flags & IFF_UP) != 0) {
880 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
881 ((ifp->if_flags ^ sc->sc_ifpflags) &
882 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
883 bm_setladrf(sc);
884 else
885 bm_init_locked(sc);
886 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
887 bm_stop(sc);
888 sc->sc_ifpflags = ifp->if_flags;
889 BM_UNLOCK(sc);
890 break;
891 case SIOCADDMULTI:
892 case SIOCDELMULTI:
893 BM_LOCK(sc);
894 bm_setladrf(sc);
895 BM_UNLOCK(sc);
896 case SIOCGIFMEDIA:
897 case SIOCSIFMEDIA:
898 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
899 break;
900 default:
901 error = ether_ioctl(ifp, cmd, data);
902 break;
903 }
904
905 return (error);
906 }
907
908 static void
bm_setladrf(struct bm_softc * sc)909 bm_setladrf(struct bm_softc *sc)
910 {
911 struct ifnet *ifp = sc->sc_ifp;
912 struct ifmultiaddr *inm;
913 uint16_t hash[4];
914 uint16_t reg;
915 uint32_t crc;
916
917 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS;
918
919 /* Turn off RX MAC while we fiddle its settings */
920 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
921 while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE)
922 DELAY(10);
923
924 if ((ifp->if_flags & IFF_PROMISC) != 0) {
925 reg |= BM_PROMISC;
926
927 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
928
929 DELAY(15);
930
931 reg = CSR_READ_2(sc, BM_RX_CONFIG);
932 reg |= BM_ENABLE;
933 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
934 return;
935 }
936
937 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
938 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
939 } else {
940 /* Clear the hash table. */
941 memset(hash, 0, sizeof(hash));
942
943 if_maddr_rlock(ifp);
944 CK_STAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) {
945 if (inm->ifma_addr->sa_family != AF_LINK)
946 continue;
947 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
948 inm->ifma_addr), ETHER_ADDR_LEN);
949
950 /* We just want the 6 most significant bits */
951 crc >>= 26;
952
953 /* Set the corresponding bit in the filter. */
954 hash[crc >> 4] |= 1 << (crc & 0xf);
955 }
956 if_maddr_runlock(ifp);
957 }
958
959 /* Write out new hash table */
960 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]);
961 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]);
962 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]);
963 CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]);
964
965 /* And turn the RX MAC back on, this time with the hash bit set */
966 reg |= BM_HASH_FILTER_ENABLE;
967 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
968
969 while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE))
970 DELAY(10);
971
972 reg = CSR_READ_2(sc, BM_RX_CONFIG);
973 reg |= BM_ENABLE;
974 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
975 }
976
977 static void
bm_init(void * xsc)978 bm_init(void *xsc)
979 {
980 struct bm_softc *sc = xsc;
981
982 BM_LOCK(sc);
983 bm_init_locked(sc);
984 BM_UNLOCK(sc);
985 }
986
987 static void
bm_chip_setup(struct bm_softc * sc)988 bm_chip_setup(struct bm_softc *sc)
989 {
990 uint16_t reg;
991 uint16_t *eaddr_sect;
992
993 eaddr_sect = (uint16_t *)(sc->sc_enaddr);
994 dbdma_stop(sc->sc_txdma);
995 dbdma_stop(sc->sc_rxdma);
996
997 /* Reset chip */
998 CSR_WRITE_2(sc, BM_RX_RESET, 0x0000);
999 CSR_WRITE_2(sc, BM_TX_RESET, 0x0001);
1000 do {
1001 DELAY(10);
1002 reg = CSR_READ_2(sc, BM_TX_RESET);
1003 } while (reg & 0x0001);
1004
1005 /* Some random junk. OS X uses the system time. We use
1006 * the low 16 bits of the MAC address. */
1007 CSR_WRITE_2(sc, BM_TX_RANDSEED, eaddr_sect[2]);
1008
1009 /* Enable transmit */
1010 reg = CSR_READ_2(sc, BM_TX_IFC);
1011 reg |= BM_ENABLE;
1012 CSR_WRITE_2(sc, BM_TX_IFC, reg);
1013
1014 CSR_READ_2(sc, BM_TX_PEAKCNT);
1015 }
1016
1017 static void
bm_stop(struct bm_softc * sc)1018 bm_stop(struct bm_softc *sc)
1019 {
1020 struct bm_txsoft *txs;
1021 uint16_t reg;
1022
1023 /* Disable TX and RX MACs */
1024 reg = CSR_READ_2(sc, BM_TX_CONFIG);
1025 reg &= ~BM_ENABLE;
1026 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
1027
1028 reg = CSR_READ_2(sc, BM_RX_CONFIG);
1029 reg &= ~BM_ENABLE;
1030 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1031
1032 DELAY(100);
1033
1034 /* Stop DMA engine */
1035 dbdma_stop(sc->sc_rxdma);
1036 dbdma_stop(sc->sc_txdma);
1037 sc->next_rxdma_slot = 0;
1038 sc->rxdma_loop_slot = 0;
1039
1040 /* Disable interrupts */
1041 bm_disable_interrupts(sc);
1042
1043 /* Don't worry about pending transmits anymore */
1044 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1045 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1046 if (txs->txs_ndescs != 0) {
1047 bus_dmamap_sync(sc->sc_tdma_tag, txs->txs_dmamap,
1048 BUS_DMASYNC_POSTWRITE);
1049 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap);
1050 if (txs->txs_mbuf != NULL) {
1051 m_freem(txs->txs_mbuf);
1052 txs->txs_mbuf = NULL;
1053 }
1054 }
1055 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1056 }
1057
1058 /* And we're down */
1059 sc->sc_ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1060 sc->sc_wdog_timer = 0;
1061 callout_stop(&sc->sc_tick_ch);
1062 }
1063
1064 static void
bm_init_locked(struct bm_softc * sc)1065 bm_init_locked(struct bm_softc *sc)
1066 {
1067 uint16_t reg;
1068 uint16_t *eaddr_sect;
1069 struct bm_rxsoft *rxs;
1070 int i;
1071
1072 eaddr_sect = (uint16_t *)(sc->sc_enaddr);
1073
1074 /* Zero RX slot info and stop DMA */
1075 dbdma_stop(sc->sc_rxdma);
1076 dbdma_stop(sc->sc_txdma);
1077 sc->next_rxdma_slot = 0;
1078 sc->rxdma_loop_slot = 0;
1079
1080 /* Initialize TX/RX DBDMA programs */
1081 dbdma_insert_stop(sc->sc_rxdma, 0);
1082 dbdma_insert_stop(sc->sc_txdma, 0);
1083 dbdma_set_current_cmd(sc->sc_rxdma, 0);
1084 dbdma_set_current_cmd(sc->sc_txdma, 0);
1085
1086 sc->next_rxdma_slot = 0;
1087 sc->next_txdma_slot = 1;
1088 sc->first_used_txdma_slot = 0;
1089
1090 for (i = 0; i < BM_MAX_RX_PACKETS; i++) {
1091 rxs = &sc->sc_rxsoft[i];
1092 rxs->dbdma_slot = i;
1093
1094 if (rxs->rxs_mbuf == NULL) {
1095 bm_add_rxbuf(sc, i);
1096
1097 if (rxs->rxs_mbuf == NULL) {
1098 /* If we can't add anymore, mark the problem */
1099 rxs->dbdma_slot = -1;
1100 break;
1101 }
1102 }
1103
1104 if (i > 0)
1105 bm_add_rxbuf_dma(sc, i);
1106 }
1107
1108 /*
1109 * Now terminate the RX ring buffer, and follow with the loop to
1110 * the beginning.
1111 */
1112 dbdma_insert_stop(sc->sc_rxdma, i - 1);
1113 dbdma_insert_branch(sc->sc_rxdma, i, 0);
1114 sc->rxdma_loop_slot = i;
1115
1116 /* Now add in the first element of the RX DMA chain */
1117 bm_add_rxbuf_dma(sc, 0);
1118
1119 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE);
1120 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE);
1121
1122 /* Zero collision counters */
1123 CSR_WRITE_2(sc, BM_TX_NCCNT, 0);
1124 CSR_WRITE_2(sc, BM_TX_FCCNT, 0);
1125 CSR_WRITE_2(sc, BM_TX_EXCNT, 0);
1126 CSR_WRITE_2(sc, BM_TX_LTCNT, 0);
1127
1128 /* Zero receive counters */
1129 CSR_WRITE_2(sc, BM_RX_FRCNT, 0);
1130 CSR_WRITE_2(sc, BM_RX_LECNT, 0);
1131 CSR_WRITE_2(sc, BM_RX_AECNT, 0);
1132 CSR_WRITE_2(sc, BM_RX_FECNT, 0);
1133 CSR_WRITE_2(sc, BM_RXCV, 0);
1134
1135 /* Prime transmit */
1136 CSR_WRITE_2(sc, BM_TX_THRESH, 0xff);
1137
1138 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0);
1139 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001);
1140
1141 /* Prime receive */
1142 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0);
1143 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001);
1144
1145 /* Clear status reg */
1146 CSR_READ_2(sc, BM_STATUS);
1147
1148 /* Zero hash filters */
1149 CSR_WRITE_2(sc, BM_HASHTAB0, 0);
1150 CSR_WRITE_2(sc, BM_HASHTAB1, 0);
1151 CSR_WRITE_2(sc, BM_HASHTAB2, 0);
1152 CSR_WRITE_2(sc, BM_HASHTAB3, 0);
1153
1154 /* Write MAC address to chip */
1155 CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]);
1156 CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]);
1157 CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]);
1158
1159 /* Final receive engine setup */
1160 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS | BM_HASH_FILTER_ENABLE;
1161 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1162
1163 /* Now turn it all on! */
1164 dbdma_reset(sc->sc_rxdma);
1165 dbdma_reset(sc->sc_txdma);
1166
1167 /* Enable RX and TX MACs. Setting the address filter has
1168 * the side effect of enabling the RX MAC. */
1169 bm_setladrf(sc);
1170
1171 reg = CSR_READ_2(sc, BM_TX_CONFIG);
1172 reg |= BM_ENABLE;
1173 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
1174
1175 /*
1176 * Enable interrupts, unwedge the controller with a dummy packet,
1177 * and nudge the DMA queue.
1178 */
1179 bm_enable_interrupts(sc);
1180 bm_dummypacket(sc);
1181 dbdma_wake(sc->sc_rxdma); /* Nudge RXDMA */
1182
1183 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING;
1184 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1185 sc->sc_ifpflags = sc->sc_ifp->if_flags;
1186
1187 /* Resync PHY and MAC states */
1188 sc->sc_mii = device_get_softc(sc->sc_miibus);
1189 sc->sc_duplex = ~IFM_FDX;
1190 mii_mediachg(sc->sc_mii);
1191
1192 /* Start the one second timer. */
1193 sc->sc_wdog_timer = 0;
1194 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc);
1195 }
1196
1197 static void
bm_tick(void * arg)1198 bm_tick(void *arg)
1199 {
1200 struct bm_softc *sc = arg;
1201
1202 /* Read error counters */
1203 if_inc_counter(sc->sc_ifp, IFCOUNTER_COLLISIONS,
1204 CSR_READ_2(sc, BM_TX_NCCNT) + CSR_READ_2(sc, BM_TX_FCCNT) +
1205 CSR_READ_2(sc, BM_TX_EXCNT) + CSR_READ_2(sc, BM_TX_LTCNT));
1206
1207 if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS,
1208 CSR_READ_2(sc, BM_RX_LECNT) + CSR_READ_2(sc, BM_RX_AECNT) +
1209 CSR_READ_2(sc, BM_RX_FECNT));
1210
1211 /* Zero collision counters */
1212 CSR_WRITE_2(sc, BM_TX_NCCNT, 0);
1213 CSR_WRITE_2(sc, BM_TX_FCCNT, 0);
1214 CSR_WRITE_2(sc, BM_TX_EXCNT, 0);
1215 CSR_WRITE_2(sc, BM_TX_LTCNT, 0);
1216
1217 /* Zero receive counters */
1218 CSR_WRITE_2(sc, BM_RX_FRCNT, 0);
1219 CSR_WRITE_2(sc, BM_RX_LECNT, 0);
1220 CSR_WRITE_2(sc, BM_RX_AECNT, 0);
1221 CSR_WRITE_2(sc, BM_RX_FECNT, 0);
1222 CSR_WRITE_2(sc, BM_RXCV, 0);
1223
1224 /* Check for link changes and run watchdog */
1225 mii_tick(sc->sc_mii);
1226 bm_miibus_statchg(sc->sc_dev);
1227
1228 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) {
1229 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc);
1230 return;
1231 }
1232
1233 /* Problems */
1234 device_printf(sc->sc_dev, "device timeout\n");
1235
1236 bm_init_locked(sc);
1237 }
1238
1239 static int
bm_add_rxbuf(struct bm_softc * sc,int idx)1240 bm_add_rxbuf(struct bm_softc *sc, int idx)
1241 {
1242 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx];
1243 struct mbuf *m;
1244 bus_dma_segment_t segs[1];
1245 int error, nsegs;
1246
1247 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1248 if (m == NULL)
1249 return (ENOBUFS);
1250 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1251
1252 if (rxs->rxs_mbuf != NULL) {
1253 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap,
1254 BUS_DMASYNC_POSTREAD);
1255 bus_dmamap_unload(sc->sc_rdma_tag, rxs->rxs_dmamap);
1256 }
1257
1258 error = bus_dmamap_load_mbuf_sg(sc->sc_rdma_tag, rxs->rxs_dmamap, m,
1259 segs, &nsegs, BUS_DMA_NOWAIT);
1260 if (error != 0) {
1261 device_printf(sc->sc_dev,
1262 "cannot load RS DMA map %d, error = %d\n", idx, error);
1263 m_freem(m);
1264 return (error);
1265 }
1266 /* If nsegs is wrong then the stack is corrupt. */
1267 KASSERT(nsegs == 1,
1268 ("%s: too many DMA segments (%d)", __func__, nsegs));
1269 rxs->rxs_mbuf = m;
1270 rxs->segment = segs[0];
1271
1272 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
1273
1274 return (0);
1275 }
1276
1277 static int
bm_add_rxbuf_dma(struct bm_softc * sc,int idx)1278 bm_add_rxbuf_dma(struct bm_softc *sc, int idx)
1279 {
1280 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx];
1281
1282 dbdma_insert_command(sc->sc_rxdma, idx, DBDMA_INPUT_LAST, 0,
1283 rxs->segment.ds_addr, rxs->segment.ds_len, DBDMA_ALWAYS,
1284 DBDMA_NEVER, DBDMA_NEVER, 0);
1285
1286 return (0);
1287 }
1288
1289 static void
bm_enable_interrupts(struct bm_softc * sc)1290 bm_enable_interrupts(struct bm_softc *sc)
1291 {
1292 CSR_WRITE_2(sc, BM_INTR_DISABLE,
1293 (sc->sc_streaming) ? BM_INTR_NONE : BM_INTR_NORMAL);
1294 }
1295
1296 static void
bm_disable_interrupts(struct bm_softc * sc)1297 bm_disable_interrupts(struct bm_softc *sc)
1298 {
1299 CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE);
1300 }
1301