1 /*-
2  * Copyright (c) 2019 Emmanuel Vadot <[email protected]>
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  * 1. Redistributions of source code must retain the above copyright
8  *    notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  *    notice, this list of conditions and the following disclaimer in the
11  *    documentation and/or other materials provided with the distribution.
12  *
13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  */
25 
26 #include <sys/cdefs.h>
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/bus.h>
30 
31 #include <dev/extres/clk/clk.h>
32 
33 #include <arm/allwinner/clkng/aw_clk.h>
34 #include <arm/allwinner/clkng/aw_clk_frac.h>
35 
36 #include "clkdev_if.h"
37 
38 /* #define	dprintf(format, arg...)	printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) */
39 #define	dprintf(format, arg...)
40 
41 /*
42  * clknode for clocks matching the formula :
43  *
44  * clk = (24Mhz * n) / m in integer mode
45  * clk = frac_out1 or frac_out2 in fractional mode
46  *
47  */
48 
49 struct aw_clk_frac_sc {
50 	uint32_t	offset;
51 
52 	struct aw_clk_factor	m;
53 	struct aw_clk_factor	n;
54 	struct aw_clk_frac	frac;
55 
56 	uint64_t		min_freq;
57 	uint64_t		max_freq;
58 
59 	uint32_t	mux_shift;
60 	uint32_t	mux_mask;
61 	uint32_t	gate_shift;
62 	uint32_t	lock_shift;
63 	uint32_t	lock_retries;
64 
65 	uint32_t	flags;
66 };
67 
68 #define	WRITE4(_clk, off, val)						\
69 	CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
70 #define	READ4(_clk, off, val)						\
71 	CLKDEV_READ_4(clknode_get_device(_clk), off, val)
72 #define	DEVICE_LOCK(_clk)							\
73 	CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
74 #define	DEVICE_UNLOCK(_clk)						\
75 	CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
76 
77 static int
aw_clk_frac_init(struct clknode * clk,device_t dev)78 aw_clk_frac_init(struct clknode *clk, device_t dev)
79 {
80 	struct aw_clk_frac_sc *sc;
81 	uint32_t val, idx;
82 
83 	sc = clknode_get_softc(clk);
84 
85 	idx = 0;
86 	if ((sc->flags & AW_CLK_HAS_MUX) != 0) {
87 		DEVICE_LOCK(clk);
88 		READ4(clk, sc->offset, &val);
89 		DEVICE_UNLOCK(clk);
90 
91 		idx = (val & sc->mux_mask) >> sc->mux_shift;
92 	}
93 
94 	dprintf("init parent idx %d\n", idx);
95 	clknode_init_parent_idx(clk, idx);
96 	return (0);
97 }
98 
99 static int
aw_clk_frac_set_gate(struct clknode * clk,bool enable)100 aw_clk_frac_set_gate(struct clknode *clk, bool enable)
101 {
102 	struct aw_clk_frac_sc *sc;
103 	uint32_t val;
104 
105 	sc = clknode_get_softc(clk);
106 
107 	if ((sc->flags & AW_CLK_HAS_GATE) == 0)
108 		return (0);
109 
110 	dprintf("%sabling gate\n", enable ? "En" : "Dis");
111 	DEVICE_LOCK(clk);
112 	READ4(clk, sc->offset, &val);
113 	if (enable)
114 		val |= (1 << sc->gate_shift);
115 	else
116 		val &= ~(1 << sc->gate_shift);
117 	WRITE4(clk, sc->offset, val);
118 	DEVICE_UNLOCK(clk);
119 
120 	return (0);
121 }
122 
123 static int
aw_clk_frac_set_mux(struct clknode * clk,int index)124 aw_clk_frac_set_mux(struct clknode *clk, int index)
125 {
126 	struct aw_clk_frac_sc *sc;
127 	uint32_t val;
128 
129 	sc = clknode_get_softc(clk);
130 
131 	if ((sc->flags & AW_CLK_HAS_MUX) == 0)
132 		return (0);
133 
134 	dprintf("Set mux to %d\n", index);
135 	DEVICE_LOCK(clk);
136 	READ4(clk, sc->offset, &val);
137 	val &= ~sc->mux_mask;
138 	val |= index << sc->mux_shift;
139 	WRITE4(clk, sc->offset, val);
140 	DEVICE_UNLOCK(clk);
141 
142 	return (0);
143 }
144 
145 static uint64_t
aw_clk_frac_find_best(struct aw_clk_frac_sc * sc,uint64_t fparent,uint64_t fout,uint32_t * factor_n,uint32_t * factor_m)146 aw_clk_frac_find_best(struct aw_clk_frac_sc *sc, uint64_t fparent, uint64_t fout,
147     uint32_t *factor_n, uint32_t *factor_m)
148 {
149 	uint64_t cur, best;
150 	uint32_t m, n, max_m, max_n, min_m, min_n;
151 
152 	*factor_n = *factor_m = 0;
153 	best = cur = 0;
154 
155 	max_m = aw_clk_factor_get_max(&sc->m);
156 	max_n = aw_clk_factor_get_max(&sc->n);
157 	min_m = aw_clk_factor_get_min(&sc->m);
158 	min_n = sc->min_freq / fparent;
159 
160 	for (n = min_n; n <= max_n; n++) {
161 		for (m = min_m; m <= max_m; m++) {
162 			cur = fparent * n / m;
163 			if (cur < sc->min_freq) {
164 				continue;
165 			}
166 			if (cur > sc->max_freq) {
167 				continue;
168 			}
169 			if (cur == fout) {
170 				*factor_n = n;
171 				*factor_m = m;
172 				return (cur);
173 			}
174 			if (abs((fout - cur)) < abs((fout - best))) {
175 				best = cur;
176 				*factor_n = n;
177 				*factor_m = m;
178 			}
179 		}
180 	}
181 
182 	return (best);
183 }
184 
185 static int
aw_clk_frac_set_freq(struct clknode * clk,uint64_t fparent,uint64_t * fout,int flags,int * stop)186 aw_clk_frac_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
187     int flags, int *stop)
188 {
189 	struct aw_clk_frac_sc *sc;
190 	uint64_t cur, best, best_frac;
191 	uint32_t val, m, n, best_m, best_n;
192 	int retry, multiple, max_mult, best_mult;
193 
194 	sc = clknode_get_softc(clk);
195 
196 	best = best_frac = cur = 0;
197 	best_mult = 0;
198 	max_mult = 1;
199 
200 	dprintf("Trying to find freq %ju with parent %ju\n", *fout, fparent);
201 	if ((flags & CLK_SET_ROUND_MULTIPLE) != 0)
202 		max_mult = 10;
203 	for (multiple = 1; multiple <= max_mult; multiple++) {
204 		/* First test the fractional frequencies */
205 		dprintf("Testing with multiple %d\n", multiple);
206 		if (*fout * multiple == sc->frac.freq0) {
207 			best = best_frac = sc->frac.freq0;
208 			best_mult = multiple;
209 			dprintf("Found with using frac.freq0 and multiple %d\n", multiple);
210 			break;
211 		}
212 		else if (*fout * multiple == sc->frac.freq1) {
213 			best = best_frac = sc->frac.freq1;
214 			best_mult = multiple;
215 			dprintf("Found with using frac.freq1 and multiple %d\n", multiple);
216 			break;
217 		}
218 		else {
219 			cur = aw_clk_frac_find_best(sc, fparent, *fout * multiple,
220 			  &n, &m);
221 			dprintf("Got %ju with n=%d, m=%d\n", cur, n, m);
222 			if (cur == (*fout * multiple)) {
223 				best = cur;
224 				best_mult = multiple;
225 				best_n = n;
226 				best_m = m;
227 				dprintf("This is the one: n=%d m=%d mult=%d\n", best_n, best_m, best_mult);
228 				break;
229 			}
230 			if (abs(((*fout * multiple) - cur)) < abs(((*fout * multiple) - best))) {
231 				best = cur;
232 				best_mult = multiple;
233 				best_n = n;
234 				best_m = m;
235 				dprintf("This is the best for now: n=%d m=%d mult=%d\n", best_n, best_m, best_mult);
236 			}
237 		}
238 	}
239 
240 	if (best < sc->min_freq ||
241 	    best > sc->max_freq) {
242 		printf("%s: Cannot set %ju for %s (min=%ju max=%ju)\n",
243 		    __func__, best, clknode_get_name(clk),
244 		    sc->min_freq, sc->max_freq);
245 		return (ERANGE);
246 	}
247 	if ((flags & CLK_SET_DRYRUN) != 0) {
248 		*fout = best;
249 		*stop = 1;
250 		return (0);
251 	}
252 
253 	if ((best < (*fout * best_mult)) &&
254 	  ((flags & CLK_SET_ROUND_DOWN) == 0)) {
255 		*stop = 1;
256 		return (ERANGE);
257 	}
258 	if ((best > *fout * best_mult) &&
259 	  ((flags & CLK_SET_ROUND_UP) == 0)) {
260 		*stop = 1;
261 		return (ERANGE);
262 	}
263 
264 	DEVICE_LOCK(clk);
265 	READ4(clk, sc->offset, &val);
266 	/* Disable clock during freq changes */
267 	val &= ~(1 << sc->gate_shift);
268 	WRITE4(clk, sc->offset, val);
269 
270 	if (best_frac != 0) {
271 		val &= ~sc->frac.mode_sel;
272 		/* M should be 0 per the manual */
273 		val &= ~sc->m.mask;
274 		if (best_frac == sc->frac.freq0)
275 			val &= ~sc->frac.freq_sel;
276 		else
277 			val |= sc->frac.freq_sel;
278 	} else {
279 		val |= sc->frac.mode_sel; /* Select integer mode */
280 		n = aw_clk_factor_get_value(&sc->n, best_n);
281 		m = aw_clk_factor_get_value(&sc->m, best_m);
282 		val &= ~sc->n.mask;
283 		val &= ~sc->m.mask;
284 		val |= n << sc->n.shift;
285 		val |= m << sc->m.shift;
286 	}
287 
288 	/* Write the clock changes */
289 	WRITE4(clk, sc->offset, val);
290 
291 	/* Enable clock now that we've change it */
292 	val |= 1 << sc->gate_shift;
293 	WRITE4(clk, sc->offset, val);
294 	DEVICE_UNLOCK(clk);
295 
296 	for (retry = 0; retry < sc->lock_retries; retry++) {
297 		READ4(clk, sc->offset, &val);
298 		if ((val & (1 << sc->lock_shift)) != 0)
299 			break;
300 		DELAY(1000);
301 	}
302 
303 	*fout = best;
304 	*stop = 1;
305 
306 	return (0);
307 }
308 
309 static int
aw_clk_frac_recalc(struct clknode * clk,uint64_t * freq)310 aw_clk_frac_recalc(struct clknode *clk, uint64_t *freq)
311 {
312 	struct aw_clk_frac_sc *sc;
313 	uint32_t val, m, n;
314 
315 	sc = clknode_get_softc(clk);
316 
317 	DEVICE_LOCK(clk);
318 	READ4(clk, sc->offset, &val);
319 	DEVICE_UNLOCK(clk);
320 
321 	if ((val & sc->frac.mode_sel) == 0) {
322 		if (val & sc->frac.freq_sel)
323 			*freq = sc->frac.freq1;
324 		else
325 			*freq = sc->frac.freq0;
326 	} else {
327 		m = aw_clk_get_factor(val, &sc->m);
328 		n = aw_clk_get_factor(val, &sc->n);
329 		*freq = *freq * n / m;
330 	}
331 
332 	return (0);
333 }
334 
335 static clknode_method_t aw_frac_clknode_methods[] = {
336 	/* Device interface */
337 	CLKNODEMETHOD(clknode_init,		aw_clk_frac_init),
338 	CLKNODEMETHOD(clknode_set_gate,		aw_clk_frac_set_gate),
339 	CLKNODEMETHOD(clknode_set_mux,		aw_clk_frac_set_mux),
340 	CLKNODEMETHOD(clknode_recalc_freq,	aw_clk_frac_recalc),
341 	CLKNODEMETHOD(clknode_set_freq,		aw_clk_frac_set_freq),
342 	CLKNODEMETHOD_END
343 };
344 
345 DEFINE_CLASS_1(aw_frac_clknode, aw_frac_clknode_class, aw_frac_clknode_methods,
346     sizeof(struct aw_clk_frac_sc), clknode_class);
347 
348 int
aw_clk_frac_register(struct clkdom * clkdom,struct aw_clk_frac_def * clkdef)349 aw_clk_frac_register(struct clkdom *clkdom, struct aw_clk_frac_def *clkdef)
350 {
351 	struct clknode *clk;
352 	struct aw_clk_frac_sc *sc;
353 
354 	clk = clknode_create(clkdom, &aw_frac_clknode_class, &clkdef->clkdef);
355 	if (clk == NULL)
356 		return (1);
357 
358 	sc = clknode_get_softc(clk);
359 
360 	sc->offset = clkdef->offset;
361 
362 	sc->m.shift = clkdef->m.shift;
363 	sc->m.width = clkdef->m.width;
364 	sc->m.mask = ((1 << sc->m.width) - 1) << sc->m.shift;
365 	sc->m.value = clkdef->m.value;
366 	sc->m.flags = clkdef->m.flags;
367 
368 	sc->n.shift = clkdef->n.shift;
369 	sc->n.width = clkdef->n.width;
370 	sc->n.mask = ((1 << sc->n.width) - 1) << sc->n.shift;
371 	sc->n.value = clkdef->n.value;
372 	sc->n.flags = clkdef->n.flags;
373 
374 	sc->frac.freq0 = clkdef->frac.freq0;
375 	sc->frac.freq1 = clkdef->frac.freq1;
376 	sc->frac.mode_sel = 1 << clkdef->frac.mode_sel;
377 	sc->frac.freq_sel = 1 << clkdef->frac.freq_sel;
378 
379 	sc->min_freq = clkdef->min_freq;
380 	sc->max_freq = clkdef->max_freq;
381 
382 	sc->mux_shift = clkdef->mux_shift;
383 	sc->mux_mask = ((1 << clkdef->mux_width) - 1) << sc->mux_shift;
384 
385 	sc->gate_shift = clkdef->gate_shift;
386 
387 	sc->lock_shift = clkdef->lock_shift;
388 	sc->lock_retries = clkdef->lock_retries;
389 
390 	sc->flags = clkdef->flags;
391 
392 	clknode_register(clkdom, clk);
393 
394 	return (0);
395 }
396