1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019 Emmanuel Vadot <[email protected]>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32
33 #include <dev/extres/clk/clk.h>
34
35 #include <arm/allwinner/clkng/aw_clk.h>
36 #include <arm/allwinner/clkng/aw_clk_nmm.h>
37
38 #include "clkdev_if.h"
39
40 /*
41 * clknode for clocks matching the formula :
42 *
43 * clk = clkin * n / m0 / m1
44 *
45 */
46
47 struct aw_clk_nmm_sc {
48 uint32_t offset;
49
50 struct aw_clk_factor n;
51 struct aw_clk_factor m0;
52 struct aw_clk_factor m1;
53
54 uint32_t gate_shift;
55 uint32_t lock_shift;
56 uint32_t lock_retries;
57
58 uint32_t flags;
59 };
60
61 #define WRITE4(_clk, off, val) \
62 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
63 #define READ4(_clk, off, val) \
64 CLKDEV_READ_4(clknode_get_device(_clk), off, val)
65 #define DEVICE_LOCK(_clk) \
66 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
67 #define DEVICE_UNLOCK(_clk) \
68 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
69
70 static int
aw_clk_nmm_init(struct clknode * clk,device_t dev)71 aw_clk_nmm_init(struct clknode *clk, device_t dev)
72 {
73
74 clknode_init_parent_idx(clk, 0);
75 return (0);
76 }
77
78 static int
aw_clk_nmm_set_gate(struct clknode * clk,bool enable)79 aw_clk_nmm_set_gate(struct clknode *clk, bool enable)
80 {
81 struct aw_clk_nmm_sc *sc;
82 uint32_t val;
83
84 sc = clknode_get_softc(clk);
85
86 if ((sc->flags & AW_CLK_HAS_GATE) == 0)
87 return (0);
88
89 DEVICE_LOCK(clk);
90 READ4(clk, sc->offset, &val);
91 if (enable)
92 val |= (1 << sc->gate_shift);
93 else
94 val &= ~(1 << sc->gate_shift);
95 WRITE4(clk, sc->offset, val);
96 DEVICE_UNLOCK(clk);
97
98 return (0);
99 }
100
101 static uint64_t
aw_clk_nmm_find_best(struct aw_clk_nmm_sc * sc,uint64_t fparent,uint64_t * fout,uint32_t * factor_n,uint32_t * factor_m0,uint32_t * factor_m1)102 aw_clk_nmm_find_best(struct aw_clk_nmm_sc *sc, uint64_t fparent, uint64_t *fout,
103 uint32_t *factor_n, uint32_t *factor_m0, uint32_t *factor_m1)
104 {
105 uint64_t cur, best;
106 uint32_t n, m0, m1;
107 uint32_t max_n, max_m0, max_m1;
108 uint32_t min_n, min_m0, min_m1;
109
110 *factor_n = *factor_m0 = *factor_m1 = 0;
111
112 max_n = aw_clk_factor_get_max(&sc->n);
113 min_n = aw_clk_factor_get_min(&sc->n);
114 max_m0 = aw_clk_factor_get_max(&sc->m0);
115 min_m0 = aw_clk_factor_get_min(&sc->m0);
116 max_m1 = aw_clk_factor_get_max(&sc->m1);
117 min_m1 = aw_clk_factor_get_min(&sc->m1);
118
119 for (m0 = min_m0; m0 <= max_m0; ) {
120 for (m1 = min_m1; m1 <= max_m1; ) {
121 for (n = min_n; n <= max_n; ) {
122 cur = fparent * n / m0 / m1;
123 if (abs(*fout - cur) < abs(*fout - best)) {
124 best = cur;
125 *factor_n = n;
126 *factor_m0 = m0;
127 *factor_m1 = m1;
128 }
129 n++;
130 }
131 m1++;
132 }
133 m0++;
134 }
135
136 return (best);
137 }
138
139 static int
aw_clk_nmm_set_freq(struct clknode * clk,uint64_t fparent,uint64_t * fout,int flags,int * stop)140 aw_clk_nmm_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
141 int flags, int *stop)
142 {
143 struct aw_clk_nmm_sc *sc;
144 uint64_t cur, best;
145 uint32_t val, n, m0, m1, best_n, best_m0, best_m1;
146 int retry;
147
148 sc = clknode_get_softc(clk);
149
150 best = cur = 0;
151
152 best = aw_clk_nmm_find_best(sc, fparent, fout,
153 &best_n, &best_m0, &best_m1);
154
155 if ((flags & CLK_SET_DRYRUN) != 0) {
156 *fout = best;
157 *stop = 1;
158 return (0);
159 }
160
161 if ((best < *fout) &&
162 ((flags & CLK_SET_ROUND_DOWN) == 0)) {
163 *stop = 1;
164 return (ERANGE);
165 }
166 if ((best > *fout) &&
167 ((flags & CLK_SET_ROUND_UP) == 0)) {
168 *stop = 1;
169 return (ERANGE);
170 }
171
172 DEVICE_LOCK(clk);
173 READ4(clk, sc->offset, &val);
174
175 n = aw_clk_factor_get_value(&sc->n, best_n);
176 m0 = aw_clk_factor_get_value(&sc->m0, best_m0);
177 m1 = aw_clk_factor_get_value(&sc->m1, best_m1);
178 val &= ~sc->n.mask;
179 val &= ~sc->m0.mask;
180 val &= ~sc->m1.mask;
181 val |= n << sc->n.shift;
182 val |= m0 << sc->m0.shift;
183 val |= m1 << sc->m1.shift;
184
185 WRITE4(clk, sc->offset, val);
186 DEVICE_UNLOCK(clk);
187
188 if ((sc->flags & AW_CLK_HAS_LOCK) != 0) {
189 for (retry = 0; retry < sc->lock_retries; retry++) {
190 READ4(clk, sc->offset, &val);
191 if ((val & (1 << sc->lock_shift)) != 0)
192 break;
193 DELAY(1000);
194 }
195 }
196
197 *fout = best;
198 *stop = 1;
199
200 return (0);
201 }
202
203 static int
aw_clk_nmm_recalc(struct clknode * clk,uint64_t * freq)204 aw_clk_nmm_recalc(struct clknode *clk, uint64_t *freq)
205 {
206 struct aw_clk_nmm_sc *sc;
207 uint32_t val, n, m0, m1;
208
209 sc = clknode_get_softc(clk);
210
211 DEVICE_LOCK(clk);
212 READ4(clk, sc->offset, &val);
213 DEVICE_UNLOCK(clk);
214
215 n = aw_clk_get_factor(val, &sc->n);
216 m0 = aw_clk_get_factor(val, &sc->m0);
217 m1 = aw_clk_get_factor(val, &sc->m1);
218
219 *freq = *freq * n / m0 / m1;
220
221 return (0);
222 }
223
224 static clknode_method_t aw_nmm_clknode_methods[] = {
225 /* Device interface */
226 CLKNODEMETHOD(clknode_init, aw_clk_nmm_init),
227 CLKNODEMETHOD(clknode_set_gate, aw_clk_nmm_set_gate),
228 CLKNODEMETHOD(clknode_recalc_freq, aw_clk_nmm_recalc),
229 CLKNODEMETHOD(clknode_set_freq, aw_clk_nmm_set_freq),
230 CLKNODEMETHOD_END
231 };
232
233 DEFINE_CLASS_1(aw_nmm_clknode, aw_nmm_clknode_class, aw_nmm_clknode_methods,
234 sizeof(struct aw_clk_nmm_sc), clknode_class);
235
236 int
aw_clk_nmm_register(struct clkdom * clkdom,struct aw_clk_nmm_def * clkdef)237 aw_clk_nmm_register(struct clkdom *clkdom, struct aw_clk_nmm_def *clkdef)
238 {
239 struct clknode *clk;
240 struct aw_clk_nmm_sc *sc;
241
242 clk = clknode_create(clkdom, &aw_nmm_clknode_class, &clkdef->clkdef);
243 if (clk == NULL)
244 return (1);
245
246 sc = clknode_get_softc(clk);
247
248 sc->offset = clkdef->offset;
249
250 sc->n.shift = clkdef->n.shift;
251 sc->n.width = clkdef->n.width;
252 sc->n.mask = ((1 << sc->n.width) - 1) << sc->n.shift;
253 sc->n.value = clkdef->n.value;
254 sc->n.flags = clkdef->n.flags;
255
256 sc->m0.shift = clkdef->m0.shift;
257 sc->m0.width = clkdef->m0.width;
258 sc->m0.mask = ((1 << sc->m0.width) - 1) << sc->m0.shift;
259 sc->m0.value = clkdef->m0.value;
260 sc->m0.flags = clkdef->m0.flags;
261
262 sc->m1.shift = clkdef->m1.shift;
263 sc->m1.width = clkdef->m1.width;
264 sc->m1.mask = ((1 << sc->m1.width) - 1) << sc->m1.shift;
265 sc->m1.value = clkdef->m1.value;
266 sc->m1.flags = clkdef->m1.flags;
267
268 sc->gate_shift = clkdef->gate_shift;
269
270 sc->lock_shift = clkdef->lock_shift;
271 sc->lock_retries = clkdef->lock_retries;
272
273 sc->flags = clkdef->flags;
274
275 clknode_register(clkdom, clk);
276
277 return (0);
278 }
279