1 /*-
2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 #include "opt_rss.h"
29 #include "opt_ratelimit.h"
30
31 #include <dev/mlx5/driver.h>
32 #include <linux/module.h>
33 #include <dev/mlx5/mlx5_core/mlx5_core.h>
34
mlx5_cmd_query_adapter(struct mlx5_core_dev * dev,u32 * out,int outlen)35 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out,
36 int outlen)
37 {
38 u32 in[MLX5_ST_SZ_DW(query_adapter_in)];
39 int err;
40
41 memset(in, 0, sizeof(in));
42
43 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
44
45 err = mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
46 return err;
47 }
48
mlx5_query_board_id(struct mlx5_core_dev * dev)49 int mlx5_query_board_id(struct mlx5_core_dev *dev)
50 {
51 u32 *out;
52 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
53 int err;
54
55 out = kzalloc(outlen, GFP_KERNEL);
56
57 err = mlx5_cmd_query_adapter(dev, out, outlen);
58 if (err)
59 goto out_out;
60
61 memcpy(dev->board_id,
62 MLX5_ADDR_OF(query_adapter_out, out,
63 query_adapter_struct.vsd_contd_psid),
64 MLX5_FLD_SZ_BYTES(query_adapter_out,
65 query_adapter_struct.vsd_contd_psid));
66
67 out_out:
68 kfree(out);
69
70 return err;
71 }
72
mlx5_core_query_vendor_id(struct mlx5_core_dev * mdev,u32 * vendor_id)73 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
74 {
75 u32 *out;
76 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
77 int err;
78
79 out = kzalloc(outlen, GFP_KERNEL);
80
81 err = mlx5_cmd_query_adapter(mdev, out, outlen);
82 if (err)
83 goto out_out;
84
85 *vendor_id = MLX5_GET(query_adapter_out, out,
86 query_adapter_struct.ieee_vendor_id);
87
88 out_out:
89 kfree(out);
90
91 return err;
92 }
93 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
94
mlx5_core_query_special_contexts(struct mlx5_core_dev * dev)95 static int mlx5_core_query_special_contexts(struct mlx5_core_dev *dev)
96 {
97 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)];
98 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)];
99 int err;
100
101 memset(in, 0, sizeof(in));
102 memset(out, 0, sizeof(out));
103
104 MLX5_SET(query_special_contexts_in, in, opcode,
105 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS);
106 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
107 if (err)
108 return err;
109
110 dev->special_contexts.resd_lkey = MLX5_GET(query_special_contexts_out,
111 out, resd_lkey);
112
113 return err;
114 }
115
mlx5_get_qcam_reg(struct mlx5_core_dev * dev)116 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
117 {
118 return mlx5_query_qcam_reg(dev, dev->caps.qcam,
119 MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
120 MLX5_QCAM_REGS_FIRST_128);
121 }
122
mlx5_get_pcam_reg(struct mlx5_core_dev * dev)123 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
124 {
125 return mlx5_query_pcam_reg(dev, dev->caps.pcam,
126 MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
127 MLX5_PCAM_REGS_5000_TO_507F);
128 }
129
mlx5_get_mcam_reg(struct mlx5_core_dev * dev)130 static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
131 {
132 return mlx5_query_mcam_reg(dev, dev->caps.mcam,
133 MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
134 MLX5_MCAM_REGS_FIRST_128);
135 }
136
mlx5_query_hca_caps(struct mlx5_core_dev * dev)137 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
138 {
139 int err;
140
141 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
142 if (err)
143 return err;
144
145 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
146 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS);
147 if (err)
148 return err;
149 }
150
151 if (MLX5_CAP_GEN(dev, pg)) {
152 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
153 if (err)
154 return err;
155 }
156
157 if (MLX5_CAP_GEN(dev, atomic)) {
158 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
159 if (err)
160 return err;
161 }
162
163 if (MLX5_CAP_GEN(dev, roce)) {
164 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
165 if (err)
166 return err;
167 }
168
169 if ((MLX5_CAP_GEN(dev, port_type) ==
170 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET &&
171 MLX5_CAP_GEN(dev, nic_flow_table)) ||
172 (MLX5_CAP_GEN(dev, port_type) == MLX5_CMD_HCA_CAP_PORT_TYPE_IB &&
173 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads))) {
174 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE);
175 if (err)
176 return err;
177 }
178
179 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) {
180 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE);
181 if (err)
182 return err;
183 }
184
185 if (MLX5_CAP_GEN(dev, vport_group_manager)) {
186 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH);
187 if (err)
188 return err;
189 }
190
191 if (MLX5_CAP_GEN(dev, snapshot)) {
192 err = mlx5_core_get_caps(dev, MLX5_CAP_SNAPSHOT);
193 if (err)
194 return err;
195 }
196
197 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
198 err = mlx5_core_get_caps(dev, MLX5_CAP_EOIB_OFFLOADS);
199 if (err)
200 return err;
201 }
202
203 if (MLX5_CAP_GEN(dev, debug)) {
204 err = mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);
205 if (err)
206 return err;
207 }
208
209 if (MLX5_CAP_GEN(dev, qos)) {
210 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
211 if (err)
212 return err;
213 }
214
215 if (MLX5_CAP_GEN(dev, qcam_reg)) {
216 err = mlx5_get_qcam_reg(dev);
217 if (err)
218 return err;
219 }
220
221 if (MLX5_CAP_GEN(dev, mcam_reg)) {
222 err = mlx5_get_mcam_reg(dev);
223 if (err)
224 return err;
225 }
226
227 if (MLX5_CAP_GEN(dev, pcam_reg)) {
228 err = mlx5_get_pcam_reg(dev);
229 if (err)
230 return err;
231 }
232
233 if (MLX5_CAP_GEN(dev, tls_tx)) {
234 err = mlx5_core_get_caps(dev, MLX5_CAP_TLS);
235 if (err)
236 return err;
237 }
238
239 err = mlx5_core_query_special_contexts(dev);
240 if (err)
241 return err;
242
243 return 0;
244 }
245
mlx5_cmd_init_hca(struct mlx5_core_dev * dev)246 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev)
247 {
248 u32 in[MLX5_ST_SZ_DW(init_hca_in)];
249 u32 out[MLX5_ST_SZ_DW(init_hca_out)];
250
251 memset(in, 0, sizeof(in));
252
253 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
254
255 memset(out, 0, sizeof(out));
256 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
257 }
258
mlx5_cmd_teardown_hca(struct mlx5_core_dev * dev)259 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
260 {
261 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
262 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
263
264 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
265 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
266 }
267
mlx5_cmd_force_teardown_hca(struct mlx5_core_dev * dev)268 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
269 {
270 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
271 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
272 int force_state;
273 int ret;
274
275 if (!MLX5_CAP_GEN(dev, force_teardown)) {
276 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
277 return -EOPNOTSUPP;
278 }
279
280 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
281 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
282
283 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
284 if (ret)
285 return ret;
286
287 force_state = MLX5_GET(teardown_hca_out, out, state);
288 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
289 mlx5_core_err(dev, "teardown with force mode failed\n");
290 return -EIO;
291 }
292
293 return 0;
294 }
295
296 #define MLX5_FAST_TEARDOWN_WAIT_MS 3000
mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev * dev)297 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
298 {
299 int end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS;
300 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
301 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
302 int state;
303 int ret;
304
305 if (!MLX5_CAP_GEN(dev, fast_teardown)) {
306 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
307 return -EOPNOTSUPP;
308 }
309
310 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
311 MLX5_SET(teardown_hca_in, in, profile,
312 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
313
314 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
315 if (ret)
316 return ret;
317
318 state = MLX5_GET(teardown_hca_out, out, state);
319 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
320 mlx5_core_warn(dev, "teardown with fast mode failed\n");
321 return -EIO;
322 }
323
324 mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED);
325
326 /* Loop until device state turns to disable */
327 end = jiffies + msecs_to_jiffies(delay_ms);
328 do {
329 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
330 break;
331
332 pause("W", 1);
333 } while (!time_after(jiffies, end));
334
335 if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
336 mlx5_core_err(dev, "NIC IFC still %d after %ums.\n",
337 mlx5_get_nic_state(dev), delay_ms);
338 return -EIO;
339 }
340 return 0;
341 }
342
mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev * dev,int enable,u64 addr)343 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
344 u64 addr)
345 {
346 u32 in[MLX5_ST_SZ_DW(set_dc_cnak_trace_in)] = {0};
347 u32 out[MLX5_ST_SZ_DW(set_dc_cnak_trace_out)] = {0};
348 __be64 be_addr;
349 void *pas;
350
351 MLX5_SET(set_dc_cnak_trace_in, in, opcode, MLX5_CMD_OP_SET_DC_CNAK_TRACE);
352 MLX5_SET(set_dc_cnak_trace_in, in, enable, enable);
353 pas = MLX5_ADDR_OF(set_dc_cnak_trace_in, in, pas);
354 be_addr = cpu_to_be64(addr);
355 memcpy(MLX5_ADDR_OF(cmd_pas, pas, pa_h), &be_addr, sizeof(be_addr));
356
357 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
358 }
359
360 enum mlxsw_reg_mcc_instruction {
361 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
362 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
363 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
364 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
365 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
366 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
367 };
368
mlx5_reg_mcc_set(struct mlx5_core_dev * dev,enum mlxsw_reg_mcc_instruction instr,u16 component_index,u32 update_handle,u32 component_size)369 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
370 enum mlxsw_reg_mcc_instruction instr,
371 u16 component_index, u32 update_handle,
372 u32 component_size)
373 {
374 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
375 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
376
377 memset(in, 0, sizeof(in));
378
379 MLX5_SET(mcc_reg, in, instruction, instr);
380 MLX5_SET(mcc_reg, in, component_index, component_index);
381 MLX5_SET(mcc_reg, in, update_handle, update_handle);
382 MLX5_SET(mcc_reg, in, component_size, component_size);
383
384 return mlx5_core_access_reg(dev, in, sizeof(in), out,
385 sizeof(out), MLX5_REG_MCC, 0, 1);
386 }
387
mlx5_reg_mcc_query(struct mlx5_core_dev * dev,u32 * update_handle,u8 * error_code,u8 * control_state)388 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
389 u32 *update_handle, u8 *error_code,
390 u8 *control_state)
391 {
392 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
393 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
394 int err;
395
396 memset(in, 0, sizeof(in));
397 memset(out, 0, sizeof(out));
398 MLX5_SET(mcc_reg, in, update_handle, *update_handle);
399
400 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
401 sizeof(out), MLX5_REG_MCC, 0, 0);
402 if (err)
403 goto out;
404
405 *update_handle = MLX5_GET(mcc_reg, out, update_handle);
406 *error_code = MLX5_GET(mcc_reg, out, error_code);
407 *control_state = MLX5_GET(mcc_reg, out, control_state);
408
409 out:
410 return err;
411 }
412
mlx5_reg_mcda_set(struct mlx5_core_dev * dev,u32 update_handle,u32 offset,u16 size,u8 * data)413 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
414 u32 update_handle,
415 u32 offset, u16 size,
416 u8 *data)
417 {
418 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
419 u32 out[MLX5_ST_SZ_DW(mcda_reg)];
420 int i, j, dw_size = size >> 2;
421 __be32 data_element;
422 u32 *in;
423
424 in = kzalloc(in_size, GFP_KERNEL);
425 if (!in)
426 return -ENOMEM;
427
428 MLX5_SET(mcda_reg, in, update_handle, update_handle);
429 MLX5_SET(mcda_reg, in, offset, offset);
430 MLX5_SET(mcda_reg, in, size, size);
431
432 for (i = 0; i < dw_size; i++) {
433 j = i * 4;
434 data_element = htonl(*(u32 *)&data[j]);
435 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
436 }
437
438 err = mlx5_core_access_reg(dev, in, in_size, out,
439 sizeof(out), MLX5_REG_MCDA, 0, 1);
440 kfree(in);
441 return err;
442 }
443
mlx5_reg_mcqi_query(struct mlx5_core_dev * dev,u16 component_index,u32 * max_component_size,u8 * log_mcda_word_size,u16 * mcda_max_write_size)444 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
445 u16 component_index,
446 u32 *max_component_size,
447 u8 *log_mcda_word_size,
448 u16 *mcda_max_write_size)
449 {
450 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)];
451 int offset = MLX5_ST_SZ_DW(mcqi_reg);
452 u32 in[MLX5_ST_SZ_DW(mcqi_reg)];
453 int err;
454
455 memset(in, 0, sizeof(in));
456 memset(out, 0, sizeof(out));
457
458 MLX5_SET(mcqi_reg, in, component_index, component_index);
459 MLX5_SET(mcqi_reg, in, data_size, MLX5_ST_SZ_BYTES(mcqi_cap));
460
461 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
462 sizeof(out), MLX5_REG_MCQI, 0, 0);
463 if (err)
464 goto out;
465
466 *max_component_size = MLX5_GET(mcqi_cap, out + offset, max_component_size);
467 *log_mcda_word_size = MLX5_GET(mcqi_cap, out + offset, log_mcda_word_size);
468 *mcda_max_write_size = MLX5_GET(mcqi_cap, out + offset, mcda_max_write_size);
469
470 out:
471 return err;
472 }
473
474 struct mlx5_mlxfw_dev {
475 struct mlxfw_dev mlxfw_dev;
476 struct mlx5_core_dev *mlx5_core_dev;
477 };
478
mlx5_component_query(struct mlxfw_dev * mlxfw_dev,u16 component_index,u32 * p_max_size,u8 * p_align_bits,u16 * p_max_write_size)479 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
480 u16 component_index, u32 *p_max_size,
481 u8 *p_align_bits, u16 *p_max_write_size)
482 {
483 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
484 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
485 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
486
487 return mlx5_reg_mcqi_query(dev, component_index, p_max_size,
488 p_align_bits, p_max_write_size);
489 }
490
mlx5_fsm_lock(struct mlxfw_dev * mlxfw_dev,u32 * fwhandle)491 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
492 {
493 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
494 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
495 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
496 u8 control_state, error_code;
497 int err;
498
499 *fwhandle = 0;
500 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
501 if (err)
502 return err;
503
504 if (control_state != MLXFW_FSM_STATE_IDLE)
505 return -EBUSY;
506
507 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
508 0, *fwhandle, 0);
509 }
510
mlx5_fsm_component_update(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index,u32 component_size)511 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
512 u16 component_index, u32 component_size)
513 {
514 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
515 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
516 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
517
518 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
519 component_index, fwhandle, component_size);
520 }
521
mlx5_fsm_block_download(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u8 * data,u16 size,u32 offset)522 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
523 u8 *data, u16 size, u32 offset)
524 {
525 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
526 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
527 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
528
529 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
530 }
531
mlx5_fsm_component_verify(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,u16 component_index)532 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
533 u16 component_index)
534 {
535 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
536 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
537 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
538
539 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
540 component_index, fwhandle, 0);
541 }
542
mlx5_fsm_activate(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)543 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
544 {
545 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
546 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
547 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
548
549 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
550 fwhandle, 0);
551 }
552
mlx5_fsm_query_state(struct mlxfw_dev * mlxfw_dev,u32 fwhandle,enum mlxfw_fsm_state * fsm_state,enum mlxfw_fsm_state_err * fsm_state_err)553 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
554 enum mlxfw_fsm_state *fsm_state,
555 enum mlxfw_fsm_state_err *fsm_state_err)
556 {
557 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
558 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
559 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
560 u8 control_state, error_code;
561 int err;
562
563 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
564 if (err)
565 return err;
566
567 *fsm_state = control_state;
568 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
569 MLXFW_FSM_STATE_ERR_MAX);
570 return 0;
571 }
572
mlx5_fsm_cancel(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)573 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
574 {
575 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
576 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
577 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
578
579 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
580 }
581
mlx5_fsm_release(struct mlxfw_dev * mlxfw_dev,u32 fwhandle)582 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
583 {
584 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
585 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
586 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
587
588 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
589 fwhandle, 0);
590 }
591
592 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
593 .component_query = mlx5_component_query,
594 .fsm_lock = mlx5_fsm_lock,
595 .fsm_component_update = mlx5_fsm_component_update,
596 .fsm_block_download = mlx5_fsm_block_download,
597 .fsm_component_verify = mlx5_fsm_component_verify,
598 .fsm_activate = mlx5_fsm_activate,
599 .fsm_query_state = mlx5_fsm_query_state,
600 .fsm_cancel = mlx5_fsm_cancel,
601 .fsm_release = mlx5_fsm_release
602 };
603
mlx5_firmware_flash(struct mlx5_core_dev * dev,const struct firmware * firmware)604 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
605 const struct firmware *firmware)
606 {
607 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
608 .mlxfw_dev = {
609 .ops = &mlx5_mlxfw_dev_ops,
610 .psid = dev->board_id,
611 .psid_size = strlen(dev->board_id),
612 },
613 .mlx5_core_dev = dev
614 };
615
616 if (!MLX5_CAP_GEN(dev, mcam_reg) ||
617 !MLX5_CAP_MCAM_REG(dev, mcqi) ||
618 !MLX5_CAP_MCAM_REG(dev, mcc) ||
619 !MLX5_CAP_MCAM_REG(dev, mcda)) {
620 pr_info("%s flashing isn't supported by the running FW\n", __func__);
621 return -EOPNOTSUPP;
622 }
623
624 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, firmware);
625 }
626