1 /*-
2 * Copyright (c) 2016 Jared McNeill <[email protected]>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /*
27 * Allwinner Gigabit Ethernet MAC (EMAC) controller
28 */
29
30 #include "opt_device_polling.h"
31
32 #include <sys/cdefs.h>
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36 #include <sys/rman.h>
37 #include <sys/kernel.h>
38 #include <sys/endian.h>
39 #include <sys/mbuf.h>
40 #include <sys/socket.h>
41 #include <sys/sockio.h>
42 #include <sys/module.h>
43 #include <sys/gpio.h>
44
45 #include <net/bpf.h>
46 #include <net/if.h>
47 #include <net/ethernet.h>
48 #include <net/if_dl.h>
49 #include <net/if_media.h>
50 #include <net/if_types.h>
51 #include <net/if_var.h>
52
53 #include <machine/bus.h>
54
55 #include <dev/ofw/ofw_bus.h>
56 #include <dev/ofw/ofw_bus_subr.h>
57
58 #include <arm/allwinner/if_awgreg.h>
59 #include <arm/allwinner/aw_sid.h>
60 #include <dev/mii/mii.h>
61 #include <dev/mii/miivar.h>
62
63 #include <dev/extres/clk/clk.h>
64 #include <dev/extres/hwreset/hwreset.h>
65 #include <dev/extres/regulator/regulator.h>
66 #include <dev/extres/syscon/syscon.h>
67
68 #include "syscon_if.h"
69 #include "miibus_if.h"
70 #include "gpio_if.h"
71
72 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
73 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
74
75 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
76 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
77 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
78 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
79
80 #define DESC_ALIGN 4
81 #define TX_DESC_COUNT 1024
82 #define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT)
83 #define RX_DESC_COUNT 256
84 #define RX_DESC_SIZE (sizeof(struct emac_desc) * RX_DESC_COUNT)
85
86 #define DESC_OFF(n) ((n) * sizeof(struct emac_desc))
87 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1))
88 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1))
89 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1))
90
91 #define TX_MAX_SEGS 20
92
93 #define SOFT_RST_RETRY 1000
94 #define MII_BUSY_RETRY 1000
95 #define MDIO_FREQ 2500000
96
97 #define BURST_LEN_DEFAULT 8
98 #define RX_TX_PRI_DEFAULT 0
99 #define PAUSE_TIME_DEFAULT 0x400
100 #define TX_INTERVAL_DEFAULT 64
101 #define RX_BATCH_DEFAULT 64
102
103 /* syscon EMAC clock register */
104 #define EMAC_CLK_REG 0x30
105 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */
106 #define EMAC_CLK_EPHY_ADDR_SHIFT 20
107 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */
108 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */
109 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */
110 #define EMAC_CLK_RMII_EN (1 << 13)
111 #define EMAC_CLK_ETXDC (0x7 << 10)
112 #define EMAC_CLK_ETXDC_SHIFT 10
113 #define EMAC_CLK_ERXDC (0x1f << 5)
114 #define EMAC_CLK_ERXDC_SHIFT 5
115 #define EMAC_CLK_PIT (0x1 << 2)
116 #define EMAC_CLK_PIT_MII (0 << 2)
117 #define EMAC_CLK_PIT_RGMII (1 << 2)
118 #define EMAC_CLK_SRC (0x3 << 0)
119 #define EMAC_CLK_SRC_MII (0 << 0)
120 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0)
121 #define EMAC_CLK_SRC_RGMII (2 << 0)
122
123 /* Burst length of RX and TX DMA transfers */
124 static int awg_burst_len = BURST_LEN_DEFAULT;
125 TUNABLE_INT("hw.awg.burst_len", &awg_burst_len);
126
127 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */
128 static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT;
129 TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri);
130
131 /* Pause time field in the transmitted control frame */
132 static int awg_pause_time = PAUSE_TIME_DEFAULT;
133 TUNABLE_INT("hw.awg.pause_time", &awg_pause_time);
134
135 /* Request a TX interrupt every <n> descriptors */
136 static int awg_tx_interval = TX_INTERVAL_DEFAULT;
137 TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval);
138
139 /* Maximum number of mbufs to send to if_input */
140 static int awg_rx_batch = RX_BATCH_DEFAULT;
141 TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch);
142
143 enum awg_type {
144 EMAC_A83T = 1,
145 EMAC_H3,
146 EMAC_A64,
147 };
148
149 static struct ofw_compat_data compat_data[] = {
150 { "allwinner,sun8i-a83t-emac", EMAC_A83T },
151 { "allwinner,sun8i-h3-emac", EMAC_H3 },
152 { "allwinner,sun50i-a64-emac", EMAC_A64 },
153 { NULL, 0 }
154 };
155
156 struct awg_bufmap {
157 bus_dmamap_t map;
158 struct mbuf *mbuf;
159 };
160
161 struct awg_txring {
162 bus_dma_tag_t desc_tag;
163 bus_dmamap_t desc_map;
164 struct emac_desc *desc_ring;
165 bus_addr_t desc_ring_paddr;
166 bus_dma_tag_t buf_tag;
167 struct awg_bufmap buf_map[TX_DESC_COUNT];
168 u_int cur, next, queued;
169 u_int segs;
170 };
171
172 struct awg_rxring {
173 bus_dma_tag_t desc_tag;
174 bus_dmamap_t desc_map;
175 struct emac_desc *desc_ring;
176 bus_addr_t desc_ring_paddr;
177 bus_dma_tag_t buf_tag;
178 struct awg_bufmap buf_map[RX_DESC_COUNT];
179 bus_dmamap_t buf_spare_map;
180 u_int cur;
181 };
182
183 enum {
184 _RES_EMAC,
185 _RES_IRQ,
186 _RES_SYSCON,
187 _RES_NITEMS
188 };
189
190 struct awg_softc {
191 struct resource *res[_RES_NITEMS];
192 struct mtx mtx;
193 if_t ifp;
194 device_t dev;
195 device_t miibus;
196 struct callout stat_ch;
197 void *ih;
198 u_int mdc_div_ratio_m;
199 int link;
200 int if_flags;
201 enum awg_type type;
202 struct syscon *syscon;
203
204 struct awg_txring tx;
205 struct awg_rxring rx;
206 };
207
208 static struct resource_spec awg_spec[] = {
209 { SYS_RES_MEMORY, 0, RF_ACTIVE },
210 { SYS_RES_IRQ, 0, RF_ACTIVE },
211 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
212 { -1, 0 }
213 };
214
215 static void awg_txeof(struct awg_softc *sc);
216 static void awg_start_locked(struct awg_softc *sc);
217
218 static void awg_tick(void *softc);
219
220 static int awg_parse_delay(device_t dev, uint32_t *tx_delay,
221 uint32_t *rx_delay);
222 static uint32_t syscon_read_emac_clk_reg(device_t dev);
223 static void syscon_write_emac_clk_reg(device_t dev, uint32_t val);
224 static phandle_t awg_get_phy_node(device_t dev);
225 static bool awg_has_internal_phy(device_t dev);
226
227 /*
228 * MII functions
229 */
230
231 static int
awg_miibus_readreg(device_t dev,int phy,int reg)232 awg_miibus_readreg(device_t dev, int phy, int reg)
233 {
234 struct awg_softc *sc;
235 int retry, val;
236
237 sc = device_get_softc(dev);
238 val = 0;
239
240 WR4(sc, EMAC_MII_CMD,
241 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) |
242 (phy << PHY_ADDR_SHIFT) |
243 (reg << PHY_REG_ADDR_SHIFT) |
244 MII_BUSY);
245 for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
246 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) {
247 val = RD4(sc, EMAC_MII_DATA);
248 break;
249 }
250 DELAY(10);
251 }
252
253 if (retry == 0)
254 device_printf(dev, "phy read timeout, phy=%d reg=%d\n",
255 phy, reg);
256
257 return (val);
258 }
259
260 static int
awg_miibus_writereg(device_t dev,int phy,int reg,int val)261 awg_miibus_writereg(device_t dev, int phy, int reg, int val)
262 {
263 struct awg_softc *sc;
264 int retry;
265
266 sc = device_get_softc(dev);
267
268 WR4(sc, EMAC_MII_DATA, val);
269 WR4(sc, EMAC_MII_CMD,
270 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) |
271 (phy << PHY_ADDR_SHIFT) |
272 (reg << PHY_REG_ADDR_SHIFT) |
273 MII_WR | MII_BUSY);
274 for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
275 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0)
276 break;
277 DELAY(10);
278 }
279
280 if (retry == 0)
281 device_printf(dev, "phy write timeout, phy=%d reg=%d\n",
282 phy, reg);
283
284 return (0);
285 }
286
287 static void
awg_miibus_statchg(device_t dev)288 awg_miibus_statchg(device_t dev)
289 {
290 struct awg_softc *sc;
291 struct mii_data *mii;
292 uint32_t val;
293
294 sc = device_get_softc(dev);
295
296 AWG_ASSERT_LOCKED(sc);
297
298 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0)
299 return;
300 mii = device_get_softc(sc->miibus);
301
302 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
303 (IFM_ACTIVE | IFM_AVALID)) {
304 switch (IFM_SUBTYPE(mii->mii_media_active)) {
305 case IFM_1000_T:
306 case IFM_1000_SX:
307 case IFM_100_TX:
308 case IFM_10_T:
309 sc->link = 1;
310 break;
311 default:
312 sc->link = 0;
313 break;
314 }
315 } else
316 sc->link = 0;
317
318 if (sc->link == 0)
319 return;
320
321 val = RD4(sc, EMAC_BASIC_CTL_0);
322 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX);
323
324 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
325 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
326 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT;
327 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
328 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT;
329 else
330 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT;
331
332 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
333 val |= BASIC_CTL_DUPLEX;
334
335 WR4(sc, EMAC_BASIC_CTL_0, val);
336
337 val = RD4(sc, EMAC_RX_CTL_0);
338 val &= ~RX_FLOW_CTL_EN;
339 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
340 val |= RX_FLOW_CTL_EN;
341 WR4(sc, EMAC_RX_CTL_0, val);
342
343 val = RD4(sc, EMAC_TX_FLOW_CTL);
344 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN);
345 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
346 val |= TX_FLOW_CTL_EN;
347 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
348 val |= awg_pause_time << PAUSE_TIME_SHIFT;
349 WR4(sc, EMAC_TX_FLOW_CTL, val);
350 }
351
352 /*
353 * Media functions
354 */
355
356 static void
awg_media_status(if_t ifp,struct ifmediareq * ifmr)357 awg_media_status(if_t ifp, struct ifmediareq *ifmr)
358 {
359 struct awg_softc *sc;
360 struct mii_data *mii;
361
362 sc = if_getsoftc(ifp);
363 mii = device_get_softc(sc->miibus);
364
365 AWG_LOCK(sc);
366 mii_pollstat(mii);
367 ifmr->ifm_active = mii->mii_media_active;
368 ifmr->ifm_status = mii->mii_media_status;
369 AWG_UNLOCK(sc);
370 }
371
372 static int
awg_media_change(if_t ifp)373 awg_media_change(if_t ifp)
374 {
375 struct awg_softc *sc;
376 struct mii_data *mii;
377 int error;
378
379 sc = if_getsoftc(ifp);
380 mii = device_get_softc(sc->miibus);
381
382 AWG_LOCK(sc);
383 error = mii_mediachg(mii);
384 AWG_UNLOCK(sc);
385
386 return (error);
387 }
388
389 /*
390 * Core functions
391 */
392
393 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */
394 static uint32_t
bitrev32(uint32_t x)395 bitrev32(uint32_t x)
396 {
397 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
398 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
399 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
400 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
401
402 return (x >> 16) | (x << 16);
403 }
404
405 static u_int
awg_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)406 awg_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
407 {
408 uint32_t crc, hashreg, hashbit, *hash = arg;
409
410 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7f;
411 crc = bitrev32(~crc) >> 26;
412 hashreg = (crc >> 5);
413 hashbit = (crc & 0x1f);
414 hash[hashreg] |= (1 << hashbit);
415
416 return (1);
417 }
418
419 static void
awg_setup_rxfilter(struct awg_softc * sc)420 awg_setup_rxfilter(struct awg_softc *sc)
421 {
422 uint32_t val, hash[2], machi, maclo;
423 uint8_t *eaddr;
424 if_t ifp;
425
426 AWG_ASSERT_LOCKED(sc);
427
428 ifp = sc->ifp;
429 val = 0;
430 hash[0] = hash[1] = 0;
431
432 if (if_getflags(ifp) & IFF_PROMISC)
433 val |= DIS_ADDR_FILTER;
434 else if (if_getflags(ifp) & IFF_ALLMULTI) {
435 val |= RX_ALL_MULTICAST;
436 hash[0] = hash[1] = ~0;
437 } else if (if_foreach_llmaddr(ifp, awg_hash_maddr, hash) > 0)
438 val |= HASH_MULTICAST;
439
440 /* Write our unicast address */
441 eaddr = if_getlladdr(ifp);
442 machi = (eaddr[5] << 8) | eaddr[4];
443 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) |
444 (eaddr[0] << 0);
445 WR4(sc, EMAC_ADDR_HIGH(0), machi);
446 WR4(sc, EMAC_ADDR_LOW(0), maclo);
447
448 /* Multicast hash filters */
449 WR4(sc, EMAC_RX_HASH_0, hash[1]);
450 WR4(sc, EMAC_RX_HASH_1, hash[0]);
451
452 /* RX frame filter config */
453 WR4(sc, EMAC_RX_FRM_FLT, val);
454 }
455
456 static void
awg_setup_core(struct awg_softc * sc)457 awg_setup_core(struct awg_softc *sc)
458 {
459 uint32_t val;
460
461 AWG_ASSERT_LOCKED(sc);
462 /* Configure DMA burst length and priorities */
463 val = awg_burst_len << BASIC_CTL_BURST_LEN_SHIFT;
464 if (awg_rx_tx_pri)
465 val |= BASIC_CTL_RX_TX_PRI;
466 WR4(sc, EMAC_BASIC_CTL_1, val);
467
468 }
469
470 static void
awg_enable_mac(struct awg_softc * sc,bool enable)471 awg_enable_mac(struct awg_softc *sc, bool enable)
472 {
473 uint32_t tx, rx;
474
475 AWG_ASSERT_LOCKED(sc);
476
477 tx = RD4(sc, EMAC_TX_CTL_0);
478 rx = RD4(sc, EMAC_RX_CTL_0);
479 if (enable) {
480 tx |= TX_EN;
481 rx |= RX_EN | CHECK_CRC;
482 } else {
483 tx &= ~TX_EN;
484 rx &= ~(RX_EN | CHECK_CRC);
485 }
486
487 WR4(sc, EMAC_TX_CTL_0, tx);
488 WR4(sc, EMAC_RX_CTL_0, rx);
489 }
490
491 static void
awg_get_eaddr(device_t dev,uint8_t * eaddr)492 awg_get_eaddr(device_t dev, uint8_t *eaddr)
493 {
494 struct awg_softc *sc;
495 uint32_t maclo, machi, rnd;
496 u_char rootkey[16];
497 uint32_t rootkey_size;
498
499 sc = device_get_softc(dev);
500
501 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff;
502 maclo = RD4(sc, EMAC_ADDR_LOW(0));
503
504 rootkey_size = sizeof(rootkey);
505 if (maclo == 0xffffffff && machi == 0xffff) {
506 /* MAC address in hardware is invalid, create one */
507 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey,
508 &rootkey_size) == 0 &&
509 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] |
510 rootkey[15]) != 0) {
511 /* MAC address is derived from the root key in SID */
512 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) |
513 (rootkey[3] << 8) | 0x02;
514 machi = (rootkey[15] << 8) | rootkey[14];
515 } else {
516 /* Create one */
517 rnd = arc4random();
518 maclo = 0x00f2 | (rnd & 0xffff0000);
519 machi = rnd & 0xffff;
520 }
521 }
522
523 eaddr[0] = maclo & 0xff;
524 eaddr[1] = (maclo >> 8) & 0xff;
525 eaddr[2] = (maclo >> 16) & 0xff;
526 eaddr[3] = (maclo >> 24) & 0xff;
527 eaddr[4] = machi & 0xff;
528 eaddr[5] = (machi >> 8) & 0xff;
529 }
530
531 /*
532 * DMA functions
533 */
534
535 static void
awg_enable_dma_intr(struct awg_softc * sc)536 awg_enable_dma_intr(struct awg_softc *sc)
537 {
538 /* Enable interrupts */
539 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN);
540 }
541
542 static void
awg_disable_dma_intr(struct awg_softc * sc)543 awg_disable_dma_intr(struct awg_softc *sc)
544 {
545 /* Disable interrupts */
546 WR4(sc, EMAC_INT_EN, 0);
547 }
548
549 static void
awg_init_dma(struct awg_softc * sc)550 awg_init_dma(struct awg_softc *sc)
551 {
552 uint32_t val;
553
554 AWG_ASSERT_LOCKED(sc);
555
556 /* Enable interrupts */
557 #ifdef DEVICE_POLLING
558 if ((if_getcapenable(sc->ifp) & IFCAP_POLLING) == 0)
559 awg_enable_dma_intr(sc);
560 else
561 awg_disable_dma_intr(sc);
562 #else
563 awg_enable_dma_intr(sc);
564 #endif
565
566 /* Enable transmit DMA */
567 val = RD4(sc, EMAC_TX_CTL_1);
568 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME);
569
570 /* Enable receive DMA */
571 val = RD4(sc, EMAC_RX_CTL_1);
572 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD);
573 }
574
575 static void
awg_stop_dma(struct awg_softc * sc)576 awg_stop_dma(struct awg_softc *sc)
577 {
578 uint32_t val;
579
580 AWG_ASSERT_LOCKED(sc);
581
582 /* Stop transmit DMA and flush data in the TX FIFO */
583 val = RD4(sc, EMAC_TX_CTL_1);
584 val &= ~TX_DMA_EN;
585 val |= FLUSH_TX_FIFO;
586 WR4(sc, EMAC_TX_CTL_1, val);
587
588 /* Disable interrupts */
589 awg_disable_dma_intr(sc);
590
591 /* Disable transmit DMA */
592 val = RD4(sc, EMAC_TX_CTL_1);
593 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN);
594
595 /* Disable receive DMA */
596 val = RD4(sc, EMAC_RX_CTL_1);
597 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN);
598 }
599
600 static int
awg_encap(struct awg_softc * sc,struct mbuf ** mp)601 awg_encap(struct awg_softc *sc, struct mbuf **mp)
602 {
603 bus_dmamap_t map;
604 bus_dma_segment_t segs[TX_MAX_SEGS];
605 int error, nsegs, cur, first, last, i;
606 u_int csum_flags;
607 uint32_t flags, status;
608 struct mbuf *m;
609
610 cur = first = sc->tx.cur;
611 map = sc->tx.buf_map[first].map;
612
613 m = *mp;
614 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, segs,
615 &nsegs, BUS_DMA_NOWAIT);
616 if (error == EFBIG) {
617 m = m_collapse(m, M_NOWAIT, TX_MAX_SEGS);
618 if (m == NULL) {
619 device_printf(sc->dev, "awg_encap: m_collapse failed\n");
620 m_freem(*mp);
621 *mp = NULL;
622 return (ENOMEM);
623 }
624 *mp = m;
625 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m,
626 segs, &nsegs, BUS_DMA_NOWAIT);
627 if (error != 0) {
628 m_freem(*mp);
629 *mp = NULL;
630 }
631 }
632 if (error != 0) {
633 device_printf(sc->dev, "awg_encap: bus_dmamap_load_mbuf_sg failed\n");
634 return (error);
635 }
636 if (nsegs == 0) {
637 m_freem(*mp);
638 *mp = NULL;
639 return (EIO);
640 }
641
642 if (sc->tx.queued + nsegs > TX_DESC_COUNT) {
643 bus_dmamap_unload(sc->tx.buf_tag, map);
644 return (ENOBUFS);
645 }
646
647 bus_dmamap_sync(sc->tx.buf_tag, map, BUS_DMASYNC_PREWRITE);
648
649 flags = TX_FIR_DESC;
650 status = 0;
651 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) {
652 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0)
653 csum_flags = TX_CHECKSUM_CTL_FULL;
654 else
655 csum_flags = TX_CHECKSUM_CTL_IP;
656 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT);
657 }
658
659 for (i = 0; i < nsegs; i++) {
660 sc->tx.segs++;
661 if (i == nsegs - 1) {
662 flags |= TX_LAST_DESC;
663 /*
664 * Can only request TX completion
665 * interrupt on last descriptor.
666 */
667 if (sc->tx.segs >= awg_tx_interval) {
668 sc->tx.segs = 0;
669 flags |= TX_INT_CTL;
670 }
671 }
672
673 sc->tx.desc_ring[cur].addr = htole32((uint32_t)segs[i].ds_addr);
674 sc->tx.desc_ring[cur].size = htole32(flags | segs[i].ds_len);
675 sc->tx.desc_ring[cur].status = htole32(status);
676
677 flags &= ~TX_FIR_DESC;
678 /*
679 * Setting of the valid bit in the first descriptor is
680 * deferred until the whole chain is fully set up.
681 */
682 status = TX_DESC_CTL;
683
684 ++sc->tx.queued;
685 cur = TX_NEXT(cur);
686 }
687
688 sc->tx.cur = cur;
689
690 /* Store mapping and mbuf in the last segment */
691 last = TX_SKIP(cur, TX_DESC_COUNT - 1);
692 sc->tx.buf_map[first].map = sc->tx.buf_map[last].map;
693 sc->tx.buf_map[last].map = map;
694 sc->tx.buf_map[last].mbuf = m;
695
696 /*
697 * The whole mbuf chain has been DMA mapped,
698 * fix the first descriptor.
699 */
700 sc->tx.desc_ring[first].status = htole32(TX_DESC_CTL);
701
702 return (0);
703 }
704
705 static void
awg_clean_txbuf(struct awg_softc * sc,int index)706 awg_clean_txbuf(struct awg_softc *sc, int index)
707 {
708 struct awg_bufmap *bmap;
709
710 --sc->tx.queued;
711
712 bmap = &sc->tx.buf_map[index];
713 if (bmap->mbuf != NULL) {
714 bus_dmamap_sync(sc->tx.buf_tag, bmap->map,
715 BUS_DMASYNC_POSTWRITE);
716 bus_dmamap_unload(sc->tx.buf_tag, bmap->map);
717 m_freem(bmap->mbuf);
718 bmap->mbuf = NULL;
719 }
720 }
721
722 static void
awg_setup_rxdesc(struct awg_softc * sc,int index,bus_addr_t paddr)723 awg_setup_rxdesc(struct awg_softc *sc, int index, bus_addr_t paddr)
724 {
725 uint32_t status, size;
726
727 status = RX_DESC_CTL;
728 size = MCLBYTES - 1;
729
730 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr);
731 sc->rx.desc_ring[index].size = htole32(size);
732 sc->rx.desc_ring[index].status = htole32(status);
733 }
734
735 static void
awg_reuse_rxdesc(struct awg_softc * sc,int index)736 awg_reuse_rxdesc(struct awg_softc *sc, int index)
737 {
738
739 sc->rx.desc_ring[index].status = htole32(RX_DESC_CTL);
740 }
741
742 static int
awg_newbuf_rx(struct awg_softc * sc,int index)743 awg_newbuf_rx(struct awg_softc *sc, int index)
744 {
745 struct mbuf *m;
746 bus_dma_segment_t seg;
747 bus_dmamap_t map;
748 int nsegs;
749
750 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
751 if (m == NULL)
752 return (ENOBUFS);
753
754 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
755 m_adj(m, ETHER_ALIGN);
756
757 if (bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, sc->rx.buf_spare_map,
758 m, &seg, &nsegs, BUS_DMA_NOWAIT) != 0) {
759 m_freem(m);
760 return (ENOBUFS);
761 }
762
763 if (sc->rx.buf_map[index].mbuf != NULL) {
764 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map,
765 BUS_DMASYNC_POSTREAD);
766 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map);
767 }
768 map = sc->rx.buf_map[index].map;
769 sc->rx.buf_map[index].map = sc->rx.buf_spare_map;
770 sc->rx.buf_spare_map = map;
771 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map,
772 BUS_DMASYNC_PREREAD);
773
774 sc->rx.buf_map[index].mbuf = m;
775 awg_setup_rxdesc(sc, index, seg.ds_addr);
776
777 return (0);
778 }
779
780 static void
awg_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)781 awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
782 {
783 if (error != 0)
784 return;
785 *(bus_addr_t *)arg = segs[0].ds_addr;
786 }
787
788 static int
awg_setup_dma(device_t dev)789 awg_setup_dma(device_t dev)
790 {
791 struct awg_softc *sc;
792 int error, i;
793
794 sc = device_get_softc(dev);
795
796 /* Setup TX ring */
797 error = bus_dma_tag_create(
798 bus_get_dma_tag(dev), /* Parent tag */
799 DESC_ALIGN, 0, /* alignment, boundary */
800 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
801 BUS_SPACE_MAXADDR, /* highaddr */
802 NULL, NULL, /* filter, filterarg */
803 TX_DESC_SIZE, 1, /* maxsize, nsegs */
804 TX_DESC_SIZE, /* maxsegsize */
805 0, /* flags */
806 NULL, NULL, /* lockfunc, lockarg */
807 &sc->tx.desc_tag);
808 if (error != 0) {
809 device_printf(dev, "cannot create TX descriptor ring tag\n");
810 return (error);
811 }
812
813 error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring,
814 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map);
815 if (error != 0) {
816 device_printf(dev, "cannot allocate TX descriptor ring\n");
817 return (error);
818 }
819
820 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map,
821 sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb,
822 &sc->tx.desc_ring_paddr, 0);
823 if (error != 0) {
824 device_printf(dev, "cannot load TX descriptor ring\n");
825 return (error);
826 }
827
828 for (i = 0; i < TX_DESC_COUNT; i++)
829 sc->tx.desc_ring[i].next =
830 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i)));
831
832 error = bus_dma_tag_create(
833 bus_get_dma_tag(dev), /* Parent tag */
834 1, 0, /* alignment, boundary */
835 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
836 BUS_SPACE_MAXADDR, /* highaddr */
837 NULL, NULL, /* filter, filterarg */
838 MCLBYTES, TX_MAX_SEGS, /* maxsize, nsegs */
839 MCLBYTES, /* maxsegsize */
840 0, /* flags */
841 NULL, NULL, /* lockfunc, lockarg */
842 &sc->tx.buf_tag);
843 if (error != 0) {
844 device_printf(dev, "cannot create TX buffer tag\n");
845 return (error);
846 }
847
848 sc->tx.queued = 0;
849 for (i = 0; i < TX_DESC_COUNT; i++) {
850 error = bus_dmamap_create(sc->tx.buf_tag, 0,
851 &sc->tx.buf_map[i].map);
852 if (error != 0) {
853 device_printf(dev, "cannot create TX buffer map\n");
854 return (error);
855 }
856 }
857
858 /* Setup RX ring */
859 error = bus_dma_tag_create(
860 bus_get_dma_tag(dev), /* Parent tag */
861 DESC_ALIGN, 0, /* alignment, boundary */
862 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
863 BUS_SPACE_MAXADDR, /* highaddr */
864 NULL, NULL, /* filter, filterarg */
865 RX_DESC_SIZE, 1, /* maxsize, nsegs */
866 RX_DESC_SIZE, /* maxsegsize */
867 0, /* flags */
868 NULL, NULL, /* lockfunc, lockarg */
869 &sc->rx.desc_tag);
870 if (error != 0) {
871 device_printf(dev, "cannot create RX descriptor ring tag\n");
872 return (error);
873 }
874
875 error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring,
876 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map);
877 if (error != 0) {
878 device_printf(dev, "cannot allocate RX descriptor ring\n");
879 return (error);
880 }
881
882 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map,
883 sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb,
884 &sc->rx.desc_ring_paddr, 0);
885 if (error != 0) {
886 device_printf(dev, "cannot load RX descriptor ring\n");
887 return (error);
888 }
889
890 error = bus_dma_tag_create(
891 bus_get_dma_tag(dev), /* Parent tag */
892 1, 0, /* alignment, boundary */
893 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
894 BUS_SPACE_MAXADDR, /* highaddr */
895 NULL, NULL, /* filter, filterarg */
896 MCLBYTES, 1, /* maxsize, nsegs */
897 MCLBYTES, /* maxsegsize */
898 0, /* flags */
899 NULL, NULL, /* lockfunc, lockarg */
900 &sc->rx.buf_tag);
901 if (error != 0) {
902 device_printf(dev, "cannot create RX buffer tag\n");
903 return (error);
904 }
905
906 error = bus_dmamap_create(sc->rx.buf_tag, 0, &sc->rx.buf_spare_map);
907 if (error != 0) {
908 device_printf(dev,
909 "cannot create RX buffer spare map\n");
910 return (error);
911 }
912
913 for (i = 0; i < RX_DESC_COUNT; i++) {
914 sc->rx.desc_ring[i].next =
915 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(i)));
916
917 error = bus_dmamap_create(sc->rx.buf_tag, 0,
918 &sc->rx.buf_map[i].map);
919 if (error != 0) {
920 device_printf(dev, "cannot create RX buffer map\n");
921 return (error);
922 }
923 sc->rx.buf_map[i].mbuf = NULL;
924 error = awg_newbuf_rx(sc, i);
925 if (error != 0) {
926 device_printf(dev, "cannot create RX buffer\n");
927 return (error);
928 }
929 }
930 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
931 BUS_DMASYNC_PREWRITE);
932
933 /* Write transmit and receive descriptor base address registers */
934 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
935 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
936
937 return (0);
938 }
939
940 static void
awg_dma_start_tx(struct awg_softc * sc)941 awg_dma_start_tx(struct awg_softc *sc)
942 {
943 uint32_t val;
944
945 AWG_ASSERT_LOCKED(sc);
946
947 /* Start and run TX DMA */
948 val = RD4(sc, EMAC_TX_CTL_1);
949 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START);
950 }
951
952 /*
953 * if_ functions
954 */
955
956 static void
awg_start_locked(struct awg_softc * sc)957 awg_start_locked(struct awg_softc *sc)
958 {
959 struct mbuf *m;
960 if_t ifp;
961 int cnt, err;
962
963 AWG_ASSERT_LOCKED(sc);
964
965 if (!sc->link)
966 return;
967
968 ifp = sc->ifp;
969
970 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
971 IFF_DRV_RUNNING)
972 return;
973
974 for (cnt = 0; ; cnt++) {
975 m = if_dequeue(ifp);
976 if (m == NULL)
977 break;
978
979 err = awg_encap(sc, &m);
980 if (err != 0) {
981 if (err == ENOBUFS)
982 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
983 if (m != NULL)
984 if_sendq_prepend(ifp, m);
985 break;
986 }
987 if_bpfmtap(ifp, m);
988 }
989
990 if (cnt != 0) {
991 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
992 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
993
994 awg_dma_start_tx(sc);
995 }
996 }
997
998 static void
awg_start(if_t ifp)999 awg_start(if_t ifp)
1000 {
1001 struct awg_softc *sc;
1002
1003 sc = if_getsoftc(ifp);
1004
1005 AWG_LOCK(sc);
1006 awg_start_locked(sc);
1007 AWG_UNLOCK(sc);
1008 }
1009
1010 static void
awg_init_locked(struct awg_softc * sc)1011 awg_init_locked(struct awg_softc *sc)
1012 {
1013 struct mii_data *mii;
1014 if_t ifp;
1015
1016 mii = device_get_softc(sc->miibus);
1017 ifp = sc->ifp;
1018
1019 AWG_ASSERT_LOCKED(sc);
1020
1021 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1022 return;
1023
1024 awg_setup_rxfilter(sc);
1025 awg_setup_core(sc);
1026 awg_enable_mac(sc, true);
1027 awg_init_dma(sc);
1028
1029 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
1030
1031 mii_mediachg(mii);
1032 callout_reset(&sc->stat_ch, hz, awg_tick, sc);
1033 }
1034
1035 static void
awg_init(void * softc)1036 awg_init(void *softc)
1037 {
1038 struct awg_softc *sc;
1039
1040 sc = softc;
1041
1042 AWG_LOCK(sc);
1043 awg_init_locked(sc);
1044 AWG_UNLOCK(sc);
1045 }
1046
1047 static void
awg_stop(struct awg_softc * sc)1048 awg_stop(struct awg_softc *sc)
1049 {
1050 if_t ifp;
1051 uint32_t val;
1052 int i;
1053
1054 AWG_ASSERT_LOCKED(sc);
1055
1056 ifp = sc->ifp;
1057
1058 callout_stop(&sc->stat_ch);
1059
1060 awg_stop_dma(sc);
1061 awg_enable_mac(sc, false);
1062
1063 sc->link = 0;
1064
1065 /* Finish handling transmitted buffers */
1066 awg_txeof(sc);
1067
1068 /* Release any untransmitted buffers. */
1069 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) {
1070 val = le32toh(sc->tx.desc_ring[i].status);
1071 if ((val & TX_DESC_CTL) != 0)
1072 break;
1073 awg_clean_txbuf(sc, i);
1074 }
1075 sc->tx.next = i;
1076 for (; sc->tx.queued > 0; i = TX_NEXT(i)) {
1077 sc->tx.desc_ring[i].status = 0;
1078 awg_clean_txbuf(sc, i);
1079 }
1080 sc->tx.cur = sc->tx.next;
1081 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
1082 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1083
1084 /* Setup RX buffers for reuse */
1085 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1086 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1087
1088 for (i = sc->rx.cur; ; i = RX_NEXT(i)) {
1089 val = le32toh(sc->rx.desc_ring[i].status);
1090 if ((val & RX_DESC_CTL) != 0)
1091 break;
1092 awg_reuse_rxdesc(sc, i);
1093 }
1094 sc->rx.cur = i;
1095 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1096 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1097
1098 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1099 }
1100
1101 static int
awg_ioctl(if_t ifp,u_long cmd,caddr_t data)1102 awg_ioctl(if_t ifp, u_long cmd, caddr_t data)
1103 {
1104 struct awg_softc *sc;
1105 struct mii_data *mii;
1106 struct ifreq *ifr;
1107 int flags, mask, error;
1108
1109 sc = if_getsoftc(ifp);
1110 mii = device_get_softc(sc->miibus);
1111 ifr = (struct ifreq *)data;
1112 error = 0;
1113
1114 switch (cmd) {
1115 case SIOCSIFFLAGS:
1116 AWG_LOCK(sc);
1117 if (if_getflags(ifp) & IFF_UP) {
1118 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1119 flags = if_getflags(ifp) ^ sc->if_flags;
1120 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0)
1121 awg_setup_rxfilter(sc);
1122 } else
1123 awg_init_locked(sc);
1124 } else {
1125 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1126 awg_stop(sc);
1127 }
1128 sc->if_flags = if_getflags(ifp);
1129 AWG_UNLOCK(sc);
1130 break;
1131 case SIOCADDMULTI:
1132 case SIOCDELMULTI:
1133 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1134 AWG_LOCK(sc);
1135 awg_setup_rxfilter(sc);
1136 AWG_UNLOCK(sc);
1137 }
1138 break;
1139 case SIOCSIFMEDIA:
1140 case SIOCGIFMEDIA:
1141 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1142 break;
1143 case SIOCSIFCAP:
1144 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1145 #ifdef DEVICE_POLLING
1146 if (mask & IFCAP_POLLING) {
1147 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1148 error = ether_poll_register(awg_poll, ifp);
1149 if (error != 0)
1150 break;
1151 AWG_LOCK(sc);
1152 awg_disable_dma_intr(sc);
1153 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1154 AWG_UNLOCK(sc);
1155 } else {
1156 error = ether_poll_deregister(ifp);
1157 AWG_LOCK(sc);
1158 awg_enable_dma_intr(sc);
1159 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1160 AWG_UNLOCK(sc);
1161 }
1162 }
1163 #endif
1164 if (mask & IFCAP_VLAN_MTU)
1165 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
1166 if (mask & IFCAP_RXCSUM)
1167 if_togglecapenable(ifp, IFCAP_RXCSUM);
1168 if (mask & IFCAP_TXCSUM)
1169 if_togglecapenable(ifp, IFCAP_TXCSUM);
1170 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1171 if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0);
1172 else
1173 if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP);
1174 break;
1175 default:
1176 error = ether_ioctl(ifp, cmd, data);
1177 break;
1178 }
1179
1180 return (error);
1181 }
1182
1183 /*
1184 * Interrupts functions
1185 */
1186
1187 static int
awg_rxintr(struct awg_softc * sc)1188 awg_rxintr(struct awg_softc *sc)
1189 {
1190 if_t ifp;
1191 struct mbuf *m, *mh, *mt;
1192 int error, index, len, cnt, npkt;
1193 uint32_t status;
1194
1195 ifp = sc->ifp;
1196 mh = mt = NULL;
1197 cnt = 0;
1198 npkt = 0;
1199
1200 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1201 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1202
1203 for (index = sc->rx.cur; ; index = RX_NEXT(index)) {
1204 status = le32toh(sc->rx.desc_ring[index].status);
1205 if ((status & RX_DESC_CTL) != 0)
1206 break;
1207
1208 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT;
1209
1210 if (len == 0) {
1211 if ((status & (RX_NO_ENOUGH_BUF_ERR | RX_OVERFLOW_ERR)) != 0)
1212 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1213 awg_reuse_rxdesc(sc, index);
1214 continue;
1215 }
1216
1217 m = sc->rx.buf_map[index].mbuf;
1218
1219 error = awg_newbuf_rx(sc, index);
1220 if (error != 0) {
1221 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1222 awg_reuse_rxdesc(sc, index);
1223 continue;
1224 }
1225
1226 m->m_pkthdr.rcvif = ifp;
1227 m->m_pkthdr.len = len;
1228 m->m_len = len;
1229 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1230
1231 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
1232 (status & RX_FRM_TYPE) != 0) {
1233 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
1234 if ((status & RX_HEADER_ERR) == 0)
1235 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1236 if ((status & RX_PAYLOAD_ERR) == 0) {
1237 m->m_pkthdr.csum_flags |=
1238 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1239 m->m_pkthdr.csum_data = 0xffff;
1240 }
1241 }
1242
1243 m->m_nextpkt = NULL;
1244 if (mh == NULL)
1245 mh = m;
1246 else
1247 mt->m_nextpkt = m;
1248 mt = m;
1249 ++cnt;
1250 ++npkt;
1251
1252 if (cnt == awg_rx_batch) {
1253 AWG_UNLOCK(sc);
1254 if_input(ifp, mh);
1255 AWG_LOCK(sc);
1256 mh = mt = NULL;
1257 cnt = 0;
1258 }
1259 }
1260
1261 if (index != sc->rx.cur) {
1262 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1263 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1264 }
1265
1266 if (mh != NULL) {
1267 AWG_UNLOCK(sc);
1268 if_input(ifp, mh);
1269 AWG_LOCK(sc);
1270 }
1271
1272 sc->rx.cur = index;
1273
1274 return (npkt);
1275 }
1276
1277 static void
awg_txeof(struct awg_softc * sc)1278 awg_txeof(struct awg_softc *sc)
1279 {
1280 struct emac_desc *desc;
1281 uint32_t status, size;
1282 if_t ifp;
1283 int i, prog;
1284
1285 AWG_ASSERT_LOCKED(sc);
1286
1287 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
1288 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1289
1290 ifp = sc->ifp;
1291
1292 prog = 0;
1293 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) {
1294 desc = &sc->tx.desc_ring[i];
1295 status = le32toh(desc->status);
1296 if ((status & TX_DESC_CTL) != 0)
1297 break;
1298 size = le32toh(desc->size);
1299 if (size & TX_LAST_DESC) {
1300 if ((status & (TX_HEADER_ERR | TX_PAYLOAD_ERR)) != 0)
1301 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1302 else
1303 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1304 }
1305 prog++;
1306 awg_clean_txbuf(sc, i);
1307 }
1308
1309 if (prog > 0) {
1310 sc->tx.next = i;
1311 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1312 }
1313 }
1314
1315 static void
awg_intr(void * arg)1316 awg_intr(void *arg)
1317 {
1318 struct awg_softc *sc;
1319 uint32_t val;
1320
1321 sc = arg;
1322
1323 AWG_LOCK(sc);
1324 val = RD4(sc, EMAC_INT_STA);
1325 WR4(sc, EMAC_INT_STA, val);
1326
1327 if (val & RX_INT)
1328 awg_rxintr(sc);
1329
1330 if (val & TX_INT)
1331 awg_txeof(sc);
1332
1333 if (val & (TX_INT | TX_BUF_UA_INT)) {
1334 if (!if_sendq_empty(sc->ifp))
1335 awg_start_locked(sc);
1336 }
1337
1338 AWG_UNLOCK(sc);
1339 }
1340
1341 #ifdef DEVICE_POLLING
1342 static int
awg_poll(if_t ifp,enum poll_cmd cmd,int count)1343 awg_poll(if_t ifp, enum poll_cmd cmd, int count)
1344 {
1345 struct awg_softc *sc;
1346 uint32_t val;
1347 int rx_npkts;
1348
1349 sc = if_getsoftc(ifp);
1350 rx_npkts = 0;
1351
1352 AWG_LOCK(sc);
1353
1354 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1355 AWG_UNLOCK(sc);
1356 return (0);
1357 }
1358
1359 rx_npkts = awg_rxintr(sc);
1360 awg_txeof(sc);
1361 if (!if_sendq_empty(ifp))
1362 awg_start_locked(sc);
1363
1364 if (cmd == POLL_AND_CHECK_STATUS) {
1365 val = RD4(sc, EMAC_INT_STA);
1366 if (val != 0)
1367 WR4(sc, EMAC_INT_STA, val);
1368 }
1369
1370 AWG_UNLOCK(sc);
1371
1372 return (rx_npkts);
1373 }
1374 #endif
1375
1376 /*
1377 * syscon functions
1378 */
1379 static uint32_t
syscon_read_emac_clk_reg(device_t dev)1380 syscon_read_emac_clk_reg(device_t dev)
1381 {
1382 struct awg_softc *sc;
1383
1384 sc = device_get_softc(dev);
1385 if (sc->syscon != NULL)
1386 return (SYSCON_READ_4(sc->syscon, EMAC_CLK_REG));
1387 else if (sc->res[_RES_SYSCON] != NULL)
1388 return (bus_read_4(sc->res[_RES_SYSCON], 0));
1389
1390 return (0);
1391 }
1392
1393 static void
syscon_write_emac_clk_reg(device_t dev,uint32_t val)1394 syscon_write_emac_clk_reg(device_t dev, uint32_t val)
1395 {
1396 struct awg_softc *sc;
1397
1398 sc = device_get_softc(dev);
1399 if (sc->syscon != NULL)
1400 SYSCON_WRITE_4(sc->syscon, EMAC_CLK_REG, val);
1401 else if (sc->res[_RES_SYSCON] != NULL)
1402 bus_write_4(sc->res[_RES_SYSCON], 0, val);
1403 }
1404
1405 /*
1406 * PHY functions
1407 */
1408
1409 static phandle_t
awg_get_phy_node(device_t dev)1410 awg_get_phy_node(device_t dev)
1411 {
1412 phandle_t node;
1413 pcell_t phy_handle;
1414
1415 node = ofw_bus_get_node(dev);
1416 if (OF_getencprop(node, "phy-handle", (void *)&phy_handle,
1417 sizeof(phy_handle)) <= 0)
1418 return (0);
1419
1420 return (OF_node_from_xref(phy_handle));
1421 }
1422
1423 static bool
awg_has_internal_phy(device_t dev)1424 awg_has_internal_phy(device_t dev)
1425 {
1426 phandle_t node, phy_node;
1427
1428 node = ofw_bus_get_node(dev);
1429 /* Legacy binding */
1430 if (OF_hasprop(node, "allwinner,use-internal-phy"))
1431 return (true);
1432
1433 phy_node = awg_get_phy_node(dev);
1434 return (phy_node != 0 && ofw_bus_node_is_compatible(OF_parent(phy_node),
1435 "allwinner,sun8i-h3-mdio-internal") != 0);
1436 }
1437
1438 static int
awg_parse_delay(device_t dev,uint32_t * tx_delay,uint32_t * rx_delay)1439 awg_parse_delay(device_t dev, uint32_t *tx_delay, uint32_t *rx_delay)
1440 {
1441 phandle_t node;
1442 uint32_t delay;
1443
1444 if (tx_delay == NULL || rx_delay == NULL)
1445 return (EINVAL);
1446 *tx_delay = *rx_delay = 0;
1447 node = ofw_bus_get_node(dev);
1448
1449 if (OF_getencprop(node, "tx-delay", &delay, sizeof(delay)) >= 0)
1450 *tx_delay = delay;
1451 else if (OF_getencprop(node, "allwinner,tx-delay-ps", &delay,
1452 sizeof(delay)) >= 0) {
1453 if ((delay % 100) != 0) {
1454 device_printf(dev, "tx-delay-ps is not a multiple of 100\n");
1455 return (EDOM);
1456 }
1457 *tx_delay = delay / 100;
1458 }
1459 if (*tx_delay > 7) {
1460 device_printf(dev, "tx-delay out of range\n");
1461 return (ERANGE);
1462 }
1463
1464 if (OF_getencprop(node, "rx-delay", &delay, sizeof(delay)) >= 0)
1465 *rx_delay = delay;
1466 else if (OF_getencprop(node, "allwinner,rx-delay-ps", &delay,
1467 sizeof(delay)) >= 0) {
1468 if ((delay % 100) != 0) {
1469 device_printf(dev, "rx-delay-ps is not within documented domain\n");
1470 return (EDOM);
1471 }
1472 *rx_delay = delay / 100;
1473 }
1474 if (*rx_delay > 31) {
1475 device_printf(dev, "rx-delay out of range\n");
1476 return (ERANGE);
1477 }
1478
1479 return (0);
1480 }
1481
1482 static int
awg_setup_phy(device_t dev)1483 awg_setup_phy(device_t dev)
1484 {
1485 struct awg_softc *sc;
1486 clk_t clk_tx, clk_tx_parent;
1487 const char *tx_parent_name;
1488 char *phy_type;
1489 phandle_t node;
1490 uint32_t reg, tx_delay, rx_delay;
1491 int error;
1492 bool use_syscon;
1493
1494 sc = device_get_softc(dev);
1495 node = ofw_bus_get_node(dev);
1496 use_syscon = false;
1497
1498 if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_type) == 0)
1499 return (0);
1500
1501 if (sc->syscon != NULL || sc->res[_RES_SYSCON] != NULL)
1502 use_syscon = true;
1503
1504 if (bootverbose)
1505 device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type,
1506 use_syscon ? "reg" : "clk");
1507
1508 if (use_syscon) {
1509 /*
1510 * Abstract away writing to syscon for devices like the pine64.
1511 * For the pine64, we get dtb from U-Boot and it still uses the
1512 * legacy setup of specifying syscon register in emac node
1513 * rather than as its own node and using an xref in emac.
1514 * These abstractions can go away once U-Boot dts is up-to-date.
1515 */
1516 reg = syscon_read_emac_clk_reg(dev);
1517 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN);
1518 if (strncmp(phy_type, "rgmii", 5) == 0)
1519 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII;
1520 else if (strcmp(phy_type, "rmii") == 0)
1521 reg |= EMAC_CLK_RMII_EN;
1522 else
1523 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII;
1524
1525 /*
1526 * Fail attach if we fail to parse either of the delay
1527 * parameters. If we don't have the proper delay to write to
1528 * syscon, then awg likely won't function properly anyways.
1529 * Lack of delay is not an error!
1530 */
1531 error = awg_parse_delay(dev, &tx_delay, &rx_delay);
1532 if (error != 0)
1533 goto fail;
1534
1535 /* Default to 0 and we'll increase it if we need to. */
1536 reg &= ~(EMAC_CLK_ETXDC | EMAC_CLK_ERXDC);
1537 if (tx_delay > 0)
1538 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT);
1539 if (rx_delay > 0)
1540 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT);
1541
1542 if (sc->type == EMAC_H3) {
1543 if (awg_has_internal_phy(dev)) {
1544 reg |= EMAC_CLK_EPHY_SELECT;
1545 reg &= ~EMAC_CLK_EPHY_SHUTDOWN;
1546 if (OF_hasprop(node,
1547 "allwinner,leds-active-low"))
1548 reg |= EMAC_CLK_EPHY_LED_POL;
1549 else
1550 reg &= ~EMAC_CLK_EPHY_LED_POL;
1551
1552 /* Set internal PHY addr to 1 */
1553 reg &= ~EMAC_CLK_EPHY_ADDR;
1554 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT);
1555 } else {
1556 reg &= ~EMAC_CLK_EPHY_SELECT;
1557 }
1558 }
1559
1560 if (bootverbose)
1561 device_printf(dev, "EMAC clock: 0x%08x\n", reg);
1562 syscon_write_emac_clk_reg(dev, reg);
1563 } else {
1564 if (strncmp(phy_type, "rgmii", 5) == 0)
1565 tx_parent_name = "emac_int_tx";
1566 else
1567 tx_parent_name = "mii_phy_tx";
1568
1569 /* Get the TX clock */
1570 error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx);
1571 if (error != 0) {
1572 device_printf(dev, "cannot get tx clock\n");
1573 goto fail;
1574 }
1575
1576 /* Find the desired parent clock based on phy-mode property */
1577 error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent);
1578 if (error != 0) {
1579 device_printf(dev, "cannot get clock '%s'\n",
1580 tx_parent_name);
1581 goto fail;
1582 }
1583
1584 /* Set TX clock parent */
1585 error = clk_set_parent_by_clk(clk_tx, clk_tx_parent);
1586 if (error != 0) {
1587 device_printf(dev, "cannot set tx clock parent\n");
1588 goto fail;
1589 }
1590
1591 /* Enable TX clock */
1592 error = clk_enable(clk_tx);
1593 if (error != 0) {
1594 device_printf(dev, "cannot enable tx clock\n");
1595 goto fail;
1596 }
1597 }
1598
1599 error = 0;
1600
1601 fail:
1602 OF_prop_free(phy_type);
1603 return (error);
1604 }
1605
1606 static int
awg_setup_extres(device_t dev)1607 awg_setup_extres(device_t dev)
1608 {
1609 struct awg_softc *sc;
1610 phandle_t node, phy_node;
1611 hwreset_t rst_ahb, rst_ephy;
1612 clk_t clk_ahb, clk_ephy;
1613 regulator_t reg;
1614 uint64_t freq;
1615 int error, div;
1616
1617 sc = device_get_softc(dev);
1618 rst_ahb = rst_ephy = NULL;
1619 clk_ahb = clk_ephy = NULL;
1620 reg = NULL;
1621 node = ofw_bus_get_node(dev);
1622 phy_node = awg_get_phy_node(dev);
1623
1624 if (phy_node == 0 && OF_hasprop(node, "phy-handle")) {
1625 error = ENXIO;
1626 device_printf(dev, "cannot get phy handle\n");
1627 goto fail;
1628 }
1629
1630 /* Get AHB clock and reset resources */
1631 error = hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst_ahb);
1632 if (error != 0)
1633 error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb);
1634 if (error != 0) {
1635 device_printf(dev, "cannot get ahb reset\n");
1636 goto fail;
1637 }
1638 if (hwreset_get_by_ofw_name(dev, 0, "ephy", &rst_ephy) != 0)
1639 if (phy_node == 0 || hwreset_get_by_ofw_idx(dev, phy_node, 0,
1640 &rst_ephy) != 0)
1641 rst_ephy = NULL;
1642 error = clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk_ahb);
1643 if (error != 0)
1644 error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb);
1645 if (error != 0) {
1646 device_printf(dev, "cannot get ahb clock\n");
1647 goto fail;
1648 }
1649 if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0)
1650 if (phy_node == 0 || clk_get_by_ofw_index(dev, phy_node, 0,
1651 &clk_ephy) != 0)
1652 clk_ephy = NULL;
1653
1654 if (OF_hasprop(node, "syscon") && syscon_get_by_ofw_property(dev, node,
1655 "syscon", &sc->syscon) != 0) {
1656 device_printf(dev, "cannot get syscon driver handle\n");
1657 goto fail;
1658 }
1659
1660 /* Configure PHY for MII or RGMII mode */
1661 if (awg_setup_phy(dev) != 0)
1662 goto fail;
1663
1664 /* Enable clocks */
1665 error = clk_enable(clk_ahb);
1666 if (error != 0) {
1667 device_printf(dev, "cannot enable ahb clock\n");
1668 goto fail;
1669 }
1670 if (clk_ephy != NULL) {
1671 error = clk_enable(clk_ephy);
1672 if (error != 0) {
1673 device_printf(dev, "cannot enable ephy clock\n");
1674 goto fail;
1675 }
1676 }
1677
1678 /* De-assert reset */
1679 error = hwreset_deassert(rst_ahb);
1680 if (error != 0) {
1681 device_printf(dev, "cannot de-assert ahb reset\n");
1682 goto fail;
1683 }
1684 if (rst_ephy != NULL) {
1685 /*
1686 * The ephy reset is left de-asserted by U-Boot. Assert it
1687 * here to make sure that we're in a known good state going
1688 * into the PHY reset.
1689 */
1690 hwreset_assert(rst_ephy);
1691 error = hwreset_deassert(rst_ephy);
1692 if (error != 0) {
1693 device_printf(dev, "cannot de-assert ephy reset\n");
1694 goto fail;
1695 }
1696 }
1697
1698 /* Enable PHY regulator if applicable */
1699 if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) {
1700 error = regulator_enable(reg);
1701 if (error != 0) {
1702 device_printf(dev, "cannot enable PHY regulator\n");
1703 goto fail;
1704 }
1705 }
1706
1707 /* Determine MDC clock divide ratio based on AHB clock */
1708 error = clk_get_freq(clk_ahb, &freq);
1709 if (error != 0) {
1710 device_printf(dev, "cannot get AHB clock frequency\n");
1711 goto fail;
1712 }
1713 div = freq / MDIO_FREQ;
1714 if (div <= 16)
1715 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16;
1716 else if (div <= 32)
1717 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32;
1718 else if (div <= 64)
1719 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64;
1720 else if (div <= 128)
1721 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128;
1722 else {
1723 device_printf(dev, "cannot determine MDC clock divide ratio\n");
1724 error = ENXIO;
1725 goto fail;
1726 }
1727
1728 if (bootverbose)
1729 device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n",
1730 (uintmax_t)freq, sc->mdc_div_ratio_m);
1731
1732 return (0);
1733
1734 fail:
1735 if (reg != NULL)
1736 regulator_release(reg);
1737 if (clk_ephy != NULL)
1738 clk_release(clk_ephy);
1739 if (clk_ahb != NULL)
1740 clk_release(clk_ahb);
1741 if (rst_ephy != NULL)
1742 hwreset_release(rst_ephy);
1743 if (rst_ahb != NULL)
1744 hwreset_release(rst_ahb);
1745 return (error);
1746 }
1747
1748 #ifdef AWG_DEBUG
1749 static void
awg_dump_regs(device_t dev)1750 awg_dump_regs(device_t dev)
1751 {
1752 static const struct {
1753 const char *name;
1754 u_int reg;
1755 } regs[] = {
1756 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 },
1757 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 },
1758 { "INT_STA", EMAC_INT_STA },
1759 { "INT_EN", EMAC_INT_EN },
1760 { "TX_CTL_0", EMAC_TX_CTL_0 },
1761 { "TX_CTL_1", EMAC_TX_CTL_1 },
1762 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL },
1763 { "TX_DMA_LIST", EMAC_TX_DMA_LIST },
1764 { "RX_CTL_0", EMAC_RX_CTL_0 },
1765 { "RX_CTL_1", EMAC_RX_CTL_1 },
1766 { "RX_DMA_LIST", EMAC_RX_DMA_LIST },
1767 { "RX_FRM_FLT", EMAC_RX_FRM_FLT },
1768 { "RX_HASH_0", EMAC_RX_HASH_0 },
1769 { "RX_HASH_1", EMAC_RX_HASH_1 },
1770 { "MII_CMD", EMAC_MII_CMD },
1771 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) },
1772 { "ADDR_LOW0", EMAC_ADDR_LOW(0) },
1773 { "TX_DMA_STA", EMAC_TX_DMA_STA },
1774 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC },
1775 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF },
1776 { "RX_DMA_STA", EMAC_RX_DMA_STA },
1777 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC },
1778 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF },
1779 { "RGMII_STA", EMAC_RGMII_STA },
1780 };
1781 struct awg_softc *sc;
1782 unsigned int n;
1783
1784 sc = device_get_softc(dev);
1785
1786 for (n = 0; n < nitems(regs); n++)
1787 device_printf(dev, " %-20s %08x\n", regs[n].name,
1788 RD4(sc, regs[n].reg));
1789 }
1790 #endif
1791
1792 #define GPIO_ACTIVE_LOW 1
1793
1794 static int
awg_phy_reset(device_t dev)1795 awg_phy_reset(device_t dev)
1796 {
1797 pcell_t gpio_prop[4], delay_prop[3];
1798 phandle_t node, gpio_node;
1799 device_t gpio;
1800 uint32_t pin, flags;
1801 uint32_t pin_value;
1802
1803 node = ofw_bus_get_node(dev);
1804 if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop,
1805 sizeof(gpio_prop)) <= 0)
1806 return (0);
1807
1808 if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop,
1809 sizeof(delay_prop)) <= 0)
1810 return (ENXIO);
1811
1812 gpio_node = OF_node_from_xref(gpio_prop[0]);
1813 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL)
1814 return (ENXIO);
1815
1816 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1,
1817 gpio_prop + 1, &pin, &flags) != 0)
1818 return (ENXIO);
1819
1820 pin_value = GPIO_PIN_LOW;
1821 if (OF_hasprop(node, "allwinner,reset-active-low"))
1822 pin_value = GPIO_PIN_HIGH;
1823
1824 if (flags & GPIO_ACTIVE_LOW)
1825 pin_value = !pin_value;
1826
1827 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
1828 GPIO_PIN_SET(gpio, pin, pin_value);
1829 DELAY(delay_prop[0]);
1830 GPIO_PIN_SET(gpio, pin, !pin_value);
1831 DELAY(delay_prop[1]);
1832 GPIO_PIN_SET(gpio, pin, pin_value);
1833 DELAY(delay_prop[2]);
1834
1835 return (0);
1836 }
1837
1838 static int
awg_reset(device_t dev)1839 awg_reset(device_t dev)
1840 {
1841 struct awg_softc *sc;
1842 int retry;
1843
1844 sc = device_get_softc(dev);
1845
1846 /* Reset PHY if necessary */
1847 if (awg_phy_reset(dev) != 0) {
1848 device_printf(dev, "failed to reset PHY\n");
1849 return (ENXIO);
1850 }
1851
1852 /* Soft reset all registers and logic */
1853 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
1854
1855 /* Wait for soft reset bit to self-clear */
1856 for (retry = SOFT_RST_RETRY; retry > 0; retry--) {
1857 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0)
1858 break;
1859 DELAY(10);
1860 }
1861 if (retry == 0) {
1862 device_printf(dev, "soft reset timed out\n");
1863 #ifdef AWG_DEBUG
1864 awg_dump_regs(dev);
1865 #endif
1866 return (ETIMEDOUT);
1867 }
1868
1869 return (0);
1870 }
1871
1872 /*
1873 * Stats
1874 */
1875
1876 static void
awg_tick(void * softc)1877 awg_tick(void *softc)
1878 {
1879 struct awg_softc *sc;
1880 struct mii_data *mii;
1881 if_t ifp;
1882 int link;
1883
1884 sc = softc;
1885 ifp = sc->ifp;
1886 mii = device_get_softc(sc->miibus);
1887
1888 AWG_ASSERT_LOCKED(sc);
1889
1890 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1891 return;
1892
1893 link = sc->link;
1894 mii_tick(mii);
1895 if (sc->link && !link)
1896 awg_start_locked(sc);
1897
1898 callout_reset(&sc->stat_ch, hz, awg_tick, sc);
1899 }
1900
1901 /*
1902 * Probe/attach functions
1903 */
1904
1905 static int
awg_probe(device_t dev)1906 awg_probe(device_t dev)
1907 {
1908 if (!ofw_bus_status_okay(dev))
1909 return (ENXIO);
1910
1911 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1912 return (ENXIO);
1913
1914 device_set_desc(dev, "Allwinner Gigabit Ethernet");
1915 return (BUS_PROBE_DEFAULT);
1916 }
1917
1918 static int
awg_attach(device_t dev)1919 awg_attach(device_t dev)
1920 {
1921 uint8_t eaddr[ETHER_ADDR_LEN];
1922 struct awg_softc *sc;
1923 int error;
1924
1925 sc = device_get_softc(dev);
1926 sc->dev = dev;
1927 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1928
1929 if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) {
1930 device_printf(dev, "cannot allocate resources for device\n");
1931 return (ENXIO);
1932 }
1933
1934 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF);
1935 callout_init_mtx(&sc->stat_ch, &sc->mtx, 0);
1936
1937 /* Setup clocks and regulators */
1938 error = awg_setup_extres(dev);
1939 if (error != 0)
1940 return (error);
1941
1942 /* Read MAC address before resetting the chip */
1943 awg_get_eaddr(dev, eaddr);
1944
1945 /* Soft reset EMAC core */
1946 error = awg_reset(dev);
1947 if (error != 0)
1948 return (error);
1949
1950 /* Setup DMA descriptors */
1951 error = awg_setup_dma(dev);
1952 if (error != 0)
1953 return (error);
1954
1955 /* Install interrupt handler */
1956 error = bus_setup_intr(dev, sc->res[_RES_IRQ],
1957 INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih);
1958 if (error != 0) {
1959 device_printf(dev, "cannot setup interrupt handler\n");
1960 return (error);
1961 }
1962
1963 /* Setup ethernet interface */
1964 sc->ifp = if_alloc(IFT_ETHER);
1965 if_setsoftc(sc->ifp, sc);
1966 if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev));
1967 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1968 if_setstartfn(sc->ifp, awg_start);
1969 if_setioctlfn(sc->ifp, awg_ioctl);
1970 if_setinitfn(sc->ifp, awg_init);
1971 if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1);
1972 if_setsendqready(sc->ifp);
1973 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP);
1974 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM);
1975 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp));
1976 #ifdef DEVICE_POLLING
1977 if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0);
1978 #endif
1979
1980 /* Attach MII driver */
1981 error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change,
1982 awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
1983 MIIF_DOPAUSE);
1984 if (error != 0) {
1985 device_printf(dev, "cannot attach PHY\n");
1986 return (error);
1987 }
1988
1989 /* Attach ethernet interface */
1990 ether_ifattach(sc->ifp, eaddr);
1991
1992 return (0);
1993 }
1994
1995 static device_method_t awg_methods[] = {
1996 /* Device interface */
1997 DEVMETHOD(device_probe, awg_probe),
1998 DEVMETHOD(device_attach, awg_attach),
1999
2000 /* MII interface */
2001 DEVMETHOD(miibus_readreg, awg_miibus_readreg),
2002 DEVMETHOD(miibus_writereg, awg_miibus_writereg),
2003 DEVMETHOD(miibus_statchg, awg_miibus_statchg),
2004
2005 DEVMETHOD_END
2006 };
2007
2008 static driver_t awg_driver = {
2009 "awg",
2010 awg_methods,
2011 sizeof(struct awg_softc),
2012 };
2013
2014 DRIVER_MODULE(awg, simplebus, awg_driver, 0, 0);
2015 DRIVER_MODULE(miibus, awg, miibus_driver, 0, 0);
2016 MODULE_DEPEND(awg, ether, 1, 1, 1);
2017 MODULE_DEPEND(awg, miibus, 1, 1, 1);
2018 MODULE_DEPEND(awg, aw_sid, 1, 1, 1);
2019 SIMPLEBUS_PNP_INFO(compat_data);
2020