1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009, Oleksandr Tymoshenko 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef __IF_ARGEVAR_H__ 33 #define __IF_ARGEVAR_H__ 34 35 #define ARGE_NPHY 32 36 #define ARGE_TX_RING_COUNT 128 37 #define ARGE_RX_RING_COUNT 128 38 #define ARGE_RX_DMA_SIZE ARGE_RX_RING_COUNT * sizeof(struct arge_desc) 39 #define ARGE_TX_DMA_SIZE ARGE_TX_RING_COUNT * sizeof(struct arge_desc) 40 #define ARGE_MAXFRAGS 8 41 #define ARGE_RING_ALIGN sizeof(struct arge_desc) 42 #define ARGE_RX_ALIGN_4BYTE sizeof(uint32_t) 43 #define ARGE_RX_ALIGN_1BYTE sizeof(char) 44 #define ARGE_TX_ALIGN_4BYTE sizeof(uint32_t) 45 #define ARGE_TX_ALIGN_1BYTE sizeof(char) 46 #define ARGE_MAXFRAGS 8 47 #define ARGE_TX_RING_ADDR(sc, i) \ 48 ((sc)->arge_rdata.arge_tx_ring_paddr + sizeof(struct arge_desc) * (i)) 49 #define ARGE_RX_RING_ADDR(sc, i) \ 50 ((sc)->arge_rdata.arge_rx_ring_paddr + sizeof(struct arge_desc) * (i)) 51 #define ARGE_INC(x,y) (x) = (((x) + 1) % y) 52 53 #define ARGE_MII_TIMEOUT 1000 54 55 #define ARGE_LOCK(_sc) mtx_lock(&(_sc)->arge_mtx) 56 #define ARGE_UNLOCK(_sc) mtx_unlock(&(_sc)->arge_mtx) 57 #define ARGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->arge_mtx, MA_OWNED) 58 59 /* 60 * register space access macros 61 */ 62 #define ARGE_BARRIER_READ(sc) bus_barrier(sc->arge_res, 0, 0, \ 63 BUS_SPACE_BARRIER_READ) 64 #define ARGE_BARRIER_WRITE(sc) bus_barrier(sc->arge_res, 0, 0, \ 65 BUS_SPACE_BARRIER_WRITE) 66 #define ARGE_BARRIER_RW(sc) bus_barrier(sc->arge_res, 0, 0, \ 67 BUS_SPACE_BARRIER_READ | \ 68 BUS_SPACE_BARRIER_WRITE) 69 #define ARGE_WRITE(sc, reg, val) do { \ 70 bus_write_4(sc->arge_res, (reg), (val)); \ 71 ARGE_BARRIER_WRITE((sc)); \ 72 ARGE_READ((sc), (reg)); \ 73 } while (0) 74 #define ARGE_READ(sc, reg) bus_read_4(sc->arge_res, (reg)) 75 76 #define ARGE_SET_BITS(sc, reg, bits) \ 77 ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) | (bits)) 78 79 #define ARGE_CLEAR_BITS(sc, reg, bits) \ 80 ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) & ~(bits)) 81 82 /* 83 * The linux driver code for the MDIO bus does a read-after-write 84 * which seems to be required on MIPS74k platforms for correct 85 * behaviour. 86 * 87 * So, ARGE_WRITE() does the write + barrier, and the following 88 * ARGE_READ() seems to flush the thing all the way through the device 89 * FIFO(s) before we continue issuing MDIO bus updates. 90 */ 91 #define ARGE_MDIO_WRITE(_sc, _reg, _val) \ 92 ARGE_WRITE((_sc), (_reg), (_val)) 93 #define ARGE_MDIO_READ(_sc, _reg) \ 94 ARGE_READ((_sc), (_reg)) 95 #define ARGE_MDIO_BARRIER_READ(_sc) ARGE_BARRIER_READ(_sc) 96 #define ARGE_MDIO_BARRIER_WRITE(_sc) ARGE_BARRIER_WRITE(_sc) 97 #define ARGE_MDIO_BARRIER_RW(_sc) ARGE_BARRIER_RW(_sc) 98 99 #define ARGE_DESC_EMPTY (1U << 31) 100 #define ARGE_DESC_MORE (1 << 24) 101 #define ARGE_DESC_SIZE_MASK ((1 << 12) - 1) 102 #define ARGE_DMASIZE(len) ((len) & ARGE_DESC_SIZE_MASK) 103 struct arge_desc { 104 uint32_t packet_addr; 105 uint32_t packet_ctrl; 106 uint32_t next_desc; 107 uint32_t padding; 108 }; 109 110 struct arge_txdesc { 111 struct mbuf *tx_m; 112 bus_dmamap_t tx_dmamap; 113 }; 114 115 struct arge_rxdesc { 116 struct mbuf *rx_m; 117 bus_dmamap_t rx_dmamap; 118 struct arge_desc *desc; 119 }; 120 121 struct arge_chain_data { 122 bus_dma_tag_t arge_parent_tag; 123 bus_dma_tag_t arge_tx_tag; 124 struct arge_txdesc arge_txdesc[ARGE_TX_RING_COUNT]; 125 bus_dma_tag_t arge_rx_tag; 126 struct arge_rxdesc arge_rxdesc[ARGE_RX_RING_COUNT]; 127 bus_dma_tag_t arge_tx_ring_tag; 128 bus_dma_tag_t arge_rx_ring_tag; 129 bus_dmamap_t arge_tx_ring_map; 130 bus_dmamap_t arge_rx_ring_map; 131 bus_dmamap_t arge_rx_sparemap; 132 int arge_tx_prod; 133 int arge_tx_cons; 134 int arge_tx_cnt; 135 int arge_rx_cons; 136 }; 137 138 struct arge_ring_data { 139 struct arge_desc *arge_rx_ring; 140 struct arge_desc *arge_tx_ring; 141 bus_addr_t arge_rx_ring_paddr; 142 bus_addr_t arge_tx_ring_paddr; 143 }; 144 145 /* 146 * Allow PLL values to be overridden. 147 */ 148 struct arge_pll_data { 149 uint32_t pll_10; 150 uint32_t pll_100; 151 uint32_t pll_1000; 152 }; 153 154 /* 155 * Hardware specific behaviours. 156 */ 157 158 /* 159 * Older chips support 4 byte only transmit and receive 160 * addresses. 161 * 162 * Later chips support arbitrary TX and later later, 163 * arbitrary RX addresses. 164 */ 165 #define ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE 0x00000001 166 #define ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE 0x00000002 167 #define ARGE_HW_FLG_TX_DESC_ALIGN_1BYTE 0x00000004 168 #define ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE 0x00000008 169 170 struct arge_softc { 171 struct ifnet *arge_ifp; /* interface info */ 172 device_t arge_dev; 173 struct ifmedia arge_ifmedia; 174 /* 175 * Media & duples settings for multiPHY MAC 176 */ 177 uint32_t arge_media_type; 178 uint32_t arge_duplex_mode; 179 uint32_t arge_phymask; 180 uint8_t arge_eaddr[ETHER_ADDR_LEN]; 181 struct resource *arge_res; 182 int arge_rid; 183 struct resource *arge_irq; 184 void *arge_intrhand; 185 device_t arge_miibus; 186 device_t arge_miiproxy; 187 ar71xx_mii_mode arge_miicfg; 188 struct arge_pll_data arge_pllcfg; 189 bus_dma_tag_t arge_parent_tag; 190 bus_dma_tag_t arge_tag; 191 struct mtx arge_mtx; 192 struct callout arge_stat_callout; 193 struct task arge_link_task; 194 struct arge_chain_data arge_cdata; 195 struct arge_ring_data arge_rdata; 196 int arge_link_status; 197 int arge_detach; 198 uint32_t arge_intr_status; 199 int arge_mac_unit; 200 int arge_if_flags; 201 uint32_t arge_hw_flags; 202 uint32_t arge_debug; 203 uint32_t arge_mdiofreq; 204 struct { 205 uint32_t tx_pkts_unaligned; 206 uint32_t tx_pkts_unaligned_start; 207 uint32_t tx_pkts_unaligned_len; 208 uint32_t tx_pkts_unaligned_tooshort; 209 uint32_t tx_pkts_nosegs; 210 uint32_t tx_pkts_aligned; 211 uint32_t rx_overflow; 212 uint32_t tx_underflow; 213 uint32_t intr_stray; 214 uint32_t intr_stray2; 215 uint32_t intr_ok; 216 } stats; 217 struct { 218 uint32_t count[32]; 219 } intr_stats; 220 }; 221 222 #endif /* __IF_ARGEVAR_H__ */ 223