1 /*-
2 * Copyright (c) 2015 Luiz Otavio O Souza <[email protected]> All rights reserved.
3 * Copyright (c) 2014-2015 M. Warner Losh <[email protected]>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * The magic-bit-bang sequence used in this code may be based on a linux
27 * platform driver in the Allwinner SDK from Allwinner Technology Co., Ltd.
28 * www.allwinnertech.com, by Daniel Wang <[email protected]>
29 * though none of the original code was copied.
30 */
31
32 #include "opt_bus.h"
33
34 #include <sys/cdefs.h>
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38 #include <sys/rman.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
41
42 #include <machine/bus.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
45
46 #include <dev/ahci/ahci.h>
47 #include <dev/extres/clk/clk.h>
48 #include <dev/extres/regulator/regulator.h>
49
50 /*
51 * Allwinner a1x/a2x/a8x SATA attachment. This is just the AHCI register
52 * set with a few extra implementation-specific registers that need to
53 * be accounted for. There's only one PHY in the system, and it needs
54 * to be trained to bring the link up. In addition, there's some DMA
55 * specific things that need to be done as well. These things are also
56 * just about completely undocumented, except in ugly code in the Linux
57 * SDK Allwinner releases.
58 */
59
60 /* BITx -- Unknown bit that needs to be set/cleared at position x */
61 /* UFx -- Uknown multi-bit field frobbed during init */
62 #define AHCI_BISTAFR 0x00A0
63 #define AHCI_BISTCR 0x00A4
64 #define AHCI_BISTFCTR 0x00A8
65 #define AHCI_BISTSR 0x00AC
66 #define AHCI_BISTDECR 0x00B0
67 #define AHCI_DIAGNR 0x00B4
68 #define AHCI_DIAGNR1 0x00B8
69 #define AHCI_OOBR 0x00BC
70 #define AHCI_PHYCS0R 0x00C0
71 /* Bits 0..17 are a mystery */
72 #define PHYCS0R_BIT18 (1 << 18)
73 #define PHYCS0R_POWER_ENABLE (1 << 19)
74 #define PHYCS0R_UF1_MASK (7 << 20) /* Unknown Field 1 */
75 #define PHYCS0R_UF1_INIT (3 << 20)
76 #define PHYCS0R_BIT23 (1 << 23)
77 #define PHYCS0R_UF2_MASK (7 << 24) /* Uknown Field 2 */
78 #define PHYCS0R_UF2_INIT (5 << 24)
79 /* Bit 27 mystery */
80 #define PHYCS0R_POWER_STATUS_MASK (7 << 28)
81 #define PHYCS0R_PS_GOOD (2 << 28)
82 /* Bit 31 mystery */
83 #define AHCI_PHYCS1R 0x00C4
84 /* Bits 0..5 are a mystery */
85 #define PHYCS1R_UF1_MASK (3 << 6)
86 #define PHYCS1R_UF1_INIT (2 << 6)
87 #define PHYCS1R_UF2_MASK (0x1f << 8)
88 #define PHYCS1R_UF2_INIT (6 << 8)
89 /* Bits 13..14 are a mystery */
90 #define PHYCS1R_BIT15 (1 << 15)
91 #define PHYCS1R_UF3_MASK (3 << 16)
92 #define PHYCS1R_UF3_INIT (2 << 16)
93 /* Bit 18 mystery */
94 #define PHYCS1R_HIGHZ (1 << 19)
95 /* Bits 20..27 mystery */
96 #define PHYCS1R_BIT28 (1 << 28)
97 /* Bits 29..31 mystery */
98 #define AHCI_PHYCS2R 0x00C8
99 /* bits 0..4 mystery */
100 #define PHYCS2R_UF1_MASK (0x1f << 5)
101 #define PHYCS2R_UF1_INIT (0x19 << 5)
102 /* Bits 10..23 mystery */
103 #define PHYCS2R_CALIBRATE (1 << 24)
104 /* Bits 25..31 mystery */
105 #define AHCI_TIMER1MS 0x00E0
106 #define AHCI_GPARAM1R 0x00E8
107 #define AHCI_GPARAM2R 0x00EC
108 #define AHCI_PPARAMR 0x00F0
109 #define AHCI_TESTR 0x00F4
110 #define AHCI_VERSIONR 0x00F8
111 #define AHCI_IDR 0x00FC
112 #define AHCI_RWCR 0x00FC
113
114 #define AHCI_P0DMACR 0x0070
115 #define AHCI_P0PHYCR 0x0078
116 #define AHCI_P0PHYSR 0x007C
117
118 #define PLL_FREQ 100000000
119
120 struct ahci_a10_softc {
121 struct ahci_controller ahci_ctlr;
122 regulator_t ahci_reg;
123 clk_t clk_pll;
124 clk_t clk_gate;
125 };
126
127 static void inline
ahci_set(struct resource * m,bus_size_t off,uint32_t set)128 ahci_set(struct resource *m, bus_size_t off, uint32_t set)
129 {
130 uint32_t val = ATA_INL(m, off);
131
132 val |= set;
133 ATA_OUTL(m, off, val);
134 }
135
136 static void inline
ahci_clr(struct resource * m,bus_size_t off,uint32_t clr)137 ahci_clr(struct resource *m, bus_size_t off, uint32_t clr)
138 {
139 uint32_t val = ATA_INL(m, off);
140
141 val &= ~clr;
142 ATA_OUTL(m, off, val);
143 }
144
145 static void inline
ahci_mask_set(struct resource * m,bus_size_t off,uint32_t mask,uint32_t set)146 ahci_mask_set(struct resource *m, bus_size_t off, uint32_t mask, uint32_t set)
147 {
148 uint32_t val = ATA_INL(m, off);
149
150 val &= mask;
151 val |= set;
152 ATA_OUTL(m, off, val);
153 }
154
155 /*
156 * Should this be phy_reset or phy_init
157 */
158 #define PHY_RESET_TIMEOUT 1000
159 static void
ahci_a10_phy_reset(device_t dev)160 ahci_a10_phy_reset(device_t dev)
161 {
162 uint32_t to, val;
163 struct ahci_controller *ctlr = device_get_softc(dev);
164
165 /*
166 * Here starts the magic -- most of the comments are based
167 * on guesswork, names of routines and printf error
168 * messages. The code works, but it will do that even if the
169 * comments are 100% BS.
170 */
171
172 /*
173 * Lock out other access while we initialize. Or at least that
174 * seems to be the case based on Linux SDK #defines. Maybe this
175 * put things into reset?
176 */
177 ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 0);
178 DELAY(100);
179
180 /*
181 * Set bit 19 in PHYCS1R. Guessing this disables driving the PHY
182 * port for a bit while we reset things.
183 */
184 ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ);
185
186 /*
187 * Frob PHYCS0R...
188 */
189 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R,
190 ~PHYCS0R_UF2_MASK,
191 PHYCS0R_UF2_INIT | PHYCS0R_BIT23 | PHYCS0R_BIT18);
192
193 /*
194 * Set three fields in PHYCS1R
195 */
196 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS1R,
197 ~(PHYCS1R_UF1_MASK | PHYCS1R_UF2_MASK | PHYCS1R_UF3_MASK),
198 PHYCS1R_UF1_INIT | PHYCS1R_UF2_INIT | PHYCS1R_UF3_INIT);
199
200 /*
201 * Two more mystery bits in PHYCS1R. -- can these be combined above?
202 */
203 ahci_set(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_BIT15 | PHYCS1R_BIT28);
204
205 /*
206 * Now clear that first mysery bit. Perhaps this starts
207 * driving the PHY again so we can power it up and start
208 * talking to the SATA drive, if any below.
209 */
210 ahci_clr(ctlr->r_mem, AHCI_PHYCS1R, PHYCS1R_HIGHZ);
211
212 /*
213 * Frob PHYCS0R again...
214 */
215 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS0R,
216 ~PHYCS0R_UF1_MASK, PHYCS0R_UF1_INIT);
217
218 /*
219 * Frob PHYCS2R, because 25 means something?
220 */
221 ahci_mask_set(ctlr->r_mem, AHCI_PHYCS2R, ~PHYCS2R_UF1_MASK,
222 PHYCS2R_UF1_INIT);
223
224 DELAY(100); /* WAG */
225
226 /*
227 * Turn on the power to the PHY and wait for it to report back
228 * good?
229 */
230 ahci_set(ctlr->r_mem, AHCI_PHYCS0R, PHYCS0R_POWER_ENABLE);
231 for (to = PHY_RESET_TIMEOUT; to > 0; to--) {
232 val = ATA_INL(ctlr->r_mem, AHCI_PHYCS0R);
233 if ((val & PHYCS0R_POWER_STATUS_MASK) == PHYCS0R_PS_GOOD)
234 break;
235 DELAY(10);
236 }
237 if (to == 0 && bootverbose)
238 device_printf(dev, "PHY Power Failed PHYCS0R = %#x\n", val);
239
240 /*
241 * Calibrate the clocks between the device and the host. This appears
242 * to be an automated process that clears the bit when it is done.
243 */
244 ahci_set(ctlr->r_mem, AHCI_PHYCS2R, PHYCS2R_CALIBRATE);
245 for (to = PHY_RESET_TIMEOUT; to > 0; to--) {
246 val = ATA_INL(ctlr->r_mem, AHCI_PHYCS2R);
247 if ((val & PHYCS2R_CALIBRATE) == 0)
248 break;
249 DELAY(10);
250 }
251 if (to == 0 && bootverbose)
252 device_printf(dev, "PHY Cal Failed PHYCS2R %#x\n", val);
253
254 /*
255 * OK, let things settle down a bit.
256 */
257 DELAY(1000);
258
259 /*
260 * Go back into normal mode now that we've calibrated the PHY.
261 */
262 ATA_OUTL(ctlr->r_mem, AHCI_RWCR, 7);
263 }
264
265 static void
ahci_a10_ch_start(struct ahci_channel * ch)266 ahci_a10_ch_start(struct ahci_channel *ch)
267 {
268 uint32_t reg;
269
270 /*
271 * Magical values from Allwinner SDK, setup the DMA before start
272 * operations on this channel.
273 */
274 reg = ATA_INL(ch->r_mem, AHCI_P0DMACR);
275 reg &= ~0xff00;
276 reg |= 0x4400;
277 ATA_OUTL(ch->r_mem, AHCI_P0DMACR, reg);
278 }
279
280 static int
ahci_a10_ctlr_reset(device_t dev)281 ahci_a10_ctlr_reset(device_t dev)
282 {
283
284 ahci_a10_phy_reset(dev);
285
286 return (ahci_ctlr_reset(dev));
287 }
288
289 static int
ahci_a10_probe(device_t dev)290 ahci_a10_probe(device_t dev)
291 {
292
293 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-ahci"))
294 return (ENXIO);
295 device_set_desc(dev, "Allwinner Integrated AHCI controller");
296
297 return (BUS_PROBE_DEFAULT);
298 }
299
300 static int
ahci_a10_attach(device_t dev)301 ahci_a10_attach(device_t dev)
302 {
303 int error;
304 struct ahci_a10_softc *sc;
305 struct ahci_controller *ctlr;
306
307 sc = device_get_softc(dev);
308 ctlr = &sc->ahci_ctlr;
309
310 ctlr->quirks = AHCI_Q_NOPMP;
311 ctlr->vendorid = 0;
312 ctlr->deviceid = 0;
313 ctlr->subvendorid = 0;
314 ctlr->subdeviceid = 0;
315 ctlr->r_rid = 0;
316 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
317 &ctlr->r_rid, RF_ACTIVE)))
318 return (ENXIO);
319
320 /* Enable the (optional) regulator */
321 if (regulator_get_by_ofw_property(dev, 0, "target-supply",
322 &sc->ahci_reg) == 0) {
323 error = regulator_enable(sc->ahci_reg);
324 if (error != 0) {
325 device_printf(dev, "Could not enable regulator\n");
326 goto fail;
327 }
328 }
329
330 /* Enable clocks */
331 error = clk_get_by_ofw_index(dev, 0, 0, &sc->clk_gate);
332 if (error != 0) {
333 device_printf(dev, "Cannot get gate clock\n");
334 goto fail;
335 }
336 error = clk_get_by_ofw_index(dev, 0, 1, &sc->clk_pll);
337 if (error != 0) {
338 device_printf(dev, "Cannot get PLL clock\n");
339 goto fail;
340 }
341 error = clk_set_freq(sc->clk_pll, PLL_FREQ, CLK_SET_ROUND_DOWN);
342 if (error != 0) {
343 device_printf(dev, "Cannot set PLL frequency\n");
344 goto fail;
345 }
346 error = clk_enable(sc->clk_pll);
347 if (error != 0) {
348 device_printf(dev, "Cannot enable PLL\n");
349 goto fail;
350 }
351 error = clk_enable(sc->clk_gate);
352 if (error != 0) {
353 device_printf(dev, "Cannot enable clk gate\n");
354 goto fail;
355 }
356
357 /* Reset controller */
358 if ((error = ahci_a10_ctlr_reset(dev)) != 0)
359 goto fail;
360
361 /*
362 * No MSI registers on this platform.
363 */
364 ctlr->msi = 0;
365 ctlr->numirqs = 1;
366
367 /* Channel start callback(). */
368 ctlr->ch_start = ahci_a10_ch_start;
369
370 /*
371 * Note: ahci_attach will release ctlr->r_mem on errors automatically
372 */
373 return (ahci_attach(dev));
374
375 fail:
376 if (sc->ahci_reg != NULL)
377 regulator_disable(sc->ahci_reg);
378 if (sc->clk_gate != NULL)
379 clk_release(sc->clk_gate);
380 if (sc->clk_pll != NULL)
381 clk_release(sc->clk_pll);
382 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
383 return (error);
384 }
385
386 static int
ahci_a10_detach(device_t dev)387 ahci_a10_detach(device_t dev)
388 {
389 struct ahci_a10_softc *sc;
390 struct ahci_controller *ctlr;
391
392 sc = device_get_softc(dev);
393 ctlr = &sc->ahci_ctlr;
394
395 if (sc->ahci_reg != NULL)
396 regulator_disable(sc->ahci_reg);
397 if (sc->clk_gate != NULL)
398 clk_release(sc->clk_gate);
399 if (sc->clk_pll != NULL)
400 clk_release(sc->clk_pll);
401 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
402 return (ahci_detach(dev));
403 }
404
405 static device_method_t ahci_ata_methods[] = {
406 DEVMETHOD(device_probe, ahci_a10_probe),
407 DEVMETHOD(device_attach, ahci_a10_attach),
408 DEVMETHOD(device_detach, ahci_a10_detach),
409 DEVMETHOD(bus_print_child, ahci_print_child),
410 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
411 DEVMETHOD(bus_release_resource, ahci_release_resource),
412 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
413 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
414 DEVMETHOD(bus_child_location, ahci_child_location),
415 DEVMETHOD_END
416 };
417
418 static driver_t ahci_ata_driver = {
419 "ahci",
420 ahci_ata_methods,
421 sizeof(struct ahci_a10_softc)
422 };
423
424 DRIVER_MODULE(a10_ahci, simplebus, ahci_ata_driver, 0, 0);
425