1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
3 *
4 * Eric Davis <[email protected]>
5 * David Christensen <[email protected]>
6 * Gary Zambrano <[email protected]>
7 *
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
11 * www.cavium.com
12 */
13
14 #define BNX2X_DRIVER_VERSION "1.78.18"
15
16 #include "bnx2x.h"
17 #include "bnx2x_vfpf.h"
18 #include "ecore_sp.h"
19 #include "ecore_init.h"
20 #include "ecore_init_ops.h"
21
22 #include "rte_version.h"
23
24 #include <sys/types.h>
25 #include <sys/stat.h>
26 #include <arpa/inet.h>
27 #include <fcntl.h>
28 #include <zlib.h>
29
30 #include <rte_bitops.h>
31 #include <rte_string_fns.h>
32
33 #include "eal_firmware.h"
34
35 #define BNX2X_PMD_VER_PREFIX "BNX2X PMD"
36 #define BNX2X_PMD_VERSION_MAJOR 1
37 #define BNX2X_PMD_VERSION_MINOR 1
38 #define BNX2X_PMD_VERSION_REVISION 0
39 #define BNX2X_PMD_VERSION_PATCH 1
40
41 static inline const char *
bnx2x_pmd_version(void)42 bnx2x_pmd_version(void)
43 {
44 static char version[32];
45
46 snprintf(version, sizeof(version), "%s %s_%d.%d.%d.%d",
47 BNX2X_PMD_VER_PREFIX,
48 BNX2X_DRIVER_VERSION,
49 BNX2X_PMD_VERSION_MAJOR,
50 BNX2X_PMD_VERSION_MINOR,
51 BNX2X_PMD_VERSION_REVISION,
52 BNX2X_PMD_VERSION_PATCH);
53
54 return version;
55 }
56
57 static z_stream zlib_stream;
58
59 #define EVL_VLID_MASK 0x0FFF
60
61 #define BNX2X_DEF_SB_ATT_IDX 0x0001
62 #define BNX2X_DEF_SB_IDX 0x0002
63
64 /*
65 * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per
66 * function HW initialization.
67 */
68 #define FLR_WAIT_USEC 10000 /* 10 msecs */
69 #define FLR_WAIT_INTERVAL 50 /* usecs */
70 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
71
72 struct pbf_pN_buf_regs {
73 int pN;
74 uint32_t init_crd;
75 uint32_t crd;
76 uint32_t crd_freed;
77 };
78
79 struct pbf_pN_cmd_regs {
80 int pN;
81 uint32_t lines_occup;
82 uint32_t lines_freed;
83 };
84
85 /* resources needed for unloading a previously loaded device */
86
87 #define BNX2X_PREV_WAIT_NEEDED 1
88 rte_spinlock_t bnx2x_prev_mtx;
89 struct bnx2x_prev_list_node {
90 LIST_ENTRY(bnx2x_prev_list_node) node;
91 uint8_t bus;
92 uint8_t slot;
93 uint8_t path;
94 uint8_t aer;
95 uint8_t undi;
96 };
97
98 static LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list
99 = LIST_HEAD_INITIALIZER(bnx2x_prev_list);
100
101 static int load_count[2][3] = { { 0 } };
102 /* per-path: 0-common, 1-port0, 2-port1 */
103
104 static void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,
105 uint8_t cmng_type);
106 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);
107 static void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,
108 uint8_t port);
109 static void bnx2x_set_reset_global(struct bnx2x_softc *sc);
110 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);
111 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);
112 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);
113 static uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,
114 uint8_t print);
115 static void bnx2x_int_disable(struct bnx2x_softc *sc);
116 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc);
117 static void bnx2x_pf_disable(struct bnx2x_softc *sc);
118 static void bnx2x_update_rx_prod(struct bnx2x_softc *sc,
119 struct bnx2x_fastpath *fp,
120 uint16_t rx_bd_prod, uint16_t rx_cq_prod);
121 static void bnx2x_link_report_locked(struct bnx2x_softc *sc);
122 static void bnx2x_link_report(struct bnx2x_softc *sc);
123 void bnx2x_link_status_update(struct bnx2x_softc *sc);
124 static int bnx2x_alloc_mem(struct bnx2x_softc *sc);
125 static void bnx2x_free_mem(struct bnx2x_softc *sc);
126 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);
127 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);
128 static __rte_noinline
129 int bnx2x_nic_load(struct bnx2x_softc *sc);
130
131 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);
132 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp);
133 static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,
134 uint8_t storm, uint16_t index, uint8_t op,
135 uint8_t update);
136
bnx2x_cmpxchg(volatile int * addr,int old,int new)137 int bnx2x_cmpxchg(volatile int *addr, int old, int new)
138 {
139 return __sync_val_compare_and_swap(addr, old, new);
140 }
141
142 int
bnx2x_dma_alloc(struct bnx2x_softc * sc,size_t size,struct bnx2x_dma * dma,const char * msg,uint32_t align)143 bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,
144 const char *msg, uint32_t align)
145 {
146 char mz_name[RTE_MEMZONE_NAMESIZE];
147 const struct rte_memzone *z;
148
149 dma->sc = sc;
150 if (IS_PF(sc))
151 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, SC_ABS_FUNC(sc), msg,
152 rte_get_timer_cycles());
153 else
154 snprintf(mz_name, sizeof(mz_name), "bnx2x%d_%s_%" PRIx64, sc->pcie_device, msg,
155 rte_get_timer_cycles());
156
157 /* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */
158 z = rte_memzone_reserve_aligned(mz_name, (uint64_t)size,
159 SOCKET_ID_ANY,
160 RTE_MEMZONE_IOVA_CONTIG, align);
161 if (z == NULL) {
162 PMD_DRV_LOG(ERR, sc, "DMA alloc failed for %s", msg);
163 return -ENOMEM;
164 }
165 dma->paddr = (uint64_t) z->iova;
166 dma->vaddr = z->addr;
167 dma->mzone = (const void *)z;
168
169 PMD_DRV_LOG(DEBUG, sc,
170 "%s: virt=%p phys=%" PRIx64, msg, dma->vaddr, dma->paddr);
171
172 return 0;
173 }
174
bnx2x_dma_free(struct bnx2x_dma * dma)175 void bnx2x_dma_free(struct bnx2x_dma *dma)
176 {
177 if (dma->mzone == NULL)
178 return;
179
180 rte_memzone_free((const struct rte_memzone *)dma->mzone);
181 dma->sc = NULL;
182 dma->paddr = 0;
183 dma->vaddr = NULL;
184 dma->nseg = 0;
185 dma->mzone = NULL;
186 }
187
bnx2x_acquire_hw_lock(struct bnx2x_softc * sc,uint32_t resource)188 static int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
189 {
190 uint32_t lock_status;
191 uint32_t resource_bit = (1 << resource);
192 int func = SC_FUNC(sc);
193 uint32_t hw_lock_control_reg;
194 int cnt;
195
196 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
197 if (resource)
198 PMD_INIT_FUNC_TRACE(sc);
199 #else
200 PMD_INIT_FUNC_TRACE(sc);
201 #endif
202
203 /* validate the resource is within range */
204 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
205 PMD_DRV_LOG(NOTICE, sc,
206 "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE",
207 resource);
208 return -1;
209 }
210
211 if (func <= 5) {
212 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
213 } else {
214 hw_lock_control_reg =
215 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
216 }
217
218 /* validate the resource is not already taken */
219 lock_status = REG_RD(sc, hw_lock_control_reg);
220 if (lock_status & resource_bit) {
221 PMD_DRV_LOG(NOTICE, sc,
222 "resource in use (status 0x%x bit 0x%x)",
223 lock_status, resource_bit);
224 return -1;
225 }
226
227 /* try every 5ms for 5 seconds */
228 for (cnt = 0; cnt < 1000; cnt++) {
229 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
230 lock_status = REG_RD(sc, hw_lock_control_reg);
231 if (lock_status & resource_bit) {
232 return 0;
233 }
234 DELAY(5000);
235 }
236
237 PMD_DRV_LOG(NOTICE, sc, "Resource 0x%x resource_bit 0x%x lock timeout!",
238 resource, resource_bit);
239 return -1;
240 }
241
bnx2x_release_hw_lock(struct bnx2x_softc * sc,uint32_t resource)242 static int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
243 {
244 uint32_t lock_status;
245 uint32_t resource_bit = (1 << resource);
246 int func = SC_FUNC(sc);
247 uint32_t hw_lock_control_reg;
248
249 #ifndef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC
250 if (resource)
251 PMD_INIT_FUNC_TRACE(sc);
252 #else
253 PMD_INIT_FUNC_TRACE(sc);
254 #endif
255
256 /* validate the resource is within range */
257 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
258 PMD_DRV_LOG(NOTICE, sc,
259 "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
260 " resource_bit 0x%x", resource, resource_bit);
261 return -1;
262 }
263
264 if (func <= 5) {
265 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
266 } else {
267 hw_lock_control_reg =
268 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
269 }
270
271 /* validate the resource is currently taken */
272 lock_status = REG_RD(sc, hw_lock_control_reg);
273 if (!(lock_status & resource_bit)) {
274 PMD_DRV_LOG(NOTICE, sc,
275 "resource not in use (status 0x%x bit 0x%x)",
276 lock_status, resource_bit);
277 return -1;
278 }
279
280 REG_WR(sc, hw_lock_control_reg, resource_bit);
281 return 0;
282 }
283
bnx2x_acquire_phy_lock(struct bnx2x_softc * sc)284 static void bnx2x_acquire_phy_lock(struct bnx2x_softc *sc)
285 {
286 BNX2X_PHY_LOCK(sc);
287 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
288 }
289
bnx2x_release_phy_lock(struct bnx2x_softc * sc)290 static void bnx2x_release_phy_lock(struct bnx2x_softc *sc)
291 {
292 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
293 BNX2X_PHY_UNLOCK(sc);
294 }
295
296 /* copy command into DMAE command memory and set DMAE command Go */
bnx2x_post_dmae(struct bnx2x_softc * sc,struct dmae_command * dmae,int idx)297 void bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)
298 {
299 uint32_t cmd_offset;
300 uint32_t i;
301
302 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
303 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
304 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));
305 }
306
307 REG_WR(sc, dmae_reg_go_c[idx], 1);
308 }
309
bnx2x_dmae_opcode_add_comp(uint32_t opcode,uint8_t comp_type)310 uint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)
311 {
312 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
313 DMAE_COMMAND_C_TYPE_ENABLE);
314 }
315
bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)316 uint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)
317 {
318 return opcode & ~DMAE_COMMAND_SRC_RESET;
319 }
320
321 uint32_t
bnx2x_dmae_opcode(struct bnx2x_softc * sc,uint8_t src_type,uint8_t dst_type,uint8_t with_comp,uint8_t comp_type)322 bnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,
323 uint8_t with_comp, uint8_t comp_type)
324 {
325 uint32_t opcode = 0;
326
327 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
328 (dst_type << DMAE_COMMAND_DST_SHIFT));
329
330 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
331
332 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
333
334 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
335 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
336
337 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
338
339 #ifdef __BIG_ENDIAN
340 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
341 #else
342 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
343 #endif
344
345 if (with_comp) {
346 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
347 }
348
349 return opcode;
350 }
351
352 static void
bnx2x_prep_dmae_with_comp(struct bnx2x_softc * sc,struct dmae_command * dmae,uint8_t src_type,uint8_t dst_type)353 bnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,
354 uint8_t src_type, uint8_t dst_type)
355 {
356 memset(dmae, 0, sizeof(struct dmae_command));
357
358 /* set the opcode */
359 dmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,
360 TRUE, DMAE_COMP_PCI);
361
362 /* fill in the completion parameters */
363 dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));
364 dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));
365 dmae->comp_val = DMAE_COMP_VAL;
366 }
367
368 /* issue a DMAE command over the init channel and wait for completion */
369 static int
bnx2x_issue_dmae_with_comp(struct bnx2x_softc * sc,struct dmae_command * dmae)370 bnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)
371 {
372 uint32_t *wb_comp = BNX2X_SP(sc, wb_comp);
373 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
374
375 /* reset completion */
376 *wb_comp = 0;
377
378 /* post the command on the channel used for initializations */
379 bnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));
380
381 /* wait for completion */
382 DELAY(500);
383
384 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
385 if (!timeout ||
386 (sc->recovery_state != BNX2X_RECOVERY_DONE &&
387 sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
388 PMD_DRV_LOG(INFO, sc, "DMAE timeout!");
389 return DMAE_TIMEOUT;
390 }
391
392 timeout--;
393 DELAY(50);
394 }
395
396 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
397 PMD_DRV_LOG(INFO, sc, "DMAE PCI error!");
398 return DMAE_PCI_ERROR;
399 }
400
401 return 0;
402 }
403
bnx2x_read_dmae(struct bnx2x_softc * sc,uint32_t src_addr,uint32_t len32)404 void bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)
405 {
406 struct dmae_command dmae;
407 uint32_t *data;
408 uint32_t i;
409 int rc;
410
411 if (!sc->dmae_ready) {
412 data = BNX2X_SP(sc, wb_data[0]);
413
414 for (i = 0; i < len32; i++) {
415 data[i] = REG_RD(sc, (src_addr + (i * 4)));
416 }
417
418 return;
419 }
420
421 /* set opcode and fixed command fields */
422 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
423
424 /* fill in addresses and len */
425 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
426 dmae.src_addr_hi = 0;
427 dmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));
428 dmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));
429 dmae.len = len32;
430
431 /* issue the command and wait for completion */
432 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
433 rte_panic("DMAE failed (%d)", rc);
434 };
435 }
436
437 void
bnx2x_write_dmae(struct bnx2x_softc * sc,rte_iova_t dma_addr,uint32_t dst_addr,uint32_t len32)438 bnx2x_write_dmae(struct bnx2x_softc *sc, rte_iova_t dma_addr, uint32_t dst_addr,
439 uint32_t len32)
440 {
441 struct dmae_command dmae;
442 int rc;
443
444 if (!sc->dmae_ready) {
445 ecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);
446 return;
447 }
448
449 /* set opcode and fixed command fields */
450 bnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
451
452 /* fill in addresses and len */
453 dmae.src_addr_lo = U64_LO(dma_addr);
454 dmae.src_addr_hi = U64_HI(dma_addr);
455 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
456 dmae.dst_addr_hi = 0;
457 dmae.len = len32;
458
459 /* issue the command and wait for completion */
460 if ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {
461 rte_panic("DMAE failed (%d)", rc);
462 }
463 }
464
465 static void
bnx2x_write_dmae_phys_len(struct bnx2x_softc * sc,rte_iova_t phys_addr,uint32_t addr,uint32_t len)466 bnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
467 uint32_t addr, uint32_t len)
468 {
469 uint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
470 uint32_t offset = 0;
471
472 while (len > dmae_wr_max) {
473 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
474 (addr + offset), /* dst GRC address */
475 dmae_wr_max);
476 offset += (dmae_wr_max * 4);
477 len -= dmae_wr_max;
478 }
479
480 bnx2x_write_dmae(sc, (phys_addr + offset), /* src DMA address */
481 (addr + offset), /* dst GRC address */
482 len);
483 }
484
485 void
bnx2x_set_ctx_validation(struct bnx2x_softc * sc,struct eth_context * cxt,uint32_t cid)486 bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,
487 uint32_t cid)
488 {
489 /* ustorm cxt validation */
490 cxt->ustorm_ag_context.cdu_usage =
491 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
492 CDU_REGION_NUMBER_UCM_AG,
493 ETH_CONNECTION_TYPE);
494 /* xcontext validation */
495 cxt->xstorm_ag_context.cdu_reserved =
496 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
497 CDU_REGION_NUMBER_XCM_AG,
498 ETH_CONNECTION_TYPE);
499 }
500
501 static void
bnx2x_storm_memset_hc_timeout(struct bnx2x_softc * sc,uint8_t fw_sb_id,uint8_t sb_index,uint8_t ticks)502 bnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,
503 uint8_t sb_index, uint8_t ticks)
504 {
505 uint32_t addr =
506 (BAR_CSTRORM_INTMEM +
507 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
508
509 REG_WR8(sc, addr, ticks);
510 }
511
512 static void
bnx2x_storm_memset_hc_disable(struct bnx2x_softc * sc,uint16_t fw_sb_id,uint8_t sb_index,uint8_t disable)513 bnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,
514 uint8_t sb_index, uint8_t disable)
515 {
516 uint32_t enable_flag =
517 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
518 uint32_t addr =
519 (BAR_CSTRORM_INTMEM +
520 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
521 uint8_t flags;
522
523 /* clear and set */
524 flags = REG_RD8(sc, addr);
525 flags &= ~HC_INDEX_DATA_HC_ENABLED;
526 flags |= enable_flag;
527 REG_WR8(sc, addr, flags);
528 }
529
530 void
bnx2x_update_coalesce_sb_index(struct bnx2x_softc * sc,uint8_t fw_sb_id,uint8_t sb_index,uint8_t disable,uint16_t usec)531 bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,
532 uint8_t sb_index, uint8_t disable, uint16_t usec)
533 {
534 uint8_t ticks = (usec / 4);
535
536 bnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);
537
538 disable = (disable) ? 1 : ((usec) ? 0 : 1);
539 bnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);
540 }
541
elink_cb_reg_read(struct bnx2x_softc * sc,uint32_t reg_addr)542 uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)
543 {
544 return REG_RD(sc, reg_addr);
545 }
546
elink_cb_reg_write(struct bnx2x_softc * sc,uint32_t reg_addr,uint32_t val)547 void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)
548 {
549 REG_WR(sc, reg_addr, val);
550 }
551
552 void
elink_cb_event_log(__rte_unused struct bnx2x_softc * sc,__rte_unused const elink_log_id_t elink_log_id,...)553 elink_cb_event_log(__rte_unused struct bnx2x_softc *sc,
554 __rte_unused const elink_log_id_t elink_log_id, ...)
555 {
556 PMD_DRV_LOG(DEBUG, sc, "ELINK EVENT LOG (%d)", elink_log_id);
557 }
558
bnx2x_set_spio(struct bnx2x_softc * sc,int spio,uint32_t mode)559 static int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)
560 {
561 uint32_t spio_reg;
562
563 /* Only 2 SPIOs are configurable */
564 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
565 PMD_DRV_LOG(NOTICE, sc, "Invalid SPIO 0x%x", spio);
566 return -1;
567 }
568
569 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
570
571 /* read SPIO and mask except the float bits */
572 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
573
574 switch (mode) {
575 case MISC_SPIO_OUTPUT_LOW:
576 /* clear FLOAT and set CLR */
577 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
578 spio_reg |= (spio << MISC_SPIO_CLR_POS);
579 break;
580
581 case MISC_SPIO_OUTPUT_HIGH:
582 /* clear FLOAT and set SET */
583 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
584 spio_reg |= (spio << MISC_SPIO_SET_POS);
585 break;
586
587 case MISC_SPIO_INPUT_HI_Z:
588 /* set FLOAT */
589 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
590 break;
591
592 default:
593 break;
594 }
595
596 REG_WR(sc, MISC_REG_SPIO, spio_reg);
597 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
598
599 return 0;
600 }
601
bnx2x_gpio_read(struct bnx2x_softc * sc,int gpio_num,uint8_t port)602 static int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)
603 {
604 /* The GPIO should be swapped if swap register is set and active */
605 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
606 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
607 int gpio_shift = gpio_num;
608 if (gpio_port)
609 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
610
611 uint32_t gpio_mask = (1 << gpio_shift);
612 uint32_t gpio_reg;
613
614 if (gpio_num > MISC_REGISTERS_GPIO_3) {
615 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
616 return -1;
617 }
618
619 /* read GPIO value */
620 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
621
622 /* get the requested pin value */
623 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
624 }
625
626 static int
bnx2x_gpio_write(struct bnx2x_softc * sc,int gpio_num,uint32_t mode,uint8_t port)627 bnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
628 {
629 /* The GPIO should be swapped if swap register is set and active */
630 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
631 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
632 int gpio_shift = gpio_num;
633 if (gpio_port)
634 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
635
636 uint32_t gpio_mask = (1 << gpio_shift);
637 uint32_t gpio_reg;
638
639 if (gpio_num > MISC_REGISTERS_GPIO_3) {
640 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
641 return -1;
642 }
643
644 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
645
646 /* read GPIO and mask except the float bits */
647 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
648
649 switch (mode) {
650 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
651 /* clear FLOAT and set CLR */
652 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
653 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
654 break;
655
656 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
657 /* clear FLOAT and set SET */
658 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
659 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
660 break;
661
662 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
663 /* set FLOAT */
664 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
665 break;
666
667 default:
668 break;
669 }
670
671 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
672 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
673
674 return 0;
675 }
676
677 static int
bnx2x_gpio_mult_write(struct bnx2x_softc * sc,uint8_t pins,uint32_t mode)678 bnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)
679 {
680 uint32_t gpio_reg;
681
682 /* any port swapping should be handled by caller */
683
684 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
685
686 /* read GPIO and mask except the float bits */
687 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
688 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
689 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
690 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
691
692 switch (mode) {
693 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
694 /* set CLR */
695 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
696 break;
697
698 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
699 /* set SET */
700 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
701 break;
702
703 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
704 /* set FLOAT */
705 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
706 break;
707
708 default:
709 PMD_DRV_LOG(NOTICE, sc,
710 "Invalid GPIO mode assignment %d", mode);
711 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
712 return -1;
713 }
714
715 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
716 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
717
718 return 0;
719 }
720
721 static int
bnx2x_gpio_int_write(struct bnx2x_softc * sc,int gpio_num,uint32_t mode,uint8_t port)722 bnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,
723 uint8_t port)
724 {
725 /* The GPIO should be swapped if swap register is set and active */
726 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
727 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
728 int gpio_shift = gpio_num;
729 if (gpio_port)
730 gpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;
731
732 uint32_t gpio_mask = (1 << gpio_shift);
733 uint32_t gpio_reg;
734
735 if (gpio_num > MISC_REGISTERS_GPIO_3) {
736 PMD_DRV_LOG(NOTICE, sc, "Invalid GPIO %d", gpio_num);
737 return -1;
738 }
739
740 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
741
742 /* read GPIO int */
743 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
744
745 switch (mode) {
746 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
747 /* clear SET and set CLR */
748 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
749 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
750 break;
751
752 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
753 /* clear CLR and set SET */
754 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
755 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
756 break;
757
758 default:
759 break;
760 }
761
762 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
763 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
764
765 return 0;
766 }
767
768 uint32_t
elink_cb_gpio_read(struct bnx2x_softc * sc,uint16_t gpio_num,uint8_t port)769 elink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)
770 {
771 return bnx2x_gpio_read(sc, gpio_num, port);
772 }
773
elink_cb_gpio_write(struct bnx2x_softc * sc,uint16_t gpio_num,uint8_t mode,uint8_t port)774 uint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
775 uint8_t port)
776 {
777 return bnx2x_gpio_write(sc, gpio_num, mode, port);
778 }
779
780 uint8_t
elink_cb_gpio_mult_write(struct bnx2x_softc * sc,uint8_t pins,uint8_t mode)781 elink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,
782 uint8_t mode /* 0=low 1=high */ )
783 {
784 return bnx2x_gpio_mult_write(sc, pins, mode);
785 }
786
elink_cb_gpio_int_write(struct bnx2x_softc * sc,uint16_t gpio_num,uint8_t mode,uint8_t port)787 uint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode, /* 0=low 1=high */
788 uint8_t port)
789 {
790 return bnx2x_gpio_int_write(sc, gpio_num, mode, port);
791 }
792
elink_cb_notify_link_changed(struct bnx2x_softc * sc)793 void elink_cb_notify_link_changed(struct bnx2x_softc *sc)
794 {
795 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
796 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
797 }
798
799 /* send the MCP a request, block until there is a reply */
800 uint32_t
elink_cb_fw_command(struct bnx2x_softc * sc,uint32_t command,uint32_t param)801 elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
802 {
803 int mb_idx = SC_FW_MB_IDX(sc);
804 uint32_t seq;
805 uint32_t rc = 0;
806 uint32_t cnt = 1;
807 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
808
809 seq = ++sc->fw_seq;
810 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
811 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
812
813 PMD_DRV_LOG(DEBUG, sc,
814 "wrote command 0x%08x to FW MB param 0x%08x",
815 (command | seq), param);
816
817 /* Let the FW do it's magic. GIve it up to 5 seconds... */
818 do {
819 DELAY(delay * 1000);
820 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
821 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
822
823 /* is this a reply to our command? */
824 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
825 rc &= FW_MSG_CODE_MASK;
826 } else {
827 /* Ruh-roh! */
828 PMD_DRV_LOG(NOTICE, sc, "FW failed to respond!");
829 rc = 0;
830 }
831
832 return rc;
833 }
834
835 static uint32_t
bnx2x_fw_command(struct bnx2x_softc * sc,uint32_t command,uint32_t param)836 bnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)
837 {
838 return elink_cb_fw_command(sc, command, param);
839 }
840
841 static void
__storm_memset_dma_mapping(struct bnx2x_softc * sc,uint32_t addr,rte_iova_t mapping)842 __storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,
843 rte_iova_t mapping)
844 {
845 REG_WR(sc, addr, U64_LO(mapping));
846 REG_WR(sc, (addr + 4), U64_HI(mapping));
847 }
848
849 static void
storm_memset_spq_addr(struct bnx2x_softc * sc,rte_iova_t mapping,uint16_t abs_fid)850 storm_memset_spq_addr(struct bnx2x_softc *sc, rte_iova_t mapping,
851 uint16_t abs_fid)
852 {
853 uint32_t addr = (XSEM_REG_FAST_MEMORY +
854 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
855 __storm_memset_dma_mapping(sc, addr, mapping);
856 }
857
858 static void
storm_memset_vf_to_pf(struct bnx2x_softc * sc,uint16_t abs_fid,uint16_t pf_id)859 storm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)
860 {
861 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),
862 pf_id);
863 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),
864 pf_id);
865 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),
866 pf_id);
867 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),
868 pf_id);
869 }
870
871 static void
storm_memset_func_en(struct bnx2x_softc * sc,uint16_t abs_fid,uint8_t enable)872 storm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)
873 {
874 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),
875 enable);
876 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),
877 enable);
878 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),
879 enable);
880 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),
881 enable);
882 }
883
884 static void
storm_memset_eq_data(struct bnx2x_softc * sc,struct event_ring_data * eq_data,uint16_t pfid)885 storm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,
886 uint16_t pfid)
887 {
888 uint32_t addr;
889 size_t size;
890
891 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
892 size = sizeof(struct event_ring_data);
893 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);
894 }
895
896 static void
storm_memset_eq_prod(struct bnx2x_softc * sc,uint16_t eq_prod,uint16_t pfid)897 storm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)
898 {
899 uint32_t addr = (BAR_CSTRORM_INTMEM +
900 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
901 REG_WR16(sc, addr, eq_prod);
902 }
903
904 /*
905 * Post a slowpath command.
906 *
907 * A slowpath command is used to propagate a configuration change through
908 * the controller in a controlled manner, allowing each STORM processor and
909 * other H/W blocks to phase in the change. The commands sent on the
910 * slowpath are referred to as ramrods. Depending on the ramrod used the
911 * completion of the ramrod will occur in different ways. Here's a
912 * breakdown of ramrods and how they complete:
913 *
914 * RAMROD_CMD_ID_ETH_PORT_SETUP
915 * Used to setup the leading connection on a port. Completes on the
916 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
917 *
918 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
919 * Used to setup an additional connection on a port. Completes on the
920 * RCQ of the multi-queue/RSS connection being initialized.
921 *
922 * RAMROD_CMD_ID_ETH_STAT_QUERY
923 * Used to force the storm processors to update the statistics database
924 * in host memory. This ramrod is send on the leading connection CID and
925 * completes as an index increment of the CSTORM on the default status
926 * block.
927 *
928 * RAMROD_CMD_ID_ETH_UPDATE
929 * Used to update the state of the leading connection, usually to update
930 * the RSS indirection table. Completes on the RCQ of the leading
931 * connection. (Not currently used under FreeBSD until OS support becomes
932 * available.)
933 *
934 * RAMROD_CMD_ID_ETH_HALT
935 * Used when tearing down a connection prior to driver unload. Completes
936 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
937 * use this on the leading connection.
938 *
939 * RAMROD_CMD_ID_ETH_SET_MAC
940 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
941 * the RCQ of the leading connection.
942 *
943 * RAMROD_CMD_ID_ETH_CFC_DEL
944 * Used when tearing down a connection prior to driver unload. Completes
945 * on the RCQ of the leading connection (since the current connection
946 * has been completely removed from controller memory).
947 *
948 * RAMROD_CMD_ID_ETH_PORT_DEL
949 * Used to tear down the leading connection prior to driver unload,
950 * typically fp[0]. Completes as an index increment of the CSTORM on the
951 * default status block.
952 *
953 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
954 * Used for connection offload. Completes on the RCQ of the multi-queue
955 * RSS connection that is being offloaded. (Not currently used under
956 * FreeBSD.)
957 *
958 * There can only be one command pending per function.
959 *
960 * Returns:
961 * 0 = Success, !0 = Failure.
962 */
963
964 /* must be called under the spq lock */
bnx2x_sp_get_next(struct bnx2x_softc * sc)965 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)
966 {
967 struct eth_spe *next_spe = sc->spq_prod_bd;
968
969 if (sc->spq_prod_bd == sc->spq_last_bd) {
970 /* wrap back to the first eth_spq */
971 sc->spq_prod_bd = sc->spq;
972 sc->spq_prod_idx = 0;
973 } else {
974 sc->spq_prod_bd++;
975 sc->spq_prod_idx++;
976 }
977
978 return next_spe;
979 }
980
981 /* must be called under the spq lock */
bnx2x_sp_prod_update(struct bnx2x_softc * sc)982 static void bnx2x_sp_prod_update(struct bnx2x_softc *sc)
983 {
984 int func = SC_FUNC(sc);
985
986 /*
987 * Make sure that BD data is updated before writing the producer.
988 * BD data is written to the memory, the producer is read from the
989 * memory, thus we need a full memory barrier to ensure the ordering.
990 */
991 mb();
992
993 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
994 sc->spq_prod_idx);
995
996 mb();
997 }
998
999 /**
1000 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
1001 *
1002 * @cmd: command to check
1003 * @cmd_type: command type
1004 */
bnx2x_is_contextless_ramrod(int cmd,int cmd_type)1005 static int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
1006 {
1007 if ((cmd_type == NONE_CONNECTION_TYPE) ||
1008 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
1009 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
1010 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
1011 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
1012 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
1013 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
1014 return TRUE;
1015 } else {
1016 return FALSE;
1017 }
1018 }
1019
1020 /**
1021 * bnx2x_sp_post - place a single command on an SP ring
1022 *
1023 * @sc: driver handle
1024 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
1025 * @cid: SW CID the command is related to
1026 * @data_hi: command private data address (high 32 bits)
1027 * @data_lo: command private data address (low 32 bits)
1028 * @cmd_type: command type (e.g. NONE, ETH)
1029 *
1030 * SP data is handled as if it's always an address pair, thus data fields are
1031 * not swapped to little endian in upper functions. Instead this function swaps
1032 * data as if it's two uint32 fields.
1033 */
1034 int
bnx2x_sp_post(struct bnx2x_softc * sc,int command,int cid,uint32_t data_hi,uint32_t data_lo,int cmd_type)1035 bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,
1036 uint32_t data_lo, int cmd_type)
1037 {
1038 struct eth_spe *spe;
1039 uint16_t type;
1040 int common;
1041
1042 common = bnx2x_is_contextless_ramrod(command, cmd_type);
1043
1044 if (common) {
1045 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
1046 PMD_DRV_LOG(INFO, sc, "EQ ring is full!");
1047 return -1;
1048 }
1049 } else {
1050 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
1051 PMD_DRV_LOG(INFO, sc, "SPQ ring is full!");
1052 return -1;
1053 }
1054 }
1055
1056 spe = bnx2x_sp_get_next(sc);
1057
1058 /* CID needs port number to be encoded int it */
1059 spe->hdr.conn_and_cmd_data =
1060 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
1061
1062 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1063
1064 /* TBD: Check if it works for VFs */
1065 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
1066 SPE_HDR_FUNCTION_ID);
1067
1068 spe->hdr.type = htole16(type);
1069
1070 spe->data.update_data_addr.hi = htole32(data_hi);
1071 spe->data.update_data_addr.lo = htole32(data_lo);
1072
1073 /*
1074 * It's ok if the actual decrement is issued towards the memory
1075 * somewhere between the lock and unlock. Thus no more explicit
1076 * memory barrier is needed.
1077 */
1078 if (common) {
1079 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
1080 } else {
1081 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
1082 }
1083
1084 PMD_DRV_LOG(DEBUG, sc,
1085 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x"
1086 "data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)",
1087 sc->spq_prod_idx,
1088 (uint32_t) U64_HI(sc->spq_dma.paddr),
1089 (uint32_t) (U64_LO(sc->spq_dma.paddr) +
1090 (uint8_t *) sc->spq_prod_bd -
1091 (uint8_t *) sc->spq), command, common,
1092 HW_CID(sc, cid), data_hi, data_lo, type,
1093 atomic_load_acq_long(&sc->cq_spq_left),
1094 atomic_load_acq_long(&sc->eq_spq_left));
1095
1096 /* RAMROD completion is processed in bnx2x_intr_legacy()
1097 * which can run from different contexts.
1098 * Ask bnx2x_intr_intr() to process RAMROD
1099 * completion whenever it gets scheduled.
1100 */
1101 rte_atomic32_set(&sc->scan_fp, 1);
1102 bnx2x_sp_prod_update(sc);
1103
1104 return 0;
1105 }
1106
bnx2x_drv_pulse(struct bnx2x_softc * sc)1107 static void bnx2x_drv_pulse(struct bnx2x_softc *sc)
1108 {
1109 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
1110 sc->fw_drv_pulse_wr_seq);
1111 }
1112
bnx2x_tx_queue_has_work(const struct bnx2x_fastpath * fp)1113 static int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)
1114 {
1115 uint16_t hw_cons;
1116 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1117
1118 if (unlikely(!txq)) {
1119 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1120 return 0;
1121 }
1122
1123 mb(); /* status block fields can change */
1124 hw_cons = le16toh(*fp->tx_cons_sb);
1125 return hw_cons != txq->tx_pkt_head;
1126 }
1127
bnx2x_has_tx_work(struct bnx2x_fastpath * fp)1128 static uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
1129 {
1130 /* expand this for multi-cos if ever supported */
1131 return bnx2x_tx_queue_has_work(fp);
1132 }
1133
bnx2x_has_rx_work(struct bnx2x_fastpath * fp)1134 static int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
1135 {
1136 uint16_t rx_cq_cons_sb;
1137 struct bnx2x_rx_queue *rxq;
1138 rxq = fp->sc->rx_queues[fp->index];
1139 if (unlikely(!rxq)) {
1140 PMD_RX_LOG(ERR, "ERROR: RX queue is NULL");
1141 return 0;
1142 }
1143
1144 mb(); /* status block fields can change */
1145 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
1146 if (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==
1147 MAX_RCQ_ENTRIES(rxq)))
1148 rx_cq_cons_sb++;
1149
1150 PMD_RX_LOG(DEBUG, "hw CQ cons = %d, sw CQ cons = %d",
1151 rx_cq_cons_sb, rxq->rx_cq_head);
1152
1153 return rxq->rx_cq_head != rx_cq_cons_sb;
1154 }
1155
1156 static void
bnx2x_sp_event(struct bnx2x_softc * sc,struct bnx2x_fastpath * fp,union eth_rx_cqe * rr_cqe)1157 bnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
1158 union eth_rx_cqe *rr_cqe)
1159 {
1160 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1161 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1162 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
1163 struct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
1164
1165 PMD_DRV_LOG(DEBUG, sc,
1166 "fp=%d cid=%d got ramrod #%d state is %x type is %d",
1167 fp->index, cid, command, sc->state,
1168 rr_cqe->ramrod_cqe.ramrod_type);
1169
1170 switch (command) {
1171 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1172 PMD_DRV_LOG(DEBUG, sc, "got UPDATE ramrod. CID %d", cid);
1173 drv_cmd = ECORE_Q_CMD_UPDATE;
1174 break;
1175
1176 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1177 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] setup ramrod", cid);
1178 drv_cmd = ECORE_Q_CMD_SETUP;
1179 break;
1180
1181 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1182 PMD_DRV_LOG(DEBUG, sc,
1183 "got MULTI[%d] tx-only setup ramrod", cid);
1184 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
1185 break;
1186
1187 case (RAMROD_CMD_ID_ETH_HALT):
1188 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] halt ramrod", cid);
1189 drv_cmd = ECORE_Q_CMD_HALT;
1190 break;
1191
1192 case (RAMROD_CMD_ID_ETH_TERMINATE):
1193 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] terminate ramrod", cid);
1194 drv_cmd = ECORE_Q_CMD_TERMINATE;
1195 break;
1196
1197 case (RAMROD_CMD_ID_ETH_EMPTY):
1198 PMD_DRV_LOG(DEBUG, sc, "got MULTI[%d] empty ramrod", cid);
1199 drv_cmd = ECORE_Q_CMD_EMPTY;
1200 break;
1201
1202 default:
1203 PMD_DRV_LOG(DEBUG, sc,
1204 "ERROR: unexpected MC reply (%d)"
1205 "on fp[%d]", command, fp->index);
1206 return;
1207 }
1208
1209 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
1210 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
1211 /*
1212 * q_obj->complete_cmd() failure means that this was
1213 * an unexpected completion.
1214 *
1215 * In this case we don't want to increase the sc->spq_left
1216 * because apparently we haven't sent this command the first
1217 * place.
1218 */
1219 // rte_panic("Unexpected SP completion");
1220 return;
1221 }
1222
1223 atomic_add_acq_long(&sc->cq_spq_left, 1);
1224
1225 PMD_DRV_LOG(DEBUG, sc, "sc->cq_spq_left 0x%lx",
1226 atomic_load_acq_long(&sc->cq_spq_left));
1227 }
1228
bnx2x_rxeof(struct bnx2x_softc * sc,struct bnx2x_fastpath * fp)1229 static uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
1230 {
1231 struct bnx2x_rx_queue *rxq;
1232 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1233 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
1234
1235 rte_spinlock_lock(&(fp)->rx_mtx);
1236
1237 rxq = sc->rx_queues[fp->index];
1238 if (!rxq) {
1239 PMD_RX_LOG(ERR, "RX queue %d is NULL", fp->index);
1240 rte_spinlock_unlock(&(fp)->rx_mtx);
1241 return 0;
1242 }
1243
1244 /* CQ "next element" is of the size of the regular element */
1245 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
1246 if (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==
1247 USABLE_RCQ_ENTRIES_PER_PAGE)) {
1248 hw_cq_cons++;
1249 }
1250
1251 bd_cons = rxq->rx_bd_head;
1252 bd_prod = rxq->rx_bd_tail;
1253 bd_prod_fw = bd_prod;
1254 sw_cq_cons = rxq->rx_cq_head;
1255 sw_cq_prod = rxq->rx_cq_tail;
1256
1257 /*
1258 * Memory barrier necessary as speculative reads of the rx
1259 * buffer can be ahead of the index in the status block
1260 */
1261 rmb();
1262
1263 while (sw_cq_cons != hw_cq_cons) {
1264 union eth_rx_cqe *cqe;
1265 struct eth_fast_path_rx_cqe *cqe_fp;
1266 uint8_t cqe_fp_flags;
1267 enum eth_rx_cqe_type cqe_fp_type;
1268
1269 comp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);
1270 bd_prod = RX_BD(bd_prod, rxq);
1271 bd_cons = RX_BD(bd_cons, rxq);
1272
1273 cqe = &rxq->cq_ring[comp_ring_cons];
1274 cqe_fp = &cqe->fast_path_cqe;
1275 cqe_fp_flags = cqe_fp->type_error_flags;
1276 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1277
1278 /* is this a slowpath msg? */
1279 if (CQE_TYPE_SLOW(cqe_fp_type)) {
1280 bnx2x_sp_event(sc, fp, cqe);
1281 goto next_cqe;
1282 }
1283
1284 /* is this an error packet? */
1285 if (unlikely(cqe_fp_flags &
1286 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
1287 PMD_RX_LOG(DEBUG, "flags 0x%x rx packet %u",
1288 cqe_fp_flags, sw_cq_cons);
1289 goto next_rx;
1290 }
1291
1292 PMD_RX_LOG(DEBUG, "Dropping fastpath called from attn poller!");
1293
1294 next_rx:
1295 bd_cons = NEXT_RX_BD(bd_cons);
1296 bd_prod = NEXT_RX_BD(bd_prod);
1297 bd_prod_fw = NEXT_RX_BD(bd_prod_fw);
1298
1299 next_cqe:
1300 sw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);
1301 sw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);
1302
1303 } /* while work to do */
1304
1305 rxq->rx_bd_head = bd_cons;
1306 rxq->rx_bd_tail = bd_prod_fw;
1307 rxq->rx_cq_head = sw_cq_cons;
1308 rxq->rx_cq_tail = sw_cq_prod;
1309
1310 PMD_RX_LOG(DEBUG, "BD prod = %d, sw CQ prod = %d",
1311 bd_prod_fw, sw_cq_prod);
1312
1313 /* Update producers */
1314 bnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);
1315
1316 rte_spinlock_unlock(&(fp)->rx_mtx);
1317
1318 return sw_cq_cons != hw_cq_cons;
1319 }
1320
1321 static uint16_t
bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath * fp,struct bnx2x_tx_queue * txq,uint16_t pkt_idx,uint16_t bd_idx)1322 bnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,
1323 uint16_t pkt_idx, uint16_t bd_idx)
1324 {
1325 struct eth_tx_start_bd *tx_start_bd =
1326 &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;
1327 uint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);
1328 struct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];
1329
1330 if (likely(tx_mbuf != NULL)) {
1331 rte_pktmbuf_free_seg(tx_mbuf);
1332 } else {
1333 PMD_RX_LOG(ERR, "fp[%02d] lost mbuf %lu",
1334 fp->index, (unsigned long)TX_BD(pkt_idx, txq));
1335 }
1336
1337 txq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;
1338 txq->nb_tx_avail += nbd;
1339
1340 while (nbd--)
1341 bd_idx = NEXT_TX_BD(bd_idx);
1342
1343 return bd_idx;
1344 }
1345
1346 /* processes transmit completions */
bnx2x_txeof(__rte_unused struct bnx2x_softc * sc,struct bnx2x_fastpath * fp)1347 uint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)
1348 {
1349 uint16_t bd_cons, hw_cons, sw_cons;
1350 __rte_unused uint16_t tx_bd_avail;
1351
1352 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
1353
1354 if (unlikely(!txq)) {
1355 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
1356 return 0;
1357 }
1358
1359 bd_cons = txq->tx_bd_head;
1360 hw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);
1361 sw_cons = txq->tx_pkt_head;
1362
1363 while (sw_cons != hw_cons) {
1364 bd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);
1365 sw_cons++;
1366 }
1367
1368 txq->tx_pkt_head = sw_cons;
1369 txq->tx_bd_head = bd_cons;
1370
1371 tx_bd_avail = txq->nb_tx_avail;
1372
1373 PMD_TX_LOG(DEBUG, "fp[%02d] avail=%u cons_sb=%u, "
1374 "pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u",
1375 fp->index, tx_bd_avail, hw_cons,
1376 txq->tx_pkt_head, txq->tx_pkt_tail,
1377 txq->tx_bd_head, txq->tx_bd_tail);
1378 return TRUE;
1379 }
1380
bnx2x_drain_tx_queues(struct bnx2x_softc * sc)1381 static void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)
1382 {
1383 struct bnx2x_fastpath *fp;
1384 int i, count;
1385
1386 /* wait until all TX fastpath tasks have completed */
1387 for (i = 0; i < sc->num_queues; i++) {
1388 fp = &sc->fp[i];
1389
1390 count = 1000;
1391
1392 while (bnx2x_has_tx_work(fp)) {
1393 bnx2x_txeof(sc, fp);
1394
1395 if (count == 0) {
1396 PMD_TX_LOG(ERR,
1397 "Timeout waiting for fp[%d] "
1398 "transmits to complete!", i);
1399 rte_panic("tx drain failure");
1400 return;
1401 }
1402
1403 count--;
1404 DELAY(1000);
1405 rmb();
1406 }
1407 }
1408
1409 return;
1410 }
1411
1412 static int
bnx2x_del_all_macs(struct bnx2x_softc * sc,struct ecore_vlan_mac_obj * mac_obj,int mac_type,uint8_t wait_for_comp)1413 bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,
1414 int mac_type, uint8_t wait_for_comp)
1415 {
1416 uint32_t ramrod_flags = 0, vlan_mac_flags = 0;
1417 int rc;
1418
1419 /* wait for completion of requested */
1420 if (wait_for_comp) {
1421 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
1422 }
1423
1424 /* Set the mac type of addresses we want to clear */
1425 rte_bit_relaxed_set32(mac_type, &vlan_mac_flags);
1426
1427 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1428 if (rc < 0)
1429 PMD_DRV_LOG(ERR, sc, "Failed to delete MACs (%d)", rc);
1430
1431 return rc;
1432 }
1433
1434 static int
bnx2x_fill_accept_flags(struct bnx2x_softc * sc,uint32_t rx_mode,uint32_t * rx_accept_flags,uint32_t * tx_accept_flags)1435 bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,
1436 uint32_t *rx_accept_flags, uint32_t *tx_accept_flags)
1437 {
1438 /* Clear the flags first */
1439 *rx_accept_flags = 0;
1440 *tx_accept_flags = 0;
1441
1442 switch (rx_mode) {
1443 case BNX2X_RX_MODE_NONE:
1444 /*
1445 * 'drop all' supersedes any accept flags that may have been
1446 * passed to the function.
1447 */
1448 break;
1449
1450 case BNX2X_RX_MODE_NORMAL:
1451 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1452 rte_bit_relaxed_set32(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
1453 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1454
1455 /* internal switching mode */
1456 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1457 rte_bit_relaxed_set32(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
1458 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1459
1460 break;
1461
1462 case BNX2X_RX_MODE_ALLMULTI:
1463 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1464 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1465 rx_accept_flags);
1466 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1467
1468 /* internal switching mode */
1469 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, tx_accept_flags);
1470 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1471 tx_accept_flags);
1472 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1473
1474 break;
1475
1476 case BNX2X_RX_MODE_ALLMULTI_PROMISC:
1477 case BNX2X_RX_MODE_PROMISC:
1478 /*
1479 * According to definition of SI mode, iface in promisc mode
1480 * should receive matched and unmatched (in resolution of port)
1481 * unicast packets.
1482 */
1483 rte_bit_relaxed_set32(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
1484 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST, rx_accept_flags);
1485 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1486 rx_accept_flags);
1487 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
1488
1489 /* internal switching mode */
1490 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_MULTICAST,
1491 tx_accept_flags);
1492 rte_bit_relaxed_set32(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
1493
1494 if (IS_MF_SI(sc)) {
1495 rte_bit_relaxed_set32(ECORE_ACCEPT_ALL_UNICAST,
1496 tx_accept_flags);
1497 } else {
1498 rte_bit_relaxed_set32(ECORE_ACCEPT_UNICAST,
1499 tx_accept_flags);
1500 }
1501
1502 break;
1503
1504 default:
1505 PMD_RX_LOG(ERR, "Unknown rx_mode (%d)", rx_mode);
1506 return -1;
1507 }
1508
1509 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
1510 if (rx_mode != BNX2X_RX_MODE_NONE) {
1511 rte_bit_relaxed_set32(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
1512 rte_bit_relaxed_set32(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
1513 }
1514
1515 return 0;
1516 }
1517
1518 static int
bnx2x_set_q_rx_mode(struct bnx2x_softc * sc,uint8_t cl_id,unsigned long rx_mode_flags,unsigned long rx_accept_flags,unsigned long tx_accept_flags,unsigned long ramrod_flags)1519 bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,
1520 unsigned long rx_mode_flags,
1521 unsigned long rx_accept_flags,
1522 unsigned long tx_accept_flags, unsigned long ramrod_flags)
1523 {
1524 struct ecore_rx_mode_ramrod_params ramrod_param;
1525 int rc;
1526
1527 memset(&ramrod_param, 0, sizeof(ramrod_param));
1528
1529 /* Prepare ramrod parameters */
1530 ramrod_param.cid = 0;
1531 ramrod_param.cl_id = cl_id;
1532 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
1533 ramrod_param.func_id = SC_FUNC(sc);
1534
1535 ramrod_param.pstate = &sc->sp_state;
1536 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
1537
1538 ramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);
1539 ramrod_param.rdata_mapping =
1540 (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),
1541 rte_bit_relaxed_set32(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
1542
1543 ramrod_param.ramrod_flags = ramrod_flags;
1544 ramrod_param.rx_mode_flags = rx_mode_flags;
1545
1546 ramrod_param.rx_accept_flags = rx_accept_flags;
1547 ramrod_param.tx_accept_flags = tx_accept_flags;
1548
1549 rc = ecore_config_rx_mode(sc, &ramrod_param);
1550 if (rc < 0) {
1551 PMD_RX_LOG(ERR, "Set rx_mode %d failed", sc->rx_mode);
1552 return rc;
1553 }
1554
1555 return 0;
1556 }
1557
bnx2x_set_storm_rx_mode(struct bnx2x_softc * sc)1558 int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)
1559 {
1560 uint32_t rx_mode_flags = 0, ramrod_flags = 0;
1561 uint32_t rx_accept_flags = 0, tx_accept_flags = 0;
1562 int rc;
1563
1564 rc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
1565 &tx_accept_flags);
1566 if (rc) {
1567 return rc;
1568 }
1569
1570 rte_bit_relaxed_set32(RAMROD_RX, &ramrod_flags);
1571 rte_bit_relaxed_set32(RAMROD_TX, &ramrod_flags);
1572 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
1573
1574 return bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
1575 rx_accept_flags, tx_accept_flags,
1576 ramrod_flags);
1577 }
1578
1579 /* returns the "mcp load_code" according to global load_count array */
bnx2x_nic_load_no_mcp(struct bnx2x_softc * sc)1580 static int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)
1581 {
1582 int path = SC_PATH(sc);
1583 int port = SC_PORT(sc);
1584
1585 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1586 path, load_count[path][0], load_count[path][1],
1587 load_count[path][2]);
1588
1589 load_count[path][0]++;
1590 load_count[path][1 + port]++;
1591 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1592 path, load_count[path][0], load_count[path][1],
1593 load_count[path][2]);
1594 if (load_count[path][0] == 1)
1595 return FW_MSG_CODE_DRV_LOAD_COMMON;
1596 else if (load_count[path][1 + port] == 1)
1597 return FW_MSG_CODE_DRV_LOAD_PORT;
1598 else
1599 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
1600 }
1601
1602 /* returns the "mcp load_code" according to global load_count array */
bnx2x_nic_unload_no_mcp(struct bnx2x_softc * sc)1603 static int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)
1604 {
1605 int port = SC_PORT(sc);
1606 int path = SC_PATH(sc);
1607
1608 PMD_DRV_LOG(INFO, sc, "NO MCP - load counts[%d] %d, %d, %d",
1609 path, load_count[path][0], load_count[path][1],
1610 load_count[path][2]);
1611 load_count[path][0]--;
1612 load_count[path][1 + port]--;
1613 PMD_DRV_LOG(INFO, sc, "NO MCP - new load counts[%d] %d, %d, %d",
1614 path, load_count[path][0], load_count[path][1],
1615 load_count[path][2]);
1616 if (load_count[path][0] == 0) {
1617 return FW_MSG_CODE_DRV_UNLOAD_COMMON;
1618 } else if (load_count[path][1 + port] == 0) {
1619 return FW_MSG_CODE_DRV_UNLOAD_PORT;
1620 } else {
1621 return FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
1622 }
1623 }
1624
1625 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
bnx2x_send_unload_req(struct bnx2x_softc * sc,int unload_mode)1626 static uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)
1627 {
1628 uint32_t reset_code = 0;
1629
1630 /* Select the UNLOAD request mode */
1631 if (unload_mode == UNLOAD_NORMAL) {
1632 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1633 } else {
1634 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
1635 }
1636
1637 /* Send the request to the MCP */
1638 if (!BNX2X_NOMCP(sc)) {
1639 reset_code = bnx2x_fw_command(sc, reset_code, 0);
1640 } else {
1641 reset_code = bnx2x_nic_unload_no_mcp(sc);
1642 }
1643
1644 return reset_code;
1645 }
1646
1647 /* send UNLOAD_DONE command to the MCP */
bnx2x_send_unload_done(struct bnx2x_softc * sc,uint8_t keep_link)1648 static void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)
1649 {
1650 uint32_t reset_param =
1651 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
1652
1653 /* Report UNLOAD_DONE to MCP */
1654 if (!BNX2X_NOMCP(sc)) {
1655 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
1656 }
1657 }
1658
bnx2x_func_wait_started(struct bnx2x_softc * sc)1659 static int bnx2x_func_wait_started(struct bnx2x_softc *sc)
1660 {
1661 int tout = 50;
1662
1663 if (!sc->port.pmf) {
1664 return 0;
1665 }
1666
1667 /*
1668 * (assumption: No Attention from MCP at this stage)
1669 * PMF probably in the middle of TX disable/enable transaction
1670 * 1. Sync IRS for default SB
1671 * 2. Sync SP queue - this guarantees us that attention handling started
1672 * 3. Wait, that TX disable/enable transaction completes
1673 *
1674 * 1+2 guarantee that if DCBX attention was scheduled it already changed
1675 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
1676 * received completion for the transaction the state is TX_STOPPED.
1677 * State will return to STARTED after completion of TX_STOPPED-->STARTED
1678 * transaction.
1679 */
1680
1681 while (ecore_func_get_state(sc, &sc->func_obj) !=
1682 ECORE_F_STATE_STARTED && tout--) {
1683 DELAY(20000);
1684 }
1685
1686 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
1687 /*
1688 * Failed to complete the transaction in a "good way"
1689 * Force both transactions with CLR bit.
1690 */
1691 struct ecore_func_state_params func_params = { NULL };
1692
1693 PMD_DRV_LOG(NOTICE, sc, "Unexpected function state! "
1694 "Forcing STARTED-->TX_STOPPED-->STARTED");
1695
1696 func_params.f_obj = &sc->func_obj;
1697 rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY,
1698 &func_params.ramrod_flags);
1699
1700 /* STARTED-->TX_STOPPED */
1701 func_params.cmd = ECORE_F_CMD_TX_STOP;
1702 ecore_func_state_change(sc, &func_params);
1703
1704 /* TX_STOPPED-->STARTED */
1705 func_params.cmd = ECORE_F_CMD_TX_START;
1706 return ecore_func_state_change(sc, &func_params);
1707 }
1708
1709 return 0;
1710 }
1711
bnx2x_stop_queue(struct bnx2x_softc * sc,int index)1712 static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)
1713 {
1714 struct bnx2x_fastpath *fp = &sc->fp[index];
1715 struct ecore_queue_state_params q_params = { NULL };
1716 int rc;
1717
1718 PMD_DRV_LOG(DEBUG, sc, "stopping queue %d cid %d", index, fp->index);
1719
1720 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
1721 /* We want to wait for completion in this context */
1722 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
1723
1724 /* Stop the primary connection: */
1725
1726 /* ...halt the connection */
1727 q_params.cmd = ECORE_Q_CMD_HALT;
1728 rc = ecore_queue_state_change(sc, &q_params);
1729 if (rc) {
1730 return rc;
1731 }
1732
1733 /* ...terminate the connection */
1734 q_params.cmd = ECORE_Q_CMD_TERMINATE;
1735 memset(&q_params.params.terminate, 0,
1736 sizeof(q_params.params.terminate));
1737 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
1738 rc = ecore_queue_state_change(sc, &q_params);
1739 if (rc) {
1740 return rc;
1741 }
1742
1743 /* ...delete cfc entry */
1744 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
1745 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
1746 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
1747 return ecore_queue_state_change(sc, &q_params);
1748 }
1749
1750 /* wait for the outstanding SP commands */
bnx2x_wait_sp_comp(struct bnx2x_softc * sc,uint32_t mask)1751 static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, uint32_t mask)
1752 {
1753 uint32_t tmp;
1754 int tout = 5000; /* wait for 5 secs tops */
1755
1756 while (tout--) {
1757 mb();
1758 if (!(atomic_load_acq_int(&sc->sp_state) & mask))
1759 return TRUE;
1760
1761 DELAY(1000);
1762 }
1763
1764 mb();
1765
1766 tmp = atomic_load_acq_int(&sc->sp_state);
1767 if (tmp & mask) {
1768 PMD_DRV_LOG(INFO, sc, "Filtering completion timed out: "
1769 "sp_state 0x%x, mask 0x%x", tmp, mask);
1770 return FALSE;
1771 }
1772
1773 return FALSE;
1774 }
1775
bnx2x_func_stop(struct bnx2x_softc * sc)1776 static int bnx2x_func_stop(struct bnx2x_softc *sc)
1777 {
1778 struct ecore_func_state_params func_params = { NULL };
1779 int rc;
1780
1781 /* prepare parameters for function state transitions */
1782 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1783 func_params.f_obj = &sc->func_obj;
1784 func_params.cmd = ECORE_F_CMD_STOP;
1785
1786 /*
1787 * Try to stop the function the 'good way'. If it fails (in case
1788 * of a parity error during bnx2x_chip_cleanup()) and we are
1789 * not in a debug mode, perform a state transaction in order to
1790 * enable further HW_RESET transaction.
1791 */
1792 rc = ecore_func_state_change(sc, &func_params);
1793 if (rc) {
1794 PMD_DRV_LOG(NOTICE, sc, "FUNC_STOP ramrod failed. "
1795 "Running a dry transaction");
1796 rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY,
1797 &func_params.ramrod_flags);
1798 return ecore_func_state_change(sc, &func_params);
1799 }
1800
1801 return 0;
1802 }
1803
bnx2x_reset_hw(struct bnx2x_softc * sc,uint32_t load_code)1804 static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)
1805 {
1806 struct ecore_func_state_params func_params = { NULL };
1807
1808 /* Prepare parameters for function state transitions */
1809 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1810
1811 func_params.f_obj = &sc->func_obj;
1812 func_params.cmd = ECORE_F_CMD_HW_RESET;
1813
1814 func_params.params.hw_init.load_phase = load_code;
1815
1816 return ecore_func_state_change(sc, &func_params);
1817 }
1818
bnx2x_int_disable_sync(struct bnx2x_softc * sc,int disable_hw)1819 static void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)
1820 {
1821 if (disable_hw) {
1822 /* prevent the HW from sending interrupts */
1823 bnx2x_int_disable(sc);
1824 }
1825 }
1826
1827 static void
bnx2x_chip_cleanup(struct bnx2x_softc * sc,uint32_t unload_mode,uint8_t keep_link)1828 bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
1829 {
1830 int port = SC_PORT(sc);
1831 struct ecore_mcast_ramrod_params rparam = { NULL };
1832 uint32_t reset_code;
1833 int i, rc = 0;
1834
1835 bnx2x_drain_tx_queues(sc);
1836
1837 /* give HW time to discard old tx messages */
1838 DELAY(1000);
1839
1840 /* Clean all ETH MACs */
1841 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,
1842 FALSE);
1843 if (rc < 0) {
1844 PMD_DRV_LOG(NOTICE, sc,
1845 "Failed to delete all ETH MACs (%d)", rc);
1846 }
1847
1848 /* Clean up UC list */
1849 rc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,
1850 TRUE);
1851 if (rc < 0) {
1852 PMD_DRV_LOG(NOTICE, sc,
1853 "Failed to delete UC MACs list (%d)", rc);
1854 }
1855
1856 /* Disable LLH */
1857 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
1858
1859 /* Set "drop all" to stop Rx */
1860
1861 /*
1862 * We need to take the if_maddr_lock() here in order to prevent
1863 * a race between the completion code and this code.
1864 */
1865
1866 if (rte_bit_relaxed_get32(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state))
1867 rte_bit_relaxed_set32(ECORE_FILTER_RX_MODE_SCHED,
1868 &sc->sp_state);
1869 else
1870 bnx2x_set_storm_rx_mode(sc);
1871
1872 /* Clean up multicast configuration */
1873 rparam.mcast_obj = &sc->mcast_obj;
1874 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1875 if (rc < 0) {
1876 PMD_DRV_LOG(NOTICE, sc,
1877 "Failed to send DEL MCAST command (%d)", rc);
1878 }
1879
1880 /*
1881 * Send the UNLOAD_REQUEST to the MCP. This will return if
1882 * this function should perform FUNCTION, PORT, or COMMON HW
1883 * reset.
1884 */
1885 reset_code = bnx2x_send_unload_req(sc, unload_mode);
1886
1887 /*
1888 * (assumption: No Attention from MCP at this stage)
1889 * PMF probably in the middle of TX disable/enable transaction
1890 */
1891 rc = bnx2x_func_wait_started(sc);
1892 if (rc) {
1893 PMD_DRV_LOG(NOTICE, sc, "bnx2x_func_wait_started failed");
1894 }
1895
1896 /*
1897 * Close multi and leading connections
1898 * Completions for ramrods are collected in a synchronous way
1899 */
1900 for (i = 0; i < sc->num_queues; i++) {
1901 if (bnx2x_stop_queue(sc, i)) {
1902 goto unload_error;
1903 }
1904 }
1905
1906 /*
1907 * If SP settings didn't get completed so far - something
1908 * very wrong has happen.
1909 */
1910 if (!bnx2x_wait_sp_comp(sc, ~0x0U))
1911 PMD_DRV_LOG(NOTICE, sc, "Common slow path ramrods got stuck!");
1912
1913 unload_error:
1914
1915 rc = bnx2x_func_stop(sc);
1916 if (rc) {
1917 PMD_DRV_LOG(NOTICE, sc, "Function stop failed!");
1918 }
1919
1920 /* disable HW interrupts */
1921 bnx2x_int_disable_sync(sc, TRUE);
1922
1923 /* Reset the chip */
1924 rc = bnx2x_reset_hw(sc, reset_code);
1925 if (rc) {
1926 PMD_DRV_LOG(NOTICE, sc, "Hardware reset failed");
1927 }
1928
1929 /* Report UNLOAD_DONE to MCP */
1930 bnx2x_send_unload_done(sc, keep_link);
1931 }
1932
bnx2x_disable_close_the_gate(struct bnx2x_softc * sc)1933 static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)
1934 {
1935 uint32_t val;
1936
1937 PMD_DRV_LOG(DEBUG, sc, "Disabling 'close the gates'");
1938
1939 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
1940 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
1941 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
1942 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
1943 }
1944
1945 /*
1946 * Cleans the object that have internal lists without sending
1947 * ramrods. Should be run when interrupts are disabled.
1948 */
bnx2x_squeeze_objects(struct bnx2x_softc * sc)1949 static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)
1950 {
1951 uint32_t ramrod_flags = 0, vlan_mac_flags = 0;
1952 struct ecore_mcast_ramrod_params rparam = { NULL };
1953 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
1954 int rc;
1955
1956 /* Cleanup MACs' object first... */
1957
1958 /* Wait for completion of requested */
1959 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
1960 /* Perform a dry cleanup */
1961 rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
1962
1963 /* Clean ETH primary MAC */
1964 rte_bit_relaxed_set32(ECORE_ETH_MAC, &vlan_mac_flags);
1965 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
1966 &ramrod_flags);
1967 if (rc != 0) {
1968 PMD_DRV_LOG(NOTICE, sc, "Failed to clean ETH MACs (%d)", rc);
1969 }
1970
1971 /* Cleanup UC list */
1972 vlan_mac_flags = 0;
1973 rte_bit_relaxed_set32(ECORE_UC_LIST_MAC, &vlan_mac_flags);
1974 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
1975 if (rc != 0) {
1976 PMD_DRV_LOG(NOTICE, sc,
1977 "Failed to clean UC list MACs (%d)", rc);
1978 }
1979
1980 /* Now clean mcast object... */
1981
1982 rparam.mcast_obj = &sc->mcast_obj;
1983 rte_bit_relaxed_set32(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
1984
1985 /* Add a DEL command... */
1986 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
1987 if (rc < 0) {
1988 PMD_DRV_LOG(NOTICE, sc,
1989 "Failed to send DEL MCAST command (%d)", rc);
1990 }
1991
1992 /* now wait until all pending commands are cleared */
1993
1994 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
1995 while (rc != 0) {
1996 if (rc < 0) {
1997 PMD_DRV_LOG(NOTICE, sc,
1998 "Failed to clean MCAST object (%d)", rc);
1999 return;
2000 }
2001
2002 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
2003 }
2004 }
2005
2006 /* stop the controller */
2007 __rte_noinline
2008 int
bnx2x_nic_unload(struct bnx2x_softc * sc,uint32_t unload_mode,uint8_t keep_link)2009 bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)
2010 {
2011 uint8_t global = FALSE;
2012 uint32_t val;
2013
2014 PMD_INIT_FUNC_TRACE(sc);
2015
2016 PMD_DRV_LOG(DEBUG, sc, "Starting NIC unload...");
2017
2018 /* mark driver as unloaded in shmem2 */
2019 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
2020 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
2021 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
2022 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2023 }
2024
2025 if (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&
2026 (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {
2027 /*
2028 * We can get here if the driver has been unloaded
2029 * during parity error recovery and is either waiting for a
2030 * leader to complete or for other functions to unload and
2031 * then ifconfig down has been issued. In this case we want to
2032 * unload and let other functions to complete a recovery
2033 * process.
2034 */
2035 sc->recovery_state = BNX2X_RECOVERY_DONE;
2036 sc->is_leader = 0;
2037 bnx2x_release_leader_lock(sc);
2038 mb();
2039
2040 PMD_DRV_LOG(NOTICE, sc, "Can't unload in closed or error state");
2041 return -1;
2042 }
2043
2044 /*
2045 * Nothing to do during unload if previous bnx2x_nic_load()
2046 * did not complete successfully - all resources are released.
2047 */
2048 if ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {
2049 return 0;
2050 }
2051
2052 sc->state = BNX2X_STATE_CLOSING_WAITING_HALT;
2053 mb();
2054
2055 sc->rx_mode = BNX2X_RX_MODE_NONE;
2056 bnx2x_set_rx_mode(sc);
2057 mb();
2058
2059 if (IS_PF(sc)) {
2060 /* set ALWAYS_ALIVE bit in shmem */
2061 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2062
2063 bnx2x_drv_pulse(sc);
2064
2065 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2066 bnx2x_save_statistics(sc);
2067 }
2068
2069 /* wait till consumers catch up with producers in all queues */
2070 bnx2x_drain_tx_queues(sc);
2071
2072 /* if VF indicate to PF this function is going down (PF will delete sp
2073 * elements and clear initializations
2074 */
2075 if (IS_VF(sc)) {
2076 bnx2x_vf_unload(sc);
2077 } else if (unload_mode != UNLOAD_RECOVERY) {
2078 /* if this is a normal/close unload need to clean up chip */
2079 bnx2x_chip_cleanup(sc, unload_mode, keep_link);
2080 } else {
2081 /* Send the UNLOAD_REQUEST to the MCP */
2082 bnx2x_send_unload_req(sc, unload_mode);
2083
2084 /*
2085 * Prevent transactions to host from the functions on the
2086 * engine that doesn't reset global blocks in case of global
2087 * attention once global blocks are reset and gates are opened
2088 * (the engine which leader will perform the recovery
2089 * last).
2090 */
2091 if (!CHIP_IS_E1x(sc)) {
2092 bnx2x_pf_disable(sc);
2093 }
2094
2095 /* disable HW interrupts */
2096 bnx2x_int_disable_sync(sc, TRUE);
2097
2098 /* Report UNLOAD_DONE to MCP */
2099 bnx2x_send_unload_done(sc, FALSE);
2100 }
2101
2102 /*
2103 * At this stage no more interrupts will arrive so we may safely clean
2104 * the queueable objects here in case they failed to get cleaned so far.
2105 */
2106 if (IS_PF(sc)) {
2107 bnx2x_squeeze_objects(sc);
2108 }
2109
2110 /* There should be no more pending SP commands at this stage */
2111 sc->sp_state = 0;
2112
2113 sc->port.pmf = 0;
2114
2115 if (IS_PF(sc)) {
2116 bnx2x_free_mem(sc);
2117 }
2118
2119 /* free the host hardware/software hsi structures */
2120 bnx2x_free_hsi_mem(sc);
2121
2122 bnx2x_free_fw_stats_mem(sc);
2123
2124 sc->state = BNX2X_STATE_CLOSED;
2125
2126 /*
2127 * Check if there are pending parity attentions. If there are - set
2128 * RECOVERY_IN_PROGRESS.
2129 */
2130 if (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {
2131 bnx2x_set_reset_in_progress(sc);
2132
2133 /* Set RESET_IS_GLOBAL if needed */
2134 if (global) {
2135 bnx2x_set_reset_global(sc);
2136 }
2137 }
2138
2139 /*
2140 * The last driver must disable a "close the gate" if there is no
2141 * parity attention or "process kill" pending.
2142 */
2143 if (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&
2144 bnx2x_reset_is_done(sc, SC_PATH(sc))) {
2145 bnx2x_disable_close_the_gate(sc);
2146 }
2147
2148 PMD_DRV_LOG(DEBUG, sc, "Ended NIC unload");
2149
2150 return 0;
2151 }
2152
2153 /*
2154 * Encapsulate an mbuf cluster into the Tx BD chain and makes the memory
2155 * visible to the controller.
2156 *
2157 * If an mbuf is submitted to this routine and cannot be given to the
2158 * controller (e.g. it has too many fragments) then the function may free
2159 * the mbuf and return to the caller.
2160 *
2161 * Returns:
2162 * int: Number of TX BDs used for the mbuf
2163 *
2164 * Note the side effect that an mbuf may be freed if it causes a problem.
2165 */
bnx2x_tx_encap(struct bnx2x_tx_queue * txq,struct rte_mbuf * m0)2166 int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
2167 {
2168 struct eth_tx_start_bd *tx_start_bd;
2169 uint16_t bd_prod, pkt_prod;
2170 struct bnx2x_softc *sc;
2171 uint32_t nbds = 0;
2172
2173 sc = txq->sc;
2174 bd_prod = txq->tx_bd_tail;
2175 pkt_prod = txq->tx_pkt_tail;
2176
2177 txq->sw_ring[TX_BD(pkt_prod, txq)] = m0;
2178
2179 tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
2180
2181 tx_start_bd->addr_lo =
2182 rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));
2183 tx_start_bd->addr_hi =
2184 rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));
2185 tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
2186 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2187 tx_start_bd->general_data =
2188 (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
2189
2190 tx_start_bd->nbd = rte_cpu_to_le_16(2);
2191
2192 if (m0->ol_flags & RTE_MBUF_F_TX_VLAN) {
2193 tx_start_bd->vlan_or_ethertype =
2194 rte_cpu_to_le_16(m0->vlan_tci);
2195 tx_start_bd->bd_flags.as_bitfield |=
2196 (X_ETH_OUTBAND_VLAN <<
2197 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2198 } else {
2199 if (IS_PF(sc))
2200 tx_start_bd->vlan_or_ethertype =
2201 rte_cpu_to_le_16(pkt_prod);
2202 else {
2203 /* when transmitting in a vf, start bd
2204 * must hold the ethertype for fw to enforce it
2205 */
2206 struct rte_ether_hdr *eh =
2207 rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2208
2209 /* Still need to consider inband vlan for enforced */
2210 if (eh->ether_type ==
2211 rte_cpu_to_be_16(RTE_ETHER_TYPE_VLAN)) {
2212 struct rte_vlan_hdr *vh =
2213 (struct rte_vlan_hdr *)(eh + 1);
2214 tx_start_bd->bd_flags.as_bitfield |=
2215 (X_ETH_INBAND_VLAN <<
2216 ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
2217 tx_start_bd->vlan_or_ethertype =
2218 rte_cpu_to_le_16(ntohs(vh->vlan_tci));
2219 } else {
2220 tx_start_bd->vlan_or_ethertype =
2221 (rte_cpu_to_le_16
2222 (rte_be_to_cpu_16(eh->ether_type)));
2223 }
2224 }
2225 }
2226
2227 bd_prod = NEXT_TX_BD(bd_prod);
2228 if (IS_VF(sc)) {
2229 struct eth_tx_parse_bd_e2 *tx_parse_bd;
2230 const struct rte_ether_hdr *eh =
2231 rte_pktmbuf_mtod(m0, struct rte_ether_hdr *);
2232 uint8_t mac_type = UNICAST_ADDRESS;
2233
2234 tx_parse_bd =
2235 &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;
2236 if (rte_is_multicast_ether_addr(&eh->dst_addr)) {
2237 if (rte_is_broadcast_ether_addr(&eh->dst_addr))
2238 mac_type = BROADCAST_ADDRESS;
2239 else
2240 mac_type = MULTICAST_ADDRESS;
2241 }
2242 tx_parse_bd->parsing_data =
2243 (mac_type << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
2244
2245 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,
2246 &eh->dst_addr.addr_bytes[0], 2);
2247 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,
2248 &eh->dst_addr.addr_bytes[2], 2);
2249 rte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,
2250 &eh->dst_addr.addr_bytes[4], 2);
2251 rte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,
2252 &eh->src_addr.addr_bytes[0], 2);
2253 rte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,
2254 &eh->src_addr.addr_bytes[2], 2);
2255 rte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,
2256 &eh->src_addr.addr_bytes[4], 2);
2257
2258 tx_parse_bd->data.mac_addr.dst_hi =
2259 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);
2260 tx_parse_bd->data.mac_addr.dst_mid =
2261 rte_cpu_to_be_16(tx_parse_bd->data.
2262 mac_addr.dst_mid);
2263 tx_parse_bd->data.mac_addr.dst_lo =
2264 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);
2265 tx_parse_bd->data.mac_addr.src_hi =
2266 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);
2267 tx_parse_bd->data.mac_addr.src_mid =
2268 rte_cpu_to_be_16(tx_parse_bd->data.
2269 mac_addr.src_mid);
2270 tx_parse_bd->data.mac_addr.src_lo =
2271 rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);
2272
2273 PMD_TX_LOG(DEBUG,
2274 "PBD dst %x %x %x src %x %x %x p_data %x",
2275 tx_parse_bd->data.mac_addr.dst_hi,
2276 tx_parse_bd->data.mac_addr.dst_mid,
2277 tx_parse_bd->data.mac_addr.dst_lo,
2278 tx_parse_bd->data.mac_addr.src_hi,
2279 tx_parse_bd->data.mac_addr.src_mid,
2280 tx_parse_bd->data.mac_addr.src_lo,
2281 tx_parse_bd->parsing_data);
2282 }
2283
2284 PMD_TX_LOG(DEBUG,
2285 "start bd: nbytes %d flags %x vlan %x",
2286 tx_start_bd->nbytes,
2287 tx_start_bd->bd_flags.as_bitfield,
2288 tx_start_bd->vlan_or_ethertype);
2289
2290 bd_prod = NEXT_TX_BD(bd_prod);
2291 pkt_prod++;
2292
2293 if (TX_IDX(bd_prod) < 2)
2294 nbds++;
2295
2296 txq->nb_tx_avail -= 2;
2297 txq->tx_bd_tail = bd_prod;
2298 txq->tx_pkt_tail = pkt_prod;
2299
2300 return nbds + 2;
2301 }
2302
bnx2x_cid_ilt_lines(struct bnx2x_softc * sc)2303 static uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)
2304 {
2305 return L2_ILT_LINES(sc);
2306 }
2307
bnx2x_ilt_set_info(struct bnx2x_softc * sc)2308 static void bnx2x_ilt_set_info(struct bnx2x_softc *sc)
2309 {
2310 struct ilt_client_info *ilt_client;
2311 struct ecore_ilt *ilt = sc->ilt;
2312 uint16_t line = 0;
2313
2314 PMD_INIT_FUNC_TRACE(sc);
2315
2316 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
2317
2318 /* CDU */
2319 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
2320 ilt_client->client_num = ILT_CLIENT_CDU;
2321 ilt_client->page_size = CDU_ILT_PAGE_SZ;
2322 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
2323 ilt_client->start = line;
2324 line += bnx2x_cid_ilt_lines(sc);
2325
2326 if (CNIC_SUPPORT(sc)) {
2327 line += CNIC_ILT_LINES;
2328 }
2329
2330 ilt_client->end = (line - 1);
2331
2332 /* QM */
2333 if (QM_INIT(sc->qm_cid_count)) {
2334 ilt_client = &ilt->clients[ILT_CLIENT_QM];
2335 ilt_client->client_num = ILT_CLIENT_QM;
2336 ilt_client->page_size = QM_ILT_PAGE_SZ;
2337 ilt_client->flags = 0;
2338 ilt_client->start = line;
2339
2340 /* 4 bytes for each cid */
2341 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
2342 QM_ILT_PAGE_SZ);
2343
2344 ilt_client->end = (line - 1);
2345 }
2346
2347 if (CNIC_SUPPORT(sc)) {
2348 /* SRC */
2349 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
2350 ilt_client->client_num = ILT_CLIENT_SRC;
2351 ilt_client->page_size = SRC_ILT_PAGE_SZ;
2352 ilt_client->flags = 0;
2353 ilt_client->start = line;
2354 line += SRC_ILT_LINES;
2355 ilt_client->end = (line - 1);
2356
2357 /* TM */
2358 ilt_client = &ilt->clients[ILT_CLIENT_TM];
2359 ilt_client->client_num = ILT_CLIENT_TM;
2360 ilt_client->page_size = TM_ILT_PAGE_SZ;
2361 ilt_client->flags = 0;
2362 ilt_client->start = line;
2363 line += TM_ILT_LINES;
2364 ilt_client->end = (line - 1);
2365 }
2366
2367 assert((line <= ILT_MAX_LINES));
2368 }
2369
bnx2x_set_fp_rx_buf_size(struct bnx2x_softc * sc)2370 static void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)
2371 {
2372 int i;
2373
2374 for (i = 0; i < sc->num_queues; i++) {
2375 /* get the Rx buffer size for RX frames */
2376 sc->fp[i].rx_buf_size =
2377 (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
2378 }
2379 }
2380
bnx2x_alloc_ilt_mem(struct bnx2x_softc * sc)2381 int bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)
2382 {
2383
2384 sc->ilt = rte_malloc("", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);
2385
2386 return sc->ilt == NULL;
2387 }
2388
bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc * sc)2389 static int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)
2390 {
2391 sc->ilt->lines = rte_calloc("",
2392 sizeof(struct ilt_line), ILT_MAX_LINES,
2393 RTE_CACHE_LINE_SIZE);
2394 return sc->ilt->lines == NULL;
2395 }
2396
bnx2x_free_ilt_mem(struct bnx2x_softc * sc)2397 void bnx2x_free_ilt_mem(struct bnx2x_softc *sc)
2398 {
2399 rte_free(sc->ilt);
2400 sc->ilt = NULL;
2401 }
2402
bnx2x_free_ilt_lines_mem(struct bnx2x_softc * sc)2403 static void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)
2404 {
2405 if (sc->ilt->lines != NULL) {
2406 rte_free(sc->ilt->lines);
2407 sc->ilt->lines = NULL;
2408 }
2409 }
2410
bnx2x_free_mem(struct bnx2x_softc * sc)2411 static void bnx2x_free_mem(struct bnx2x_softc *sc)
2412 {
2413 uint32_t i;
2414
2415 for (i = 0; i < L2_ILT_LINES(sc); i++) {
2416 sc->context[i].vcxt = NULL;
2417 sc->context[i].size = 0;
2418 }
2419
2420 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
2421
2422 bnx2x_free_ilt_lines_mem(sc);
2423 }
2424
bnx2x_alloc_mem(struct bnx2x_softc * sc)2425 static int bnx2x_alloc_mem(struct bnx2x_softc *sc)
2426 {
2427 int context_size;
2428 int allocated;
2429 int i;
2430 char cdu_name[RTE_MEMZONE_NAMESIZE];
2431
2432 /*
2433 * Allocate memory for CDU context:
2434 * This memory is allocated separately and not in the generic ILT
2435 * functions because CDU differs in few aspects:
2436 * 1. There can be multiple entities allocating memory for context -
2437 * regular L2, CNIC, and SRIOV drivers. Each separately controls
2438 * its own ILT lines.
2439 * 2. Since CDU page-size is not a single 4KB page (which is the case
2440 * for the other ILT clients), to be efficient we want to support
2441 * allocation of sub-page-size in the last entry.
2442 * 3. Context pointers are used by the driver to pass to FW / update
2443 * the context (for the other ILT clients the pointers are used just to
2444 * free the memory during unload).
2445 */
2446 context_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));
2447 for (i = 0, allocated = 0; allocated < context_size; i++) {
2448 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
2449 (context_size - allocated));
2450
2451 snprintf(cdu_name, sizeof(cdu_name), "cdu_%d", i);
2452 if (bnx2x_dma_alloc(sc, sc->context[i].size,
2453 &sc->context[i].vcxt_dma,
2454 cdu_name, BNX2X_PAGE_SIZE) != 0) {
2455 bnx2x_free_mem(sc);
2456 return -1;
2457 }
2458
2459 sc->context[i].vcxt =
2460 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
2461
2462 allocated += sc->context[i].size;
2463 }
2464
2465 bnx2x_alloc_ilt_lines_mem(sc);
2466
2467 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
2468 PMD_DRV_LOG(NOTICE, sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed");
2469 bnx2x_free_mem(sc);
2470 return -1;
2471 }
2472
2473 return 0;
2474 }
2475
bnx2x_free_fw_stats_mem(struct bnx2x_softc * sc)2476 static void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)
2477 {
2478 bnx2x_dma_free(&sc->fw_stats_dma);
2479 sc->fw_stats_num = 0;
2480
2481 sc->fw_stats_req_size = 0;
2482 sc->fw_stats_req = NULL;
2483 sc->fw_stats_req_mapping = 0;
2484
2485 sc->fw_stats_data_size = 0;
2486 sc->fw_stats_data = NULL;
2487 sc->fw_stats_data_mapping = 0;
2488 }
2489
bnx2x_alloc_fw_stats_mem(struct bnx2x_softc * sc)2490 static int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)
2491 {
2492 uint8_t num_queue_stats;
2493 int num_groups, vf_headroom = 0;
2494
2495 /* number of queues for statistics is number of eth queues */
2496 num_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);
2497
2498 /*
2499 * Total number of FW statistics requests =
2500 * 1 for port stats + 1 for PF stats + num of queues
2501 */
2502 sc->fw_stats_num = (2 + num_queue_stats);
2503
2504 /*
2505 * Request is built from stats_query_header and an array of
2506 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
2507 * rules. The real number or requests is configured in the
2508 * stats_query_header.
2509 */
2510 num_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;
2511 if ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)
2512 num_groups++;
2513
2514 sc->fw_stats_req_size =
2515 (sizeof(struct stats_query_header) +
2516 (num_groups * sizeof(struct stats_query_cmd_group)));
2517
2518 /*
2519 * Data for statistics requests + stats_counter.
2520 * stats_counter holds per-STORM counters that are incremented when
2521 * STORM has finished with the current request. Memory for FCoE
2522 * offloaded statistics are counted anyway, even if they will not be sent.
2523 * VF stats are not accounted for here as the data of VF stats is stored
2524 * in memory allocated by the VF, not here.
2525 */
2526 sc->fw_stats_data_size =
2527 (sizeof(struct stats_counter) +
2528 sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +
2529 /* sizeof(struct fcoe_statistics_params) + */
2530 (sizeof(struct per_queue_stats) * num_queue_stats));
2531
2532 if (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
2533 &sc->fw_stats_dma, "fw_stats",
2534 RTE_CACHE_LINE_SIZE) != 0) {
2535 bnx2x_free_fw_stats_mem(sc);
2536 return -1;
2537 }
2538
2539 /* set up the shortcuts */
2540
2541 sc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;
2542 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
2543
2544 sc->fw_stats_data =
2545 (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +
2546 sc->fw_stats_req_size);
2547 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
2548 sc->fw_stats_req_size);
2549
2550 return 0;
2551 }
2552
2553 /*
2554 * Bits map:
2555 * 0-7 - Engine0 load counter.
2556 * 8-15 - Engine1 load counter.
2557 * 16 - Engine0 RESET_IN_PROGRESS bit.
2558 * 17 - Engine1 RESET_IN_PROGRESS bit.
2559 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
2560 * function on the engine
2561 * 19 - Engine1 ONE_IS_LOADED.
2562 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
2563 * leader to complete (check for both RESET_IN_PROGRESS bits and not
2564 * for just the one belonging to its engine).
2565 */
2566 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
2567 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
2568 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
2569 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
2570 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
2571 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
2572 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
2573 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
2574
2575 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
bnx2x_set_reset_global(struct bnx2x_softc * sc)2576 static void bnx2x_set_reset_global(struct bnx2x_softc *sc)
2577 {
2578 uint32_t val;
2579 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2580 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2581 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
2582 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2583 }
2584
2585 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
bnx2x_clear_reset_global(struct bnx2x_softc * sc)2586 static void bnx2x_clear_reset_global(struct bnx2x_softc *sc)
2587 {
2588 uint32_t val;
2589 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2590 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2591 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
2592 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2593 }
2594
2595 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
bnx2x_reset_is_global(struct bnx2x_softc * sc)2596 static uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)
2597 {
2598 return REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT;
2599 }
2600
2601 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
bnx2x_set_reset_done(struct bnx2x_softc * sc)2602 static void bnx2x_set_reset_done(struct bnx2x_softc *sc)
2603 {
2604 uint32_t val;
2605 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2606 BNX2X_PATH0_RST_IN_PROG_BIT;
2607
2608 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2609
2610 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2611 /* Clear the bit */
2612 val &= ~bit;
2613 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2614
2615 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2616 }
2617
2618 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
bnx2x_set_reset_in_progress(struct bnx2x_softc * sc)2619 static void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)
2620 {
2621 uint32_t val;
2622 uint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :
2623 BNX2X_PATH0_RST_IN_PROG_BIT;
2624
2625 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2626
2627 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2628 /* Set the bit */
2629 val |= bit;
2630 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2631
2632 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2633 }
2634
2635 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
bnx2x_reset_is_done(struct bnx2x_softc * sc,int engine)2636 static uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)
2637 {
2638 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2639 uint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :
2640 BNX2X_PATH0_RST_IN_PROG_BIT;
2641
2642 /* return false if bit is set */
2643 return (val & bit) ? FALSE : TRUE;
2644 }
2645
2646 /* get the load status for an engine, should be run under rtnl lock */
bnx2x_get_load_status(struct bnx2x_softc * sc,int engine)2647 static uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)
2648 {
2649 uint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :
2650 BNX2X_PATH0_LOAD_CNT_MASK;
2651 uint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2652 BNX2X_PATH0_LOAD_CNT_SHIFT;
2653 uint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2654
2655 val = ((val & mask) >> shift);
2656
2657 return val != 0;
2658 }
2659
2660 /* set pf load mark */
bnx2x_set_pf_load(struct bnx2x_softc * sc)2661 static void bnx2x_set_pf_load(struct bnx2x_softc *sc)
2662 {
2663 uint32_t val;
2664 uint32_t val1;
2665 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2666 BNX2X_PATH0_LOAD_CNT_MASK;
2667 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2668 BNX2X_PATH0_LOAD_CNT_SHIFT;
2669
2670 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2671
2672 PMD_INIT_FUNC_TRACE(sc);
2673
2674 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2675
2676 /* get the current counter value */
2677 val1 = ((val & mask) >> shift);
2678
2679 /* set bit of this PF */
2680 val1 |= (1 << SC_ABS_FUNC(sc));
2681
2682 /* clear the old value */
2683 val &= ~mask;
2684
2685 /* set the new one */
2686 val |= ((val1 << shift) & mask);
2687
2688 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2689
2690 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2691 }
2692
2693 /* clear pf load mark */
bnx2x_clear_pf_load(struct bnx2x_softc * sc)2694 static uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)
2695 {
2696 uint32_t val1, val;
2697 uint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :
2698 BNX2X_PATH0_LOAD_CNT_MASK;
2699 uint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
2700 BNX2X_PATH0_LOAD_CNT_SHIFT;
2701
2702 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2703 val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);
2704
2705 /* get the current counter value */
2706 val1 = (val & mask) >> shift;
2707
2708 /* clear bit of that PF */
2709 val1 &= ~(1 << SC_ABS_FUNC(sc));
2710
2711 /* clear the old value */
2712 val &= ~mask;
2713
2714 /* set the new one */
2715 val |= ((val1 << shift) & mask);
2716
2717 REG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);
2718 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
2719 return val1 != 0;
2720 }
2721
2722 /* send load request to MCP and analyze response */
bnx2x_nic_load_request(struct bnx2x_softc * sc,uint32_t * load_code)2723 static int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)
2724 {
2725 PMD_INIT_FUNC_TRACE(sc);
2726
2727 /* init fw_seq */
2728 sc->fw_seq =
2729 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
2730 DRV_MSG_SEQ_NUMBER_MASK);
2731
2732 PMD_DRV_LOG(DEBUG, sc, "initial fw_seq 0x%04x", sc->fw_seq);
2733
2734 #ifdef BNX2X_PULSE
2735 /* get the current FW pulse sequence */
2736 sc->fw_drv_pulse_wr_seq =
2737 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
2738 DRV_PULSE_SEQ_MASK);
2739 #else
2740 /* set ALWAYS_ALIVE bit in shmem */
2741 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2742 bnx2x_drv_pulse(sc);
2743 #endif
2744
2745 /* load request */
2746 (*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
2747 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2748
2749 /* if the MCP fails to respond we must abort */
2750 if (!(*load_code)) {
2751 PMD_DRV_LOG(NOTICE, sc, "MCP response failure!");
2752 return -1;
2753 }
2754
2755 /* if MCP refused then must abort */
2756 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2757 PMD_DRV_LOG(NOTICE, sc, "MCP refused load request");
2758 return -1;
2759 }
2760
2761 return 0;
2762 }
2763
2764 /*
2765 * Check whether another PF has already loaded FW to chip. In virtualized
2766 * environments a pf from anoth VM may have already initialized the device
2767 * including loading FW.
2768 */
bnx2x_nic_load_analyze_req(struct bnx2x_softc * sc,uint32_t load_code)2769 static int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)
2770 {
2771 uint32_t my_fw, loaded_fw;
2772
2773 /* is another pf loaded on this engine? */
2774 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
2775 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
2776 /* build my FW version dword */
2777 my_fw = (BNX2X_5710_FW_MAJOR_VERSION +
2778 (BNX2X_5710_FW_MINOR_VERSION << 8) +
2779 (BNX2X_5710_FW_REVISION_VERSION << 16) +
2780 (BNX2X_5710_FW_ENGINEERING_VERSION << 24));
2781
2782 /* read loaded FW from chip */
2783 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
2784 PMD_DRV_LOG(DEBUG, sc, "loaded FW 0x%08x / my FW 0x%08x",
2785 loaded_fw, my_fw);
2786
2787 /* abort nic load if version mismatch */
2788 if (my_fw != loaded_fw) {
2789 PMD_DRV_LOG(NOTICE, sc,
2790 "FW 0x%08x already loaded (mine is 0x%08x)",
2791 loaded_fw, my_fw);
2792 return -1;
2793 }
2794 }
2795
2796 return 0;
2797 }
2798
2799 /* mark PMF if applicable */
bnx2x_nic_load_pmf(struct bnx2x_softc * sc,uint32_t load_code)2800 static void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)
2801 {
2802 uint32_t ncsi_oem_data_addr;
2803
2804 PMD_INIT_FUNC_TRACE(sc);
2805
2806 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2807 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2808 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2809 /*
2810 * Barrier here for ordering between the writing to sc->port.pmf here
2811 * and reading it from the periodic task.
2812 */
2813 sc->port.pmf = 1;
2814 mb();
2815 } else {
2816 sc->port.pmf = 0;
2817 }
2818
2819 PMD_DRV_LOG(DEBUG, sc, "pmf %d", sc->port.pmf);
2820
2821 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
2822 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
2823 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
2824 if (ncsi_oem_data_addr) {
2825 REG_WR(sc,
2826 (ncsi_oem_data_addr +
2827 offsetof(struct glob_ncsi_oem_data,
2828 driver_version)), 0);
2829 }
2830 }
2831 }
2832 }
2833
bnx2x_read_mf_cfg(struct bnx2x_softc * sc)2834 static void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)
2835 {
2836 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
2837 int abs_func;
2838 int vn;
2839
2840 if (BNX2X_NOMCP(sc)) {
2841 return; /* what should be the default bvalue in this case */
2842 }
2843
2844 /*
2845 * The formula for computing the absolute function number is...
2846 * For 2 port configuration (4 functions per port):
2847 * abs_func = 2 * vn + SC_PORT + SC_PATH
2848 * For 4 port configuration (2 functions per port):
2849 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
2850 */
2851 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
2852 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
2853 if (abs_func >= E1H_FUNC_MAX) {
2854 break;
2855 }
2856 sc->devinfo.mf_info.mf_config[vn] =
2857 MFCFG_RD(sc, func_mf_config[abs_func].config);
2858 }
2859
2860 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
2861 FUNC_MF_CFG_FUNC_DISABLED) {
2862 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
2863 sc->flags |= BNX2X_MF_FUNC_DIS;
2864 } else {
2865 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
2866 sc->flags &= ~BNX2X_MF_FUNC_DIS;
2867 }
2868 }
2869
2870 /* acquire split MCP access lock register */
bnx2x_acquire_alr(struct bnx2x_softc * sc)2871 static int bnx2x_acquire_alr(struct bnx2x_softc *sc)
2872 {
2873 uint32_t j, val;
2874
2875 for (j = 0; j < 1000; j++) {
2876 val = (1UL << 31);
2877 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
2878 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
2879 if (val & (1L << 31))
2880 break;
2881
2882 DELAY(5000);
2883 }
2884
2885 if (!(val & (1L << 31))) {
2886 PMD_DRV_LOG(NOTICE, sc, "Cannot acquire MCP access lock register");
2887 return -1;
2888 }
2889
2890 return 0;
2891 }
2892
2893 /* release split MCP access lock register */
bnx2x_release_alr(struct bnx2x_softc * sc)2894 static void bnx2x_release_alr(struct bnx2x_softc *sc)
2895 {
2896 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
2897 }
2898
bnx2x_fan_failure(struct bnx2x_softc * sc)2899 static void bnx2x_fan_failure(struct bnx2x_softc *sc)
2900 {
2901 int port = SC_PORT(sc);
2902 uint32_t ext_phy_config;
2903
2904 /* mark the failure */
2905 ext_phy_config =
2906 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2907
2908 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2909 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2910 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
2911 ext_phy_config);
2912
2913 /* log the failure */
2914 PMD_DRV_LOG(INFO, sc,
2915 "Fan Failure has caused the driver to shutdown "
2916 "the card to prevent permanent damage. "
2917 "Please contact OEM Support for assistance");
2918
2919 rte_panic("Schedule task to handle fan failure");
2920 }
2921
2922 /* this function is called upon a link interrupt */
bnx2x_link_attn(struct bnx2x_softc * sc)2923 static void bnx2x_link_attn(struct bnx2x_softc *sc)
2924 {
2925 uint32_t pause_enabled = 0;
2926 struct host_port_stats *pstats;
2927 int cmng_fns;
2928
2929 /* Make sure that we are synced with the current statistics */
2930 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
2931
2932 elink_link_update(&sc->link_params, &sc->link_vars);
2933
2934 if (sc->link_vars.link_up) {
2935
2936 /* dropless flow control */
2937 if (sc->dropless_fc) {
2938 pause_enabled = 0;
2939
2940 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
2941 pause_enabled = 1;
2942 }
2943
2944 REG_WR(sc,
2945 (BAR_USTRORM_INTMEM +
2946 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
2947 pause_enabled);
2948 }
2949
2950 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
2951 pstats = BNX2X_SP(sc, port_stats);
2952 /* reset old mac stats */
2953 memset(&(pstats->mac_stx[0]), 0,
2954 sizeof(struct mac_stx));
2955 }
2956
2957 if (sc->state == BNX2X_STATE_OPEN) {
2958 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
2959 }
2960 }
2961
2962 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
2963 cmng_fns = bnx2x_get_cmng_fns_mode(sc);
2964
2965 if (cmng_fns != CMNG_FNS_NONE) {
2966 bnx2x_cmng_fns_init(sc, FALSE, cmng_fns);
2967 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
2968 }
2969 }
2970
2971 bnx2x_link_report_locked(sc);
2972
2973 if (IS_MF(sc)) {
2974 bnx2x_link_sync_notify(sc);
2975 }
2976 }
2977
bnx2x_attn_int_asserted(struct bnx2x_softc * sc,uint32_t asserted)2978 static void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)
2979 {
2980 int port = SC_PORT(sc);
2981 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2982 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2983 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2984 NIG_REG_MASK_INTERRUPT_PORT0;
2985 uint32_t aeu_mask;
2986 uint32_t nig_mask = 0;
2987 uint32_t reg_addr;
2988 uint32_t igu_acked;
2989 uint32_t cnt;
2990
2991 if (sc->attn_state & asserted) {
2992 PMD_DRV_LOG(ERR, sc, "IGU ERROR attn=0x%08x", asserted);
2993 }
2994
2995 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2996
2997 aeu_mask = REG_RD(sc, aeu_addr);
2998
2999 aeu_mask &= ~(asserted & 0x3ff);
3000
3001 REG_WR(sc, aeu_addr, aeu_mask);
3002
3003 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3004
3005 sc->attn_state |= asserted;
3006
3007 if (asserted & ATTN_HARD_WIRED_MASK) {
3008 if (asserted & ATTN_NIG_FOR_FUNC) {
3009
3010 bnx2x_acquire_phy_lock(sc);
3011 /* save nig interrupt mask */
3012 nig_mask = REG_RD(sc, nig_int_mask_addr);
3013
3014 /* If nig_mask is not set, no need to call the update function */
3015 if (nig_mask) {
3016 REG_WR(sc, nig_int_mask_addr, 0);
3017
3018 bnx2x_link_attn(sc);
3019 }
3020
3021 /* handle unicore attn? */
3022 }
3023
3024 if (asserted & ATTN_SW_TIMER_4_FUNC) {
3025 PMD_DRV_LOG(DEBUG, sc, "ATTN_SW_TIMER_4_FUNC!");
3026 }
3027
3028 if (asserted & GPIO_2_FUNC) {
3029 PMD_DRV_LOG(DEBUG, sc, "GPIO_2_FUNC!");
3030 }
3031
3032 if (asserted & GPIO_3_FUNC) {
3033 PMD_DRV_LOG(DEBUG, sc, "GPIO_3_FUNC!");
3034 }
3035
3036 if (asserted & GPIO_4_FUNC) {
3037 PMD_DRV_LOG(DEBUG, sc, "GPIO_4_FUNC!");
3038 }
3039
3040 if (port == 0) {
3041 if (asserted & ATTN_GENERAL_ATTN_1) {
3042 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_1!");
3043 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3044 }
3045 if (asserted & ATTN_GENERAL_ATTN_2) {
3046 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_2!");
3047 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3048 }
3049 if (asserted & ATTN_GENERAL_ATTN_3) {
3050 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_3!");
3051 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3052 }
3053 } else {
3054 if (asserted & ATTN_GENERAL_ATTN_4) {
3055 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_4!");
3056 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3057 }
3058 if (asserted & ATTN_GENERAL_ATTN_5) {
3059 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_5!");
3060 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3061 }
3062 if (asserted & ATTN_GENERAL_ATTN_6) {
3063 PMD_DRV_LOG(DEBUG, sc, "ATTN_GENERAL_ATTN_6!");
3064 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3065 }
3066 }
3067 }
3068 /* hardwired */
3069 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3070 reg_addr =
3071 (HC_REG_COMMAND_REG + port * 32 +
3072 COMMAND_REG_ATTN_BITS_SET);
3073 } else {
3074 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);
3075 }
3076
3077 PMD_DRV_LOG(DEBUG, sc, "about to mask 0x%08x at %s addr 0x%08x",
3078 asserted,
3079 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
3080 reg_addr);
3081 REG_WR(sc, reg_addr, asserted);
3082
3083 /* now set back the mask */
3084 if (asserted & ATTN_NIG_FOR_FUNC) {
3085 /*
3086 * Verify that IGU ack through BAR was written before restoring
3087 * NIG mask. This loop should exit after 2-3 iterations max.
3088 */
3089 if (sc->devinfo.int_block != INT_BLOCK_HC) {
3090 cnt = 0;
3091
3092 do {
3093 igu_acked =
3094 REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
3095 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)
3096 && (++cnt < MAX_IGU_ATTN_ACK_TO));
3097
3098 if (!igu_acked) {
3099 PMD_DRV_LOG(ERR, sc,
3100 "Failed to verify IGU ack on time");
3101 }
3102
3103 mb();
3104 }
3105
3106 REG_WR(sc, nig_int_mask_addr, nig_mask);
3107
3108 bnx2x_release_phy_lock(sc);
3109 }
3110 }
3111
3112 static void
bnx2x_print_next_block(__rte_unused struct bnx2x_softc * sc,__rte_unused int idx,__rte_unused const char * blk)3113 bnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,
3114 __rte_unused const char *blk)
3115 {
3116 PMD_DRV_LOG(INFO, sc, "%s%s", idx ? ", " : "", blk);
3117 }
3118
3119 static int
bnx2x_check_blocks_with_parity0(struct bnx2x_softc * sc,uint32_t sig,int par_num,uint8_t print)3120 bnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3121 uint8_t print)
3122 {
3123 uint32_t cur_bit = 0;
3124 int i = 0;
3125
3126 for (i = 0; sig; i++) {
3127 cur_bit = ((uint32_t) 0x1 << i);
3128 if (sig & cur_bit) {
3129 switch (cur_bit) {
3130 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3131 if (print)
3132 bnx2x_print_next_block(sc, par_num++,
3133 "BRB");
3134 break;
3135 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3136 if (print)
3137 bnx2x_print_next_block(sc, par_num++,
3138 "PARSER");
3139 break;
3140 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3141 if (print)
3142 bnx2x_print_next_block(sc, par_num++,
3143 "TSDM");
3144 break;
3145 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3146 if (print)
3147 bnx2x_print_next_block(sc, par_num++,
3148 "SEARCHER");
3149 break;
3150 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3151 if (print)
3152 bnx2x_print_next_block(sc, par_num++,
3153 "TCM");
3154 break;
3155 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3156 if (print)
3157 bnx2x_print_next_block(sc, par_num++,
3158 "TSEMI");
3159 break;
3160 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3161 if (print)
3162 bnx2x_print_next_block(sc, par_num++,
3163 "XPB");
3164 break;
3165 }
3166
3167 /* Clear the bit */
3168 sig &= ~cur_bit;
3169 }
3170 }
3171
3172 return par_num;
3173 }
3174
3175 static int
bnx2x_check_blocks_with_parity1(struct bnx2x_softc * sc,uint32_t sig,int par_num,uint8_t * global,uint8_t print)3176 bnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3177 uint8_t * global, uint8_t print)
3178 {
3179 int i = 0;
3180 uint32_t cur_bit = 0;
3181 for (i = 0; sig; i++) {
3182 cur_bit = ((uint32_t) 0x1 << i);
3183 if (sig & cur_bit) {
3184 switch (cur_bit) {
3185 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3186 if (print)
3187 bnx2x_print_next_block(sc, par_num++,
3188 "PBF");
3189 break;
3190 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3191 if (print)
3192 bnx2x_print_next_block(sc, par_num++,
3193 "QM");
3194 break;
3195 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3196 if (print)
3197 bnx2x_print_next_block(sc, par_num++,
3198 "TM");
3199 break;
3200 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3201 if (print)
3202 bnx2x_print_next_block(sc, par_num++,
3203 "XSDM");
3204 break;
3205 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3206 if (print)
3207 bnx2x_print_next_block(sc, par_num++,
3208 "XCM");
3209 break;
3210 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3211 if (print)
3212 bnx2x_print_next_block(sc, par_num++,
3213 "XSEMI");
3214 break;
3215 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3216 if (print)
3217 bnx2x_print_next_block(sc, par_num++,
3218 "DOORBELLQ");
3219 break;
3220 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3221 if (print)
3222 bnx2x_print_next_block(sc, par_num++,
3223 "NIG");
3224 break;
3225 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3226 if (print)
3227 bnx2x_print_next_block(sc, par_num++,
3228 "VAUX PCI CORE");
3229 *global = TRUE;
3230 break;
3231 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3232 if (print)
3233 bnx2x_print_next_block(sc, par_num++,
3234 "DEBUG");
3235 break;
3236 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3237 if (print)
3238 bnx2x_print_next_block(sc, par_num++,
3239 "USDM");
3240 break;
3241 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3242 if (print)
3243 bnx2x_print_next_block(sc, par_num++,
3244 "UCM");
3245 break;
3246 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3247 if (print)
3248 bnx2x_print_next_block(sc, par_num++,
3249 "USEMI");
3250 break;
3251 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3252 if (print)
3253 bnx2x_print_next_block(sc, par_num++,
3254 "UPB");
3255 break;
3256 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3257 if (print)
3258 bnx2x_print_next_block(sc, par_num++,
3259 "CSDM");
3260 break;
3261 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3262 if (print)
3263 bnx2x_print_next_block(sc, par_num++,
3264 "CCM");
3265 break;
3266 }
3267
3268 /* Clear the bit */
3269 sig &= ~cur_bit;
3270 }
3271 }
3272
3273 return par_num;
3274 }
3275
3276 static int
bnx2x_check_blocks_with_parity2(struct bnx2x_softc * sc,uint32_t sig,int par_num,uint8_t print)3277 bnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3278 uint8_t print)
3279 {
3280 uint32_t cur_bit = 0;
3281 int i = 0;
3282
3283 for (i = 0; sig; i++) {
3284 cur_bit = ((uint32_t) 0x1 << i);
3285 if (sig & cur_bit) {
3286 switch (cur_bit) {
3287 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3288 if (print)
3289 bnx2x_print_next_block(sc, par_num++,
3290 "CSEMI");
3291 break;
3292 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3293 if (print)
3294 bnx2x_print_next_block(sc, par_num++,
3295 "PXP");
3296 break;
3297 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3298 if (print)
3299 bnx2x_print_next_block(sc, par_num++,
3300 "PXPPCICLOCKCLIENT");
3301 break;
3302 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3303 if (print)
3304 bnx2x_print_next_block(sc, par_num++,
3305 "CFC");
3306 break;
3307 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3308 if (print)
3309 bnx2x_print_next_block(sc, par_num++,
3310 "CDU");
3311 break;
3312 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3313 if (print)
3314 bnx2x_print_next_block(sc, par_num++,
3315 "DMAE");
3316 break;
3317 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3318 if (print)
3319 bnx2x_print_next_block(sc, par_num++,
3320 "IGU");
3321 break;
3322 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3323 if (print)
3324 bnx2x_print_next_block(sc, par_num++,
3325 "MISC");
3326 break;
3327 }
3328
3329 /* Clear the bit */
3330 sig &= ~cur_bit;
3331 }
3332 }
3333
3334 return par_num;
3335 }
3336
3337 static int
bnx2x_check_blocks_with_parity3(struct bnx2x_softc * sc,uint32_t sig,int par_num,uint8_t * global,uint8_t print)3338 bnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3339 uint8_t * global, uint8_t print)
3340 {
3341 uint32_t cur_bit = 0;
3342 int i = 0;
3343
3344 for (i = 0; sig; i++) {
3345 cur_bit = ((uint32_t) 0x1 << i);
3346 if (sig & cur_bit) {
3347 switch (cur_bit) {
3348 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3349 if (print)
3350 bnx2x_print_next_block(sc, par_num++,
3351 "MCP ROM");
3352 *global = TRUE;
3353 break;
3354 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3355 if (print)
3356 bnx2x_print_next_block(sc, par_num++,
3357 "MCP UMP RX");
3358 *global = TRUE;
3359 break;
3360 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3361 if (print)
3362 bnx2x_print_next_block(sc, par_num++,
3363 "MCP UMP TX");
3364 *global = TRUE;
3365 break;
3366 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3367 if (print)
3368 bnx2x_print_next_block(sc, par_num++,
3369 "MCP SCPAD");
3370 *global = TRUE;
3371 break;
3372 }
3373
3374 /* Clear the bit */
3375 sig &= ~cur_bit;
3376 }
3377 }
3378
3379 return par_num;
3380 }
3381
3382 static int
bnx2x_check_blocks_with_parity4(struct bnx2x_softc * sc,uint32_t sig,int par_num,uint8_t print)3383 bnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,
3384 uint8_t print)
3385 {
3386 uint32_t cur_bit = 0;
3387 int i = 0;
3388
3389 for (i = 0; sig; i++) {
3390 cur_bit = ((uint32_t) 0x1 << i);
3391 if (sig & cur_bit) {
3392 switch (cur_bit) {
3393 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3394 if (print)
3395 bnx2x_print_next_block(sc, par_num++,
3396 "PGLUE_B");
3397 break;
3398 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3399 if (print)
3400 bnx2x_print_next_block(sc, par_num++,
3401 "ATC");
3402 break;
3403 }
3404
3405 /* Clear the bit */
3406 sig &= ~cur_bit;
3407 }
3408 }
3409
3410 return par_num;
3411 }
3412
3413 static uint8_t
bnx2x_parity_attn(struct bnx2x_softc * sc,uint8_t * global,uint8_t print,uint32_t * sig)3414 bnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,
3415 uint32_t * sig)
3416 {
3417 int par_num = 0;
3418
3419 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
3420 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
3421 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
3422 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
3423 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
3424 PMD_DRV_LOG(ERR, sc,
3425 "Parity error: HW block parity attention:"
3426 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x",
3427 (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),
3428 (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),
3429 (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),
3430 (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),
3431 (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));
3432
3433 if (print)
3434 PMD_DRV_LOG(INFO, sc, "Parity errors detected in blocks: ");
3435
3436 par_num =
3437 bnx2x_check_blocks_with_parity0(sc, sig[0] &
3438 HW_PRTY_ASSERT_SET_0,
3439 par_num, print);
3440 par_num =
3441 bnx2x_check_blocks_with_parity1(sc, sig[1] &
3442 HW_PRTY_ASSERT_SET_1,
3443 par_num, global, print);
3444 par_num =
3445 bnx2x_check_blocks_with_parity2(sc, sig[2] &
3446 HW_PRTY_ASSERT_SET_2,
3447 par_num, print);
3448 par_num =
3449 bnx2x_check_blocks_with_parity3(sc, sig[3] &
3450 HW_PRTY_ASSERT_SET_3,
3451 par_num, global, print);
3452 par_num =
3453 bnx2x_check_blocks_with_parity4(sc, sig[4] &
3454 HW_PRTY_ASSERT_SET_4,
3455 par_num, print);
3456
3457 if (print)
3458 PMD_DRV_LOG(INFO, sc, "");
3459
3460 return TRUE;
3461 }
3462
3463 return FALSE;
3464 }
3465
3466 static uint8_t
bnx2x_chk_parity_attn(struct bnx2x_softc * sc,uint8_t * global,uint8_t print)3467 bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)
3468 {
3469 struct attn_route attn = { {0} };
3470 int port = SC_PORT(sc);
3471
3472 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
3473 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
3474 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
3475 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
3476
3477 if (!CHIP_IS_E1x(sc))
3478 attn.sig[4] =
3479 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
3480
3481 return bnx2x_parity_attn(sc, global, print, attn.sig);
3482 }
3483
bnx2x_attn_int_deasserted4(struct bnx2x_softc * sc,uint32_t attn)3484 static void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)
3485 {
3486 uint32_t val;
3487
3488 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3489 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3490 PMD_DRV_LOG(INFO, sc, "ERROR: PGLUE hw attention 0x%08x", val);
3491 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3492 PMD_DRV_LOG(INFO, sc,
3493 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR");
3494 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3495 PMD_DRV_LOG(INFO, sc,
3496 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR");
3497 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3498 PMD_DRV_LOG(INFO, sc,
3499 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN");
3500 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3501 PMD_DRV_LOG(INFO, sc,
3502 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN");
3503 if (val &
3504 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3505 PMD_DRV_LOG(INFO, sc,
3506 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN");
3507 if (val &
3508 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3509 PMD_DRV_LOG(INFO, sc,
3510 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN");
3511 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3512 PMD_DRV_LOG(INFO, sc,
3513 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN");
3514 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3515 PMD_DRV_LOG(INFO, sc,
3516 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN");
3517 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3518 PMD_DRV_LOG(INFO, sc,
3519 "ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW");
3520 }
3521
3522 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3523 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
3524 PMD_DRV_LOG(INFO, sc, "ERROR: ATC hw attention 0x%08x", val);
3525 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3526 PMD_DRV_LOG(INFO, sc,
3527 "ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR");
3528 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3529 PMD_DRV_LOG(INFO, sc,
3530 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND");
3531 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3532 PMD_DRV_LOG(INFO, sc,
3533 "ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS");
3534 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3535 PMD_DRV_LOG(INFO, sc,
3536 "ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT");
3537 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3538 PMD_DRV_LOG(INFO, sc,
3539 "ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR");
3540 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3541 PMD_DRV_LOG(INFO, sc,
3542 "ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU");
3543 }
3544
3545 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3546 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3547 PMD_DRV_LOG(INFO, sc,
3548 "ERROR: FATAL parity attention set4 0x%08x",
3549 (uint32_t) (attn &
3550 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
3551 |
3552 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3553 }
3554 }
3555
bnx2x_e1h_disable(struct bnx2x_softc * sc)3556 static void bnx2x_e1h_disable(struct bnx2x_softc *sc)
3557 {
3558 int port = SC_PORT(sc);
3559
3560 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3561 }
3562
bnx2x_e1h_enable(struct bnx2x_softc * sc)3563 static void bnx2x_e1h_enable(struct bnx2x_softc *sc)
3564 {
3565 int port = SC_PORT(sc);
3566
3567 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3568 }
3569
3570 /*
3571 * called due to MCP event (on pmf):
3572 * reread new bandwidth configuration
3573 * configure FW
3574 * notify others function about the change
3575 */
bnx2x_config_mf_bw(struct bnx2x_softc * sc)3576 static void bnx2x_config_mf_bw(struct bnx2x_softc *sc)
3577 {
3578 if (sc->link_vars.link_up) {
3579 bnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
3580 bnx2x_link_sync_notify(sc);
3581 }
3582
3583 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
3584 }
3585
bnx2x_set_mf_bw(struct bnx2x_softc * sc)3586 static void bnx2x_set_mf_bw(struct bnx2x_softc *sc)
3587 {
3588 bnx2x_config_mf_bw(sc);
3589 bnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3590 }
3591
bnx2x_handle_eee_event(struct bnx2x_softc * sc)3592 static void bnx2x_handle_eee_event(struct bnx2x_softc *sc)
3593 {
3594 bnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3595 }
3596
3597 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3598
bnx2x_drv_info_ether_stat(struct bnx2x_softc * sc)3599 static void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)
3600 {
3601 struct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;
3602
3603 strncpy(ether_stat->version, BNX2X_DRIVER_VERSION,
3604 ETH_STAT_INFO_VERSION_LEN);
3605
3606 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
3607 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3608 ether_stat->mac_local + MAC_PAD,
3609 MAC_PAD, ETH_ALEN);
3610
3611 ether_stat->mtu_size = sc->mtu;
3612
3613 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3614 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
3615
3616 ether_stat->txq_size = sc->tx_ring_size;
3617 ether_stat->rxq_size = sc->rx_ring_size;
3618 }
3619
bnx2x_handle_drv_info_req(struct bnx2x_softc * sc)3620 static void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)
3621 {
3622 enum drv_info_opcode op_code;
3623 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
3624
3625 /* if drv_info version supported by MFW doesn't match - send NACK */
3626 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3627 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3628 return;
3629 }
3630
3631 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3632 DRV_INFO_CONTROL_OP_CODE_SHIFT);
3633
3634 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
3635
3636 switch (op_code) {
3637 case ETH_STATS_OPCODE:
3638 bnx2x_drv_info_ether_stat(sc);
3639 break;
3640 case FCOE_STATS_OPCODE:
3641 case ISCSI_STATS_OPCODE:
3642 default:
3643 /* if op code isn't supported - send NACK */
3644 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3645 return;
3646 }
3647
3648 /*
3649 * If we got drv_info attn from MFW then these fields are defined in
3650 * shmem2 for sure
3651 */
3652 SHMEM2_WR(sc, drv_info_host_addr_lo,
3653 U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3654 SHMEM2_WR(sc, drv_info_host_addr_hi,
3655 U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));
3656
3657 bnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3658 }
3659
bnx2x_dcc_event(struct bnx2x_softc * sc,uint32_t dcc_event)3660 static void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)
3661 {
3662 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3663 /*
3664 * This is the only place besides the function initialization
3665 * where the sc->flags can change so it is done without any
3666 * locks
3667 */
3668 if (sc->devinfo.
3669 mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3670 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function disabled");
3671 sc->flags |= BNX2X_MF_FUNC_DIS;
3672 bnx2x_e1h_disable(sc);
3673 } else {
3674 PMD_DRV_LOG(DEBUG, sc, "mf_cfg function enabled");
3675 sc->flags &= ~BNX2X_MF_FUNC_DIS;
3676 bnx2x_e1h_enable(sc);
3677 }
3678 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3679 }
3680
3681 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3682 bnx2x_config_mf_bw(sc);
3683 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3684 }
3685
3686 /* Report results to MCP */
3687 if (dcc_event)
3688 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
3689 else
3690 bnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
3691 }
3692
bnx2x_pmf_update(struct bnx2x_softc * sc)3693 static void bnx2x_pmf_update(struct bnx2x_softc *sc)
3694 {
3695 int port = SC_PORT(sc);
3696 uint32_t val;
3697
3698 sc->port.pmf = 1;
3699
3700 /*
3701 * We need the mb() to ensure the ordering between the writing to
3702 * sc->port.pmf here and reading it from the bnx2x_periodic_task().
3703 */
3704 mb();
3705
3706 /* enable nig attention */
3707 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
3708 if (sc->devinfo.int_block == INT_BLOCK_HC) {
3709 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
3710 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
3711 } else if (!CHIP_IS_E1x(sc)) {
3712 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
3713 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
3714 }
3715
3716 bnx2x_stats_handle(sc, STATS_EVENT_PMF);
3717 }
3718
bnx2x_mc_assert(struct bnx2x_softc * sc)3719 static int bnx2x_mc_assert(struct bnx2x_softc *sc)
3720 {
3721 char last_idx;
3722 int i, rc = 0;
3723 __rte_unused uint32_t row0, row1, row2, row3;
3724
3725 /* XSTORM */
3726 last_idx =
3727 REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
3728 if (last_idx)
3729 PMD_DRV_LOG(ERR, sc, "XSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3730
3731 /* print the asserts */
3732 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3733
3734 row0 =
3735 REG_RD(sc,
3736 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
3737 row1 =
3738 REG_RD(sc,
3739 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3740 4);
3741 row2 =
3742 REG_RD(sc,
3743 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3744 8);
3745 row3 =
3746 REG_RD(sc,
3747 BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +
3748 12);
3749
3750 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3751 PMD_DRV_LOG(ERR, sc,
3752 "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3753 i, row3, row2, row1, row0);
3754 rc++;
3755 } else {
3756 break;
3757 }
3758 }
3759
3760 /* TSTORM */
3761 last_idx =
3762 REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
3763 if (last_idx) {
3764 PMD_DRV_LOG(ERR, sc, "TSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3765 }
3766
3767 /* print the asserts */
3768 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3769
3770 row0 =
3771 REG_RD(sc,
3772 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
3773 row1 =
3774 REG_RD(sc,
3775 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3776 4);
3777 row2 =
3778 REG_RD(sc,
3779 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3780 8);
3781 row3 =
3782 REG_RD(sc,
3783 BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +
3784 12);
3785
3786 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3787 PMD_DRV_LOG(ERR, sc,
3788 "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3789 i, row3, row2, row1, row0);
3790 rc++;
3791 } else {
3792 break;
3793 }
3794 }
3795
3796 /* CSTORM */
3797 last_idx =
3798 REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
3799 if (last_idx) {
3800 PMD_DRV_LOG(ERR, sc, "CSTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3801 }
3802
3803 /* print the asserts */
3804 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3805
3806 row0 =
3807 REG_RD(sc,
3808 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
3809 row1 =
3810 REG_RD(sc,
3811 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3812 4);
3813 row2 =
3814 REG_RD(sc,
3815 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3816 8);
3817 row3 =
3818 REG_RD(sc,
3819 BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +
3820 12);
3821
3822 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3823 PMD_DRV_LOG(ERR, sc,
3824 "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3825 i, row3, row2, row1, row0);
3826 rc++;
3827 } else {
3828 break;
3829 }
3830 }
3831
3832 /* USTORM */
3833 last_idx =
3834 REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
3835 if (last_idx) {
3836 PMD_DRV_LOG(ERR, sc, "USTORM_ASSERT_LIST_INDEX 0x%x", last_idx);
3837 }
3838
3839 /* print the asserts */
3840 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
3841
3842 row0 =
3843 REG_RD(sc,
3844 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
3845 row1 =
3846 REG_RD(sc,
3847 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3848 4);
3849 row2 =
3850 REG_RD(sc,
3851 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3852 8);
3853 row3 =
3854 REG_RD(sc,
3855 BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +
3856 12);
3857
3858 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
3859 PMD_DRV_LOG(ERR, sc,
3860 "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x",
3861 i, row3, row2, row1, row0);
3862 rc++;
3863 } else {
3864 break;
3865 }
3866 }
3867
3868 return rc;
3869 }
3870
bnx2x_attn_int_deasserted3(struct bnx2x_softc * sc,uint32_t attn)3871 static void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)
3872 {
3873 int func = SC_FUNC(sc);
3874 uint32_t val;
3875
3876 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3877
3878 if (attn & BNX2X_PMF_LINK_ASSERT(sc)) {
3879
3880 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
3881 bnx2x_read_mf_cfg(sc);
3882 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
3883 MFCFG_RD(sc,
3884 func_mf_config[SC_ABS_FUNC(sc)].config);
3885 val =
3886 SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
3887
3888 if (val & DRV_STATUS_DCC_EVENT_MASK)
3889 bnx2x_dcc_event(sc,
3890 (val &
3891 DRV_STATUS_DCC_EVENT_MASK));
3892
3893 if (val & DRV_STATUS_SET_MF_BW)
3894 bnx2x_set_mf_bw(sc);
3895
3896 if (val & DRV_STATUS_DRV_INFO_REQ)
3897 bnx2x_handle_drv_info_req(sc);
3898
3899 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
3900 bnx2x_pmf_update(sc);
3901
3902 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3903 bnx2x_handle_eee_event(sc);
3904
3905 if (sc->link_vars.periodic_flags &
3906 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
3907 /* sync with link */
3908 bnx2x_acquire_phy_lock(sc);
3909 sc->link_vars.periodic_flags &=
3910 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
3911 bnx2x_release_phy_lock(sc);
3912 if (IS_MF(sc)) {
3913 bnx2x_link_sync_notify(sc);
3914 }
3915 bnx2x_link_report(sc);
3916 }
3917
3918 /*
3919 * Always call it here: bnx2x_link_report() will
3920 * prevent the link indication duplication.
3921 */
3922 bnx2x_link_status_update(sc);
3923
3924 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3925
3926 PMD_DRV_LOG(ERR, sc, "MC assert!");
3927 bnx2x_mc_assert(sc);
3928 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3929 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3930 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3931 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3932 rte_panic("MC assert!");
3933
3934 } else if (attn & BNX2X_MCP_ASSERT) {
3935
3936 PMD_DRV_LOG(ERR, sc, "MCP assert!");
3937 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3938
3939 } else {
3940 PMD_DRV_LOG(ERR, sc,
3941 "Unknown HW assert! (attn 0x%08x)", attn);
3942 }
3943 }
3944
3945 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3946 PMD_DRV_LOG(ERR, sc, "LATCHED attention 0x%08x (masked)", attn);
3947 if (attn & BNX2X_GRC_TIMEOUT) {
3948 val = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
3949 PMD_DRV_LOG(ERR, sc, "GRC time-out 0x%08x", val);
3950 }
3951 if (attn & BNX2X_GRC_RSV) {
3952 val = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
3953 PMD_DRV_LOG(ERR, sc, "GRC reserved 0x%08x", val);
3954 }
3955 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3956 }
3957 }
3958
bnx2x_attn_int_deasserted2(struct bnx2x_softc * sc,uint32_t attn)3959 static void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)
3960 {
3961 int port = SC_PORT(sc);
3962 int reg_offset;
3963 uint32_t val0, mask0, val1, mask1;
3964 uint32_t val;
3965
3966 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3967 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
3968 PMD_DRV_LOG(ERR, sc, "CFC hw attention 0x%08x", val);
3969 /* CFC error attention */
3970 if (val & 0x2) {
3971 PMD_DRV_LOG(ERR, sc, "FATAL error from CFC");
3972 }
3973 }
3974
3975 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3976 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
3977 PMD_DRV_LOG(ERR, sc, "PXP hw attention-0 0x%08x", val);
3978 /* RQ_USDMDP_FIFO_OVERFLOW */
3979 if (val & 0x18000) {
3980 PMD_DRV_LOG(ERR, sc, "FATAL error from PXP");
3981 }
3982
3983 if (!CHIP_IS_E1x(sc)) {
3984 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
3985 PMD_DRV_LOG(ERR, sc, "PXP hw attention-1 0x%08x", val);
3986 }
3987 }
3988 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
3989 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
3990
3991 if (attn & AEU_PXP2_HW_INT_BIT) {
3992 /* CQ47854 workaround do not panic on
3993 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
3994 */
3995 if (!CHIP_IS_E1x(sc)) {
3996 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
3997 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
3998 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
3999 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
4000 /*
4001 * If the only PXP2_EOP_ERROR_BIT is set in
4002 * STS0 and STS1 - clear it
4003 *
4004 * probably we lose additional attentions between
4005 * STS0 and STS_CLR0, in this case user will not
4006 * be notified about them
4007 */
4008 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
4009 !(val1 & mask1))
4010 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
4011
4012 /* print the register, since no one can restore it */
4013 PMD_DRV_LOG(ERR, sc,
4014 "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x", val0);
4015
4016 /*
4017 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
4018 * then notify
4019 */
4020 if (val0 & PXP2_EOP_ERROR_BIT) {
4021 PMD_DRV_LOG(ERR, sc, "PXP2_WR_PGLUE_EOP_ERROR");
4022
4023 /*
4024 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
4025 * set then clear attention from PXP2 block without panic
4026 */
4027 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
4028 ((val1 & mask1) == 0))
4029 attn &= ~AEU_PXP2_HW_INT_BIT;
4030 }
4031 }
4032 }
4033
4034 if (attn & HW_INTERRUT_ASSERT_SET_2) {
4035 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4036 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4037
4038 val = REG_RD(sc, reg_offset);
4039 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4040 REG_WR(sc, reg_offset, val);
4041
4042 PMD_DRV_LOG(ERR, sc,
4043 "FATAL HW block attention set2 0x%x",
4044 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));
4045 rte_panic("HW block attention set2");
4046 }
4047 }
4048
bnx2x_attn_int_deasserted1(struct bnx2x_softc * sc,uint32_t attn)4049 static void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)
4050 {
4051 int port = SC_PORT(sc);
4052 int reg_offset;
4053 uint32_t val;
4054
4055 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4056 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
4057 PMD_DRV_LOG(ERR, sc, "DB hw attention 0x%08x", val);
4058 /* DORQ discard attention */
4059 if (val & 0x2) {
4060 PMD_DRV_LOG(ERR, sc, "FATAL error from DORQ");
4061 }
4062 }
4063
4064 if (attn & HW_INTERRUT_ASSERT_SET_1) {
4065 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4066 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4067
4068 val = REG_RD(sc, reg_offset);
4069 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4070 REG_WR(sc, reg_offset, val);
4071
4072 PMD_DRV_LOG(ERR, sc,
4073 "FATAL HW block attention set1 0x%08x",
4074 (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));
4075 rte_panic("HW block attention set1");
4076 }
4077 }
4078
bnx2x_attn_int_deasserted0(struct bnx2x_softc * sc,uint32_t attn)4079 static void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)
4080 {
4081 int port = SC_PORT(sc);
4082 int reg_offset;
4083 uint32_t val;
4084
4085 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4086 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
4087
4088 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4089 val = REG_RD(sc, reg_offset);
4090 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4091 REG_WR(sc, reg_offset, val);
4092
4093 PMD_DRV_LOG(WARNING, sc, "SPIO5 hw attention");
4094
4095 /* Fan failure attention */
4096 elink_hw_reset_phy(&sc->link_params);
4097 bnx2x_fan_failure(sc);
4098 }
4099
4100 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
4101 bnx2x_acquire_phy_lock(sc);
4102 elink_handle_module_detect_int(&sc->link_params);
4103 bnx2x_release_phy_lock(sc);
4104 }
4105
4106 if (attn & HW_INTERRUT_ASSERT_SET_0) {
4107 val = REG_RD(sc, reg_offset);
4108 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4109 REG_WR(sc, reg_offset, val);
4110
4111 rte_panic("FATAL HW block attention set0 0x%lx",
4112 (attn & (unsigned long)HW_INTERRUT_ASSERT_SET_0));
4113 }
4114 }
4115
bnx2x_attn_int_deasserted(struct bnx2x_softc * sc,uint32_t deasserted)4116 static void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)
4117 {
4118 struct attn_route attn;
4119 struct attn_route *group_mask;
4120 int port = SC_PORT(sc);
4121 int index;
4122 uint32_t reg_addr;
4123 uint32_t val;
4124 uint32_t aeu_mask;
4125 uint8_t global = FALSE;
4126
4127 /*
4128 * Need to take HW lock because MCP or other port might also
4129 * try to handle this event.
4130 */
4131 bnx2x_acquire_alr(sc);
4132
4133 if (bnx2x_chk_parity_attn(sc, &global, TRUE)) {
4134 sc->recovery_state = BNX2X_RECOVERY_INIT;
4135
4136 /* disable HW interrupts */
4137 bnx2x_int_disable(sc);
4138 bnx2x_release_alr(sc);
4139 return;
4140 }
4141
4142 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
4143 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
4144 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
4145 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
4146 if (!CHIP_IS_E1x(sc)) {
4147 attn.sig[4] =
4148 REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);
4149 } else {
4150 attn.sig[4] = 0;
4151 }
4152
4153 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4154 if (deasserted & (1 << index)) {
4155 group_mask = &sc->attn_group[index];
4156
4157 bnx2x_attn_int_deasserted4(sc,
4158 attn.
4159 sig[4] & group_mask->sig[4]);
4160 bnx2x_attn_int_deasserted3(sc,
4161 attn.
4162 sig[3] & group_mask->sig[3]);
4163 bnx2x_attn_int_deasserted1(sc,
4164 attn.
4165 sig[1] & group_mask->sig[1]);
4166 bnx2x_attn_int_deasserted2(sc,
4167 attn.
4168 sig[2] & group_mask->sig[2]);
4169 bnx2x_attn_int_deasserted0(sc,
4170 attn.
4171 sig[0] & group_mask->sig[0]);
4172 }
4173 }
4174
4175 bnx2x_release_alr(sc);
4176
4177 if (sc->devinfo.int_block == INT_BLOCK_HC) {
4178 reg_addr = (HC_REG_COMMAND_REG + port * 32 +
4179 COMMAND_REG_ATTN_BITS_CLR);
4180 } else {
4181 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);
4182 }
4183
4184 val = ~deasserted;
4185 PMD_DRV_LOG(DEBUG, sc,
4186 "about to mask 0x%08x at %s addr 0x%08x", val,
4187 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU",
4188 reg_addr);
4189 REG_WR(sc, reg_addr, val);
4190
4191 if (~sc->attn_state & deasserted) {
4192 PMD_DRV_LOG(ERR, sc, "IGU error");
4193 }
4194
4195 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4196 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4197
4198 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4199
4200 aeu_mask = REG_RD(sc, reg_addr);
4201
4202 aeu_mask |= (deasserted & 0x3ff);
4203
4204 REG_WR(sc, reg_addr, aeu_mask);
4205 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4206
4207 sc->attn_state &= ~deasserted;
4208 }
4209
bnx2x_attn_int(struct bnx2x_softc * sc)4210 static void bnx2x_attn_int(struct bnx2x_softc *sc)
4211 {
4212 /* read local copy of bits */
4213 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
4214 uint32_t attn_ack =
4215 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
4216 uint32_t attn_state = sc->attn_state;
4217
4218 /* look for changed bits */
4219 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
4220 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
4221
4222 PMD_DRV_LOG(DEBUG, sc,
4223 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x",
4224 attn_bits, attn_ack, asserted, deasserted);
4225
4226 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
4227 PMD_DRV_LOG(ERR, sc, "BAD attention state");
4228 }
4229
4230 /* handle bits that were raised */
4231 if (asserted) {
4232 bnx2x_attn_int_asserted(sc, asserted);
4233 }
4234
4235 if (deasserted) {
4236 bnx2x_attn_int_deasserted(sc, deasserted);
4237 }
4238 }
4239
bnx2x_update_dsb_idx(struct bnx2x_softc * sc)4240 static uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)
4241 {
4242 struct host_sp_status_block *def_sb = sc->def_sb;
4243 uint16_t rc = 0;
4244
4245 if (!def_sb)
4246 return 0;
4247
4248 mb(); /* status block is written to by the chip */
4249
4250 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
4251 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
4252 rc |= BNX2X_DEF_SB_ATT_IDX;
4253 }
4254
4255 if (sc->def_idx != def_sb->sp_sb.running_index) {
4256 sc->def_idx = def_sb->sp_sb.running_index;
4257 rc |= BNX2X_DEF_SB_IDX;
4258 }
4259
4260 mb();
4261
4262 return rc;
4263 }
4264
bnx2x_cid_to_q_obj(struct bnx2x_softc * sc,uint32_t cid)4265 static struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,
4266 uint32_t cid)
4267 {
4268 return &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;
4269 }
4270
bnx2x_handle_mcast_eqe(struct bnx2x_softc * sc)4271 static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)
4272 {
4273 struct ecore_mcast_ramrod_params rparam;
4274 int rc;
4275
4276 memset(&rparam, 0, sizeof(rparam));
4277
4278 rparam.mcast_obj = &sc->mcast_obj;
4279
4280 /* clear pending state for the last command */
4281 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
4282
4283 /* if there are pending mcast commands - send them */
4284 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
4285 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4286 if (rc < 0) {
4287 PMD_DRV_LOG(INFO, sc,
4288 "Failed to send pending mcast commands (%d)",
4289 rc);
4290 }
4291 }
4292 }
4293
4294 static void
bnx2x_handle_classification_eqe(struct bnx2x_softc * sc,union event_ring_elem * elem)4295 bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)
4296 {
4297 uint32_t ramrod_flags = 0;
4298 int rc = 0;
4299 uint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4300 struct ecore_vlan_mac_obj *vlan_mac_obj;
4301
4302 /* always push next commands out, don't wait here */
4303 rte_bit_relaxed_set32(RAMROD_CONT, &ramrod_flags);
4304
4305 switch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {
4306 case ECORE_FILTER_MAC_PENDING:
4307 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MAC completions");
4308 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
4309 break;
4310
4311 case ECORE_FILTER_MCAST_PENDING:
4312 PMD_DRV_LOG(DEBUG, sc, "Got SETUP_MCAST completions");
4313 bnx2x_handle_mcast_eqe(sc);
4314 return;
4315
4316 default:
4317 PMD_DRV_LOG(NOTICE, sc, "Unsupported classification command: %d",
4318 elem->message.data.eth_event.echo);
4319 return;
4320 }
4321
4322 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
4323
4324 if (rc < 0) {
4325 PMD_DRV_LOG(NOTICE, sc,
4326 "Failed to schedule new commands (%d)", rc);
4327 } else if (rc > 0) {
4328 PMD_DRV_LOG(DEBUG, sc, "Scheduled next pending commands...");
4329 }
4330 }
4331
bnx2x_handle_rx_mode_eqe(struct bnx2x_softc * sc)4332 static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)
4333 {
4334 rte_bit_relaxed_clear32(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
4335
4336 /* send rx_mode command again if was requested */
4337 if (rte_bit_relaxed_test_and_clear32(ECORE_FILTER_RX_MODE_SCHED,
4338 &sc->sp_state))
4339 bnx2x_set_storm_rx_mode(sc);
4340 }
4341
bnx2x_update_eq_prod(struct bnx2x_softc * sc,uint16_t prod)4342 static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)
4343 {
4344 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
4345 wmb(); /* keep prod updates ordered */
4346 }
4347
bnx2x_eq_int(struct bnx2x_softc * sc)4348 static void bnx2x_eq_int(struct bnx2x_softc *sc)
4349 {
4350 uint16_t hw_cons, sw_cons, sw_prod;
4351 union event_ring_elem *elem;
4352 uint8_t echo;
4353 uint32_t cid;
4354 uint8_t opcode;
4355 int spqe_cnt = 0;
4356 struct ecore_queue_sp_obj *q_obj;
4357 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
4358 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
4359
4360 hw_cons = le16toh(*sc->eq_cons_sb);
4361
4362 /*
4363 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
4364 * when we get to the next-page we need to adjust so the loop
4365 * condition below will be met. The next element is the size of a
4366 * regular element and hence incrementing by 1
4367 */
4368 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
4369 hw_cons++;
4370 }
4371
4372 /*
4373 * This function may never run in parallel with itself for a
4374 * specific sc and no need for a read memory barrier here.
4375 */
4376 sw_cons = sc->eq_cons;
4377 sw_prod = sc->eq_prod;
4378
4379 for (;
4380 sw_cons != hw_cons;
4381 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4382
4383 elem = &sc->eq[EQ_DESC(sw_cons)];
4384
4385 /* elem CID originates from FW, actually LE */
4386 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4387 opcode = elem->message.opcode;
4388
4389 /* handle eq element */
4390 switch (opcode) {
4391 case EVENT_RING_OPCODE_STAT_QUERY:
4392 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "got statistics completion event %d",
4393 sc->stats_comp++);
4394 /* nothing to do with stats comp */
4395 goto next_spqe;
4396
4397 case EVENT_RING_OPCODE_CFC_DEL:
4398 /* handle according to cid range */
4399 /* we may want to verify here that the sc state is HALTING */
4400 PMD_DRV_LOG(DEBUG, sc, "got delete ramrod for MULTI[%d]",
4401 cid);
4402 q_obj = bnx2x_cid_to_q_obj(sc, cid);
4403 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
4404 break;
4405 }
4406 goto next_spqe;
4407
4408 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4409 PMD_DRV_LOG(DEBUG, sc, "got STOP TRAFFIC");
4410 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
4411 break;
4412 }
4413 goto next_spqe;
4414
4415 case EVENT_RING_OPCODE_START_TRAFFIC:
4416 PMD_DRV_LOG(DEBUG, sc, "got START TRAFFIC");
4417 if (f_obj->complete_cmd
4418 (sc, f_obj, ECORE_F_CMD_TX_START)) {
4419 break;
4420 }
4421 goto next_spqe;
4422
4423 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4424 echo = elem->message.data.function_update_event.echo;
4425 if (echo == SWITCH_UPDATE) {
4426 PMD_DRV_LOG(DEBUG, sc,
4427 "got FUNC_SWITCH_UPDATE ramrod");
4428 if (f_obj->complete_cmd(sc, f_obj,
4429 ECORE_F_CMD_SWITCH_UPDATE))
4430 {
4431 break;
4432 }
4433 } else {
4434 PMD_DRV_LOG(DEBUG, sc,
4435 "AFEX: ramrod completed FUNCTION_UPDATE");
4436 f_obj->complete_cmd(sc, f_obj,
4437 ECORE_F_CMD_AFEX_UPDATE);
4438 }
4439 goto next_spqe;
4440
4441 case EVENT_RING_OPCODE_FORWARD_SETUP:
4442 q_obj = &bnx2x_fwd_sp_obj(sc, q_obj);
4443 if (q_obj->complete_cmd(sc, q_obj,
4444 ECORE_Q_CMD_SETUP_TX_ONLY)) {
4445 break;
4446 }
4447 goto next_spqe;
4448
4449 case EVENT_RING_OPCODE_FUNCTION_START:
4450 PMD_DRV_LOG(DEBUG, sc, "got FUNC_START ramrod");
4451 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
4452 break;
4453 }
4454 goto next_spqe;
4455
4456 case EVENT_RING_OPCODE_FUNCTION_STOP:
4457 PMD_DRV_LOG(DEBUG, sc, "got FUNC_STOP ramrod");
4458 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
4459 break;
4460 }
4461 goto next_spqe;
4462 }
4463
4464 switch (opcode | sc->state) {
4465 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):
4466 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):
4467 cid =
4468 elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4469 PMD_DRV_LOG(DEBUG, sc, "got RSS_UPDATE ramrod. CID %d",
4470 cid);
4471 rss_raw->clear_pending(rss_raw);
4472 break;
4473
4474 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4475 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4476 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):
4477 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):
4478 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):
4479 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4480 PMD_DRV_LOG(DEBUG, sc,
4481 "got (un)set mac ramrod");
4482 bnx2x_handle_classification_eqe(sc, elem);
4483 break;
4484
4485 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):
4486 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):
4487 case (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4488 PMD_DRV_LOG(DEBUG, sc,
4489 "got mcast ramrod");
4490 bnx2x_handle_mcast_eqe(sc);
4491 break;
4492
4493 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):
4494 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):
4495 case (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):
4496 PMD_DRV_LOG(DEBUG, sc,
4497 "got rx_mode ramrod");
4498 bnx2x_handle_rx_mode_eqe(sc);
4499 break;
4500
4501 default:
4502 /* unknown event log error and continue */
4503 PMD_DRV_LOG(INFO, sc, "Unknown EQ event %d, sc->state 0x%x",
4504 elem->message.opcode, sc->state);
4505 }
4506
4507 next_spqe:
4508 spqe_cnt++;
4509 } /* for */
4510
4511 mb();
4512 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
4513
4514 sc->eq_cons = sw_cons;
4515 sc->eq_prod = sw_prod;
4516
4517 /* make sure that above mem writes were issued towards the memory */
4518 wmb();
4519
4520 /* update producer */
4521 bnx2x_update_eq_prod(sc, sc->eq_prod);
4522 }
4523
bnx2x_handle_sp_tq(struct bnx2x_softc * sc)4524 static int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)
4525 {
4526 uint16_t status;
4527 int rc = 0;
4528
4529 PMD_DRV_LOG(DEBUG, sc, "---> SP TASK <---");
4530
4531 /* what work needs to be performed? */
4532 status = bnx2x_update_dsb_idx(sc);
4533
4534 PMD_DRV_LOG(DEBUG, sc, "dsb status 0x%04x", status);
4535
4536 /* HW attentions */
4537 if (status & BNX2X_DEF_SB_ATT_IDX) {
4538 PMD_DRV_LOG(DEBUG, sc, "---> ATTN INTR <---");
4539 bnx2x_attn_int(sc);
4540 status &= ~BNX2X_DEF_SB_ATT_IDX;
4541 rc = 1;
4542 }
4543
4544 /* SP events: STAT_QUERY and others */
4545 if (status & BNX2X_DEF_SB_IDX) {
4546 /* handle EQ completions */
4547 PMD_DRV_LOG(DEBUG, sc, "---> EQ INTR <---");
4548 bnx2x_eq_int(sc);
4549 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4550 le16toh(sc->def_idx), IGU_INT_NOP, 1);
4551 status &= ~BNX2X_DEF_SB_IDX;
4552 }
4553
4554 /* if status is non zero then something went wrong */
4555 if (unlikely(status)) {
4556 PMD_DRV_LOG(INFO, sc,
4557 "Got an unknown SP interrupt! (0x%04x)", status);
4558 }
4559
4560 /* ack status block only if something was actually handled */
4561 bnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
4562 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
4563
4564 return rc;
4565 }
4566
bnx2x_handle_fp_tq(struct bnx2x_fastpath * fp)4567 static void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp)
4568 {
4569 struct bnx2x_softc *sc = fp->sc;
4570 uint8_t more_rx = FALSE;
4571
4572 /* Make sure FP is initialized */
4573 if (!fp->sb_running_index)
4574 return;
4575
4576 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc,
4577 "---> FP TASK QUEUE (%d) <--", fp->index);
4578
4579 /* update the fastpath index */
4580 bnx2x_update_fp_sb_idx(fp);
4581
4582 if (rte_atomic32_read(&sc->scan_fp) == 1) {
4583 if (bnx2x_has_rx_work(fp)) {
4584 more_rx = bnx2x_rxeof(sc, fp);
4585 }
4586
4587 if (more_rx) {
4588 /* still more work to do */
4589 bnx2x_handle_fp_tq(fp);
4590 return;
4591 }
4592 /* We have completed slow path completion, clear the flag */
4593 rte_atomic32_set(&sc->scan_fp, 0);
4594 }
4595
4596 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4597 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
4598 }
4599
4600 /*
4601 * Legacy interrupt entry point.
4602 *
4603 * Verifies that the controller generated the interrupt and
4604 * then calls a separate routine to handle the various
4605 * interrupt causes: link, RX, and TX.
4606 */
bnx2x_intr_legacy(struct bnx2x_softc * sc)4607 int bnx2x_intr_legacy(struct bnx2x_softc *sc)
4608 {
4609 struct bnx2x_fastpath *fp;
4610 uint32_t status, mask;
4611 int i, rc = 0;
4612
4613 /*
4614 * 0 for ustorm, 1 for cstorm
4615 * the bits returned from ack_int() are 0-15
4616 * bit 0 = attention status block
4617 * bit 1 = fast path status block
4618 * a mask of 0x2 or more = tx/rx event
4619 * a mask of 1 = slow path event
4620 */
4621
4622 status = bnx2x_ack_int(sc);
4623
4624 /* the interrupt is not for us */
4625 if (unlikely(status == 0)) {
4626 return 0;
4627 }
4628
4629 PMD_DEBUG_PERIODIC_LOG(DEBUG, sc, "Interrupt status 0x%04x", status);
4630 //bnx2x_dump_status_block(sc);
4631
4632 FOR_EACH_ETH_QUEUE(sc, i) {
4633 fp = &sc->fp[i];
4634 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
4635 if (status & mask) {
4636 /* acknowledge and disable further fastpath interrupts */
4637 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
4638 0, IGU_INT_DISABLE, 0);
4639 bnx2x_handle_fp_tq(fp);
4640 status &= ~mask;
4641 }
4642 }
4643
4644 if (unlikely(status & 0x1)) {
4645 /* acknowledge and disable further slowpath interrupts */
4646 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
4647 0, IGU_INT_DISABLE, 0);
4648 rc = bnx2x_handle_sp_tq(sc);
4649 status &= ~0x1;
4650 }
4651
4652 if (unlikely(status)) {
4653 PMD_DRV_LOG(WARNING, sc,
4654 "Unexpected fastpath status (0x%08x)!", status);
4655 }
4656
4657 return rc;
4658 }
4659
4660 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);
4661 static int bnx2x_init_hw_common(struct bnx2x_softc *sc);
4662 static int bnx2x_init_hw_port(struct bnx2x_softc *sc);
4663 static int bnx2x_init_hw_func(struct bnx2x_softc *sc);
4664 static void bnx2x_reset_common(struct bnx2x_softc *sc);
4665 static void bnx2x_reset_port(struct bnx2x_softc *sc);
4666 static void bnx2x_reset_func(struct bnx2x_softc *sc);
4667 static int bnx2x_init_firmware(struct bnx2x_softc *sc);
4668 static void bnx2x_release_firmware(struct bnx2x_softc *sc);
4669
4670 static struct
4671 ecore_func_sp_drv_ops bnx2x_func_sp_drv = {
4672 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
4673 .init_hw_cmn = bnx2x_init_hw_common,
4674 .init_hw_port = bnx2x_init_hw_port,
4675 .init_hw_func = bnx2x_init_hw_func,
4676
4677 .reset_hw_cmn = bnx2x_reset_common,
4678 .reset_hw_port = bnx2x_reset_port,
4679 .reset_hw_func = bnx2x_reset_func,
4680
4681 .init_fw = bnx2x_init_firmware,
4682 .release_fw = bnx2x_release_firmware,
4683 };
4684
bnx2x_init_func_obj(struct bnx2x_softc * sc)4685 static void bnx2x_init_func_obj(struct bnx2x_softc *sc)
4686 {
4687 sc->dmae_ready = 0;
4688
4689 PMD_INIT_FUNC_TRACE(sc);
4690
4691 ecore_init_func_obj(sc,
4692 &sc->func_obj,
4693 BNX2X_SP(sc, func_rdata),
4694 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_rdata),
4695 BNX2X_SP(sc, func_afex_rdata),
4696 (rte_iova_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),
4697 &bnx2x_func_sp_drv);
4698 }
4699
bnx2x_init_hw(struct bnx2x_softc * sc,uint32_t load_code)4700 static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)
4701 {
4702 struct ecore_func_state_params func_params = { NULL };
4703 int rc;
4704
4705 PMD_INIT_FUNC_TRACE(sc);
4706
4707 /* prepare the parameters for function state transitions */
4708 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4709
4710 func_params.f_obj = &sc->func_obj;
4711 func_params.cmd = ECORE_F_CMD_HW_INIT;
4712
4713 func_params.params.hw_init.load_phase = load_code;
4714
4715 /*
4716 * Via a plethora of function pointers, we will eventually reach
4717 * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().
4718 */
4719 rc = ecore_func_state_change(sc, &func_params);
4720
4721 return rc;
4722 }
4723
4724 static void
bnx2x_fill(struct bnx2x_softc * sc,uint32_t addr,int fill,uint32_t len)4725 bnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)
4726 {
4727 uint32_t i;
4728
4729 if (!(len % 4) && !(addr % 4)) {
4730 for (i = 0; i < len; i += 4) {
4731 REG_WR(sc, (addr + i), fill);
4732 }
4733 } else {
4734 for (i = 0; i < len; i++) {
4735 REG_WR8(sc, (addr + i), fill);
4736 }
4737 }
4738 }
4739
4740 /* writes FP SP data to FW - data_size in dwords */
4741 static void
bnx2x_wr_fp_sb_data(struct bnx2x_softc * sc,int fw_sb_id,uint32_t * sb_data_p,uint32_t data_size)4742 bnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,
4743 uint32_t data_size)
4744 {
4745 uint32_t index;
4746
4747 for (index = 0; index < data_size; index++) {
4748 REG_WR(sc,
4749 (BAR_CSTRORM_INTMEM +
4750 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4751 (sizeof(uint32_t) * index)), *(sb_data_p + index));
4752 }
4753 }
4754
bnx2x_zero_fp_sb(struct bnx2x_softc * sc,int fw_sb_id)4755 static void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)
4756 {
4757 struct hc_status_block_data_e2 sb_data_e2;
4758 struct hc_status_block_data_e1x sb_data_e1x;
4759 uint32_t *sb_data_p;
4760 uint32_t data_size = 0;
4761
4762 if (!CHIP_IS_E1x(sc)) {
4763 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4764 sb_data_e2.common.state = SB_DISABLED;
4765 sb_data_e2.common.p_func.vf_valid = FALSE;
4766 sb_data_p = (uint32_t *) & sb_data_e2;
4767 data_size = (sizeof(struct hc_status_block_data_e2) /
4768 sizeof(uint32_t));
4769 } else {
4770 memset(&sb_data_e1x, 0,
4771 sizeof(struct hc_status_block_data_e1x));
4772 sb_data_e1x.common.state = SB_DISABLED;
4773 sb_data_e1x.common.p_func.vf_valid = FALSE;
4774 sb_data_p = (uint32_t *) & sb_data_e1x;
4775 data_size = (sizeof(struct hc_status_block_data_e1x) /
4776 sizeof(uint32_t));
4777 }
4778
4779 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4780
4781 bnx2x_fill(sc,
4782 (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,
4783 CSTORM_STATUS_BLOCK_SIZE);
4784 bnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
4785 0, CSTORM_SYNC_BLOCK_SIZE);
4786 }
4787
4788 static void
bnx2x_wr_sp_sb_data(struct bnx2x_softc * sc,struct hc_sp_status_block_data * sp_sb_data)4789 bnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,
4790 struct hc_sp_status_block_data *sp_sb_data)
4791 {
4792 uint32_t i;
4793
4794 for (i = 0;
4795 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
4796 i++) {
4797 REG_WR(sc,
4798 (BAR_CSTRORM_INTMEM +
4799 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
4800 (i * sizeof(uint32_t))),
4801 *((uint32_t *) sp_sb_data + i));
4802 }
4803 }
4804
bnx2x_zero_sp_sb(struct bnx2x_softc * sc)4805 static void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)
4806 {
4807 struct hc_sp_status_block_data sp_sb_data;
4808
4809 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4810
4811 sp_sb_data.state = SB_DISABLED;
4812 sp_sb_data.p_func.vf_valid = FALSE;
4813
4814 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
4815
4816 bnx2x_fill(sc,
4817 (BAR_CSTRORM_INTMEM +
4818 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
4819 0, CSTORM_SP_STATUS_BLOCK_SIZE);
4820 bnx2x_fill(sc,
4821 (BAR_CSTRORM_INTMEM +
4822 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
4823 0, CSTORM_SP_SYNC_BLOCK_SIZE);
4824 }
4825
4826 static void
bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm * hc_sm,int igu_sb_id,int igu_seg_id)4827 bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,
4828 int igu_seg_id)
4829 {
4830 hc_sm->igu_sb_id = igu_sb_id;
4831 hc_sm->igu_seg_id = igu_seg_id;
4832 hc_sm->timer_value = 0xFF;
4833 hc_sm->time_to_expire = 0xFFFFFFFF;
4834 }
4835
bnx2x_map_sb_state_machines(struct hc_index_data * index_data)4836 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4837 {
4838 /* zero out state machine indices */
4839
4840 /* rx indices */
4841 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4842
4843 /* tx indices */
4844 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4845 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4846 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4847 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4848
4849 /* map indices */
4850
4851 /* rx indices */
4852 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4853 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4854
4855 /* tx indices */
4856 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4857 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4858 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4859 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4860 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4861 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4862 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4863 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
4864 }
4865
4866 static void
bnx2x_init_sb(struct bnx2x_softc * sc,rte_iova_t busaddr,int vfid,uint8_t vf_valid,int fw_sb_id,int igu_sb_id)4867 bnx2x_init_sb(struct bnx2x_softc *sc, rte_iova_t busaddr, int vfid,
4868 uint8_t vf_valid, int fw_sb_id, int igu_sb_id)
4869 {
4870 struct hc_status_block_data_e2 sb_data_e2;
4871 struct hc_status_block_data_e1x sb_data_e1x;
4872 struct hc_status_block_sm *hc_sm_p;
4873 uint32_t *sb_data_p;
4874 int igu_seg_id;
4875 int data_size;
4876
4877 if (CHIP_INT_MODE_IS_BC(sc)) {
4878 igu_seg_id = HC_SEG_ACCESS_NORM;
4879 } else {
4880 igu_seg_id = IGU_SEG_ACCESS_NORM;
4881 }
4882
4883 bnx2x_zero_fp_sb(sc, fw_sb_id);
4884
4885 if (!CHIP_IS_E1x(sc)) {
4886 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4887 sb_data_e2.common.state = SB_ENABLED;
4888 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
4889 sb_data_e2.common.p_func.vf_id = vfid;
4890 sb_data_e2.common.p_func.vf_valid = vf_valid;
4891 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
4892 sb_data_e2.common.same_igu_sb_1b = TRUE;
4893 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
4894 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
4895 hc_sm_p = sb_data_e2.common.state_machine;
4896 sb_data_p = (uint32_t *) & sb_data_e2;
4897 data_size = (sizeof(struct hc_status_block_data_e2) /
4898 sizeof(uint32_t));
4899 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4900 } else {
4901 memset(&sb_data_e1x, 0,
4902 sizeof(struct hc_status_block_data_e1x));
4903 sb_data_e1x.common.state = SB_ENABLED;
4904 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
4905 sb_data_e1x.common.p_func.vf_id = 0xff;
4906 sb_data_e1x.common.p_func.vf_valid = FALSE;
4907 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
4908 sb_data_e1x.common.same_igu_sb_1b = TRUE;
4909 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
4910 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
4911 hc_sm_p = sb_data_e1x.common.state_machine;
4912 sb_data_p = (uint32_t *) & sb_data_e1x;
4913 data_size = (sizeof(struct hc_status_block_data_e1x) /
4914 sizeof(uint32_t));
4915 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4916 }
4917
4918 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
4919 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
4920
4921 /* write indices to HW - PCI guarantees endianity of regpairs */
4922 bnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
4923 }
4924
bnx2x_fp_qzone_id(struct bnx2x_fastpath * fp)4925 static uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
4926 {
4927 if (CHIP_IS_E1x(fp->sc)) {
4928 return fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H;
4929 } else {
4930 return fp->cl_id;
4931 }
4932 }
4933
4934 static uint32_t
bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc * sc,struct bnx2x_fastpath * fp)4935 bnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)
4936 {
4937 uint32_t offset = BAR_USTRORM_INTMEM;
4938
4939 if (IS_VF(sc)) {
4940 return PXP_VF_ADDR_USDM_QUEUES_START +
4941 (sc->acquire_resp.resc.hw_qid[fp->index] *
4942 sizeof(struct ustorm_queue_zone_data));
4943 } else if (!CHIP_IS_E1x(sc)) {
4944 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
4945 } else {
4946 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
4947 }
4948
4949 return offset;
4950 }
4951
bnx2x_init_eth_fp(struct bnx2x_softc * sc,int idx)4952 static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)
4953 {
4954 struct bnx2x_fastpath *fp = &sc->fp[idx];
4955 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
4956 uint32_t q_type = 0;
4957 int cos;
4958
4959 fp->sc = sc;
4960 fp->index = idx;
4961
4962 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
4963 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
4964
4965 if (CHIP_IS_E1x(sc))
4966 fp->cl_id = SC_L_ID(sc) + idx;
4967 else
4968 /* want client ID same as IGU SB ID for non-E1 */
4969 fp->cl_id = fp->igu_sb_id;
4970 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
4971
4972 /* setup sb indices */
4973 if (!CHIP_IS_E1x(sc)) {
4974 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
4975 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
4976 } else {
4977 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
4978 fp->sb_running_index =
4979 fp->status_block.e1x_sb->sb.running_index;
4980 }
4981
4982 /* init shortcut */
4983 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);
4984
4985 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
4986
4987 for (cos = 0; cos < sc->max_cos; cos++) {
4988 cids[cos] = idx;
4989 }
4990 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
4991
4992 /* nothing more for a VF to do */
4993 if (IS_VF(sc)) {
4994 return;
4995 }
4996
4997 bnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,
4998 fp->fw_sb_id, fp->igu_sb_id);
4999
5000 bnx2x_update_fp_sb_idx(fp);
5001
5002 /* Configure Queue State object */
5003 rte_bit_relaxed_set32(ECORE_Q_TYPE_HAS_RX, &q_type);
5004 rte_bit_relaxed_set32(ECORE_Q_TYPE_HAS_TX, &q_type);
5005
5006 ecore_init_queue_obj(sc,
5007 &sc->sp_objs[idx].q_obj,
5008 fp->cl_id,
5009 cids,
5010 sc->max_cos,
5011 SC_FUNC(sc),
5012 BNX2X_SP(sc, q_rdata),
5013 (rte_iova_t)BNX2X_SP_MAPPING(sc, q_rdata),
5014 q_type);
5015
5016 /* configure classification DBs */
5017 ecore_init_mac_obj(sc,
5018 &sc->sp_objs[idx].mac_obj,
5019 fp->cl_id,
5020 idx,
5021 SC_FUNC(sc),
5022 BNX2X_SP(sc, mac_rdata),
5023 (rte_iova_t)BNX2X_SP_MAPPING(sc, mac_rdata),
5024 ECORE_FILTER_MAC_PENDING, &sc->sp_state,
5025 ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);
5026 }
5027
5028 static void
bnx2x_update_rx_prod(struct bnx2x_softc * sc,struct bnx2x_fastpath * fp,uint16_t rx_bd_prod,uint16_t rx_cq_prod)5029 bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
5030 uint16_t rx_bd_prod, uint16_t rx_cq_prod)
5031 {
5032 struct ustorm_eth_rx_producers rx_prods;
5033 uint32_t i;
5034
5035 memset(&rx_prods, 0, sizeof(rx_prods));
5036
5037 /* update producers */
5038 rx_prods.bd_prod = rx_bd_prod;
5039 rx_prods.cqe_prod = rx_cq_prod;
5040
5041 /*
5042 * Make sure that the BD and SGE data is updated before updating the
5043 * producers since FW might read the BD/SGE right after the producer
5044 * is updated.
5045 * This is only applicable for weak-ordered memory model archs such
5046 * as IA-64. The following barrier is also mandatory since FW will
5047 * assumes BDs must have buffers.
5048 */
5049 wmb();
5050
5051 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
5052 REG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),
5053 ((uint32_t *)&rx_prods)[i]);
5054 }
5055
5056 wmb(); /* keep prod updates ordered */
5057 }
5058
bnx2x_init_rx_rings(struct bnx2x_softc * sc)5059 static void bnx2x_init_rx_rings(struct bnx2x_softc *sc)
5060 {
5061 struct bnx2x_fastpath *fp;
5062 int i;
5063 struct bnx2x_rx_queue *rxq;
5064
5065 for (i = 0; i < sc->num_queues; i++) {
5066 fp = &sc->fp[i];
5067 rxq = sc->rx_queues[fp->index];
5068 if (!rxq) {
5069 PMD_RX_LOG(ERR, "RX queue is NULL");
5070 return;
5071 }
5072
5073 rxq->rx_bd_head = 0;
5074 rxq->rx_bd_tail = rxq->nb_rx_desc;
5075 rxq->rx_cq_head = 0;
5076 rxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);
5077 *fp->rx_cq_cons_sb = 0;
5078
5079 /*
5080 * Activate the BD ring...
5081 * Warning, this will generate an interrupt (to the TSTORM)
5082 * so this can only be done after the chip is initialized
5083 */
5084 bnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);
5085
5086 if (i != 0) {
5087 continue;
5088 }
5089 }
5090 }
5091
bnx2x_init_tx_ring_one(struct bnx2x_fastpath * fp)5092 static void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)
5093 {
5094 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
5095
5096 fp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;
5097 fp->tx_db.data.zero_fill1 = 0;
5098 fp->tx_db.data.prod = 0;
5099
5100 if (!txq) {
5101 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
5102 return;
5103 }
5104
5105 txq->tx_pkt_tail = 0;
5106 txq->tx_pkt_head = 0;
5107 txq->tx_bd_tail = 0;
5108 txq->tx_bd_head = 0;
5109 }
5110
bnx2x_init_tx_rings(struct bnx2x_softc * sc)5111 static void bnx2x_init_tx_rings(struct bnx2x_softc *sc)
5112 {
5113 int i;
5114
5115 for (i = 0; i < sc->num_queues; i++) {
5116 bnx2x_init_tx_ring_one(&sc->fp[i]);
5117 }
5118 }
5119
bnx2x_init_def_sb(struct bnx2x_softc * sc)5120 static void bnx2x_init_def_sb(struct bnx2x_softc *sc)
5121 {
5122 struct host_sp_status_block *def_sb = sc->def_sb;
5123 rte_iova_t mapping = sc->def_sb_dma.paddr;
5124 int igu_sp_sb_index;
5125 int igu_seg_id;
5126 int port = SC_PORT(sc);
5127 int func = SC_FUNC(sc);
5128 int reg_offset, reg_offset_en5;
5129 uint64_t section;
5130 int index, sindex;
5131 struct hc_sp_status_block_data sp_sb_data;
5132
5133 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5134
5135 if (CHIP_INT_MODE_IS_BC(sc)) {
5136 igu_sp_sb_index = DEF_SB_IGU_ID;
5137 igu_seg_id = HC_SEG_ACCESS_DEF;
5138 } else {
5139 igu_sp_sb_index = sc->igu_dsb_id;
5140 igu_seg_id = IGU_SEG_ACCESS_DEF;
5141 }
5142
5143 /* attentions */
5144 section = ((uint64_t) mapping +
5145 offsetof(struct host_sp_status_block, atten_status_block));
5146 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5147 sc->attn_state = 0;
5148
5149 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5150 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5151
5152 reg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5153 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
5154
5155 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5156 /* take care of sig[0]..sig[4] */
5157 for (sindex = 0; sindex < 4; sindex++) {
5158 sc->attn_group[index].sig[sindex] =
5159 REG_RD(sc,
5160 (reg_offset + (sindex * 0x4) +
5161 (0x10 * index)));
5162 }
5163
5164 if (!CHIP_IS_E1x(sc)) {
5165 /*
5166 * enable5 is separate from the rest of the registers,
5167 * and the address skip is 4 and not 16 between the
5168 * different groups
5169 */
5170 sc->attn_group[index].sig[4] =
5171 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
5172 } else {
5173 sc->attn_group[index].sig[4] = 0;
5174 }
5175 }
5176
5177 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5178 reg_offset =
5179 port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
5180 REG_WR(sc, reg_offset, U64_LO(section));
5181 REG_WR(sc, (reg_offset + 4), U64_HI(section));
5182 } else if (!CHIP_IS_E1x(sc)) {
5183 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5184 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5185 }
5186
5187 section = ((uint64_t) mapping +
5188 offsetof(struct host_sp_status_block, sp_sb));
5189
5190 bnx2x_zero_sp_sb(sc);
5191
5192 /* PCI guarantees endianity of regpair */
5193 sp_sb_data.state = SB_ENABLED;
5194 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5195 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5196 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5197 sp_sb_data.igu_seg_id = igu_seg_id;
5198 sp_sb_data.p_func.pf_id = func;
5199 sp_sb_data.p_func.vnic_id = SC_VN(sc);
5200 sp_sb_data.p_func.vf_id = 0xff;
5201
5202 bnx2x_wr_sp_sb_data(sc, &sp_sb_data);
5203
5204 bnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5205 }
5206
bnx2x_init_sp_ring(struct bnx2x_softc * sc)5207 static void bnx2x_init_sp_ring(struct bnx2x_softc *sc)
5208 {
5209 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
5210 sc->spq_prod_idx = 0;
5211 sc->dsb_sp_prod =
5212 &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
5213 sc->spq_prod_bd = sc->spq;
5214 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
5215 }
5216
bnx2x_init_eq_ring(struct bnx2x_softc * sc)5217 static void bnx2x_init_eq_ring(struct bnx2x_softc *sc)
5218 {
5219 union event_ring_elem *elem;
5220 int i;
5221
5222 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5223 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
5224
5225 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
5226 BNX2X_PAGE_SIZE *
5227 (i % NUM_EQ_PAGES)));
5228 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
5229 BNX2X_PAGE_SIZE *
5230 (i % NUM_EQ_PAGES)));
5231 }
5232
5233 sc->eq_cons = 0;
5234 sc->eq_prod = NUM_EQ_DESC;
5235 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
5236
5237 atomic_store_rel_long(&sc->eq_spq_left,
5238 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
5239 NUM_EQ_DESC) - 1));
5240 }
5241
bnx2x_init_internal_common(struct bnx2x_softc * sc)5242 static void bnx2x_init_internal_common(struct bnx2x_softc *sc)
5243 {
5244 int i;
5245
5246 /*
5247 * Zero this manually as its initialization is currently missing
5248 * in the initTool.
5249 */
5250 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
5251 REG_WR(sc,
5252 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
5253 0);
5254 }
5255
5256 if (!CHIP_IS_E1x(sc)) {
5257 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
5258 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :
5259 HC_IGU_NBC_MODE);
5260 }
5261 }
5262
bnx2x_init_internal(struct bnx2x_softc * sc,uint32_t load_code)5263 static void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)
5264 {
5265 switch (load_code) {
5266 case FW_MSG_CODE_DRV_LOAD_COMMON:
5267 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5268 bnx2x_init_internal_common(sc);
5269 /* no break */
5270
5271 case FW_MSG_CODE_DRV_LOAD_PORT:
5272 /* nothing to do */
5273 /* no break */
5274
5275 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5276 /* internal memory per function is initialized inside bnx2x_pf_init */
5277 break;
5278
5279 default:
5280 PMD_DRV_LOG(NOTICE, sc, "Unknown load_code (0x%x) from MCP",
5281 load_code);
5282 break;
5283 }
5284 }
5285
5286 static void
storm_memset_func_cfg(struct bnx2x_softc * sc,struct tstorm_eth_function_common_config * tcfg,uint16_t abs_fid)5287 storm_memset_func_cfg(struct bnx2x_softc *sc,
5288 struct tstorm_eth_function_common_config *tcfg,
5289 uint16_t abs_fid)
5290 {
5291 uint32_t addr;
5292 size_t size;
5293
5294 addr = (BAR_TSTRORM_INTMEM +
5295 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
5296 size = sizeof(struct tstorm_eth_function_common_config);
5297 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);
5298 }
5299
bnx2x_func_init(struct bnx2x_softc * sc,struct bnx2x_func_init_params * p)5300 static void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)
5301 {
5302 struct tstorm_eth_function_common_config tcfg = { 0 };
5303
5304 if (CHIP_IS_E1x(sc)) {
5305 storm_memset_func_cfg(sc, &tcfg, p->func_id);
5306 }
5307
5308 /* Enable the function in the FW */
5309 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
5310 storm_memset_func_en(sc, p->func_id, 1);
5311
5312 /* spq */
5313 if (p->func_flgs & FUNC_FLG_SPQ) {
5314 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
5315 REG_WR(sc,
5316 (XSEM_REG_FAST_MEMORY +
5317 XSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);
5318 }
5319 }
5320
5321 /*
5322 * Calculates the sum of vn_min_rates.
5323 * It's needed for further normalizing of the min_rates.
5324 * Returns:
5325 * sum of vn_min_rates.
5326 * or
5327 * 0 - if all the min_rates are 0.
5328 * In the later case fairness algorithm should be deactivated.
5329 * If all min rates are not zero then those that are zeroes will be set to 1.
5330 */
bnx2x_calc_vn_min(struct bnx2x_softc * sc,struct cmng_init_input * input)5331 static void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)
5332 {
5333 uint32_t vn_cfg;
5334 uint32_t vn_min_rate;
5335 int all_zero = 1;
5336 int vn;
5337
5338 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5339 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5340 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
5341 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
5342
5343 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5344 /* skip hidden VNs */
5345 vn_min_rate = 0;
5346 } else if (!vn_min_rate) {
5347 /* If min rate is zero - set it to 100 */
5348 vn_min_rate = DEF_MIN_RATE;
5349 } else {
5350 all_zero = 0;
5351 }
5352
5353 input->vnic_min_rate[vn] = vn_min_rate;
5354 }
5355
5356 /* if ETS or all min rates are zeros - disable fairness */
5357 if (all_zero) {
5358 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5359 } else {
5360 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
5361 }
5362 }
5363
5364 static uint16_t
bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc * sc,uint32_t mf_cfg)5365 bnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)
5366 {
5367 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
5368 FUNC_MF_CFG_MAX_BW_SHIFT);
5369
5370 if (!max_cfg) {
5371 PMD_DRV_LOG(DEBUG, sc,
5372 "Max BW configured to 0 - using 100 instead");
5373 max_cfg = 100;
5374 }
5375
5376 return max_cfg;
5377 }
5378
5379 static void
bnx2x_calc_vn_max(struct bnx2x_softc * sc,int vn,struct cmng_init_input * input)5380 bnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)
5381 {
5382 uint16_t vn_max_rate;
5383 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
5384 uint32_t max_cfg;
5385
5386 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
5387 vn_max_rate = 0;
5388 } else {
5389 max_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);
5390
5391 if (IS_MF_SI(sc)) {
5392 /* max_cfg in percents of linkspeed */
5393 vn_max_rate =
5394 ((sc->link_vars.line_speed * max_cfg) / 100);
5395 } else { /* SD modes */
5396 /* max_cfg is absolute in 100Mb units */
5397 vn_max_rate = (max_cfg * 100);
5398 }
5399 }
5400
5401 input->vnic_max_rate[vn] = vn_max_rate;
5402 }
5403
5404 static void
bnx2x_cmng_fns_init(struct bnx2x_softc * sc,uint8_t read_cfg,uint8_t cmng_type)5405 bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)
5406 {
5407 struct cmng_init_input input;
5408 int vn;
5409
5410 memset(&input, 0, sizeof(struct cmng_init_input));
5411
5412 input.port_rate = sc->link_vars.line_speed;
5413
5414 if (cmng_type == CMNG_FNS_MINMAX) {
5415 /* read mf conf from shmem */
5416 if (read_cfg) {
5417 bnx2x_read_mf_cfg(sc);
5418 }
5419
5420 /* get VN min rate and enable fairness if not 0 */
5421 bnx2x_calc_vn_min(sc, &input);
5422
5423 /* get VN max rate */
5424 if (sc->port.pmf) {
5425 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5426 bnx2x_calc_vn_max(sc, vn, &input);
5427 }
5428 }
5429
5430 /* always enable rate shaping and fairness */
5431 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
5432
5433 ecore_init_cmng(&input, &sc->cmng);
5434 return;
5435 }
5436 }
5437
bnx2x_get_cmng_fns_mode(struct bnx2x_softc * sc)5438 static int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)
5439 {
5440 if (CHIP_REV_IS_SLOW(sc)) {
5441 return CMNG_FNS_NONE;
5442 }
5443
5444 if (IS_MF(sc)) {
5445 return CMNG_FNS_MINMAX;
5446 }
5447
5448 return CMNG_FNS_NONE;
5449 }
5450
5451 static void
storm_memset_cmng(struct bnx2x_softc * sc,struct cmng_init * cmng,uint8_t port)5452 storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)
5453 {
5454 int vn;
5455 int func;
5456 uint32_t addr;
5457 size_t size;
5458
5459 addr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
5460 size = sizeof(struct cmng_struct_per_port);
5461 ecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);
5462
5463 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
5464 func = func_by_vn(sc, vn);
5465
5466 addr = (BAR_XSTRORM_INTMEM +
5467 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
5468 size = sizeof(struct rate_shaping_vars_per_vn);
5469 ecore_storm_memset_struct(sc, addr, size,
5470 (uint32_t *) & cmng->
5471 vnic.vnic_max_rate[vn]);
5472
5473 addr = (BAR_XSTRORM_INTMEM +
5474 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
5475 size = sizeof(struct fairness_vars_per_vn);
5476 ecore_storm_memset_struct(sc, addr, size,
5477 (uint32_t *) & cmng->
5478 vnic.vnic_min_rate[vn]);
5479 }
5480 }
5481
bnx2x_pf_init(struct bnx2x_softc * sc)5482 static void bnx2x_pf_init(struct bnx2x_softc *sc)
5483 {
5484 struct bnx2x_func_init_params func_init;
5485 struct event_ring_data eq_data;
5486 uint16_t flags;
5487
5488 memset(&eq_data, 0, sizeof(struct event_ring_data));
5489 memset(&func_init, 0, sizeof(struct bnx2x_func_init_params));
5490
5491 if (!CHIP_IS_E1x(sc)) {
5492 /* reset IGU PF statistics: MSIX + ATTN */
5493 /* PF */
5494 REG_WR(sc,
5495 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5496 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5497 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5498 4)), 0);
5499 /* ATTN */
5500 REG_WR(sc,
5501 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
5502 (BNX2X_IGU_STAS_MSG_VF_CNT * 4) +
5503 (BNX2X_IGU_STAS_MSG_PF_CNT * 4) +
5504 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *
5505 4)), 0);
5506 }
5507
5508 /* function setup flags */
5509 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
5510
5511 func_init.func_flgs = flags;
5512 func_init.pf_id = SC_FUNC(sc);
5513 func_init.func_id = SC_FUNC(sc);
5514 func_init.spq_map = sc->spq_dma.paddr;
5515 func_init.spq_prod = sc->spq_prod_idx;
5516
5517 bnx2x_func_init(sc, &func_init);
5518
5519 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
5520
5521 /*
5522 * Congestion management values depend on the link rate.
5523 * There is no active link so initial link rate is set to 10Gbps.
5524 * When the link comes up the congestion management values are
5525 * re-calculated according to the actual link rate.
5526 */
5527 sc->link_vars.line_speed = SPEED_10000;
5528 bnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));
5529
5530 /* Only the PMF sets the HW */
5531 if (sc->port.pmf) {
5532 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
5533 }
5534
5535 /* init Event Queue - PCI bus guarantees correct endainity */
5536 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
5537 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
5538 eq_data.producer = sc->eq_prod;
5539 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
5540 eq_data.sb_id = DEF_SB_ID;
5541 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
5542 }
5543
bnx2x_hc_int_enable(struct bnx2x_softc * sc)5544 static void bnx2x_hc_int_enable(struct bnx2x_softc *sc)
5545 {
5546 int port = SC_PORT(sc);
5547 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5548 uint32_t val = REG_RD(sc, addr);
5549 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5550 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5551 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5552 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5553
5554 if (msix) {
5555 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5556 HC_CONFIG_0_REG_INT_LINE_EN_0);
5557 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5558 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5559 if (single_msix) {
5560 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
5561 }
5562 } else if (msi) {
5563 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5564 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5565 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5566 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5567 } else {
5568 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5569 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5570 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5571 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5572
5573 REG_WR(sc, addr, val);
5574
5575 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5576 }
5577
5578 REG_WR(sc, addr, val);
5579
5580 /* ensure that HC_CONFIG is written before leading/trailing edge config */
5581 mb();
5582
5583 /* init leading/trailing edge */
5584 if (IS_MF(sc)) {
5585 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5586 if (sc->port.pmf) {
5587 /* enable nig and gpio3 attention */
5588 val |= 0x1100;
5589 }
5590 } else {
5591 val = 0xffff;
5592 }
5593
5594 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);
5595 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);
5596
5597 /* make sure that interrupts are indeed enabled from here on */
5598 mb();
5599 }
5600
bnx2x_igu_int_enable(struct bnx2x_softc * sc)5601 static void bnx2x_igu_int_enable(struct bnx2x_softc *sc)
5602 {
5603 uint32_t val;
5604 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)
5605 || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5606 uint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);
5607 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);
5608
5609 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5610
5611 if (msix) {
5612 val &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5613 val |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);
5614 if (single_msix) {
5615 val |= IGU_PF_CONF_SINGLE_ISR_EN;
5616 }
5617 } else if (msi) {
5618 val &= ~IGU_PF_CONF_INT_LINE_EN;
5619 val |= (IGU_PF_CONF_MSI_MSIX_EN |
5620 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5621 } else {
5622 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
5623 val |= (IGU_PF_CONF_INT_LINE_EN |
5624 IGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);
5625 }
5626
5627 /* clean previous status - need to configure igu prior to ack */
5628 if ((!msix) || single_msix) {
5629 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5630 bnx2x_ack_int(sc);
5631 }
5632
5633 val |= IGU_PF_CONF_FUNC_EN;
5634
5635 PMD_DRV_LOG(DEBUG, sc, "write 0x%x to IGU mode %s",
5636 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
5637
5638 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5639
5640 mb();
5641
5642 /* init leading/trailing edge */
5643 if (IS_MF(sc)) {
5644 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
5645 if (sc->port.pmf) {
5646 /* enable nig and gpio3 attention */
5647 val |= 0x1100;
5648 }
5649 } else {
5650 val = 0xffff;
5651 }
5652
5653 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
5654 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
5655
5656 /* make sure that interrupts are indeed enabled from here on */
5657 mb();
5658 }
5659
bnx2x_int_enable(struct bnx2x_softc * sc)5660 static void bnx2x_int_enable(struct bnx2x_softc *sc)
5661 {
5662 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5663 bnx2x_hc_int_enable(sc);
5664 } else {
5665 bnx2x_igu_int_enable(sc);
5666 }
5667 }
5668
bnx2x_hc_int_disable(struct bnx2x_softc * sc)5669 static void bnx2x_hc_int_disable(struct bnx2x_softc *sc)
5670 {
5671 int port = SC_PORT(sc);
5672 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5673 uint32_t val = REG_RD(sc, addr);
5674
5675 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5676 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5677 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5678 /* flush all outstanding writes */
5679 mb();
5680
5681 REG_WR(sc, addr, val);
5682 if (REG_RD(sc, addr) != val) {
5683 PMD_DRV_LOG(ERR, sc, "proper val not read from HC IGU!");
5684 }
5685 }
5686
bnx2x_igu_int_disable(struct bnx2x_softc * sc)5687 static void bnx2x_igu_int_disable(struct bnx2x_softc *sc)
5688 {
5689 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
5690
5691 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
5692 IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);
5693
5694 PMD_DRV_LOG(DEBUG, sc, "write %x to IGU", val);
5695
5696 /* flush all outstanding writes */
5697 mb();
5698
5699 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
5700 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
5701 PMD_DRV_LOG(ERR, sc, "proper val not read from IGU!");
5702 }
5703 }
5704
bnx2x_int_disable(struct bnx2x_softc * sc)5705 static void bnx2x_int_disable(struct bnx2x_softc *sc)
5706 {
5707 if (sc->devinfo.int_block == INT_BLOCK_HC) {
5708 bnx2x_hc_int_disable(sc);
5709 } else {
5710 bnx2x_igu_int_disable(sc);
5711 }
5712 }
5713
bnx2x_nic_init(struct bnx2x_softc * sc,int load_code)5714 static void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)
5715 {
5716 int i;
5717
5718 PMD_INIT_FUNC_TRACE(sc);
5719
5720 for (i = 0; i < sc->num_queues; i++) {
5721 bnx2x_init_eth_fp(sc, i);
5722 }
5723
5724 rmb(); /* ensure status block indices were read */
5725
5726 bnx2x_init_rx_rings(sc);
5727 bnx2x_init_tx_rings(sc);
5728
5729 if (IS_VF(sc)) {
5730 bnx2x_memset_stats(sc);
5731 return;
5732 }
5733
5734 /* initialize MOD_ABS interrupts */
5735 elink_init_mod_abs_int(sc, &sc->link_vars,
5736 sc->devinfo.chip_id,
5737 sc->devinfo.shmem_base,
5738 sc->devinfo.shmem2_base, SC_PORT(sc));
5739
5740 bnx2x_init_def_sb(sc);
5741 bnx2x_update_dsb_idx(sc);
5742 bnx2x_init_sp_ring(sc);
5743 bnx2x_init_eq_ring(sc);
5744 bnx2x_init_internal(sc, load_code);
5745 bnx2x_pf_init(sc);
5746 bnx2x_stats_init(sc);
5747
5748 /* flush all before enabling interrupts */
5749 mb();
5750
5751 bnx2x_int_enable(sc);
5752
5753 /* check for SPIO5 */
5754 bnx2x_attn_int_deasserted0(sc,
5755 REG_RD(sc,
5756 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5757 SC_PORT(sc) * 4)) &
5758 AEU_INPUTS_ATTN_BITS_SPIO5);
5759 }
5760
bnx2x_init_objs(struct bnx2x_softc * sc)5761 static void bnx2x_init_objs(struct bnx2x_softc *sc)
5762 {
5763 /* mcast rules must be added to tx if tx switching is enabled */
5764 ecore_obj_type o_type;
5765 if (sc->flags & BNX2X_TX_SWITCHING)
5766 o_type = ECORE_OBJ_TYPE_RX_TX;
5767 else
5768 o_type = ECORE_OBJ_TYPE_RX;
5769
5770 /* RX_MODE controlling object */
5771 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
5772
5773 /* multicast configuration controlling object */
5774 ecore_init_mcast_obj(sc,
5775 &sc->mcast_obj,
5776 sc->fp[0].cl_id,
5777 sc->fp[0].index,
5778 SC_FUNC(sc),
5779 SC_FUNC(sc),
5780 BNX2X_SP(sc, mcast_rdata),
5781 (rte_iova_t)BNX2X_SP_MAPPING(sc, mcast_rdata),
5782 ECORE_FILTER_MCAST_PENDING,
5783 &sc->sp_state, o_type);
5784
5785 /* Setup CAM credit pools */
5786 ecore_init_mac_credit_pool(sc,
5787 &sc->macs_pool,
5788 SC_FUNC(sc),
5789 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5790 VNICS_PER_PATH(sc));
5791
5792 ecore_init_vlan_credit_pool(sc,
5793 &sc->vlans_pool,
5794 SC_ABS_FUNC(sc) >> 1,
5795 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
5796 VNICS_PER_PATH(sc));
5797
5798 /* RSS configuration object */
5799 ecore_init_rss_config_obj(sc, &sc->rss_conf_obj, sc->fp->cl_id,
5800 sc->fp->index, SC_FUNC(sc), SC_FUNC(sc),
5801 BNX2X_SP(sc, rss_rdata),
5802 (rte_iova_t)BNX2X_SP_MAPPING(sc, rss_rdata),
5803 ECORE_FILTER_RSS_CONF_PENDING, &sc->sp_state,
5804 ECORE_OBJ_TYPE_RX);
5805 }
5806
5807 /*
5808 * Initialize the function. This must be called before sending CLIENT_SETUP
5809 * for the first client.
5810 */
bnx2x_func_start(struct bnx2x_softc * sc)5811 static int bnx2x_func_start(struct bnx2x_softc *sc)
5812 {
5813 struct ecore_func_state_params func_params = { NULL };
5814 struct ecore_func_start_params *start_params =
5815 &func_params.params.start;
5816
5817 /* Prepare parameters for function state transitions */
5818 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
5819
5820 func_params.f_obj = &sc->func_obj;
5821 func_params.cmd = ECORE_F_CMD_START;
5822
5823 /* Function parameters */
5824 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
5825 start_params->sd_vlan_tag = OVLAN(sc);
5826
5827 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
5828 start_params->network_cos_mode = STATIC_COS;
5829 } else { /* CHIP_IS_E1X */
5830 start_params->network_cos_mode = FW_WRR;
5831 }
5832
5833 return ecore_func_state_change(sc, &func_params);
5834 }
5835
bnx2x_set_power_state(struct bnx2x_softc * sc,uint8_t state)5836 static int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)
5837 {
5838 uint16_t pmcsr;
5839
5840 /* If there is no power capability, silently succeed */
5841 if (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {
5842 PMD_DRV_LOG(INFO, sc, "No power capability");
5843 return 0;
5844 }
5845
5846 pci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,
5847 2);
5848
5849 switch (state) {
5850 case PCI_PM_D0:
5851 pci_write_word(sc,
5852 (sc->devinfo.pcie_pm_cap_reg +
5853 PCIR_POWER_STATUS),
5854 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));
5855
5856 if (pmcsr & PCIM_PSTAT_DMASK) {
5857 /* delay required during transition out of D3hot */
5858 DELAY(20000);
5859 }
5860
5861 break;
5862
5863 case PCI_PM_D3hot:
5864 /* don't shut down the power for emulation and FPGA */
5865 if (CHIP_REV_IS_SLOW(sc)) {
5866 return 0;
5867 }
5868
5869 pmcsr &= ~PCIM_PSTAT_DMASK;
5870 pmcsr |= PCIM_PSTAT_D3;
5871
5872 if (sc->wol) {
5873 pmcsr |= PCIM_PSTAT_PMEENABLE;
5874 }
5875
5876 pci_write_long(sc,
5877 (sc->devinfo.pcie_pm_cap_reg +
5878 PCIR_POWER_STATUS), pmcsr);
5879
5880 /*
5881 * No more memory access after this point until device is brought back
5882 * to D0 state.
5883 */
5884 break;
5885
5886 default:
5887 PMD_DRV_LOG(NOTICE, sc, "Can't support PCI power state = %d",
5888 state);
5889 return -1;
5890 }
5891
5892 return 0;
5893 }
5894
5895 /* return true if succeeded to acquire the lock */
bnx2x_trylock_hw_lock(struct bnx2x_softc * sc,uint32_t resource)5896 static uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)
5897 {
5898 uint32_t lock_status;
5899 uint32_t resource_bit = (1 << resource);
5900 int func = SC_FUNC(sc);
5901 uint32_t hw_lock_control_reg;
5902
5903 /* Validating that the resource is within range */
5904 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5905 PMD_DRV_LOG(INFO, sc,
5906 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)",
5907 resource, HW_LOCK_MAX_RESOURCE_VALUE);
5908 return FALSE;
5909 }
5910
5911 if (func <= 5) {
5912 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);
5913 } else {
5914 hw_lock_control_reg =
5915 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);
5916 }
5917
5918 /* try to acquire the lock */
5919 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5920 lock_status = REG_RD(sc, hw_lock_control_reg);
5921 if (lock_status & resource_bit) {
5922 return TRUE;
5923 }
5924
5925 PMD_DRV_LOG(NOTICE, sc, "Failed to get a resource lock 0x%x", resource);
5926
5927 return FALSE;
5928 }
5929
5930 /*
5931 * Get the recovery leader resource id according to the engine this function
5932 * belongs to. Currently only only 2 engines is supported.
5933 */
bnx2x_get_leader_lock_resource(struct bnx2x_softc * sc)5934 static int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)
5935 {
5936 if (SC_PATH(sc)) {
5937 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
5938 } else {
5939 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
5940 }
5941 }
5942
5943 /* try to acquire a leader lock for current engine */
bnx2x_trylock_leader_lock(struct bnx2x_softc * sc)5944 static uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)
5945 {
5946 return bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5947 }
5948
bnx2x_release_leader_lock(struct bnx2x_softc * sc)5949 static int bnx2x_release_leader_lock(struct bnx2x_softc *sc)
5950 {
5951 return bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));
5952 }
5953
5954 /* close gates #2, #3 and #4 */
bnx2x_set_234_gates(struct bnx2x_softc * sc,uint8_t close)5955 static void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)
5956 {
5957 uint32_t val;
5958
5959 /* gates #2 and #4a are closed/opened */
5960 /* #4 */
5961 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);
5962 /* #2 */
5963 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);
5964
5965 /* #3 */
5966 if (CHIP_IS_E1x(sc)) {
5967 /* prevent interrupts from HC on both ports */
5968 val = REG_RD(sc, HC_REG_CONFIG_1);
5969 if (close)
5970 REG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)
5971 HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5972 else
5973 REG_WR(sc, HC_REG_CONFIG_1,
5974 (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));
5975
5976 val = REG_RD(sc, HC_REG_CONFIG_0);
5977 if (close)
5978 REG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)
5979 HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5980 else
5981 REG_WR(sc, HC_REG_CONFIG_0,
5982 (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));
5983
5984 } else {
5985 /* Prevent incoming interrupts in IGU */
5986 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
5987
5988 if (close)
5989 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5990 (val & ~(uint32_t)
5991 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5992 else
5993 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
5994 (val |
5995 IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
5996 }
5997
5998 wmb();
5999 }
6000
6001 /* poll for pending writes bit, it should get cleared in no more than 1s */
bnx2x_er_poll_igu_vq(struct bnx2x_softc * sc)6002 static int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)
6003 {
6004 uint32_t cnt = 1000;
6005 uint32_t pend_bits = 0;
6006
6007 do {
6008 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
6009
6010 if (pend_bits == 0) {
6011 break;
6012 }
6013
6014 DELAY(1000);
6015 } while (cnt-- > 0);
6016
6017 if (cnt <= 0) {
6018 PMD_DRV_LOG(NOTICE, sc, "Still pending IGU requests bits=0x%08x!",
6019 pend_bits);
6020 return -1;
6021 }
6022
6023 return 0;
6024 }
6025
6026 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
6027
bnx2x_clp_reset_prep(struct bnx2x_softc * sc,uint32_t * magic_val)6028 static void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6029 {
6030 /* Do some magic... */
6031 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6032 *magic_val = val & SHARED_MF_CLP_MAGIC;
6033 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
6034 }
6035
6036 /* restore the value of the 'magic' bit */
bnx2x_clp_reset_done(struct bnx2x_softc * sc,uint32_t magic_val)6037 static void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)
6038 {
6039 /* Restore the 'magic' bit value... */
6040 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
6041 MFCFG_WR(sc, shared_mf_config.clp_mb,
6042 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
6043 }
6044
6045 /* prepare for MCP reset, takes care of CLP configurations */
bnx2x_reset_mcp_prep(struct bnx2x_softc * sc,uint32_t * magic_val)6046 static void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)
6047 {
6048 uint32_t shmem;
6049 uint32_t validity_offset;
6050
6051 /* set `magic' bit in order to save MF config */
6052 bnx2x_clp_reset_prep(sc, magic_val);
6053
6054 /* get shmem offset */
6055 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6056 validity_offset =
6057 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
6058
6059 /* Clear validity map flags */
6060 if (shmem > 0) {
6061 REG_WR(sc, shmem + validity_offset, 0);
6062 }
6063 }
6064
6065 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
6066 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
6067
bnx2x_mcp_wait_one(struct bnx2x_softc * sc)6068 static void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)
6069 {
6070 /* special handling for emulation and FPGA (10 times longer) */
6071 if (CHIP_REV_IS_SLOW(sc)) {
6072 DELAY((MCP_ONE_TIMEOUT * 10) * 1000);
6073 } else {
6074 DELAY((MCP_ONE_TIMEOUT) * 1000);
6075 }
6076 }
6077
6078 /* initialize shmem_base and waits for validity signature to appear */
bnx2x_init_shmem(struct bnx2x_softc * sc)6079 static int bnx2x_init_shmem(struct bnx2x_softc *sc)
6080 {
6081 int cnt = 0;
6082 uint32_t val = 0;
6083
6084 do {
6085 sc->devinfo.shmem_base =
6086 sc->link_params.shmem_base =
6087 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
6088
6089 if (sc->devinfo.shmem_base) {
6090 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
6091 if (val & SHR_MEM_VALIDITY_MB)
6092 return 0;
6093 }
6094
6095 bnx2x_mcp_wait_one(sc);
6096
6097 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
6098
6099 PMD_DRV_LOG(NOTICE, sc, "BAD MCP validity signature");
6100
6101 return -1;
6102 }
6103
bnx2x_reset_mcp_comp(struct bnx2x_softc * sc,uint32_t magic_val)6104 static int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)
6105 {
6106 int rc = bnx2x_init_shmem(sc);
6107
6108 /* Restore the `magic' bit value */
6109 bnx2x_clp_reset_done(sc, magic_val);
6110
6111 return rc;
6112 }
6113
bnx2x_pxp_prep(struct bnx2x_softc * sc)6114 static void bnx2x_pxp_prep(struct bnx2x_softc *sc)
6115 {
6116 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
6117 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
6118 wmb();
6119 }
6120
6121 /*
6122 * Reset the whole chip except for:
6123 * - PCIE core
6124 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
6125 * - IGU
6126 * - MISC (including AEU)
6127 * - GRC
6128 * - RBCN, RBCP
6129 */
bnx2x_process_kill_chip_reset(struct bnx2x_softc * sc,uint8_t global)6130 static void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)
6131 {
6132 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
6133 uint32_t global_bits2, stay_reset2;
6134
6135 /*
6136 * Bits that have to be set in reset_mask2 if we want to reset 'global'
6137 * (per chip) blocks.
6138 */
6139 global_bits2 =
6140 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
6141 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
6142
6143 /*
6144 * Don't reset the following blocks.
6145 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
6146 * reset, as in 4 port device they might still be owned
6147 * by the MCP (there is only one leader per path).
6148 */
6149 not_reset_mask1 =
6150 MISC_REGISTERS_RESET_REG_1_RST_HC |
6151 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
6152 MISC_REGISTERS_RESET_REG_1_RST_PXP;
6153
6154 not_reset_mask2 =
6155 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
6156 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
6157 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
6158 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
6159 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
6160 MISC_REGISTERS_RESET_REG_2_RST_GRC |
6161 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
6162 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
6163 MISC_REGISTERS_RESET_REG_2_RST_ATC |
6164 MISC_REGISTERS_RESET_REG_2_PGLC |
6165 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
6166 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
6167 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
6168 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
6169 MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;
6170
6171 /*
6172 * Keep the following blocks in reset:
6173 * - all xxMACs are handled by the elink code.
6174 */
6175 stay_reset2 =
6176 MISC_REGISTERS_RESET_REG_2_XMAC |
6177 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
6178
6179 /* Full reset masks according to the chip */
6180 reset_mask1 = 0xffffffff;
6181
6182 if (CHIP_IS_E1H(sc))
6183 reset_mask2 = 0x1ffff;
6184 else if (CHIP_IS_E2(sc))
6185 reset_mask2 = 0xfffff;
6186 else /* CHIP_IS_E3 */
6187 reset_mask2 = 0x3ffffff;
6188
6189 /* Don't reset global blocks unless we need to */
6190 if (!global)
6191 reset_mask2 &= ~global_bits2;
6192
6193 /*
6194 * In case of attention in the QM, we need to reset PXP
6195 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
6196 * because otherwise QM reset would release 'close the gates' shortly
6197 * before resetting the PXP, then the PSWRQ would send a write
6198 * request to PGLUE. Then when PXP is reset, PGLUE would try to
6199 * read the payload data from PSWWR, but PSWWR would not
6200 * respond. The write queue in PGLUE would stuck, dmae commands
6201 * would not return. Therefore it's important to reset the second
6202 * reset register (containing the
6203 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
6204 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
6205 * bit).
6206 */
6207 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6208 reset_mask2 & (~not_reset_mask2));
6209
6210 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6211 reset_mask1 & (~not_reset_mask1));
6212
6213 mb();
6214 wmb();
6215
6216 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
6217 reset_mask2 & (~stay_reset2));
6218
6219 mb();
6220 wmb();
6221
6222 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
6223 wmb();
6224 }
6225
bnx2x_process_kill(struct bnx2x_softc * sc,uint8_t global)6226 static int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)
6227 {
6228 int cnt = 1000;
6229 uint32_t val = 0;
6230 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
6231 uint32_t tags_63_32 = 0;
6232
6233 /* Empty the Tetris buffer, wait for 1s */
6234 do {
6235 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
6236 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
6237 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
6238 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
6239 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
6240 if (CHIP_IS_E3(sc)) {
6241 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
6242 }
6243
6244 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
6245 ((port_is_idle_0 & 0x1) == 0x1) &&
6246 ((port_is_idle_1 & 0x1) == 0x1) &&
6247 (pgl_exp_rom2 == 0xffffffff) &&
6248 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
6249 break;
6250 DELAY(1000);
6251 } while (cnt-- > 0);
6252
6253 if (cnt <= 0) {
6254 PMD_DRV_LOG(NOTICE, sc,
6255 "ERROR: Tetris buffer didn't get empty or there "
6256 "are still outstanding read requests after 1s! "
6257 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
6258 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x",
6259 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
6260 pgl_exp_rom2);
6261 return -1;
6262 }
6263
6264 mb();
6265
6266 /* Close gates #2, #3 and #4 */
6267 bnx2x_set_234_gates(sc, TRUE);
6268
6269 /* Poll for IGU VQs for 57712 and newer chips */
6270 if (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {
6271 return -1;
6272 }
6273
6274 /* clear "unprepared" bit */
6275 REG_WR(sc, MISC_REG_UNPREPARED, 0);
6276 mb();
6277
6278 /* Make sure all is written to the chip before the reset */
6279 wmb();
6280
6281 /*
6282 * Wait for 1ms to empty GLUE and PCI-E core queues,
6283 * PSWHST, GRC and PSWRD Tetris buffer.
6284 */
6285 DELAY(1000);
6286
6287 /* Prepare to chip reset: */
6288 /* MCP */
6289 if (global) {
6290 bnx2x_reset_mcp_prep(sc, &val);
6291 }
6292
6293 /* PXP */
6294 bnx2x_pxp_prep(sc);
6295 mb();
6296
6297 /* reset the chip */
6298 bnx2x_process_kill_chip_reset(sc, global);
6299 mb();
6300
6301 /* Recover after reset: */
6302 /* MCP */
6303 if (global && bnx2x_reset_mcp_comp(sc, val)) {
6304 return -1;
6305 }
6306
6307 /* Open the gates #2, #3 and #4 */
6308 bnx2x_set_234_gates(sc, FALSE);
6309
6310 return 0;
6311 }
6312
bnx2x_leader_reset(struct bnx2x_softc * sc)6313 static int bnx2x_leader_reset(struct bnx2x_softc *sc)
6314 {
6315 int rc = 0;
6316 uint8_t global = bnx2x_reset_is_global(sc);
6317 uint32_t load_code;
6318
6319 /*
6320 * If not going to reset MCP, load "fake" driver to reset HW while
6321 * driver is owner of the HW.
6322 */
6323 if (!global && !BNX2X_NOMCP(sc)) {
6324 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6325 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6326 if (!load_code) {
6327 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6328 rc = -1;
6329 goto exit_leader_reset;
6330 }
6331
6332 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6333 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6334 PMD_DRV_LOG(NOTICE, sc,
6335 "MCP unexpected response, aborting");
6336 rc = -1;
6337 goto exit_leader_reset2;
6338 }
6339
6340 load_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
6341 if (!load_code) {
6342 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
6343 rc = -1;
6344 goto exit_leader_reset2;
6345 }
6346 }
6347
6348 /* try to recover after the failure */
6349 if (bnx2x_process_kill(sc, global)) {
6350 PMD_DRV_LOG(NOTICE, sc, "Something bad occurred on engine %d!",
6351 SC_PATH(sc));
6352 rc = -1;
6353 goto exit_leader_reset2;
6354 }
6355
6356 /*
6357 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
6358 * state.
6359 */
6360 bnx2x_set_reset_done(sc);
6361 if (global) {
6362 bnx2x_clear_reset_global(sc);
6363 }
6364
6365 exit_leader_reset2:
6366
6367 /* unload "fake driver" if it was loaded */
6368 if (!global &&!BNX2X_NOMCP(sc)) {
6369 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
6370 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
6371 }
6372
6373 exit_leader_reset:
6374
6375 sc->is_leader = 0;
6376 bnx2x_release_leader_lock(sc);
6377
6378 mb();
6379 return rc;
6380 }
6381
6382 /*
6383 * prepare INIT transition, parameters configured:
6384 * - HC configuration
6385 * - Queue's CDU context
6386 */
6387 static void
bnx2x_pf_q_prep_init(struct bnx2x_softc * sc,struct bnx2x_fastpath * fp,struct ecore_queue_init_params * init_params)6388 bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6389 struct ecore_queue_init_params *init_params)
6390 {
6391 uint8_t cos;
6392 int cxt_index, cxt_offset;
6393
6394 rte_bit_relaxed_set32(ECORE_Q_FLG_HC, &init_params->rx.flags);
6395 rte_bit_relaxed_set32(ECORE_Q_FLG_HC, &init_params->tx.flags);
6396
6397 rte_bit_relaxed_set32(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
6398 rte_bit_relaxed_set32(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
6399
6400 /* HC rate */
6401 init_params->rx.hc_rate =
6402 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
6403 init_params->tx.hc_rate =
6404 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
6405
6406 /* FW SB ID */
6407 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
6408
6409 /* CQ index among the SB indices */
6410 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6411 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
6412
6413 /* set maximum number of COSs supported by this queue */
6414 init_params->max_cos = sc->max_cos;
6415
6416 /* set the context pointers queue object */
6417 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
6418 cxt_index = fp->index / ILT_PAGE_CIDS;
6419 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
6420 init_params->cxts[cos] =
6421 &sc->context[cxt_index].vcxt[cxt_offset].eth;
6422 }
6423 }
6424
6425 /* set flags that are common for the Tx-only and not normal connections */
6426 static unsigned long
bnx2x_get_common_flags(struct bnx2x_softc * sc,uint8_t zero_stats)6427 bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)
6428 {
6429 uint32_t flags = 0;
6430
6431 /* PF driver will always initialize the Queue to an ACTIVE state */
6432 rte_bit_relaxed_set32(ECORE_Q_FLG_ACTIVE, &flags);
6433
6434 /*
6435 * tx only connections collect statistics (on the same index as the
6436 * parent connection). The statistics are zeroed when the parent
6437 * connection is initialized.
6438 */
6439
6440 rte_bit_relaxed_set32(ECORE_Q_FLG_STATS, &flags);
6441 if (zero_stats) {
6442 rte_bit_relaxed_set32(ECORE_Q_FLG_ZERO_STATS, &flags);
6443 }
6444
6445 /*
6446 * tx only connections can support tx-switching, though their
6447 * CoS-ness doesn't survive the loopback
6448 */
6449 if (sc->flags & BNX2X_TX_SWITCHING) {
6450 rte_bit_relaxed_set32(ECORE_Q_FLG_TX_SWITCH, &flags);
6451 }
6452
6453 rte_bit_relaxed_set32(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
6454
6455 return flags;
6456 }
6457
bnx2x_get_q_flags(struct bnx2x_softc * sc,uint8_t leading)6458 static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)
6459 {
6460 uint32_t flags = 0;
6461
6462 if (IS_MF_SD(sc)) {
6463 rte_bit_relaxed_set32(ECORE_Q_FLG_OV, &flags);
6464 }
6465
6466 if (leading) {
6467 rte_bit_relaxed_set32(ECORE_Q_FLG_LEADING_RSS, &flags);
6468 rte_bit_relaxed_set32(ECORE_Q_FLG_MCAST, &flags);
6469 }
6470
6471 rte_bit_relaxed_set32(ECORE_Q_FLG_VLAN, &flags);
6472
6473 /* merge with common flags */
6474 return flags | bnx2x_get_common_flags(sc, TRUE);
6475 }
6476
6477 static void
bnx2x_pf_q_prep_general(struct bnx2x_softc * sc,struct bnx2x_fastpath * fp,struct ecore_general_setup_params * gen_init,uint8_t cos)6478 bnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6479 struct ecore_general_setup_params *gen_init, uint8_t cos)
6480 {
6481 gen_init->stat_id = bnx2x_stats_id(fp);
6482 gen_init->spcl_id = fp->cl_id;
6483 gen_init->mtu = sc->mtu;
6484 gen_init->cos = cos;
6485 }
6486
6487 static void
bnx2x_pf_rx_q_prep(struct bnx2x_softc * sc,struct bnx2x_fastpath * fp,struct rxq_pause_params * pause,struct ecore_rxq_setup_params * rxq_init)6488 bnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6489 struct rxq_pause_params *pause,
6490 struct ecore_rxq_setup_params *rxq_init)
6491 {
6492 struct bnx2x_rx_queue *rxq;
6493
6494 rxq = sc->rx_queues[fp->index];
6495 if (!rxq) {
6496 PMD_RX_LOG(ERR, "RX queue is NULL");
6497 return;
6498 }
6499 /* pause */
6500 pause->bd_th_lo = BD_TH_LO(sc);
6501 pause->bd_th_hi = BD_TH_HI(sc);
6502
6503 pause->rcq_th_lo = RCQ_TH_LO(sc);
6504 pause->rcq_th_hi = RCQ_TH_HI(sc);
6505
6506 /* validate rings have enough entries to cross high thresholds */
6507 if (sc->dropless_fc &&
6508 pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {
6509 PMD_DRV_LOG(WARNING, sc, "rx bd ring threshold limit");
6510 }
6511
6512 if (sc->dropless_fc &&
6513 pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {
6514 PMD_DRV_LOG(WARNING, sc, "rcq ring threshold limit");
6515 }
6516
6517 pause->pri_map = 1;
6518
6519 /* rxq setup */
6520 rxq_init->dscr_map = (rte_iova_t)rxq->rx_ring_phys_addr;
6521 rxq_init->rcq_map = (rte_iova_t)rxq->cq_ring_phys_addr;
6522 rxq_init->rcq_np_map = (rte_iova_t)(rxq->cq_ring_phys_addr +
6523 BNX2X_PAGE_SIZE);
6524
6525 /*
6526 * This should be a maximum number of data bytes that may be
6527 * placed on the BD (not including paddings).
6528 */
6529 rxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);
6530
6531 rxq_init->cl_qzone_id = fp->cl_qzone_id;
6532 rxq_init->rss_engine_id = SC_FUNC(sc);
6533 rxq_init->mcast_engine_id = SC_FUNC(sc);
6534
6535 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
6536 rxq_init->fw_sb_id = fp->fw_sb_id;
6537
6538 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
6539
6540 /*
6541 * configure silent vlan removal
6542 * if multi function mode is afex, then mask default vlan
6543 */
6544 if (IS_MF_AFEX(sc)) {
6545 rxq_init->silent_removal_value =
6546 sc->devinfo.mf_info.afex_def_vlan_tag;
6547 rxq_init->silent_removal_mask = EVL_VLID_MASK;
6548 }
6549 }
6550
6551 static void
bnx2x_pf_tx_q_prep(struct bnx2x_softc * sc,struct bnx2x_fastpath * fp,struct ecore_txq_setup_params * txq_init,uint8_t cos)6552 bnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
6553 struct ecore_txq_setup_params *txq_init, uint8_t cos)
6554 {
6555 struct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];
6556
6557 if (!txq) {
6558 PMD_TX_LOG(ERR, "ERROR: TX queue is NULL");
6559 return;
6560 }
6561 txq_init->dscr_map = (rte_iova_t)txq->tx_ring_phys_addr;
6562 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
6563 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
6564 txq_init->fw_sb_id = fp->fw_sb_id;
6565
6566 /*
6567 * set the TSS leading client id for Tx classification to the
6568 * leading RSS client id
6569 */
6570 txq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);
6571 }
6572
6573 /*
6574 * This function performs 2 steps in a queue state machine:
6575 * 1) RESET->INIT
6576 * 2) INIT->SETUP
6577 */
6578 static int
bnx2x_setup_queue(struct bnx2x_softc * sc,struct bnx2x_fastpath * fp,uint8_t leading)6579 bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)
6580 {
6581 struct ecore_queue_state_params q_params = { NULL };
6582 struct ecore_queue_setup_params *setup_params = &q_params.params.setup;
6583 int rc;
6584
6585 PMD_DRV_LOG(DEBUG, sc, "setting up queue %d", fp->index);
6586
6587 bnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6588
6589 q_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;
6590
6591 /* we want to wait for completion in this context */
6592 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
6593
6594 /* prepare the INIT parameters */
6595 bnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);
6596
6597 /* Set the command */
6598 q_params.cmd = ECORE_Q_CMD_INIT;
6599
6600 /* Change the state to INIT */
6601 rc = ecore_queue_state_change(sc, &q_params);
6602 if (rc) {
6603 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) INIT failed", fp->index);
6604 return rc;
6605 }
6606
6607 PMD_DRV_LOG(DEBUG, sc, "init complete");
6608
6609 /* now move the Queue to the SETUP state */
6610 memset(setup_params, 0, sizeof(*setup_params));
6611
6612 /* set Queue flags */
6613 setup_params->flags = bnx2x_get_q_flags(sc, leading);
6614
6615 /* set general SETUP parameters */
6616 bnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,
6617 FIRST_TX_COS_INDEX);
6618
6619 bnx2x_pf_rx_q_prep(sc, fp,
6620 &setup_params->pause_params,
6621 &setup_params->rxq_params);
6622
6623 bnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);
6624
6625 /* Set the command */
6626 q_params.cmd = ECORE_Q_CMD_SETUP;
6627
6628 /* change the state to SETUP */
6629 rc = ecore_queue_state_change(sc, &q_params);
6630 if (rc) {
6631 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) SETUP failed", fp->index);
6632 return rc;
6633 }
6634
6635 return rc;
6636 }
6637
bnx2x_setup_leading(struct bnx2x_softc * sc)6638 static int bnx2x_setup_leading(struct bnx2x_softc *sc)
6639 {
6640 if (IS_PF(sc))
6641 return bnx2x_setup_queue(sc, &sc->fp[0], TRUE);
6642 else /* VF */
6643 return bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);
6644 }
6645
6646 static int
bnx2x_config_rss_pf(struct bnx2x_softc * sc,struct ecore_rss_config_obj * rss_obj,uint8_t config_hash)6647 bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,
6648 uint8_t config_hash)
6649 {
6650 struct ecore_config_rss_params params = { NULL };
6651 uint32_t i;
6652
6653 /*
6654 * Although RSS is meaningless when there is a single HW queue we
6655 * still need it enabled in order to have HW Rx hash generated.
6656 */
6657
6658 params.rss_obj = rss_obj;
6659
6660 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
6661
6662 rte_bit_relaxed_set32(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
6663
6664 /* RSS configuration */
6665 rte_bit_relaxed_set32(ECORE_RSS_IPV4, ¶ms.rss_flags);
6666 rte_bit_relaxed_set32(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
6667 rte_bit_relaxed_set32(ECORE_RSS_IPV6, ¶ms.rss_flags);
6668 rte_bit_relaxed_set32(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
6669 if (rss_obj->udp_rss_v4) {
6670 rte_bit_relaxed_set32(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
6671 }
6672 if (rss_obj->udp_rss_v6) {
6673 rte_bit_relaxed_set32(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
6674 }
6675
6676 /* Hash bits */
6677 params.rss_result_mask = MULTI_MASK;
6678
6679 rte_memcpy(params.ind_table, rss_obj->ind_table,
6680 sizeof(params.ind_table));
6681
6682 if (config_hash) {
6683 /* RSS keys */
6684 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
6685 params.rss_key[i] = (uint32_t) rte_rand();
6686 }
6687
6688 rte_bit_relaxed_set32(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
6689 }
6690
6691 if (IS_PF(sc))
6692 return ecore_config_rss(sc, ¶ms);
6693 else
6694 return bnx2x_vf_config_rss(sc, ¶ms);
6695 }
6696
bnx2x_config_rss_eth(struct bnx2x_softc * sc,uint8_t config_hash)6697 static int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)
6698 {
6699 return bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);
6700 }
6701
bnx2x_init_rss_pf(struct bnx2x_softc * sc)6702 static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)
6703 {
6704 uint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);
6705 uint32_t i;
6706
6707 /*
6708 * Prepare the initial contents of the indirection table if
6709 * RSS is enabled
6710 */
6711 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
6712 sc->rss_conf_obj.ind_table[i] =
6713 (sc->fp->cl_id + (i % num_eth_queues));
6714 }
6715
6716 if (sc->udp_rss) {
6717 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
6718 }
6719
6720 /*
6721 * For 57711 SEARCHER configuration (rss_keys) is
6722 * per-port, so if explicit configuration is needed, do it only
6723 * for a PMF.
6724 *
6725 * For 57712 and newer it's a per-function configuration.
6726 */
6727 return bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));
6728 }
6729
6730 static int
bnx2x_set_mac_one(struct bnx2x_softc * sc,uint8_t * mac,struct ecore_vlan_mac_obj * obj,uint8_t set,int mac_type,uint32_t * ramrod_flags)6731 bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,
6732 struct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,
6733 uint32_t *ramrod_flags)
6734 {
6735 struct ecore_vlan_mac_ramrod_params ramrod_param;
6736 int rc;
6737
6738 memset(&ramrod_param, 0, sizeof(ramrod_param));
6739
6740 /* fill in general parameters */
6741 ramrod_param.vlan_mac_obj = obj;
6742 ramrod_param.ramrod_flags = *ramrod_flags;
6743
6744 /* fill a user request section if needed */
6745 if (!rte_bit_relaxed_get32(RAMROD_CONT, ramrod_flags)) {
6746 rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,
6747 ETH_ALEN);
6748
6749 rte_bit_relaxed_set32(mac_type,
6750 &ramrod_param.user_req.vlan_mac_flags);
6751
6752 /* Set the command: ADD or DEL */
6753 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
6754 ECORE_VLAN_MAC_DEL;
6755 }
6756
6757 rc = ecore_config_vlan_mac(sc, &ramrod_param);
6758
6759 if (rc == ECORE_EXISTS) {
6760 PMD_DRV_LOG(INFO, sc, "Failed to schedule ADD operations (EEXIST)");
6761 /* do not treat adding same MAC as error */
6762 rc = 0;
6763 } else if (rc < 0) {
6764 PMD_DRV_LOG(ERR, sc,
6765 "%s MAC failed (%d)", (set ? "Set" : "Delete"), rc);
6766 }
6767
6768 return rc;
6769 }
6770
bnx2x_set_eth_mac(struct bnx2x_softc * sc,uint8_t set)6771 static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)
6772 {
6773 uint32_t ramrod_flags = 0;
6774
6775 PMD_DRV_LOG(DEBUG, sc, "Adding Ethernet MAC");
6776
6777 rte_bit_relaxed_set32(RAMROD_COMP_WAIT, &ramrod_flags);
6778
6779 /* Eth MAC is set on RSS leading client (fp[0]) */
6780 return bnx2x_set_mac_one(sc, sc->link_params.mac_addr,
6781 &sc->sp_objs->mac_obj,
6782 set, ECORE_ETH_MAC, &ramrod_flags);
6783 }
6784
bnx2x_get_cur_phy_idx(struct bnx2x_softc * sc)6785 static int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)
6786 {
6787 uint32_t sel_phy_idx = 0;
6788
6789 if (sc->link_params.num_phys <= 1) {
6790 return ELINK_INT_PHY;
6791 }
6792
6793 if (sc->link_vars.link_up) {
6794 sel_phy_idx = ELINK_EXT_PHY1;
6795 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
6796 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
6797 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
6798 ELINK_SUPPORTED_FIBRE))
6799 sel_phy_idx = ELINK_EXT_PHY2;
6800 } else {
6801 switch (elink_phy_selection(&sc->link_params)) {
6802 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6803 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6804 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6805 sel_phy_idx = ELINK_EXT_PHY1;
6806 break;
6807 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6808 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6809 sel_phy_idx = ELINK_EXT_PHY2;
6810 break;
6811 }
6812 }
6813
6814 return sel_phy_idx;
6815 }
6816
bnx2x_get_link_cfg_idx(struct bnx2x_softc * sc)6817 static int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)
6818 {
6819 uint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);
6820
6821 /*
6822 * The selected activated PHY is always after swapping (in case PHY
6823 * swapping is enabled). So when swapping is enabled, we need to reverse
6824 * the configuration
6825 */
6826
6827 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
6828 if (sel_phy_idx == ELINK_EXT_PHY1)
6829 sel_phy_idx = ELINK_EXT_PHY2;
6830 else if (sel_phy_idx == ELINK_EXT_PHY2)
6831 sel_phy_idx = ELINK_EXT_PHY1;
6832 }
6833
6834 return ELINK_LINK_CONFIG_IDX(sel_phy_idx);
6835 }
6836
bnx2x_set_requested_fc(struct bnx2x_softc * sc)6837 static void bnx2x_set_requested_fc(struct bnx2x_softc *sc)
6838 {
6839 /*
6840 * Initialize link parameters structure variables
6841 * It is recommended to turn off RX FC for jumbo frames
6842 * for better performance
6843 */
6844 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
6845 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
6846 } else {
6847 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
6848 }
6849 }
6850
bnx2x_calc_fc_adv(struct bnx2x_softc * sc)6851 static void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)
6852 {
6853 uint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);
6854 switch (sc->link_vars.ieee_fc &
6855 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
6856 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
6857 default:
6858 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
6859 ADVERTISED_Pause);
6860 break;
6861
6862 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
6863 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
6864 ADVERTISED_Pause);
6865 break;
6866
6867 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
6868 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
6869 break;
6870 }
6871 }
6872
bnx2x_get_mf_speed(struct bnx2x_softc * sc)6873 static uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)
6874 {
6875 uint16_t line_speed = sc->link_vars.line_speed;
6876 if (IS_MF(sc)) {
6877 uint16_t maxCfg = bnx2x_extract_max_cfg(sc,
6878 sc->devinfo.
6879 mf_info.mf_config[SC_VN
6880 (sc)]);
6881
6882 /* calculate the current MAX line speed limit for the MF devices */
6883 if (IS_MF_SI(sc)) {
6884 line_speed = (line_speed * maxCfg) / 100;
6885 } else { /* SD mode */
6886 uint16_t vn_max_rate = maxCfg * 100;
6887
6888 if (vn_max_rate < line_speed) {
6889 line_speed = vn_max_rate;
6890 }
6891 }
6892 }
6893
6894 return line_speed;
6895 }
6896
6897 static void
bnx2x_fill_report_data(struct bnx2x_softc * sc,struct bnx2x_link_report_data * data)6898 bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)
6899 {
6900 uint16_t line_speed = bnx2x_get_mf_speed(sc);
6901
6902 memset(data, 0, sizeof(*data));
6903
6904 /* fill the report data with the effective line speed */
6905 data->line_speed = line_speed;
6906
6907 /* Link is down */
6908 if (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {
6909 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_LINK_DOWN,
6910 &data->link_report_flags);
6911 }
6912
6913 /* Full DUPLEX */
6914 if (sc->link_vars.duplex == DUPLEX_FULL) {
6915 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_FULL_DUPLEX,
6916 &data->link_report_flags);
6917 }
6918
6919 /* Rx Flow Control is ON */
6920 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
6921 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_RX_FC_ON,
6922 &data->link_report_flags);
6923 }
6924
6925 /* Tx Flow Control is ON */
6926 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
6927 rte_bit_relaxed_set32(BNX2X_LINK_REPORT_TX_FC_ON,
6928 &data->link_report_flags);
6929 }
6930 }
6931
6932 /* report link status to OS, should be called under phy_lock */
bnx2x_link_report_locked(struct bnx2x_softc * sc)6933 static void bnx2x_link_report_locked(struct bnx2x_softc *sc)
6934 {
6935 struct bnx2x_link_report_data cur_data;
6936
6937 /* reread mf_cfg */
6938 if (IS_PF(sc)) {
6939 bnx2x_read_mf_cfg(sc);
6940 }
6941
6942 /* Read the current link report info */
6943 bnx2x_fill_report_data(sc, &cur_data);
6944
6945 /* Don't report link down or exactly the same link status twice */
6946 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
6947 (rte_bit_relaxed_get32(BNX2X_LINK_REPORT_LINK_DOWN,
6948 &sc->last_reported_link.link_report_flags) &&
6949 rte_bit_relaxed_get32(BNX2X_LINK_REPORT_LINK_DOWN,
6950 &cur_data.link_report_flags))) {
6951 return;
6952 }
6953
6954 ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %x, last_reported_link = %x",
6955 cur_data.link_report_flags,
6956 sc->last_reported_link.link_report_flags);
6957
6958 sc->link_cnt++;
6959
6960 ELINK_DEBUG_P1(sc, "link status change count = %x", sc->link_cnt);
6961 /* report new link params and remember the state for the next time */
6962 rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
6963
6964 if (rte_bit_relaxed_get32(BNX2X_LINK_REPORT_LINK_DOWN,
6965 &cur_data.link_report_flags)) {
6966 ELINK_DEBUG_P0(sc, "NIC Link is Down");
6967 } else {
6968 __rte_unused const char *duplex;
6969 __rte_unused const char *flow;
6970
6971 if (rte_bit_relaxed_test_and_clear32
6972 (BNX2X_LINK_REPORT_FULL_DUPLEX,
6973 &cur_data.link_report_flags)) {
6974 duplex = "full";
6975 ELINK_DEBUG_P0(sc, "link set to full duplex");
6976 } else {
6977 duplex = "half";
6978 ELINK_DEBUG_P0(sc, "link set to half duplex");
6979 }
6980
6981 /*
6982 * Handle the FC at the end so that only these flags would be
6983 * possibly set. This way we may easily check if there is no FC
6984 * enabled.
6985 */
6986 if (cur_data.link_report_flags) {
6987 if (rte_bit_relaxed_get32
6988 (BNX2X_LINK_REPORT_RX_FC_ON,
6989 &cur_data.link_report_flags) &&
6990 rte_bit_relaxed_get32(BNX2X_LINK_REPORT_TX_FC_ON,
6991 &cur_data.link_report_flags)) {
6992 flow = "ON - receive & transmit";
6993 } else if (rte_bit_relaxed_get32
6994 (BNX2X_LINK_REPORT_RX_FC_ON,
6995 &cur_data.link_report_flags) &&
6996 !rte_bit_relaxed_get32
6997 (BNX2X_LINK_REPORT_TX_FC_ON,
6998 &cur_data.link_report_flags)) {
6999 flow = "ON - receive";
7000 } else if (!rte_bit_relaxed_get32
7001 (BNX2X_LINK_REPORT_RX_FC_ON,
7002 &cur_data.link_report_flags) &&
7003 rte_bit_relaxed_get32
7004 (BNX2X_LINK_REPORT_TX_FC_ON,
7005 &cur_data.link_report_flags)) {
7006 flow = "ON - transmit";
7007 } else {
7008 flow = "none"; /* possible? */
7009 }
7010 } else {
7011 flow = "none";
7012 }
7013
7014 PMD_DRV_LOG(INFO, sc,
7015 "NIC Link is Up, %d Mbps %s duplex, Flow control: %s",
7016 cur_data.line_speed, duplex, flow);
7017 }
7018 }
7019
7020 static void
bnx2x_link_report(struct bnx2x_softc * sc)7021 bnx2x_link_report(struct bnx2x_softc *sc)
7022 {
7023 bnx2x_acquire_phy_lock(sc);
7024 bnx2x_link_report_locked(sc);
7025 bnx2x_release_phy_lock(sc);
7026 }
7027
bnx2x_link_status_update(struct bnx2x_softc * sc)7028 void bnx2x_link_status_update(struct bnx2x_softc *sc)
7029 {
7030 if (sc->state != BNX2X_STATE_OPEN) {
7031 return;
7032 }
7033
7034 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
7035 elink_link_status_update(&sc->link_params, &sc->link_vars);
7036 } else {
7037 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
7038 ELINK_SUPPORTED_10baseT_Full |
7039 ELINK_SUPPORTED_100baseT_Half |
7040 ELINK_SUPPORTED_100baseT_Full |
7041 ELINK_SUPPORTED_1000baseT_Full |
7042 ELINK_SUPPORTED_2500baseX_Full |
7043 ELINK_SUPPORTED_10000baseT_Full |
7044 ELINK_SUPPORTED_TP |
7045 ELINK_SUPPORTED_FIBRE |
7046 ELINK_SUPPORTED_Autoneg |
7047 ELINK_SUPPORTED_Pause |
7048 ELINK_SUPPORTED_Asym_Pause);
7049 sc->port.advertising[0] = sc->port.supported[0];
7050
7051 sc->link_params.sc = sc;
7052 sc->link_params.port = SC_PORT(sc);
7053 sc->link_params.req_duplex[0] = DUPLEX_FULL;
7054 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
7055 sc->link_params.req_line_speed[0] = SPEED_10000;
7056 sc->link_params.speed_cap_mask[0] = 0x7f0000;
7057 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
7058
7059 if (CHIP_REV_IS_FPGA(sc)) {
7060 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
7061 sc->link_vars.line_speed = ELINK_SPEED_1000;
7062 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7063 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
7064 } else {
7065 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
7066 sc->link_vars.line_speed = ELINK_SPEED_10000;
7067 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
7068 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
7069 }
7070
7071 sc->link_vars.link_up = 1;
7072
7073 sc->link_vars.duplex = DUPLEX_FULL;
7074 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
7075
7076 if (IS_PF(sc)) {
7077 REG_WR(sc,
7078 NIG_REG_EGRESS_DRAIN0_MODE +
7079 sc->link_params.port * 4, 0);
7080 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7081 bnx2x_link_report(sc);
7082 }
7083 }
7084
7085 if (IS_PF(sc)) {
7086 if (sc->link_vars.link_up) {
7087 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7088 } else {
7089 bnx2x_stats_handle(sc, STATS_EVENT_STOP);
7090 }
7091 bnx2x_link_report(sc);
7092 } else {
7093 bnx2x_link_report_locked(sc);
7094 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7095 }
7096 }
7097
bnx2x_initial_phy_init(struct bnx2x_softc * sc,int load_mode)7098 static int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)
7099 {
7100 int rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);
7101 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
7102 struct elink_params *lp = &sc->link_params;
7103
7104 bnx2x_set_requested_fc(sc);
7105
7106 bnx2x_acquire_phy_lock(sc);
7107
7108 if (load_mode == LOAD_DIAG) {
7109 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
7110 /* Prefer doing PHY loopback at 10G speed, if possible */
7111 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
7112 if (lp->speed_cap_mask[cfg_idx] &
7113 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
7114 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
7115 } else {
7116 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
7117 }
7118 }
7119 }
7120
7121 if (load_mode == LOAD_LOOPBACK_EXT) {
7122 lp->loopback_mode = ELINK_LOOPBACK_EXT;
7123 }
7124
7125 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
7126
7127 bnx2x_release_phy_lock(sc);
7128
7129 bnx2x_calc_fc_adv(sc);
7130
7131 if (sc->link_vars.link_up) {
7132 bnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);
7133 bnx2x_link_report(sc);
7134 }
7135
7136 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
7137 return rc;
7138 }
7139
7140 /* update flags in shmem */
7141 static void
bnx2x_update_drv_flags(struct bnx2x_softc * sc,uint32_t flags,uint32_t set)7142 bnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)
7143 {
7144 uint32_t drv_flags;
7145
7146 if (SHMEM2_HAS(sc, drv_flags)) {
7147 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7148 drv_flags = SHMEM2_RD(sc, drv_flags);
7149
7150 if (set) {
7151 drv_flags |= flags;
7152 } else {
7153 drv_flags &= ~flags;
7154 }
7155
7156 SHMEM2_WR(sc, drv_flags, drv_flags);
7157
7158 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
7159 }
7160 }
7161
7162 /* periodic timer callout routine, only runs when the interface is up */
bnx2x_periodic_callout(struct bnx2x_softc * sc)7163 void bnx2x_periodic_callout(struct bnx2x_softc *sc)
7164 {
7165 if ((sc->state != BNX2X_STATE_OPEN) ||
7166 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
7167 PMD_DRV_LOG(DEBUG, sc, "periodic callout exit (state=0x%x)",
7168 sc->state);
7169 return;
7170 }
7171 if (!CHIP_REV_IS_SLOW(sc)) {
7172 /*
7173 * This barrier is needed to ensure the ordering between the writing
7174 * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
7175 * the reading here.
7176 */
7177 mb();
7178 if (sc->port.pmf) {
7179 bnx2x_acquire_phy_lock(sc);
7180 elink_period_func(&sc->link_params, &sc->link_vars);
7181 bnx2x_release_phy_lock(sc);
7182 }
7183 }
7184 #ifdef BNX2X_PULSE
7185 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7186 int mb_idx = SC_FW_MB_IDX(sc);
7187 uint32_t drv_pulse;
7188 uint32_t mcp_pulse;
7189
7190 ++sc->fw_drv_pulse_wr_seq;
7191 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
7192
7193 drv_pulse = sc->fw_drv_pulse_wr_seq;
7194 bnx2x_drv_pulse(sc);
7195
7196 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
7197 MCP_PULSE_SEQ_MASK);
7198
7199 /*
7200 * The delta between driver pulse and mcp response should
7201 * be 1 (before mcp response) or 0 (after mcp response).
7202 */
7203 if ((drv_pulse != mcp_pulse) &&
7204 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
7205 /* someone lost a heartbeat... */
7206 PMD_DRV_LOG(ERR, sc,
7207 "drv_pulse (0x%x) != mcp_pulse (0x%x)",
7208 drv_pulse, mcp_pulse);
7209 }
7210 }
7211 #endif
7212 }
7213
7214 /* start the controller */
7215 static __rte_noinline
bnx2x_nic_load(struct bnx2x_softc * sc)7216 int bnx2x_nic_load(struct bnx2x_softc *sc)
7217 {
7218 uint32_t val;
7219 uint32_t load_code = 0;
7220 int i, rc = 0;
7221
7222 PMD_INIT_FUNC_TRACE(sc);
7223
7224 sc->state = BNX2X_STATE_OPENING_WAITING_LOAD;
7225
7226 if (IS_PF(sc)) {
7227 /* must be called before memory allocation and HW init */
7228 bnx2x_ilt_set_info(sc);
7229 }
7230
7231 bnx2x_set_fp_rx_buf_size(sc);
7232
7233 if (IS_PF(sc)) {
7234 if (bnx2x_alloc_mem(sc) != 0) {
7235 sc->state = BNX2X_STATE_CLOSED;
7236 rc = -ENOMEM;
7237 goto bnx2x_nic_load_error0;
7238 }
7239 }
7240
7241 /* allocate the host hardware/software hsi structures */
7242 if (bnx2x_alloc_hsi_mem(sc) != 0) {
7243 PMD_DRV_LOG(ERR, sc, "bnx2x_alloc_hsi_mem was failed");
7244 sc->state = BNX2X_STATE_CLOSED;
7245 rc = -ENOMEM;
7246 goto bnx2x_nic_load_error0;
7247 }
7248
7249 if (bnx2x_alloc_fw_stats_mem(sc) != 0) {
7250 sc->state = BNX2X_STATE_CLOSED;
7251 rc = -ENOMEM;
7252 goto bnx2x_nic_load_error0;
7253 }
7254
7255 if (IS_VF(sc)) {
7256 rc = bnx2x_vf_init(sc);
7257 if (rc) {
7258 sc->state = BNX2X_STATE_ERROR;
7259 goto bnx2x_nic_load_error0;
7260 }
7261 }
7262
7263 if (IS_PF(sc)) {
7264 /* set pf load just before approaching the MCP */
7265 bnx2x_set_pf_load(sc);
7266
7267 /* if MCP exists send load request and analyze response */
7268 if (!BNX2X_NOMCP(sc)) {
7269 /* attempt to load pf */
7270 if (bnx2x_nic_load_request(sc, &load_code) != 0) {
7271 sc->state = BNX2X_STATE_CLOSED;
7272 rc = -ENXIO;
7273 goto bnx2x_nic_load_error1;
7274 }
7275
7276 /* what did the MCP say? */
7277 if (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {
7278 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7279 sc->state = BNX2X_STATE_CLOSED;
7280 rc = -ENXIO;
7281 goto bnx2x_nic_load_error2;
7282 }
7283 } else {
7284 PMD_DRV_LOG(INFO, sc, "Device has no MCP!");
7285 load_code = bnx2x_nic_load_no_mcp(sc);
7286 }
7287
7288 /* mark PMF if applicable */
7289 bnx2x_nic_load_pmf(sc, load_code);
7290
7291 /* Init Function state controlling object */
7292 bnx2x_init_func_obj(sc);
7293
7294 /* Initialize HW */
7295 if (bnx2x_init_hw(sc, load_code) != 0) {
7296 PMD_DRV_LOG(NOTICE, sc, "HW init failed");
7297 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7298 sc->state = BNX2X_STATE_CLOSED;
7299 rc = -ENXIO;
7300 goto bnx2x_nic_load_error2;
7301 }
7302 }
7303
7304 bnx2x_nic_init(sc, load_code);
7305
7306 /* Init per-function objects */
7307 if (IS_PF(sc)) {
7308 bnx2x_init_objs(sc);
7309
7310 /* set AFEX default VLAN tag to an invalid value */
7311 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
7312
7313 sc->state = BNX2X_STATE_OPENING_WAITING_PORT;
7314 rc = bnx2x_func_start(sc);
7315 if (rc) {
7316 PMD_DRV_LOG(NOTICE, sc, "Function start failed!");
7317 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7318 sc->state = BNX2X_STATE_ERROR;
7319 goto bnx2x_nic_load_error3;
7320 }
7321
7322 /* send LOAD_DONE command to MCP */
7323 if (!BNX2X_NOMCP(sc)) {
7324 load_code =
7325 bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
7326 if (!load_code) {
7327 PMD_DRV_LOG(NOTICE, sc,
7328 "MCP response failure, aborting");
7329 sc->state = BNX2X_STATE_ERROR;
7330 rc = -ENXIO;
7331 goto bnx2x_nic_load_error3;
7332 }
7333 }
7334 }
7335
7336 rc = bnx2x_setup_leading(sc);
7337 if (rc) {
7338 PMD_DRV_LOG(NOTICE, sc, "Setup leading failed!");
7339 sc->state = BNX2X_STATE_ERROR;
7340 goto bnx2x_nic_load_error3;
7341 }
7342
7343 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
7344 if (IS_PF(sc))
7345 rc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);
7346 else /* IS_VF(sc) */
7347 rc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);
7348
7349 if (rc) {
7350 PMD_DRV_LOG(NOTICE, sc, "Queue(%d) setup failed", i);
7351 sc->state = BNX2X_STATE_ERROR;
7352 goto bnx2x_nic_load_error3;
7353 }
7354 }
7355
7356 rc = bnx2x_init_rss_pf(sc);
7357 if (rc) {
7358 PMD_DRV_LOG(NOTICE, sc, "PF RSS init failed");
7359 sc->state = BNX2X_STATE_ERROR;
7360 goto bnx2x_nic_load_error3;
7361 }
7362
7363 /* now when Clients are configured we are ready to work */
7364 sc->state = BNX2X_STATE_OPEN;
7365
7366 /* Configure a ucast MAC */
7367 if (IS_PF(sc)) {
7368 rc = bnx2x_set_eth_mac(sc, TRUE);
7369 } else { /* IS_VF(sc) */
7370 rc = bnx2x_vf_set_mac(sc, TRUE);
7371 }
7372
7373 if (rc) {
7374 PMD_DRV_LOG(NOTICE, sc, "Setting Ethernet MAC failed");
7375 sc->state = BNX2X_STATE_ERROR;
7376 goto bnx2x_nic_load_error3;
7377 }
7378
7379 if (sc->port.pmf) {
7380 rc = bnx2x_initial_phy_init(sc, LOAD_OPEN);
7381 if (rc) {
7382 sc->state = BNX2X_STATE_ERROR;
7383 goto bnx2x_nic_load_error3;
7384 }
7385 }
7386
7387 sc->link_params.feature_config_flags &=
7388 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
7389
7390 /* start the Tx */
7391 switch (LOAD_OPEN) {
7392 case LOAD_NORMAL:
7393 case LOAD_OPEN:
7394 break;
7395
7396 case LOAD_DIAG:
7397 case LOAD_LOOPBACK_EXT:
7398 sc->state = BNX2X_STATE_DIAG;
7399 break;
7400
7401 default:
7402 break;
7403 }
7404
7405 if (sc->port.pmf) {
7406 bnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
7407 } else {
7408 bnx2x_link_status_update(sc);
7409 }
7410
7411 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
7412 /* mark driver is loaded in shmem2 */
7413 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
7414 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
7415 (val |
7416 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
7417 DRV_FLAGS_CAPABILITIES_LOADED_L2));
7418 }
7419
7420 /* start fast path */
7421 /* Initialize Rx filter */
7422 bnx2x_set_rx_mode(sc);
7423
7424 /* wait for all pending SP commands to complete */
7425 if (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0U)) {
7426 PMD_DRV_LOG(NOTICE, sc, "Timeout waiting for all SPs to complete!");
7427 bnx2x_periodic_stop(sc);
7428 bnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);
7429 return -ENXIO;
7430 }
7431
7432 PMD_DRV_LOG(DEBUG, sc, "NIC successfully loaded");
7433
7434 return 0;
7435
7436 bnx2x_nic_load_error3:
7437
7438 if (IS_PF(sc)) {
7439 bnx2x_int_disable_sync(sc, 1);
7440
7441 /* clean out queued objects */
7442 bnx2x_squeeze_objects(sc);
7443 }
7444
7445 bnx2x_nic_load_error2:
7446
7447 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
7448 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
7449 bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
7450 }
7451
7452 sc->port.pmf = 0;
7453
7454 bnx2x_nic_load_error1:
7455
7456 /* clear pf_load status, as it was already set */
7457 if (IS_PF(sc)) {
7458 bnx2x_clear_pf_load(sc);
7459 }
7460
7461 bnx2x_nic_load_error0:
7462
7463 bnx2x_free_fw_stats_mem(sc);
7464 bnx2x_free_hsi_mem(sc);
7465 bnx2x_free_mem(sc);
7466
7467 return rc;
7468 }
7469
7470 /*
7471 * Handles controller initialization.
7472 */
bnx2x_init(struct bnx2x_softc * sc)7473 int bnx2x_init(struct bnx2x_softc *sc)
7474 {
7475 int other_engine = SC_PATH(sc) ? 0 : 1;
7476 uint8_t other_load_status, load_status;
7477 uint8_t global = FALSE;
7478 int rc;
7479
7480 /* Check if the driver is still running and bail out if it is. */
7481 if (sc->state != BNX2X_STATE_CLOSED) {
7482 PMD_DRV_LOG(DEBUG, sc, "Init called while driver is running!");
7483 rc = 0;
7484 goto bnx2x_init_done;
7485 }
7486
7487 bnx2x_set_power_state(sc, PCI_PM_D0);
7488
7489 /*
7490 * If parity occurred during the unload, then attentions and/or
7491 * RECOVERY_IN_PROGRESS may still be set. If so we want the first function
7492 * loaded on the current engine to complete the recovery. Parity recovery
7493 * is only relevant for PF driver.
7494 */
7495 if (IS_PF(sc)) {
7496 other_load_status = bnx2x_get_load_status(sc, other_engine);
7497 load_status = bnx2x_get_load_status(sc, SC_PATH(sc));
7498
7499 if (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||
7500 bnx2x_chk_parity_attn(sc, &global, TRUE)) {
7501 do {
7502 /*
7503 * If there are attentions and they are in global blocks, set
7504 * the GLOBAL_RESET bit regardless whether it will be this
7505 * function that will complete the recovery or not.
7506 */
7507 if (global) {
7508 bnx2x_set_reset_global(sc);
7509 }
7510
7511 /*
7512 * Only the first function on the current engine should try
7513 * to recover in open. In case of attentions in global blocks
7514 * only the first in the chip should try to recover.
7515 */
7516 if ((!load_status
7517 && (!global ||!other_load_status))
7518 && bnx2x_trylock_leader_lock(sc)
7519 && !bnx2x_leader_reset(sc)) {
7520 PMD_DRV_LOG(INFO, sc,
7521 "Recovered during init");
7522 break;
7523 }
7524
7525 /* recovery has failed... */
7526 bnx2x_set_power_state(sc, PCI_PM_D3hot);
7527
7528 sc->recovery_state = BNX2X_RECOVERY_FAILED;
7529
7530 PMD_DRV_LOG(NOTICE, sc,
7531 "Recovery flow hasn't properly "
7532 "completed yet, try again later. "
7533 "If you still see this message after a "
7534 "few retries then power cycle is required.");
7535
7536 rc = -ENXIO;
7537 goto bnx2x_init_done;
7538 } while (0);
7539 }
7540 }
7541
7542 sc->recovery_state = BNX2X_RECOVERY_DONE;
7543
7544 rc = bnx2x_nic_load(sc);
7545
7546 bnx2x_init_done:
7547
7548 if (rc) {
7549 PMD_DRV_LOG(NOTICE, sc, "Initialization failed, "
7550 "stack notified driver is NOT running!");
7551 }
7552
7553 return rc;
7554 }
7555
bnx2x_get_function_num(struct bnx2x_softc * sc)7556 static void bnx2x_get_function_num(struct bnx2x_softc *sc)
7557 {
7558 uint32_t val = 0;
7559
7560 /*
7561 * Read the ME register to get the function number. The ME register
7562 * holds the relative-function number and absolute-function number. The
7563 * absolute-function number appears only in E2 and above. Before that
7564 * these bits always contained zero, therefore we cannot blindly use them.
7565 */
7566
7567 val = REG_RD(sc, BAR_ME_REGISTER);
7568
7569 sc->pfunc_rel =
7570 (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
7571 sc->path_id =
7572 (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &
7573 1;
7574
7575 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
7576 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
7577 } else {
7578 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
7579 }
7580
7581 PMD_DRV_LOG(DEBUG, sc,
7582 "Relative function %d, Absolute function %d, Path %d",
7583 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
7584 }
7585
bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc * sc)7586 static uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)
7587 {
7588 uint32_t shmem2_size;
7589 uint32_t offset;
7590 uint32_t mf_cfg_offset_value;
7591
7592 /* Non 57712 */
7593 offset = (SHMEM_ADDR(sc, func_mb) +
7594 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
7595
7596 /* 57712 plus */
7597 if (sc->devinfo.shmem2_base != 0) {
7598 shmem2_size = SHMEM2_RD(sc, size);
7599 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
7600 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
7601 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
7602 offset = mf_cfg_offset_value;
7603 }
7604 }
7605 }
7606
7607 return offset;
7608 }
7609
bnx2x_pcie_capability_read(struct bnx2x_softc * sc,int reg)7610 static uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)
7611 {
7612 uint32_t ret;
7613 struct bnx2x_pci_cap *caps;
7614
7615 /* ensure PCIe capability is enabled */
7616 caps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);
7617 if (NULL != caps) {
7618 PMD_DRV_LOG(DEBUG, sc, "Found PCIe capability: "
7619 "id=0x%04X type=0x%04X addr=0x%08X",
7620 caps->id, caps->type, caps->addr);
7621 pci_read(sc, (caps->addr + reg), &ret, 2);
7622 return ret;
7623 }
7624
7625 PMD_DRV_LOG(WARNING, sc, "PCIe capability NOT FOUND!!!");
7626
7627 return 0;
7628 }
7629
bnx2x_is_pcie_pending(struct bnx2x_softc * sc)7630 static uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)
7631 {
7632 return bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &
7633 PCIM_EXP_STA_TRANSACTION_PND;
7634 }
7635
7636 /*
7637 * Walk the PCI capabilities list for the device to find what features are
7638 * supported. These capabilities may be enabled/disabled by firmware so it's
7639 * best to walk the list rather than make assumptions.
7640 */
bnx2x_probe_pci_caps(struct bnx2x_softc * sc)7641 static void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)
7642 {
7643 PMD_INIT_FUNC_TRACE(sc);
7644
7645 struct bnx2x_pci_cap *caps;
7646 uint16_t link_status;
7647 int reg = 0;
7648
7649 /* check if PCI Power Management is enabled */
7650 caps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);
7651 if (NULL != caps) {
7652 PMD_DRV_LOG(DEBUG, sc, "Found PM capability: "
7653 "id=0x%04X type=0x%04X addr=0x%08X",
7654 caps->id, caps->type, caps->addr);
7655
7656 sc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;
7657 sc->devinfo.pcie_pm_cap_reg = caps->addr;
7658 }
7659
7660 link_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);
7661
7662 sc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);
7663 sc->devinfo.pcie_link_width =
7664 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
7665
7666 PMD_DRV_LOG(DEBUG, sc, "PCIe link speed=%d width=%d",
7667 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
7668
7669 sc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;
7670
7671 /* check if MSI capability is enabled */
7672 caps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);
7673 if (NULL != caps) {
7674 PMD_DRV_LOG(DEBUG, sc, "Found MSI capability at 0x%04x", reg);
7675
7676 sc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;
7677 sc->devinfo.pcie_msi_cap_reg = caps->addr;
7678 }
7679
7680 /* check if MSI-X capability is enabled */
7681 caps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);
7682 if (NULL != caps) {
7683 PMD_DRV_LOG(DEBUG, sc, "Found MSI-X capability at 0x%04x", reg);
7684
7685 sc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;
7686 sc->devinfo.pcie_msix_cap_reg = caps->addr;
7687 }
7688 }
7689
bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc * sc)7690 static int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)
7691 {
7692 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7693 uint32_t val;
7694
7695 /* get the outer vlan if we're in switch-dependent mode */
7696
7697 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7698 mf_info->ext_id = (uint16_t) val;
7699
7700 mf_info->multi_vnics_mode = 1;
7701
7702 if (!VALID_OVLAN(mf_info->ext_id)) {
7703 PMD_DRV_LOG(NOTICE, sc, "Invalid VLAN (%d)", mf_info->ext_id);
7704 return 1;
7705 }
7706
7707 /* get the capabilities */
7708 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
7709 FUNC_MF_CFG_PROTOCOL_ISCSI) {
7710 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
7711 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)
7712 == FUNC_MF_CFG_PROTOCOL_FCOE) {
7713 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
7714 } else {
7715 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
7716 }
7717
7718 mf_info->vnics_per_port =
7719 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7720
7721 return 0;
7722 }
7723
bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc * sc)7724 static uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)
7725 {
7726 uint32_t retval = 0;
7727 uint32_t val;
7728
7729 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7730
7731 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
7732 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
7733 retval |= MF_PROTO_SUPPORT_ETHERNET;
7734 }
7735 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
7736 retval |= MF_PROTO_SUPPORT_ISCSI;
7737 }
7738 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
7739 retval |= MF_PROTO_SUPPORT_FCOE;
7740 }
7741 }
7742
7743 return retval;
7744 }
7745
bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc * sc)7746 static int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)
7747 {
7748 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7749 uint32_t val;
7750
7751 /*
7752 * There is no outer vlan if we're in switch-independent mode.
7753 * If the mac is valid then assume multi-function.
7754 */
7755
7756 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
7757
7758 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
7759
7760 mf_info->mf_protos_supported =
7761 bnx2x_get_shmem_ext_proto_support_flags(sc);
7762
7763 mf_info->vnics_per_port =
7764 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7765
7766 return 0;
7767 }
7768
bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc * sc)7769 static int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)
7770 {
7771 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7772 uint32_t e1hov_tag;
7773 uint32_t func_config;
7774 uint32_t niv_config;
7775
7776 mf_info->multi_vnics_mode = 1;
7777
7778 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7779 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7780 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
7781
7782 mf_info->ext_id =
7783 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
7784 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
7785
7786 mf_info->default_vlan =
7787 (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
7788 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
7789
7790 mf_info->niv_allowed_priorities =
7791 (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
7792 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
7793
7794 mf_info->niv_default_cos =
7795 (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
7796 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
7797
7798 mf_info->afex_vlan_mode =
7799 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
7800 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
7801
7802 mf_info->niv_mba_enabled =
7803 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
7804 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
7805
7806 mf_info->mf_protos_supported =
7807 bnx2x_get_shmem_ext_proto_support_flags(sc);
7808
7809 mf_info->vnics_per_port =
7810 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
7811
7812 return 0;
7813 }
7814
bnx2x_check_valid_mf_cfg(struct bnx2x_softc * sc)7815 static int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)
7816 {
7817 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7818 uint32_t mf_cfg1;
7819 uint32_t mf_cfg2;
7820 uint32_t ovlan1;
7821 uint32_t ovlan2;
7822 uint8_t i, j;
7823
7824 /* various MF mode sanity checks... */
7825
7826 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
7827 PMD_DRV_LOG(NOTICE, sc,
7828 "Enumerated function %d is marked as hidden",
7829 SC_PORT(sc));
7830 return 1;
7831 }
7832
7833 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
7834 PMD_DRV_LOG(NOTICE, sc, "vnics_per_port=%d multi_vnics_mode=%d",
7835 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
7836 return 1;
7837 }
7838
7839 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7840 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
7841 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
7842 PMD_DRV_LOG(NOTICE, sc, "mf_mode=SD vnic_id=%d ovlan=%d",
7843 SC_VN(sc), OVLAN(sc));
7844 return 1;
7845 }
7846
7847 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
7848 PMD_DRV_LOG(NOTICE, sc,
7849 "mf_mode=SD multi_vnics_mode=%d ovlan=%d",
7850 mf_info->multi_vnics_mode, OVLAN(sc));
7851 return 1;
7852 }
7853
7854 /*
7855 * Verify all functions are either MF or SF mode. If MF, make sure
7856 * sure that all non-hidden functions have a valid ovlan. If SF,
7857 * make sure that all non-hidden functions have an invalid ovlan.
7858 */
7859 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7860 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7861 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7862 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
7863 (((mf_info->multi_vnics_mode)
7864 && !VALID_OVLAN(ovlan1))
7865 || ((!mf_info->multi_vnics_mode)
7866 && VALID_OVLAN(ovlan1)))) {
7867 PMD_DRV_LOG(NOTICE, sc,
7868 "mf_mode=SD function %d MF config "
7869 "mismatch, multi_vnics_mode=%d ovlan=%d",
7870 i, mf_info->multi_vnics_mode,
7871 ovlan1);
7872 return 1;
7873 }
7874 }
7875
7876 /* Verify all funcs on the same port each have a different ovlan. */
7877 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
7878 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
7879 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
7880 /* iterate from the next function on the port to the max func */
7881 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
7882 mf_cfg2 =
7883 MFCFG_RD(sc, func_mf_config[j].config);
7884 ovlan2 =
7885 MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
7886 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)
7887 && VALID_OVLAN(ovlan1)
7888 && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)
7889 && VALID_OVLAN(ovlan2)
7890 && (ovlan1 == ovlan2)) {
7891 PMD_DRV_LOG(NOTICE, sc,
7892 "mf_mode=SD functions %d and %d "
7893 "have the same ovlan (%d)",
7894 i, j, ovlan1);
7895 return 1;
7896 }
7897 }
7898 }
7899 }
7900 /* MULTI_FUNCTION_SD */
7901 return 0;
7902 }
7903
bnx2x_get_mf_cfg_info(struct bnx2x_softc * sc)7904 static int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)
7905 {
7906 struct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;
7907 uint32_t val, mac_upper;
7908 uint8_t i, vnic;
7909
7910 /* initialize mf_info defaults */
7911 mf_info->vnics_per_port = 1;
7912 mf_info->multi_vnics_mode = FALSE;
7913 mf_info->path_has_ovlan = FALSE;
7914 mf_info->mf_mode = SINGLE_FUNCTION;
7915
7916 if (!CHIP_IS_MF_CAP(sc)) {
7917 return 0;
7918 }
7919
7920 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
7921 PMD_DRV_LOG(NOTICE, sc, "Invalid mf_cfg_base!");
7922 return 1;
7923 }
7924
7925 /* get the MF mode (switch dependent / independent / single-function) */
7926
7927 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
7928
7929 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {
7930 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
7931
7932 mac_upper =
7933 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7934
7935 /* check for legal upper mac bytes */
7936 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
7937 mf_info->mf_mode = MULTI_FUNCTION_SI;
7938 } else {
7939 PMD_DRV_LOG(NOTICE, sc,
7940 "Invalid config for Switch Independent mode");
7941 }
7942
7943 break;
7944
7945 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
7946 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
7947
7948 /* get outer vlan configuration */
7949 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
7950
7951 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
7952 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7953 mf_info->mf_mode = MULTI_FUNCTION_SD;
7954 } else {
7955 PMD_DRV_LOG(NOTICE, sc,
7956 "Invalid config for Switch Dependent mode");
7957 }
7958
7959 break;
7960
7961 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
7962
7963 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
7964 return 0;
7965
7966 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
7967
7968 /*
7969 * Mark MF mode as NIV if MCP version includes NPAR-SD support
7970 * and the MAC address is valid.
7971 */
7972 mac_upper =
7973 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
7974
7975 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
7976 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
7977 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
7978 } else {
7979 PMD_DRV_LOG(NOTICE, sc, "Invalid config for AFEX mode");
7980 }
7981
7982 break;
7983
7984 default:
7985
7986 PMD_DRV_LOG(NOTICE, sc, "Unknown MF mode (0x%08x)",
7987 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
7988
7989 return 1;
7990 }
7991
7992 /* set path mf_mode (which could be different than function mf_mode) */
7993 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
7994 mf_info->path_has_ovlan = TRUE;
7995 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
7996 /*
7997 * Decide on path multi vnics mode. If we're not in MF mode and in
7998 * 4-port mode, this is good enough to check vnic-0 of the other port
7999 * on the same path
8000 */
8001 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
8002 uint8_t other_port = !(PORT_ID(sc) & 1);
8003 uint8_t abs_func_other_port =
8004 (SC_PATH(sc) + (2 * other_port));
8005
8006 val =
8007 MFCFG_RD(sc,
8008 func_mf_config
8009 [abs_func_other_port].e1hov_tag);
8010
8011 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);
8012 }
8013 }
8014
8015 if (mf_info->mf_mode == SINGLE_FUNCTION) {
8016 /* invalid MF config */
8017 if (SC_VN(sc) >= 1) {
8018 PMD_DRV_LOG(NOTICE, sc, "VNIC ID >= 1 in SF mode");
8019 return 1;
8020 }
8021
8022 return 0;
8023 }
8024
8025 /* get the MF configuration */
8026 mf_info->mf_config[SC_VN(sc)] =
8027 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8028
8029 switch (mf_info->mf_mode) {
8030 case MULTI_FUNCTION_SD:
8031
8032 bnx2x_get_shmem_mf_cfg_info_sd(sc);
8033 break;
8034
8035 case MULTI_FUNCTION_SI:
8036
8037 bnx2x_get_shmem_mf_cfg_info_si(sc);
8038 break;
8039
8040 case MULTI_FUNCTION_AFEX:
8041
8042 bnx2x_get_shmem_mf_cfg_info_niv(sc);
8043 break;
8044
8045 default:
8046
8047 PMD_DRV_LOG(NOTICE, sc, "Get MF config failed (mf_mode=0x%08x)",
8048 mf_info->mf_mode);
8049 return 1;
8050 }
8051
8052 /* get the congestion management parameters */
8053
8054 vnic = 0;
8055 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
8056 /* get min/max bw */
8057 val = MFCFG_RD(sc, func_mf_config[i].config);
8058 mf_info->min_bw[vnic] =
8059 ((val & FUNC_MF_CFG_MIN_BW_MASK) >>
8060 FUNC_MF_CFG_MIN_BW_SHIFT);
8061 mf_info->max_bw[vnic] =
8062 ((val & FUNC_MF_CFG_MAX_BW_MASK) >>
8063 FUNC_MF_CFG_MAX_BW_SHIFT);
8064 vnic++;
8065 }
8066
8067 return bnx2x_check_valid_mf_cfg(sc);
8068 }
8069
bnx2x_get_shmem_info(struct bnx2x_softc * sc)8070 static int bnx2x_get_shmem_info(struct bnx2x_softc *sc)
8071 {
8072 int port;
8073 uint32_t mac_hi, mac_lo, val;
8074
8075 PMD_INIT_FUNC_TRACE(sc);
8076
8077 port = SC_PORT(sc);
8078 mac_hi = mac_lo = 0;
8079
8080 sc->link_params.sc = sc;
8081 sc->link_params.port = port;
8082
8083 /* get the hardware config info */
8084 sc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);
8085 sc->devinfo.hw_config2 =
8086 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
8087
8088 sc->link_params.hw_led_mode =
8089 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
8090 SHARED_HW_CFG_LED_MODE_SHIFT);
8091
8092 /* get the port feature config */
8093 sc->port.config =
8094 SHMEM_RD(sc, dev_info.port_feature_config[port].config);
8095
8096 /* get the link params */
8097 sc->link_params.speed_cap_mask[ELINK_INT_PHY] =
8098 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)
8099 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8100 sc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =
8101 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)
8102 & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
8103
8104 /* get the lane config */
8105 sc->link_params.lane_config =
8106 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
8107
8108 /* get the link config */
8109 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
8110 sc->port.link_config[ELINK_INT_PHY] = val;
8111 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
8112 sc->port.link_config[ELINK_EXT_PHY1] =
8113 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
8114
8115 /* get the override preemphasis flag and enable it or turn it off */
8116 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
8117 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
8118 sc->link_params.feature_config_flags |=
8119 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8120 } else {
8121 sc->link_params.feature_config_flags &=
8122 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8123 }
8124
8125 val = sc->devinfo.bc_ver >> 8;
8126 if (val < BNX2X_BC_VER) {
8127 /* for now only warn later we might need to enforce this */
8128 PMD_DRV_LOG(NOTICE, sc, "This driver needs bc_ver %X but found %X, please upgrade BC\n",
8129 BNX2X_BC_VER, val);
8130 }
8131 sc->link_params.feature_config_flags |=
8132 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8133 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY :
8134 0;
8135
8136 sc->link_params.feature_config_flags |=
8137 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8138 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8139 sc->link_params.feature_config_flags |=
8140 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
8141 ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
8142 sc->link_params.feature_config_flags |=
8143 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8144 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8145
8146 /* get the initial value of the link params */
8147 sc->link_params.multi_phy_config =
8148 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
8149
8150 /* get external phy info */
8151 sc->port.ext_phy_config =
8152 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
8153
8154 /* get the multifunction configuration */
8155 bnx2x_get_mf_cfg_info(sc);
8156
8157 /* get the mac address */
8158 if (IS_MF(sc)) {
8159 mac_hi =
8160 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
8161 mac_lo =
8162 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
8163 } else {
8164 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
8165 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
8166 }
8167
8168 if ((mac_lo == 0) && (mac_hi == 0)) {
8169 *sc->mac_addr_str = 0;
8170 PMD_DRV_LOG(NOTICE, sc, "No Ethernet address programmed!");
8171 } else {
8172 sc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);
8173 sc->link_params.mac_addr[1] = (uint8_t) (mac_hi);
8174 sc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);
8175 sc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);
8176 sc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);
8177 sc->link_params.mac_addr[5] = (uint8_t) (mac_lo);
8178 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
8179 RTE_ETHER_ADDR_PRT_FMT,
8180 sc->link_params.mac_addr[0],
8181 sc->link_params.mac_addr[1],
8182 sc->link_params.mac_addr[2],
8183 sc->link_params.mac_addr[3],
8184 sc->link_params.mac_addr[4],
8185 sc->link_params.mac_addr[5]);
8186 PMD_DRV_LOG(DEBUG, sc,
8187 "Ethernet address: %s", sc->mac_addr_str);
8188 }
8189
8190 return 0;
8191 }
8192
bnx2x_media_detect(struct bnx2x_softc * sc)8193 static void bnx2x_media_detect(struct bnx2x_softc *sc)
8194 {
8195 uint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);
8196 switch (sc->link_params.phy[phy_idx].media_type) {
8197 case ELINK_ETH_PHY_SFPP_10G_FIBER:
8198 case ELINK_ETH_PHY_SFP_1G_FIBER:
8199 case ELINK_ETH_PHY_XFP_FIBER:
8200 case ELINK_ETH_PHY_KR:
8201 case ELINK_ETH_PHY_CX4:
8202 PMD_DRV_LOG(INFO, sc, "Found 10GBase-CX4 media.");
8203 sc->media = IFM_10G_CX4;
8204 break;
8205 case ELINK_ETH_PHY_DA_TWINAX:
8206 PMD_DRV_LOG(INFO, sc, "Found 10Gb Twinax media.");
8207 sc->media = IFM_10G_TWINAX;
8208 break;
8209 case ELINK_ETH_PHY_BASE_T:
8210 PMD_DRV_LOG(INFO, sc, "Found 10GBase-T media.");
8211 sc->media = IFM_10G_T;
8212 break;
8213 case ELINK_ETH_PHY_NOT_PRESENT:
8214 PMD_DRV_LOG(INFO, sc, "Media not present.");
8215 sc->media = 0;
8216 break;
8217 case ELINK_ETH_PHY_UNSPECIFIED:
8218 default:
8219 PMD_DRV_LOG(INFO, sc, "Unknown media!");
8220 sc->media = 0;
8221 break;
8222 }
8223 }
8224
8225 #define GET_FIELD(value, fname) \
8226 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
8227 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8228 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8229
bnx2x_get_igu_cam_info(struct bnx2x_softc * sc)8230 static int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)
8231 {
8232 int pfid = SC_FUNC(sc);
8233 int igu_sb_id;
8234 uint32_t val;
8235 uint8_t fid, igu_sb_cnt = 0;
8236
8237 sc->igu_base_sb = 0xff;
8238
8239 if (CHIP_INT_MODE_IS_BC(sc)) {
8240 int vn = SC_VN(sc);
8241 igu_sb_cnt = sc->igu_sb_cnt;
8242 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
8243 FP_SB_MAX_E1x);
8244 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
8245 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
8246 return 0;
8247 }
8248
8249 /* IGU in normal mode - read CAM */
8250 for (igu_sb_id = 0;
8251 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {
8252 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8253 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
8254 continue;
8255 }
8256 fid = IGU_FID(val);
8257 if (fid & IGU_FID_ENCODE_IS_PF) {
8258 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
8259 continue;
8260 }
8261 if (IGU_VEC(val) == 0) {
8262 /* default status block */
8263 sc->igu_dsb_id = igu_sb_id;
8264 } else {
8265 if (sc->igu_base_sb == 0xff) {
8266 sc->igu_base_sb = igu_sb_id;
8267 }
8268 igu_sb_cnt++;
8269 }
8270 }
8271 }
8272
8273 /*
8274 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
8275 * that number of CAM entries will not be equal to the value advertised in
8276 * PCI. Driver should use the minimal value of both as the actual status
8277 * block count
8278 */
8279 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
8280
8281 if (igu_sb_cnt == 0) {
8282 PMD_DRV_LOG(ERR, sc, "CAM configuration error");
8283 return -1;
8284 }
8285
8286 return 0;
8287 }
8288
8289 /*
8290 * Gather various information from the device config space, the device itself,
8291 * shmem, and the user input.
8292 */
bnx2x_get_device_info(struct bnx2x_softc * sc)8293 static int bnx2x_get_device_info(struct bnx2x_softc *sc)
8294 {
8295 uint32_t val;
8296 int rc;
8297
8298 /* get the chip revision (chip metal comes from pci config space) */
8299 sc->devinfo.chip_id = sc->link_params.chip_id =
8300 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
8301 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
8302 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
8303 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
8304
8305 /* force 57811 according to MISC register */
8306 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
8307 if (CHIP_IS_57810(sc)) {
8308 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
8309 (sc->
8310 devinfo.chip_id & 0x0000ffff));
8311 } else if (CHIP_IS_57810_MF(sc)) {
8312 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
8313 (sc->
8314 devinfo.chip_id & 0x0000ffff));
8315 }
8316 sc->devinfo.chip_id |= 0x1;
8317 }
8318
8319 PMD_DRV_LOG(DEBUG, sc,
8320 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)",
8321 sc->devinfo.chip_id,
8322 ((sc->devinfo.chip_id >> 16) & 0xffff),
8323 ((sc->devinfo.chip_id >> 12) & 0xf),
8324 ((sc->devinfo.chip_id >> 4) & 0xff),
8325 ((sc->devinfo.chip_id >> 0) & 0xf));
8326
8327 val = (REG_RD(sc, 0x2874) & 0x55);
8328 if ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
8329 sc->flags |= BNX2X_ONE_PORT_FLAG;
8330 PMD_DRV_LOG(DEBUG, sc, "single port device");
8331 }
8332
8333 /* set the doorbell size */
8334 sc->doorbell_size = (1 << BNX2X_DB_SHIFT);
8335
8336 /* determine whether the device is in 2 port or 4 port mode */
8337 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1h */
8338 if (CHIP_IS_E2E3(sc)) {
8339 /*
8340 * Read port4mode_en_ovwr[0]:
8341 * If 1, four port mode is in port4mode_en_ovwr[1].
8342 * If 0, four port mode is in port4mode_en[0].
8343 */
8344 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
8345 if (val & 1) {
8346 val = ((val >> 1) & 1);
8347 } else {
8348 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
8349 }
8350
8351 sc->devinfo.chip_port_mode =
8352 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
8353
8354 PMD_DRV_LOG(DEBUG, sc, "Port mode = %s", (val) ? "4" : "2");
8355 }
8356
8357 /* get the function and path info for the device */
8358 bnx2x_get_function_num(sc);
8359
8360 /* get the shared memory base address */
8361 sc->devinfo.shmem_base =
8362 sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
8363 sc->devinfo.shmem2_base =
8364 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
8365 MISC_REG_GENERIC_CR_0));
8366
8367 if (!sc->devinfo.shmem_base) {
8368 /* this should ONLY prevent upcoming shmem reads */
8369 PMD_DRV_LOG(INFO, sc, "MCP not active");
8370 sc->flags |= BNX2X_NO_MCP_FLAG;
8371 return 0;
8372 }
8373
8374 /* make sure the shared memory contents are valid */
8375 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
8376 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
8377 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
8378 PMD_DRV_LOG(NOTICE, sc, "Invalid SHMEM validity signature: 0x%08x",
8379 val);
8380 return 0;
8381 }
8382
8383 /* get the bootcode version */
8384 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
8385 snprintf(sc->devinfo.bc_ver_str,
8386 sizeof(sc->devinfo.bc_ver_str),
8387 "%d.%d.%d",
8388 ((sc->devinfo.bc_ver >> 24) & 0xff),
8389 ((sc->devinfo.bc_ver >> 16) & 0xff),
8390 ((sc->devinfo.bc_ver >> 8) & 0xff));
8391 PMD_DRV_LOG(DEBUG, sc, "Bootcode version: %s", sc->devinfo.bc_ver_str);
8392
8393 /* get the bootcode shmem address */
8394 sc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);
8395
8396 /* clean indirect addresses as they're not used */
8397 pci_write_long(sc, PCICFG_GRC_ADDRESS, 0);
8398 if (IS_PF(sc)) {
8399 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
8400 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
8401 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
8402 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
8403 if (CHIP_IS_E1x(sc)) {
8404 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
8405 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
8406 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
8407 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
8408 }
8409 }
8410
8411 /* get the nvram size */
8412 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
8413 sc->devinfo.flash_size =
8414 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
8415
8416 bnx2x_set_power_state(sc, PCI_PM_D0);
8417 /* get various configuration parameters from shmem */
8418 bnx2x_get_shmem_info(sc);
8419
8420 /* initialize IGU parameters */
8421 if (CHIP_IS_E1x(sc)) {
8422 sc->devinfo.int_block = INT_BLOCK_HC;
8423 sc->igu_dsb_id = DEF_SB_IGU_ID;
8424 sc->igu_base_sb = 0;
8425 } else {
8426 sc->devinfo.int_block = INT_BLOCK_IGU;
8427
8428 /* do not allow device reset during IGU info processing */
8429 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8430
8431 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
8432
8433 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8434 int tout = 5000;
8435
8436 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
8437 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
8438 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
8439
8440 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8441 tout--;
8442 DELAY(1000);
8443 }
8444
8445 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
8446 PMD_DRV_LOG(NOTICE, sc,
8447 "FORCING IGU Normal Mode failed!!!");
8448 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8449 return -1;
8450 }
8451 }
8452
8453 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8454 PMD_DRV_LOG(DEBUG, sc, "IGU Backward Compatible Mode");
8455 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
8456 } else {
8457 PMD_DRV_LOG(DEBUG, sc, "IGU Normal Mode");
8458 }
8459
8460 rc = bnx2x_get_igu_cam_info(sc);
8461
8462 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
8463
8464 if (rc) {
8465 return rc;
8466 }
8467 }
8468
8469 /*
8470 * Get base FW non-default (fast path) status block ID. This value is
8471 * used to initialize the fw_sb_id saved on the fp/queue structure to
8472 * determine the id used by the FW.
8473 */
8474 if (CHIP_IS_E1x(sc)) {
8475 sc->base_fw_ndsb =
8476 ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
8477 } else {
8478 /*
8479 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
8480 * the same queue are indicated on the same IGU SB). So we prefer
8481 * FW and IGU SBs to be the same value.
8482 */
8483 sc->base_fw_ndsb = sc->igu_base_sb;
8484 }
8485
8486 elink_phy_probe(&sc->link_params);
8487
8488 return 0;
8489 }
8490
8491 static void
bnx2x_link_settings_supported(struct bnx2x_softc * sc,uint32_t switch_cfg)8492 bnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)
8493 {
8494 uint32_t cfg_size = 0;
8495 uint32_t idx;
8496 uint8_t port = SC_PORT(sc);
8497
8498 /* aggregation of supported attributes of all external phys */
8499 sc->port.supported[0] = 0;
8500 sc->port.supported[1] = 0;
8501
8502 switch (sc->link_params.num_phys) {
8503 case 1:
8504 sc->port.supported[0] =
8505 sc->link_params.phy[ELINK_INT_PHY].supported;
8506 cfg_size = 1;
8507 break;
8508 case 2:
8509 sc->port.supported[0] =
8510 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8511 cfg_size = 1;
8512 break;
8513 case 3:
8514 if (sc->link_params.multi_phy_config &
8515 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8516 sc->port.supported[1] =
8517 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8518 sc->port.supported[0] =
8519 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8520 } else {
8521 sc->port.supported[0] =
8522 sc->link_params.phy[ELINK_EXT_PHY1].supported;
8523 sc->port.supported[1] =
8524 sc->link_params.phy[ELINK_EXT_PHY2].supported;
8525 }
8526 cfg_size = 2;
8527 break;
8528 }
8529
8530 if (!(sc->port.supported[0] || sc->port.supported[1])) {
8531 PMD_DRV_LOG(ERR, sc,
8532 "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)",
8533 SHMEM_RD(sc,
8534 dev_info.port_hw_config
8535 [port].external_phy_config),
8536 SHMEM_RD(sc,
8537 dev_info.port_hw_config
8538 [port].external_phy_config2));
8539 return;
8540 }
8541
8542 if (CHIP_IS_E3(sc))
8543 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
8544 else {
8545 switch (switch_cfg) {
8546 case ELINK_SWITCH_CFG_1G:
8547 sc->port.phy_addr =
8548 REG_RD(sc,
8549 NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);
8550 break;
8551 case ELINK_SWITCH_CFG_10G:
8552 sc->port.phy_addr =
8553 REG_RD(sc,
8554 NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);
8555 break;
8556 default:
8557 PMD_DRV_LOG(ERR, sc,
8558 "Invalid switch config in"
8559 "link_config=0x%08x",
8560 sc->port.link_config[0]);
8561 return;
8562 }
8563 }
8564
8565 PMD_DRV_LOG(INFO, sc, "PHY addr 0x%08x", sc->port.phy_addr);
8566
8567 /* mask what we support according to speed_cap_mask per configuration */
8568 for (idx = 0; idx < cfg_size; idx++) {
8569 if (!(sc->link_params.speed_cap_mask[idx] &
8570 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
8571 sc->port.supported[idx] &=
8572 ~ELINK_SUPPORTED_10baseT_Half;
8573 }
8574
8575 if (!(sc->link_params.speed_cap_mask[idx] &
8576 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
8577 sc->port.supported[idx] &=
8578 ~ELINK_SUPPORTED_10baseT_Full;
8579 }
8580
8581 if (!(sc->link_params.speed_cap_mask[idx] &
8582 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
8583 sc->port.supported[idx] &=
8584 ~ELINK_SUPPORTED_100baseT_Half;
8585 }
8586
8587 if (!(sc->link_params.speed_cap_mask[idx] &
8588 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
8589 sc->port.supported[idx] &=
8590 ~ELINK_SUPPORTED_100baseT_Full;
8591 }
8592
8593 if (!(sc->link_params.speed_cap_mask[idx] &
8594 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
8595 sc->port.supported[idx] &=
8596 ~ELINK_SUPPORTED_1000baseT_Full;
8597 }
8598
8599 if (!(sc->link_params.speed_cap_mask[idx] &
8600 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
8601 sc->port.supported[idx] &=
8602 ~ELINK_SUPPORTED_2500baseX_Full;
8603 }
8604
8605 if (!(sc->link_params.speed_cap_mask[idx] &
8606 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8607 sc->port.supported[idx] &=
8608 ~ELINK_SUPPORTED_10000baseT_Full;
8609 }
8610
8611 if (!(sc->link_params.speed_cap_mask[idx] &
8612 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
8613 sc->port.supported[idx] &=
8614 ~ELINK_SUPPORTED_20000baseKR2_Full;
8615 }
8616 }
8617
8618 PMD_DRV_LOG(INFO, sc, "PHY supported 0=0x%08x 1=0x%08x",
8619 sc->port.supported[0], sc->port.supported[1]);
8620 }
8621
bnx2x_link_settings_requested(struct bnx2x_softc * sc)8622 static void bnx2x_link_settings_requested(struct bnx2x_softc *sc)
8623 {
8624 uint32_t link_config;
8625 uint32_t idx;
8626 uint32_t cfg_size = 0;
8627
8628 sc->port.advertising[0] = 0;
8629 sc->port.advertising[1] = 0;
8630
8631 switch (sc->link_params.num_phys) {
8632 case 1:
8633 case 2:
8634 cfg_size = 1;
8635 break;
8636 case 3:
8637 cfg_size = 2;
8638 break;
8639 }
8640
8641 for (idx = 0; idx < cfg_size; idx++) {
8642 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
8643 link_config = sc->port.link_config[idx];
8644
8645 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8646 case PORT_FEATURE_LINK_SPEED_AUTO:
8647 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
8648 sc->link_params.req_line_speed[idx] =
8649 ELINK_SPEED_AUTO_NEG;
8650 sc->port.advertising[idx] |=
8651 sc->port.supported[idx];
8652 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
8653 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)
8654 sc->port.advertising[idx] |=
8655 (ELINK_SUPPORTED_100baseT_Half |
8656 ELINK_SUPPORTED_100baseT_Full);
8657 } else {
8658 /* force 10G, no AN */
8659 sc->link_params.req_line_speed[idx] =
8660 ELINK_SPEED_10000;
8661 sc->port.advertising[idx] |=
8662 (ADVERTISED_10000baseT_Full |
8663 ADVERTISED_FIBRE);
8664 continue;
8665 }
8666 break;
8667
8668 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8669 if (sc->
8670 port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)
8671 {
8672 sc->link_params.req_line_speed[idx] =
8673 ELINK_SPEED_10;
8674 sc->port.advertising[idx] |=
8675 (ADVERTISED_10baseT_Full | ADVERTISED_TP);
8676 } else {
8677 PMD_DRV_LOG(ERR, sc,
8678 "Invalid NVRAM config link_config=0x%08x "
8679 "speed_cap_mask=0x%08x",
8680 link_config,
8681 sc->
8682 link_params.speed_cap_mask[idx]);
8683 return;
8684 }
8685 break;
8686
8687 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8688 if (sc->
8689 port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)
8690 {
8691 sc->link_params.req_line_speed[idx] =
8692 ELINK_SPEED_10;
8693 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8694 sc->port.advertising[idx] |=
8695 (ADVERTISED_10baseT_Half | ADVERTISED_TP);
8696 } else {
8697 PMD_DRV_LOG(ERR, sc,
8698 "Invalid NVRAM config link_config=0x%08x "
8699 "speed_cap_mask=0x%08x",
8700 link_config,
8701 sc->
8702 link_params.speed_cap_mask[idx]);
8703 return;
8704 }
8705 break;
8706
8707 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8708 if (sc->
8709 port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)
8710 {
8711 sc->link_params.req_line_speed[idx] =
8712 ELINK_SPEED_100;
8713 sc->port.advertising[idx] |=
8714 (ADVERTISED_100baseT_Full | ADVERTISED_TP);
8715 } else {
8716 PMD_DRV_LOG(ERR, sc,
8717 "Invalid NVRAM config link_config=0x%08x "
8718 "speed_cap_mask=0x%08x",
8719 link_config,
8720 sc->
8721 link_params.speed_cap_mask[idx]);
8722 return;
8723 }
8724 break;
8725
8726 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8727 if (sc->
8728 port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)
8729 {
8730 sc->link_params.req_line_speed[idx] =
8731 ELINK_SPEED_100;
8732 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
8733 sc->port.advertising[idx] |=
8734 (ADVERTISED_100baseT_Half | ADVERTISED_TP);
8735 } else {
8736 PMD_DRV_LOG(ERR, sc,
8737 "Invalid NVRAM config link_config=0x%08x "
8738 "speed_cap_mask=0x%08x",
8739 link_config,
8740 sc->
8741 link_params.speed_cap_mask[idx]);
8742 return;
8743 }
8744 break;
8745
8746 case PORT_FEATURE_LINK_SPEED_1G:
8747 if (sc->port.supported[idx] &
8748 ELINK_SUPPORTED_1000baseT_Full) {
8749 sc->link_params.req_line_speed[idx] =
8750 ELINK_SPEED_1000;
8751 sc->port.advertising[idx] |=
8752 (ADVERTISED_1000baseT_Full | ADVERTISED_TP);
8753 } else {
8754 PMD_DRV_LOG(ERR, sc,
8755 "Invalid NVRAM config link_config=0x%08x "
8756 "speed_cap_mask=0x%08x",
8757 link_config,
8758 sc->
8759 link_params.speed_cap_mask[idx]);
8760 return;
8761 }
8762 break;
8763
8764 case PORT_FEATURE_LINK_SPEED_2_5G:
8765 if (sc->port.supported[idx] &
8766 ELINK_SUPPORTED_2500baseX_Full) {
8767 sc->link_params.req_line_speed[idx] =
8768 ELINK_SPEED_2500;
8769 sc->port.advertising[idx] |=
8770 (ADVERTISED_2500baseX_Full | ADVERTISED_TP);
8771 } else {
8772 PMD_DRV_LOG(ERR, sc,
8773 "Invalid NVRAM config link_config=0x%08x "
8774 "speed_cap_mask=0x%08x",
8775 link_config,
8776 sc->
8777 link_params.speed_cap_mask[idx]);
8778 return;
8779 }
8780 break;
8781
8782 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8783 if (sc->port.supported[idx] &
8784 ELINK_SUPPORTED_10000baseT_Full) {
8785 sc->link_params.req_line_speed[idx] =
8786 ELINK_SPEED_10000;
8787 sc->port.advertising[idx] |=
8788 (ADVERTISED_10000baseT_Full |
8789 ADVERTISED_FIBRE);
8790 } else {
8791 PMD_DRV_LOG(ERR, sc,
8792 "Invalid NVRAM config link_config=0x%08x "
8793 "speed_cap_mask=0x%08x",
8794 link_config,
8795 sc->
8796 link_params.speed_cap_mask[idx]);
8797 return;
8798 }
8799 break;
8800
8801 case PORT_FEATURE_LINK_SPEED_20G:
8802 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
8803 break;
8804
8805 default:
8806 PMD_DRV_LOG(ERR, sc,
8807 "Invalid NVRAM config link_config=0x%08x "
8808 "speed_cap_mask=0x%08x", link_config,
8809 sc->link_params.speed_cap_mask[idx]);
8810 sc->link_params.req_line_speed[idx] =
8811 ELINK_SPEED_AUTO_NEG;
8812 sc->port.advertising[idx] = sc->port.supported[idx];
8813 break;
8814 }
8815
8816 sc->link_params.req_flow_ctrl[idx] =
8817 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
8818
8819 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
8820 if (!
8821 (sc->
8822 port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
8823 sc->link_params.req_flow_ctrl[idx] =
8824 ELINK_FLOW_CTRL_NONE;
8825 } else {
8826 bnx2x_set_requested_fc(sc);
8827 }
8828 }
8829 }
8830 }
8831
bnx2x_get_phy_info(struct bnx2x_softc * sc)8832 static void bnx2x_get_phy_info(struct bnx2x_softc *sc)
8833 {
8834 uint8_t port = SC_PORT(sc);
8835 uint32_t eee_mode;
8836
8837 PMD_INIT_FUNC_TRACE(sc);
8838
8839 /* shmem data already read in bnx2x_get_shmem_info() */
8840
8841 bnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);
8842 bnx2x_link_settings_requested(sc);
8843
8844 /* configure link feature according to nvram value */
8845 eee_mode =
8846 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))
8847 & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
8848 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
8849 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
8850 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
8851 ELINK_EEE_MODE_ENABLE_LPI |
8852 ELINK_EEE_MODE_OUTPUT_TIME);
8853 } else {
8854 sc->link_params.eee_mode = 0;
8855 }
8856
8857 /* get the media type */
8858 bnx2x_media_detect(sc);
8859 }
8860
bnx2x_set_modes_bitmap(struct bnx2x_softc * sc)8861 static void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)
8862 {
8863 uint32_t flags = MODE_ASIC | MODE_PORT2;
8864
8865 if (CHIP_IS_E2(sc)) {
8866 flags |= MODE_E2;
8867 } else if (CHIP_IS_E3(sc)) {
8868 flags |= MODE_E3;
8869 if (CHIP_REV(sc) == CHIP_REV_Ax) {
8870 flags |= MODE_E3_A0;
8871 } else { /*if (CHIP_REV(sc) == CHIP_REV_Bx) */
8872
8873 flags |= MODE_E3_B0 | MODE_COS3;
8874 }
8875 }
8876
8877 if (IS_MF(sc)) {
8878 flags |= MODE_MF;
8879 switch (sc->devinfo.mf_info.mf_mode) {
8880 case MULTI_FUNCTION_SD:
8881 flags |= MODE_MF_SD;
8882 break;
8883 case MULTI_FUNCTION_SI:
8884 flags |= MODE_MF_SI;
8885 break;
8886 case MULTI_FUNCTION_AFEX:
8887 flags |= MODE_MF_AFEX;
8888 break;
8889 }
8890 } else {
8891 flags |= MODE_SF;
8892 }
8893
8894 #if defined(__LITTLE_ENDIAN)
8895 flags |= MODE_LITTLE_ENDIAN;
8896 #else /* __BIG_ENDIAN */
8897 flags |= MODE_BIG_ENDIAN;
8898 #endif
8899
8900 INIT_MODE_FLAGS(sc) = flags;
8901 }
8902
bnx2x_alloc_hsi_mem(struct bnx2x_softc * sc)8903 int bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)
8904 {
8905 struct bnx2x_fastpath *fp;
8906 char buf[32];
8907 uint32_t i;
8908
8909 if (IS_PF(sc)) {
8910 /************************/
8911 /* DEFAULT STATUS BLOCK */
8912 /************************/
8913
8914 if (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),
8915 &sc->def_sb_dma, "def_sb",
8916 RTE_CACHE_LINE_SIZE) != 0) {
8917 return -1;
8918 }
8919
8920 sc->def_sb =
8921 (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
8922 /***************/
8923 /* EVENT QUEUE */
8924 /***************/
8925
8926 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8927 &sc->eq_dma, "ev_queue",
8928 RTE_CACHE_LINE_SIZE) != 0) {
8929 sc->def_sb = NULL;
8930 return -1;
8931 }
8932
8933 sc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;
8934
8935 /*************/
8936 /* SLOW PATH */
8937 /*************/
8938
8939 if (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),
8940 &sc->sp_dma, "sp",
8941 RTE_CACHE_LINE_SIZE) != 0) {
8942 sc->eq = NULL;
8943 sc->def_sb = NULL;
8944 return -1;
8945 }
8946
8947 sc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;
8948
8949 /*******************/
8950 /* SLOW PATH QUEUE */
8951 /*******************/
8952
8953 if (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,
8954 &sc->spq_dma, "sp_queue",
8955 RTE_CACHE_LINE_SIZE) != 0) {
8956 sc->sp = NULL;
8957 sc->eq = NULL;
8958 sc->def_sb = NULL;
8959 return -1;
8960 }
8961
8962 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
8963
8964 /***************************/
8965 /* FW DECOMPRESSION BUFFER */
8966 /***************************/
8967
8968 if (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
8969 "fw_buf", RTE_CACHE_LINE_SIZE) != 0) {
8970 sc->spq = NULL;
8971 sc->sp = NULL;
8972 sc->eq = NULL;
8973 sc->def_sb = NULL;
8974 return -1;
8975 }
8976
8977 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
8978 }
8979
8980 /*************/
8981 /* FASTPATHS */
8982 /*************/
8983
8984 /* allocate DMA memory for each fastpath structure */
8985 for (i = 0; i < sc->num_queues; i++) {
8986 fp = &sc->fp[i];
8987 fp->sc = sc;
8988 fp->index = i;
8989
8990 /*******************/
8991 /* FP STATUS BLOCK */
8992 /*******************/
8993
8994 snprintf(buf, sizeof(buf), "fp_%d_sb", i);
8995 if (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),
8996 &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {
8997 PMD_DRV_LOG(NOTICE, sc, "Failed to alloc %s", buf);
8998 return -1;
8999 } else {
9000 if (CHIP_IS_E2E3(sc)) {
9001 fp->status_block.e2_sb =
9002 (struct host_hc_status_block_e2 *)
9003 fp->sb_dma.vaddr;
9004 } else {
9005 fp->status_block.e1x_sb =
9006 (struct host_hc_status_block_e1x *)
9007 fp->sb_dma.vaddr;
9008 }
9009 }
9010 }
9011
9012 return 0;
9013 }
9014
bnx2x_free_hsi_mem(struct bnx2x_softc * sc)9015 void bnx2x_free_hsi_mem(struct bnx2x_softc *sc)
9016 {
9017 struct bnx2x_fastpath *fp;
9018 int i;
9019
9020 for (i = 0; i < sc->num_queues; i++) {
9021 fp = &sc->fp[i];
9022
9023 /*******************/
9024 /* FP STATUS BLOCK */
9025 /*******************/
9026
9027 memset(&fp->status_block, 0, sizeof(fp->status_block));
9028 bnx2x_dma_free(&fp->sb_dma);
9029 }
9030
9031 if (IS_PF(sc)) {
9032 /***************************/
9033 /* FW DECOMPRESSION BUFFER */
9034 /***************************/
9035
9036 bnx2x_dma_free(&sc->gz_buf_dma);
9037 sc->gz_buf = NULL;
9038
9039 /*******************/
9040 /* SLOW PATH QUEUE */
9041 /*******************/
9042
9043 bnx2x_dma_free(&sc->spq_dma);
9044 sc->spq = NULL;
9045
9046 /*************/
9047 /* SLOW PATH */
9048 /*************/
9049
9050 bnx2x_dma_free(&sc->sp_dma);
9051 sc->sp = NULL;
9052
9053 /***************/
9054 /* EVENT QUEUE */
9055 /***************/
9056
9057 bnx2x_dma_free(&sc->eq_dma);
9058 sc->eq = NULL;
9059
9060 /************************/
9061 /* DEFAULT STATUS BLOCK */
9062 /************************/
9063
9064 bnx2x_dma_free(&sc->def_sb_dma);
9065 sc->def_sb = NULL;
9066 }
9067 }
9068
9069 /*
9070 * Previous driver DMAE transaction may have occurred when pre-boot stage
9071 * ended and boot began. This would invalidate the addresses of the
9072 * transaction, resulting in was-error bit set in the PCI causing all
9073 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
9074 * the interrupt which detected this from the pglueb and the was-done bit
9075 */
bnx2x_prev_interrupted_dmae(struct bnx2x_softc * sc)9076 static void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)
9077 {
9078 uint32_t val;
9079
9080 if (!CHIP_IS_E1x(sc)) {
9081 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
9082 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9083 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9084 1 << SC_FUNC(sc));
9085 }
9086 }
9087 }
9088
bnx2x_prev_mcp_done(struct bnx2x_softc * sc)9089 static int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)
9090 {
9091 uint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
9092 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9093 if (!rc) {
9094 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9095 return -1;
9096 }
9097
9098 return 0;
9099 }
9100
bnx2x_prev_path_get_entry(struct bnx2x_softc * sc)9101 static struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)
9102 {
9103 struct bnx2x_prev_list_node *tmp;
9104
9105 LIST_FOREACH(tmp, &bnx2x_prev_list, node) {
9106 if ((sc->pcie_bus == tmp->bus) &&
9107 (sc->pcie_device == tmp->slot) &&
9108 (SC_PATH(sc) == tmp->path)) {
9109 return tmp;
9110 }
9111 }
9112
9113 return NULL;
9114 }
9115
bnx2x_prev_is_path_marked(struct bnx2x_softc * sc)9116 static uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)
9117 {
9118 struct bnx2x_prev_list_node *tmp;
9119 int rc = FALSE;
9120
9121 rte_spinlock_lock(&bnx2x_prev_mtx);
9122
9123 tmp = bnx2x_prev_path_get_entry(sc);
9124 if (tmp) {
9125 if (tmp->aer) {
9126 PMD_DRV_LOG(DEBUG, sc,
9127 "Path %d/%d/%d was marked by AER",
9128 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9129 } else {
9130 rc = TRUE;
9131 PMD_DRV_LOG(DEBUG, sc,
9132 "Path %d/%d/%d was already cleaned from previous drivers",
9133 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9134 }
9135 }
9136
9137 rte_spinlock_unlock(&bnx2x_prev_mtx);
9138
9139 return rc;
9140 }
9141
bnx2x_prev_mark_path(struct bnx2x_softc * sc,uint8_t after_undi)9142 static int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)
9143 {
9144 struct bnx2x_prev_list_node *tmp;
9145
9146 rte_spinlock_lock(&bnx2x_prev_mtx);
9147
9148 /* Check whether the entry for this path already exists */
9149 tmp = bnx2x_prev_path_get_entry(sc);
9150 if (tmp) {
9151 if (!tmp->aer) {
9152 PMD_DRV_LOG(DEBUG, sc,
9153 "Re-marking AER in path %d/%d/%d",
9154 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9155 } else {
9156 PMD_DRV_LOG(DEBUG, sc,
9157 "Removing AER indication from path %d/%d/%d",
9158 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
9159 tmp->aer = 0;
9160 }
9161
9162 rte_spinlock_unlock(&bnx2x_prev_mtx);
9163 return 0;
9164 }
9165
9166 rte_spinlock_unlock(&bnx2x_prev_mtx);
9167
9168 /* Create an entry for this path and add it */
9169 tmp = rte_malloc("", sizeof(struct bnx2x_prev_list_node),
9170 RTE_CACHE_LINE_SIZE);
9171 if (!tmp) {
9172 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate 'bnx2x_prev_list_node'");
9173 return -1;
9174 }
9175
9176 tmp->bus = sc->pcie_bus;
9177 tmp->slot = sc->pcie_device;
9178 tmp->path = SC_PATH(sc);
9179 tmp->aer = 0;
9180 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
9181
9182 rte_spinlock_lock(&bnx2x_prev_mtx);
9183
9184 LIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);
9185
9186 rte_spinlock_unlock(&bnx2x_prev_mtx);
9187
9188 return 0;
9189 }
9190
bnx2x_do_flr(struct bnx2x_softc * sc)9191 static int bnx2x_do_flr(struct bnx2x_softc *sc)
9192 {
9193 int i;
9194
9195 /* only E2 and onwards support FLR */
9196 if (CHIP_IS_E1x(sc)) {
9197 PMD_DRV_LOG(WARNING, sc, "FLR not supported in E1H");
9198 return -1;
9199 }
9200
9201 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9202 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9203 PMD_DRV_LOG(WARNING, sc,
9204 "FLR not supported by BC_VER: 0x%08x",
9205 sc->devinfo.bc_ver);
9206 return -1;
9207 }
9208
9209 /* Wait for Transaction Pending bit clean */
9210 for (i = 0; i < 4; i++) {
9211 if (i) {
9212 DELAY(((1 << (i - 1)) * 100) * 1000);
9213 }
9214
9215 if (!bnx2x_is_pcie_pending(sc)) {
9216 goto clear;
9217 }
9218 }
9219
9220 PMD_DRV_LOG(NOTICE, sc, "PCIE transaction is not cleared, "
9221 "proceeding with reset anyway");
9222
9223 clear:
9224 bnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
9225
9226 return 0;
9227 }
9228
9229 struct bnx2x_mac_vals {
9230 uint32_t xmac_addr;
9231 uint32_t xmac_val;
9232 uint32_t emac_addr;
9233 uint32_t emac_val;
9234 uint32_t umac_addr;
9235 uint32_t umac_val;
9236 uint32_t bmac_addr;
9237 uint32_t bmac_val[2];
9238 };
9239
9240 static void
bnx2x_prev_unload_close_mac(struct bnx2x_softc * sc,struct bnx2x_mac_vals * vals)9241 bnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)
9242 {
9243 uint32_t val, base_addr, offset, mask, reset_reg;
9244 uint8_t mac_stopped = FALSE;
9245 uint8_t port = SC_PORT(sc);
9246 uint32_t wb_data[2];
9247
9248 /* reset addresses as they also mark which values were changed */
9249 vals->bmac_addr = 0;
9250 vals->umac_addr = 0;
9251 vals->xmac_addr = 0;
9252 vals->emac_addr = 0;
9253
9254 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
9255
9256 if (!CHIP_IS_E3(sc)) {
9257 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9258 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9259 if ((mask & reset_reg) && val) {
9260 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
9261 : NIG_REG_INGRESS_BMAC0_MEM;
9262 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
9263 : BIGMAC_REGISTER_BMAC_CONTROL;
9264
9265 /*
9266 * use rd/wr since we cannot use dmae. This is safe
9267 * since MCP won't access the bus due to the request
9268 * to unload, and no function on the path can be
9269 * loaded at this time.
9270 */
9271 wb_data[0] = REG_RD(sc, base_addr + offset);
9272 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
9273 vals->bmac_addr = base_addr + offset;
9274 vals->bmac_val[0] = wb_data[0];
9275 vals->bmac_val[1] = wb_data[1];
9276 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
9277 REG_WR(sc, vals->bmac_addr, wb_data[0]);
9278 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
9279 }
9280
9281 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;
9282 vals->emac_val = REG_RD(sc, vals->emac_addr);
9283 REG_WR(sc, vals->emac_addr, 0);
9284 mac_stopped = TRUE;
9285 } else {
9286 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9287 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9288 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
9289 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9290 val & ~(1 << 1));
9291 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,
9292 val | (1 << 1));
9293 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9294 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
9295 REG_WR(sc, vals->xmac_addr, 0);
9296 mac_stopped = TRUE;
9297 }
9298
9299 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9300 if (mask & reset_reg) {
9301 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9302 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9303 vals->umac_val = REG_RD(sc, vals->umac_addr);
9304 REG_WR(sc, vals->umac_addr, 0);
9305 mac_stopped = TRUE;
9306 }
9307 }
9308
9309 if (mac_stopped) {
9310 DELAY(20000);
9311 }
9312 }
9313
9314 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9315 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9316 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9317 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9318
9319 static void
bnx2x_prev_unload_undi_inc(struct bnx2x_softc * sc,uint8_t port,uint8_t inc)9320 bnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)
9321 {
9322 uint16_t rcq, bd;
9323 uint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));
9324
9325 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9326 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9327
9328 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9329 REG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9330 }
9331
bnx2x_prev_unload_common(struct bnx2x_softc * sc)9332 static int bnx2x_prev_unload_common(struct bnx2x_softc *sc)
9333 {
9334 uint32_t reset_reg, tmp_reg = 0, rc;
9335 uint8_t prev_undi = FALSE;
9336 struct bnx2x_mac_vals mac_vals;
9337 uint32_t timer_count = 1000;
9338 uint32_t prev_brb;
9339
9340 /*
9341 * It is possible a previous function received 'common' answer,
9342 * but hasn't loaded yet, therefore creating a scenario of
9343 * multiple functions receiving 'common' on the same path.
9344 */
9345 memset(&mac_vals, 0, sizeof(mac_vals));
9346
9347 if (bnx2x_prev_is_path_marked(sc)) {
9348 return bnx2x_prev_mcp_done(sc);
9349 }
9350
9351 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
9352
9353 /* Reset should be performed after BRB is emptied */
9354 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9355 /* Close the MAC Rx to prevent BRB from filling up */
9356 bnx2x_prev_unload_close_mac(sc, &mac_vals);
9357
9358 /* close LLH filters towards the BRB */
9359 elink_set_rx_filter(&sc->link_params, 0);
9360
9361 /*
9362 * Check if the UNDI driver was previously loaded.
9363 * UNDI driver initializes CID offset for normal bell to 0x7
9364 */
9365 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9366 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
9367 if (tmp_reg == 0x7) {
9368 PMD_DRV_LOG(DEBUG, sc, "UNDI previously loaded");
9369 prev_undi = TRUE;
9370 /* clear the UNDI indication */
9371 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
9372 /* clear possible idle check errors */
9373 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
9374 }
9375 }
9376
9377 /* wait until BRB is empty */
9378 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9379 while (timer_count) {
9380 prev_brb = tmp_reg;
9381
9382 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
9383 if (!tmp_reg) {
9384 break;
9385 }
9386
9387 PMD_DRV_LOG(DEBUG, sc, "BRB still has 0x%08x", tmp_reg);
9388
9389 /* reset timer as long as BRB actually gets emptied */
9390 if (prev_brb > tmp_reg) {
9391 timer_count = 1000;
9392 } else {
9393 timer_count--;
9394 }
9395
9396 /* If UNDI resides in memory, manually increment it */
9397 if (prev_undi) {
9398 bnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
9399 }
9400
9401 DELAY(10);
9402 }
9403
9404 if (!timer_count) {
9405 PMD_DRV_LOG(NOTICE, sc, "Failed to empty BRB");
9406 }
9407 }
9408
9409 /* No packets are in the pipeline, path is ready for reset */
9410 bnx2x_reset_common(sc);
9411
9412 if (mac_vals.xmac_addr) {
9413 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
9414 }
9415 if (mac_vals.umac_addr) {
9416 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
9417 }
9418 if (mac_vals.emac_addr) {
9419 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
9420 }
9421 if (mac_vals.bmac_addr) {
9422 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9423 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9424 }
9425
9426 rc = bnx2x_prev_mark_path(sc, prev_undi);
9427 if (rc) {
9428 bnx2x_prev_mcp_done(sc);
9429 return rc;
9430 }
9431
9432 return bnx2x_prev_mcp_done(sc);
9433 }
9434
bnx2x_prev_unload_uncommon(struct bnx2x_softc * sc)9435 static int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)
9436 {
9437 int rc;
9438
9439 /* Test if previous unload process was already finished for this path */
9440 if (bnx2x_prev_is_path_marked(sc)) {
9441 return bnx2x_prev_mcp_done(sc);
9442 }
9443
9444 /*
9445 * If function has FLR capabilities, and existing FW version matches
9446 * the one required, then FLR will be sufficient to clean any residue
9447 * left by previous driver
9448 */
9449 rc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9450 if (!rc) {
9451 /* fw version is good */
9452 rc = bnx2x_do_flr(sc);
9453 }
9454
9455 if (!rc) {
9456 /* FLR was performed */
9457 return 0;
9458 }
9459
9460 PMD_DRV_LOG(INFO, sc, "Could not FLR");
9461
9462 /* Close the MCP request, return failure */
9463 rc = bnx2x_prev_mcp_done(sc);
9464 if (!rc) {
9465 rc = BNX2X_PREV_WAIT_NEEDED;
9466 }
9467
9468 return rc;
9469 }
9470
bnx2x_prev_unload(struct bnx2x_softc * sc)9471 static int bnx2x_prev_unload(struct bnx2x_softc *sc)
9472 {
9473 int time_counter = 10;
9474 uint32_t fw, hw_lock_reg, hw_lock_val;
9475 uint32_t rc = 0;
9476
9477 PMD_INIT_FUNC_TRACE(sc);
9478
9479 /*
9480 * Clear HW from errors which may have resulted from an interrupted
9481 * DMAE transaction.
9482 */
9483 bnx2x_prev_interrupted_dmae(sc);
9484
9485 /* Release previously held locks */
9486 hw_lock_reg = (SC_FUNC(sc) <= 5) ?
9487 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
9488 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
9489
9490 hw_lock_val = (REG_RD(sc, hw_lock_reg));
9491 if (hw_lock_val) {
9492 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9493 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held NVRAM lock\n");
9494 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
9495 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
9496 }
9497 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held HW lock\n");
9498 REG_WR(sc, hw_lock_reg, 0xffffffff);
9499 }
9500
9501 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
9502 PMD_DRV_LOG(DEBUG, sc, "Releasing previously held ALR\n");
9503 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
9504 }
9505
9506 do {
9507 /* Lock MCP using an unload request */
9508 fw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9509 if (!fw) {
9510 PMD_DRV_LOG(NOTICE, sc, "MCP response failure, aborting");
9511 rc = -1;
9512 break;
9513 }
9514
9515 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9516 rc = bnx2x_prev_unload_common(sc);
9517 break;
9518 }
9519
9520 /* non-common reply from MCP might require looping */
9521 rc = bnx2x_prev_unload_uncommon(sc);
9522 if (rc != BNX2X_PREV_WAIT_NEEDED) {
9523 break;
9524 }
9525
9526 DELAY(20000);
9527 } while (--time_counter);
9528
9529 if (!time_counter || rc) {
9530 PMD_DRV_LOG(NOTICE, sc, "Failed to unload previous driver!");
9531 rc = -1;
9532 }
9533
9534 return rc;
9535 }
9536
9537 static void
bnx2x_dcbx_set_state(struct bnx2x_softc * sc,uint8_t dcb_on,uint32_t dcbx_enabled)9538 bnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)
9539 {
9540 if (!CHIP_IS_E1x(sc)) {
9541 sc->dcb_state = dcb_on;
9542 sc->dcbx_enabled = dcbx_enabled;
9543 } else {
9544 sc->dcb_state = FALSE;
9545 sc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
9546 }
9547 PMD_DRV_LOG(DEBUG, sc,
9548 "DCB state [%s:%s]",
9549 dcb_on ? "ON" : "OFF",
9550 (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? "user-mode" :
9551 (dcbx_enabled ==
9552 BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static"
9553 : (dcbx_enabled ==
9554 BNX2X_DCBX_ENABLED_ON_NEG_ON) ?
9555 "on-chip with negotiation" : "invalid");
9556 }
9557
bnx2x_set_qm_cid_count(struct bnx2x_softc * sc)9558 static int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)
9559 {
9560 int cid_count = BNX2X_L2_MAX_CID(sc);
9561
9562 if (CNIC_SUPPORT(sc)) {
9563 cid_count += CNIC_CID_MAX;
9564 }
9565
9566 return roundup(cid_count, QM_CID_ROUND);
9567 }
9568
bnx2x_init_multi_cos(struct bnx2x_softc * sc)9569 static void bnx2x_init_multi_cos(struct bnx2x_softc *sc)
9570 {
9571 int pri, cos;
9572
9573 uint32_t pri_map = 0;
9574
9575 for (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {
9576 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
9577 if (cos < sc->max_cos) {
9578 sc->prio_to_cos[pri] = cos;
9579 } else {
9580 PMD_DRV_LOG(WARNING, sc,
9581 "Invalid COS %d for priority %d "
9582 "(max COS is %d), setting to 0", cos, pri,
9583 (sc->max_cos - 1));
9584 sc->prio_to_cos[pri] = 0;
9585 }
9586 }
9587 }
9588
bnx2x_pci_get_caps(struct bnx2x_softc * sc)9589 static int bnx2x_pci_get_caps(struct bnx2x_softc *sc)
9590 {
9591 struct {
9592 uint8_t id;
9593 uint8_t next;
9594 } pci_cap;
9595 uint16_t status;
9596 struct bnx2x_pci_cap *cap;
9597
9598 cap = sc->pci_caps = rte_zmalloc("caps", sizeof(struct bnx2x_pci_cap),
9599 RTE_CACHE_LINE_SIZE);
9600 if (!cap) {
9601 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9602 return -ENOMEM;
9603 }
9604
9605 #ifndef RTE_EXEC_ENV_FREEBSD
9606 pci_read(sc, PCI_STATUS, &status, 2);
9607 if (!(status & PCI_STATUS_CAP_LIST)) {
9608 #else
9609 pci_read(sc, PCIR_STATUS, &status, 2);
9610 if (!(status & PCIM_STATUS_CAPPRESENT)) {
9611 #endif
9612 PMD_DRV_LOG(NOTICE, sc, "PCIe capability reading failed");
9613 return -1;
9614 }
9615
9616 #ifndef RTE_EXEC_ENV_FREEBSD
9617 pci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);
9618 #else
9619 pci_read(sc, PCIR_CAP_PTR, &pci_cap.next, 1);
9620 #endif
9621 while (pci_cap.next) {
9622 cap->addr = pci_cap.next & ~3;
9623 pci_read(sc, pci_cap.next & ~3, &pci_cap, 2);
9624 if (pci_cap.id == 0xff)
9625 break;
9626 cap->id = pci_cap.id;
9627 cap->type = BNX2X_PCI_CAP;
9628 cap->next = rte_zmalloc("pci_cap",
9629 sizeof(struct bnx2x_pci_cap),
9630 RTE_CACHE_LINE_SIZE);
9631 if (!cap->next) {
9632 PMD_DRV_LOG(NOTICE, sc, "Failed to allocate memory");
9633 return -ENOMEM;
9634 }
9635 cap = cap->next;
9636 }
9637
9638 return 0;
9639 }
9640
9641 static void bnx2x_init_rte(struct bnx2x_softc *sc)
9642 {
9643 if (IS_VF(sc)) {
9644 sc->max_tx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9645 sc->igu_sb_cnt);
9646 sc->max_rx_queues = min(BNX2X_VF_MAX_QUEUES_PER_VF,
9647 sc->igu_sb_cnt);
9648 } else {
9649 sc->max_rx_queues = BNX2X_MAX_RSS_COUNT(sc);
9650 sc->max_tx_queues = sc->max_rx_queues;
9651 }
9652 }
9653
9654 #define FW_HEADER_LEN 104
9655 #define FW_NAME_57711 "/lib/firmware/bnx2x/bnx2x-e1h-7.13.11.0.fw"
9656 #define FW_NAME_57810 "/lib/firmware/bnx2x/bnx2x-e2-7.13.11.0.fw"
9657
9658 void bnx2x_load_firmware(struct bnx2x_softc *sc)
9659 {
9660 const char *fwname;
9661 void *buf;
9662 size_t bufsz;
9663
9664 fwname = sc->devinfo.device_id == CHIP_NUM_57711
9665 ? FW_NAME_57711 : FW_NAME_57810;
9666 if (rte_firmware_read(fwname, &buf, &bufsz) != 0) {
9667 PMD_DRV_LOG(NOTICE, sc, "Can't open firmware file");
9668 return;
9669 }
9670
9671 sc->firmware = rte_zmalloc("bnx2x_fw", bufsz, RTE_CACHE_LINE_SIZE);
9672 if (!sc->firmware) {
9673 PMD_DRV_LOG(NOTICE, sc, "Can't allocate memory for firmware");
9674 goto out;
9675 }
9676
9677 sc->fw_len = bufsz;
9678 if (sc->fw_len < FW_HEADER_LEN) {
9679 PMD_DRV_LOG(NOTICE, sc,
9680 "Invalid fw size: %" PRIu64, sc->fw_len);
9681 goto out;
9682 }
9683
9684 memcpy(sc->firmware, buf, sc->fw_len);
9685 PMD_DRV_LOG(DEBUG, sc, "fw_len = %" PRIu64, sc->fw_len);
9686 out:
9687 free(buf);
9688 }
9689
9690 static void
9691 bnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)
9692 {
9693 uint32_t *src = (uint32_t *) data;
9694 uint32_t i, j, tmp;
9695
9696 for (i = 0, j = 0; i < len / 8; ++i, j += 2) {
9697 tmp = rte_be_to_cpu_32(src[j]);
9698 dst[i].op = (tmp >> 24) & 0xFF;
9699 dst[i].offset = tmp & 0xFFFFFF;
9700 dst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);
9701 }
9702 }
9703
9704 static void
9705 bnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)
9706 {
9707 uint16_t *src = (uint16_t *) data;
9708 uint32_t i;
9709
9710 for (i = 0; i < len / 2; ++i)
9711 dst[i] = rte_be_to_cpu_16(src[i]);
9712 }
9713
9714 static void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)
9715 {
9716 uint32_t *src = (uint32_t *) data;
9717 uint32_t i;
9718
9719 for (i = 0; i < len / 4; ++i)
9720 dst[i] = rte_be_to_cpu_32(src[i]);
9721 }
9722
9723 static void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)
9724 {
9725 uint32_t *src = (uint32_t *) data;
9726 uint32_t i, j, tmp;
9727
9728 for (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {
9729 dst[i].base = rte_be_to_cpu_32(src[j++]);
9730 tmp = rte_be_to_cpu_32(src[j]);
9731 dst[i].m1 = (tmp >> 16) & 0xFFFF;
9732 dst[i].m2 = tmp & 0xFFFF;
9733 ++j;
9734 tmp = rte_be_to_cpu_32(src[j]);
9735 dst[i].m3 = (tmp >> 16) & 0xFFFF;
9736 dst[i].size = tmp & 0xFFFF;
9737 }
9738 }
9739
9740 /*
9741 * Device attach function.
9742 *
9743 * Allocates device resources, performs secondary chip identification, and
9744 * initializes driver instance variables. This function is called from driver
9745 * load after a successful probe.
9746 *
9747 * Returns:
9748 * 0 = Success, >0 = Failure
9749 */
9750 int bnx2x_attach(struct bnx2x_softc *sc)
9751 {
9752 int rc;
9753
9754 PMD_DRV_LOG(DEBUG, sc, "Starting attach...");
9755
9756 rc = bnx2x_pci_get_caps(sc);
9757 if (rc) {
9758 PMD_DRV_LOG(NOTICE, sc, "PCIe caps reading was failed");
9759 return rc;
9760 }
9761
9762 sc->state = BNX2X_STATE_CLOSED;
9763
9764 pci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);
9765
9766 sc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
9767
9768 /* get PCI capabilities */
9769 bnx2x_probe_pci_caps(sc);
9770
9771 if (sc->devinfo.pcie_msix_cap_reg != 0) {
9772 uint32_t val;
9773 pci_read(sc,
9774 (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,
9775 2);
9776 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
9777 } else {
9778 sc->igu_sb_cnt = 1;
9779 }
9780
9781 /* Init RTE stuff */
9782 bnx2x_init_rte(sc);
9783
9784 if (IS_PF(sc)) {
9785 /* Enable internal target-read (in case we are probed after PF
9786 * FLR). Must be done prior to any BAR read access. Only for
9787 * 57712 and up
9788 */
9789 if (!CHIP_IS_E1x(sc)) {
9790 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,
9791 1);
9792 DELAY(200000);
9793 }
9794
9795 /* get device info and set params */
9796 if (bnx2x_get_device_info(sc) != 0) {
9797 PMD_DRV_LOG(NOTICE, sc, "getting device info");
9798 return -ENXIO;
9799 }
9800
9801 /* get phy settings from shmem and 'and' against admin settings */
9802 bnx2x_get_phy_info(sc);
9803 } else {
9804 /* Left mac of VF unfilled, PF should set it for VF */
9805 memset(sc->link_params.mac_addr, 0, RTE_ETHER_ADDR_LEN);
9806 }
9807
9808 sc->wol = 0;
9809
9810 /* set the default MTU (changed via ifconfig) */
9811 sc->mtu = RTE_ETHER_MTU;
9812
9813 bnx2x_set_modes_bitmap(sc);
9814
9815 /* need to reset chip if UNDI was active */
9816 if (IS_PF(sc) && !BNX2X_NOMCP(sc)) {
9817 /* init fw_seq */
9818 sc->fw_seq =
9819 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
9820 DRV_MSG_SEQ_NUMBER_MASK);
9821 PMD_DRV_LOG(DEBUG, sc, "prev unload fw_seq 0x%04x",
9822 sc->fw_seq);
9823 bnx2x_prev_unload(sc);
9824 }
9825
9826 bnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);
9827
9828 /* calculate qm_cid_count */
9829 sc->qm_cid_count = bnx2x_set_qm_cid_count(sc);
9830
9831 sc->max_cos = 1;
9832 bnx2x_init_multi_cos(sc);
9833
9834 return 0;
9835 }
9836
9837 static void
9838 bnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,
9839 uint16_t index, uint8_t op, uint8_t update)
9840 {
9841 uint32_t igu_addr = sc->igu_base_addr;
9842 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
9843 bnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);
9844 }
9845
9846 static void
9847 bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,
9848 uint16_t index, uint8_t op, uint8_t update)
9849 {
9850 if (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))
9851 bnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
9852 else {
9853 uint8_t segment;
9854 if (CHIP_INT_MODE_IS_BC(sc)) {
9855 segment = storm;
9856 } else if (igu_sb_id != sc->igu_dsb_id) {
9857 segment = IGU_SEG_ACCESS_DEF;
9858 } else if (storm == ATTENTION_ID) {
9859 segment = IGU_SEG_ACCESS_ATTN;
9860 } else {
9861 segment = IGU_SEG_ACCESS_DEF;
9862 }
9863 bnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
9864 }
9865 }
9866
9867 static void
9868 bnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,
9869 uint8_t is_pf)
9870 {
9871 uint32_t data, ctl, cnt = 100;
9872 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
9873 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
9874 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +
9875 (idu_sb_id / 32) * 4;
9876 uint32_t sb_bit = 1 << (idu_sb_id % 32);
9877 uint32_t func_encode = func |
9878 (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
9879 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
9880
9881 /* Not supported in BC mode */
9882 if (CHIP_INT_MODE_IS_BC(sc)) {
9883 return;
9884 }
9885
9886 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
9887 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
9888 IGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);
9889
9890 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
9891 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
9892 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
9893
9894 REG_WR(sc, igu_addr_data, data);
9895
9896 mb();
9897
9898 PMD_DRV_LOG(DEBUG, sc, "write 0x%08x to IGU(via GRC) addr 0x%x",
9899 ctl, igu_addr_ctl);
9900 REG_WR(sc, igu_addr_ctl, ctl);
9901
9902 mb();
9903
9904 /* wait for clean up to finish */
9905 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
9906 DELAY(20000);
9907 }
9908
9909 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
9910 PMD_DRV_LOG(DEBUG, sc,
9911 "Unable to finish IGU cleanup: "
9912 "idu_sb_id %d offset %d bit %d (cnt %d)",
9913 idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);
9914 }
9915 }
9916
9917 static void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)
9918 {
9919 bnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
9920 }
9921
9922 /*******************/
9923 /* ECORE CALLBACKS */
9924 /*******************/
9925
9926 static void bnx2x_reset_common(struct bnx2x_softc *sc)
9927 {
9928 uint32_t val = 0x1400;
9929
9930 PMD_INIT_FUNC_TRACE(sc);
9931
9932 /* reset_common */
9933 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),
9934 0xd3ffff7f);
9935
9936 if (CHIP_IS_E3(sc)) {
9937 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
9938 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
9939 }
9940
9941 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
9942 }
9943
9944 static void bnx2x_common_init_phy(struct bnx2x_softc *sc)
9945 {
9946 uint32_t shmem_base[2];
9947 uint32_t shmem2_base[2];
9948
9949 /* Avoid common init in case MFW supports LFA */
9950 if (SHMEM2_RD(sc, size) >
9951 (uint32_t) offsetof(struct shmem2_region,
9952 lfa_host_addr[SC_PORT(sc)])) {
9953 return;
9954 }
9955
9956 shmem_base[0] = sc->devinfo.shmem_base;
9957 shmem2_base[0] = sc->devinfo.shmem2_base;
9958
9959 if (!CHIP_IS_E1x(sc)) {
9960 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
9961 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
9962 }
9963
9964 bnx2x_acquire_phy_lock(sc);
9965 elink_common_init_phy(sc, shmem_base, shmem2_base,
9966 sc->devinfo.chip_id, 0);
9967 bnx2x_release_phy_lock(sc);
9968 }
9969
9970 static void bnx2x_pf_disable(struct bnx2x_softc *sc)
9971 {
9972 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
9973
9974 val &= ~IGU_PF_CONF_FUNC_EN;
9975
9976 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
9977 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
9978 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
9979 }
9980
9981 static void bnx2x_init_pxp(struct bnx2x_softc *sc)
9982 {
9983 uint16_t devctl;
9984 int r_order, w_order;
9985
9986 devctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);
9987
9988 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
9989 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
9990
9991 ecore_init_pxp_arb(sc, r_order, w_order);
9992 }
9993
9994 static uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)
9995 {
9996 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9997 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
9998 return base + (SC_ABS_FUNC(sc)) * stride;
9999 }
10000
10001 /*
10002 * Called only on E1H or E2.
10003 * When pretending to be PF, the pretend value is the function number 0..7.
10004 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
10005 * combination.
10006 */
10007 static int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)
10008 {
10009 uint32_t pretend_reg;
10010
10011 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))
10012 return -1;
10013
10014 /* get my own pretend register */
10015 pretend_reg = bnx2x_get_pretend_reg(sc);
10016 REG_WR(sc, pretend_reg, pretend_func_val);
10017 REG_RD(sc, pretend_reg);
10018 return 0;
10019 }
10020
10021 static void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)
10022 {
10023 int is_required;
10024 uint32_t val;
10025 int port;
10026
10027 is_required = 0;
10028 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
10029 SHARED_HW_CFG_FAN_FAILURE_MASK);
10030
10031 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
10032 is_required = 1;
10033 }
10034 /*
10035 * The fan failure mechanism is usually related to the PHY type since
10036 * the power consumption of the board is affected by the PHY. Currently,
10037 * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.
10038 */
10039 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
10040 for (port = PORT_0; port < PORT_MAX; port++) {
10041 is_required |= elink_fan_failure_det_req(sc,
10042 sc->
10043 devinfo.shmem_base,
10044 sc->
10045 devinfo.shmem2_base,
10046 port);
10047 }
10048 }
10049
10050 if (is_required == 0) {
10051 return;
10052 }
10053
10054 /* Fan failure is indicated by SPIO 5 */
10055 bnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
10056
10057 /* set to active low mode */
10058 val = REG_RD(sc, MISC_REG_SPIO_INT);
10059 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
10060 REG_WR(sc, MISC_REG_SPIO_INT, val);
10061
10062 /* enable interrupt to signal the IGU */
10063 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10064 val |= MISC_SPIO_SPIO5;
10065 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
10066 }
10067
10068 static void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)
10069 {
10070 uint32_t val;
10071
10072 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
10073 if (!CHIP_IS_E1x(sc)) {
10074 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
10075 } else {
10076 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
10077 }
10078 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10079 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10080 /*
10081 * mask read length error interrupts in brb for parser
10082 * (parsing unit and 'checksum and crc' unit)
10083 * these errors are legal (PU reads fixed length and CAC can cause
10084 * read length error on truncated packets)
10085 */
10086 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
10087 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
10088 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
10089 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
10090 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
10091 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
10092 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
10093 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
10094 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
10095 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
10096 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
10097 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
10098 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
10099 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
10100 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
10101 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
10102 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
10103 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
10104 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
10105
10106 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
10107 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
10108 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
10109 if (!CHIP_IS_E1x(sc)) {
10110 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
10111 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
10112 }
10113 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
10114
10115 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
10116 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
10117 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
10118 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
10119
10120 if (!CHIP_IS_E1x(sc)) {
10121 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
10122 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
10123 }
10124
10125 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
10126 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
10127 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
10128 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
10129 }
10130
10131 /**
10132 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
10133 *
10134 * @sc: driver handle
10135 */
10136 static int bnx2x_init_hw_common(struct bnx2x_softc *sc)
10137 {
10138 uint8_t abs_func_id;
10139 uint32_t val;
10140
10141 PMD_DRV_LOG(DEBUG, sc,
10142 "starting common init for func %d", SC_ABS_FUNC(sc));
10143
10144 /*
10145 * take the RESET lock to protect undi_unload flow from accessing
10146 * registers while we are resetting the chip
10147 */
10148 bnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10149
10150 bnx2x_reset_common(sc);
10151
10152 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
10153
10154 val = 0xfffc;
10155 if (CHIP_IS_E3(sc)) {
10156 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
10157 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
10158 }
10159
10160 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
10161
10162 bnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
10163
10164 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
10165
10166 if (!CHIP_IS_E1x(sc)) {
10167 /*
10168 * 4-port mode or 2-port mode we need to turn off master-enable for
10169 * everyone. After that we turn it back on for self. So, we disregard
10170 * multi-function, and always disable all functions on the given path,
10171 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
10172 */
10173 for (abs_func_id = SC_PATH(sc);
10174 abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {
10175 if (abs_func_id == SC_ABS_FUNC(sc)) {
10176 REG_WR(sc,
10177 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
10178 1);
10179 continue;
10180 }
10181
10182 bnx2x_pretend_func(sc, abs_func_id);
10183
10184 /* clear pf enable */
10185 bnx2x_pf_disable(sc);
10186
10187 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10188 }
10189 }
10190
10191 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
10192
10193 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
10194 bnx2x_init_pxp(sc);
10195
10196 #ifdef __BIG_ENDIAN
10197 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
10198 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
10199 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
10200 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
10201 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
10202 /* make sure this value is 0 */
10203 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
10204
10205 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
10206 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
10207 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
10208 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
10209 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
10210 #endif
10211
10212 ecore_ilt_init_page_size(sc, INITOP_SET);
10213
10214 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
10215 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
10216 }
10217
10218 /* let the HW do it's magic... */
10219 DELAY(100000);
10220
10221 /* finish PXP init */
10222
10223 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
10224 if (val != 1) {
10225 PMD_DRV_LOG(NOTICE, sc, "PXP2 CFG failed");
10226 return -1;
10227 }
10228 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
10229 if (val != 1) {
10230 PMD_DRV_LOG(NOTICE, sc, "PXP2 RD_INIT failed");
10231 return -1;
10232 }
10233
10234 /*
10235 * Timer bug workaround for E2 only. We need to set the entire ILT to have
10236 * entries with value "0" and valid bit on. This needs to be done by the
10237 * first PF that is loaded in a path (i.e. common phase)
10238 */
10239 if (!CHIP_IS_E1x(sc)) {
10240 /*
10241 * In E2 there is a bug in the timers block that can cause function 6 / 7
10242 * (i.e. vnic3) to start even if it is marked as "scan-off".
10243 * This occurs when a different function (func2,3) is being marked
10244 * as "scan-off". Real-life scenario for example: if a driver is being
10245 * load-unloaded while func6,7 are down. This will cause the timer to access
10246 * the ilt, translate to a logical address and send a request to read/write.
10247 * Since the ilt for the function that is down is not valid, this will cause
10248 * a translation error which is unrecoverable.
10249 * The Workaround is intended to make sure that when this happens nothing
10250 * fatal will occur. The workaround:
10251 * 1. First PF driver which loads on a path will:
10252 * a. After taking the chip out of reset, by using pretend,
10253 * it will write "0" to the following registers of
10254 * the other vnics.
10255 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10256 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
10257 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
10258 * And for itself it will write '1' to
10259 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
10260 * dmae-operations (writing to pram for example.)
10261 * note: can be done for only function 6,7 but cleaner this
10262 * way.
10263 * b. Write zero+valid to the entire ILT.
10264 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
10265 * VNIC3 (of that port). The range allocated will be the
10266 * entire ILT. This is needed to prevent ILT range error.
10267 * 2. Any PF driver load flow:
10268 * a. ILT update with the physical addresses of the allocated
10269 * logical pages.
10270 * b. Wait 20msec. - note that this timeout is needed to make
10271 * sure there are no requests in one of the PXP internal
10272 * queues with "old" ILT addresses.
10273 * c. PF enable in the PGLC.
10274 * d. Clear the was_error of the PF in the PGLC. (could have
10275 * occurred while driver was down)
10276 * e. PF enable in the CFC (WEAK + STRONG)
10277 * f. Timers scan enable
10278 * 3. PF driver unload flow:
10279 * a. Clear the Timers scan_en.
10280 * b. Polling for scan_on=0 for that PF.
10281 * c. Clear the PF enable bit in the PXP.
10282 * d. Clear the PF enable in the CFC (WEAK + STRONG)
10283 * e. Write zero+valid to all ILT entries (The valid bit must
10284 * stay set)
10285 * f. If this is VNIC 3 of a port then also init
10286 * first_timers_ilt_entry to zero and last_timers_ilt_entry
10287 * to the last entry in the ILT.
10288 *
10289 * Notes:
10290 * Currently the PF error in the PGLC is non recoverable.
10291 * In the future the there will be a recovery routine for this error.
10292 * Currently attention is masked.
10293 * Having an MCP lock on the load/unload process does not guarantee that
10294 * there is no Timer disable during Func6/7 enable. This is because the
10295 * Timers scan is currently being cleared by the MCP on FLR.
10296 * Step 2.d can be done only for PF6/7 and the driver can also check if
10297 * there is error before clearing it. But the flow above is simpler and
10298 * more general.
10299 * All ILT entries are written by zero+valid and not just PF6/7
10300 * ILT entries since in the future the ILT entries allocation for
10301 * PF-s might be dynamic.
10302 */
10303 struct ilt_client_info ilt_cli;
10304 struct ecore_ilt ilt;
10305
10306 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
10307 memset(&ilt, 0, sizeof(struct ecore_ilt));
10308
10309 /* initialize dummy TM client */
10310 ilt_cli.start = 0;
10311 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
10312 ilt_cli.client_num = ILT_CLIENT_TM;
10313
10314 /*
10315 * Step 1: set zeroes to all ilt page entries with valid bit on
10316 * Step 2: set the timers first/last ilt entry to point
10317 * to the entire range to prevent ILT range error for 3rd/4th
10318 * vnic (this code assumes existence of the vnic)
10319 *
10320 * both steps performed by call to ecore_ilt_client_init_op()
10321 * with dummy TM client
10322 *
10323 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
10324 * and his brother are split registers
10325 */
10326
10327 bnx2x_pretend_func(sc, (SC_PATH(sc) + 6));
10328 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
10329 bnx2x_pretend_func(sc, SC_ABS_FUNC(sc));
10330
10331 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
10332 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
10333 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
10334 }
10335
10336 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
10337 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
10338
10339 if (!CHIP_IS_E1x(sc)) {
10340 int factor = 0;
10341
10342 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
10343 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
10344
10345 /* let the HW do it's magic... */
10346 do {
10347 DELAY(200000);
10348 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
10349 } while (factor-- && (val != 1));
10350
10351 if (val != 1) {
10352 PMD_DRV_LOG(NOTICE, sc, "ATC_INIT failed");
10353 return -1;
10354 }
10355 }
10356
10357 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
10358
10359 /* clean the DMAE memory */
10360 sc->dmae_ready = 1;
10361 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
10362
10363 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
10364
10365 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
10366
10367 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
10368
10369 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
10370
10371 bnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
10372 bnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
10373 bnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
10374 bnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
10375
10376 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
10377
10378 /* QM queues pointers table */
10379 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
10380
10381 /* soft reset pulse */
10382 REG_WR(sc, QM_REG_SOFT_RESET, 1);
10383 REG_WR(sc, QM_REG_SOFT_RESET, 0);
10384
10385 if (CNIC_SUPPORT(sc))
10386 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
10387
10388 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
10389
10390 if (!CHIP_REV_IS_SLOW(sc)) {
10391 /* enable hw interrupt from doorbell Q */
10392 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
10393 }
10394
10395 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
10396
10397 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
10398 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
10399 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
10400
10401 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
10402 if (IS_MF_AFEX(sc)) {
10403 /*
10404 * configure that AFEX and VLAN headers must be
10405 * received in AFEX mode
10406 */
10407 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
10408 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
10409 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
10410 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
10411 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
10412 } else {
10413 /*
10414 * Bit-map indicating which L2 hdrs may appear
10415 * after the basic Ethernet header
10416 */
10417 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
10418 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10419 }
10420 }
10421
10422 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
10423 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
10424 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
10425 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
10426
10427 if (!CHIP_IS_E1x(sc)) {
10428 /* reset VFC memories */
10429 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10430 VFC_MEMORIES_RST_REG_CAM_RST |
10431 VFC_MEMORIES_RST_REG_RAM_RST);
10432 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
10433 VFC_MEMORIES_RST_REG_CAM_RST |
10434 VFC_MEMORIES_RST_REG_RAM_RST);
10435
10436 DELAY(20000);
10437 }
10438
10439 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
10440 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
10441 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
10442 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
10443
10444 /* sync semi rtc */
10445 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
10446 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
10447
10448 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
10449 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
10450 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
10451
10452 if (!CHIP_IS_E1x(sc)) {
10453 if (IS_MF_AFEX(sc)) {
10454 /*
10455 * configure that AFEX and VLAN headers must be
10456 * sent in AFEX mode
10457 */
10458 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
10459 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
10460 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
10461 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
10462 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
10463 } else {
10464 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
10465 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
10466 }
10467 }
10468
10469 REG_WR(sc, SRC_REG_SOFT_RST, 1);
10470
10471 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
10472
10473 if (CNIC_SUPPORT(sc)) {
10474 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
10475 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
10476 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
10477 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
10478 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
10479 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
10480 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
10481 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
10482 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
10483 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
10484 }
10485 REG_WR(sc, SRC_REG_SOFT_RST, 0);
10486
10487 if (sizeof(union cdu_context) != 1024) {
10488 /* we currently assume that a context is 1024 bytes */
10489 PMD_DRV_LOG(NOTICE, sc,
10490 "please adjust the size of cdu_context(%ld)",
10491 (long)sizeof(union cdu_context));
10492 }
10493
10494 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
10495 val = (4 << 24) + (0 << 12) + 1024;
10496 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
10497
10498 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
10499
10500 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
10501 /* enable context validation interrupt from CFC */
10502 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
10503
10504 /* set the thresholds to prevent CFC/CDU race */
10505 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
10506 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
10507
10508 if (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {
10509 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
10510 }
10511
10512 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
10513 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
10514
10515 /* Reset PCIE errors for debug */
10516 REG_WR(sc, 0x2814, 0xffffffff);
10517 REG_WR(sc, 0x3820, 0xffffffff);
10518
10519 if (!CHIP_IS_E1x(sc)) {
10520 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
10521 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
10522 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
10523 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
10524 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
10525 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
10526 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
10527 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
10528 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
10529 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
10530 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
10531 }
10532
10533 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
10534
10535 /* in E3 this done in per-port section */
10536 if (!CHIP_IS_E3(sc))
10537 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
10538
10539 if (CHIP_IS_E1H(sc)) {
10540 /* not applicable for E2 (and above ...) */
10541 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
10542 }
10543
10544 if (CHIP_REV_IS_SLOW(sc)) {
10545 DELAY(200000);
10546 }
10547
10548 /* finish CFC init */
10549 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
10550 if (val != 1) {
10551 PMD_DRV_LOG(NOTICE, sc, "CFC LL_INIT failed");
10552 return -1;
10553 }
10554 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
10555 if (val != 1) {
10556 PMD_DRV_LOG(NOTICE, sc, "CFC AC_INIT failed");
10557 return -1;
10558 }
10559 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
10560 if (val != 1) {
10561 PMD_DRV_LOG(NOTICE, sc, "CFC CAM_INIT failed");
10562 return -1;
10563 }
10564 REG_WR(sc, CFC_REG_DEBUG0, 0);
10565
10566 bnx2x_setup_fan_failure_detection(sc);
10567
10568 /* clear PXP2 attentions */
10569 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
10570
10571 bnx2x_enable_blocks_attention(sc);
10572
10573 if (!CHIP_REV_IS_SLOW(sc)) {
10574 ecore_enable_blocks_parity(sc);
10575 }
10576
10577 if (!BNX2X_NOMCP(sc)) {
10578 if (CHIP_IS_E1x(sc)) {
10579 bnx2x_common_init_phy(sc);
10580 }
10581 }
10582
10583 return 0;
10584 }
10585
10586 /**
10587 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
10588 *
10589 * @sc: driver handle
10590 */
10591 static int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)
10592 {
10593 int rc = bnx2x_init_hw_common(sc);
10594
10595 if (rc) {
10596 return rc;
10597 }
10598
10599 /* In E2 2-PORT mode, same ext phy is used for the two paths */
10600 if (!BNX2X_NOMCP(sc)) {
10601 bnx2x_common_init_phy(sc);
10602 }
10603
10604 return 0;
10605 }
10606
10607 static int bnx2x_init_hw_port(struct bnx2x_softc *sc)
10608 {
10609 int port = SC_PORT(sc);
10610 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
10611 uint32_t low, high;
10612 uint32_t val;
10613
10614 PMD_DRV_LOG(DEBUG, sc, "starting port init for port %d", port);
10615
10616 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
10617
10618 ecore_init_block(sc, BLOCK_MISC, init_phase);
10619 ecore_init_block(sc, BLOCK_PXP, init_phase);
10620 ecore_init_block(sc, BLOCK_PXP2, init_phase);
10621
10622 /*
10623 * Timers bug workaround: disables the pf_master bit in pglue at
10624 * common phase, we need to enable it here before any dmae access are
10625 * attempted. Therefore we manually added the enable-master to the
10626 * port phase (it also happens in the function phase)
10627 */
10628 if (!CHIP_IS_E1x(sc)) {
10629 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
10630 }
10631
10632 ecore_init_block(sc, BLOCK_ATC, init_phase);
10633 ecore_init_block(sc, BLOCK_DMAE, init_phase);
10634 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
10635 ecore_init_block(sc, BLOCK_QM, init_phase);
10636
10637 ecore_init_block(sc, BLOCK_TCM, init_phase);
10638 ecore_init_block(sc, BLOCK_UCM, init_phase);
10639 ecore_init_block(sc, BLOCK_CCM, init_phase);
10640 ecore_init_block(sc, BLOCK_XCM, init_phase);
10641
10642 /* QM cid (connection) count */
10643 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
10644
10645 if (CNIC_SUPPORT(sc)) {
10646 ecore_init_block(sc, BLOCK_TM, init_phase);
10647 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);
10648 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);
10649 }
10650
10651 ecore_init_block(sc, BLOCK_DORQ, init_phase);
10652
10653 ecore_init_block(sc, BLOCK_BRB1, init_phase);
10654
10655 if (CHIP_IS_E1H(sc)) {
10656 if (IS_MF(sc)) {
10657 low = (BNX2X_ONE_PORT(sc) ? 160 : 246);
10658 } else if (sc->mtu > 4096) {
10659 if (BNX2X_ONE_PORT(sc)) {
10660 low = 160;
10661 } else {
10662 val = sc->mtu;
10663 /* (24*1024 + val*4)/256 */
10664 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
10665 }
10666 } else {
10667 low = (BNX2X_ONE_PORT(sc) ? 80 : 160);
10668 }
10669 high = (low + 56); /* 14*1024/256 */
10670 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
10671 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
10672 }
10673
10674 if (CHIP_IS_MODE_4_PORT(sc)) {
10675 REG_WR(sc, SC_PORT(sc) ?
10676 BRB1_REG_MAC_GUARANTIED_1 :
10677 BRB1_REG_MAC_GUARANTIED_0, 40);
10678 }
10679
10680 ecore_init_block(sc, BLOCK_PRS, init_phase);
10681 if (CHIP_IS_E3B0(sc)) {
10682 if (IS_MF_AFEX(sc)) {
10683 /* configure headers for AFEX mode */
10684 if (SC_PORT(sc)) {
10685 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,
10686 0xE);
10687 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,
10688 0x6);
10689 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);
10690 } else {
10691 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10692 0xE);
10693 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,
10694 0x6);
10695 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
10696 }
10697 } else {
10698 /* Ovlan exists only if we are in multi-function +
10699 * switch-dependent mode, in switch-independent there
10700 * is no ovlan headers
10701 */
10702 REG_WR(sc, SC_PORT(sc) ?
10703 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
10704 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
10705 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
10706 }
10707 }
10708
10709 ecore_init_block(sc, BLOCK_TSDM, init_phase);
10710 ecore_init_block(sc, BLOCK_CSDM, init_phase);
10711 ecore_init_block(sc, BLOCK_USDM, init_phase);
10712 ecore_init_block(sc, BLOCK_XSDM, init_phase);
10713
10714 ecore_init_block(sc, BLOCK_TSEM, init_phase);
10715 ecore_init_block(sc, BLOCK_USEM, init_phase);
10716 ecore_init_block(sc, BLOCK_CSEM, init_phase);
10717 ecore_init_block(sc, BLOCK_XSEM, init_phase);
10718
10719 ecore_init_block(sc, BLOCK_UPB, init_phase);
10720 ecore_init_block(sc, BLOCK_XPB, init_phase);
10721
10722 ecore_init_block(sc, BLOCK_PBF, init_phase);
10723
10724 if (CHIP_IS_E1x(sc)) {
10725 /* configure PBF to work without PAUSE mtu 9000 */
10726 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
10727
10728 /* update threshold */
10729 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));
10730 /* update init credit */
10731 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,
10732 (9040 / 16) + 553 - 22);
10733
10734 /* probe changes */
10735 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
10736 DELAY(50);
10737 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
10738 }
10739
10740 if (CNIC_SUPPORT(sc)) {
10741 ecore_init_block(sc, BLOCK_SRC, init_phase);
10742 }
10743
10744 ecore_init_block(sc, BLOCK_CDU, init_phase);
10745 ecore_init_block(sc, BLOCK_CFC, init_phase);
10746 ecore_init_block(sc, BLOCK_HC, init_phase);
10747 ecore_init_block(sc, BLOCK_IGU, init_phase);
10748 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
10749 /* init aeu_mask_attn_func_0/1:
10750 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
10751 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
10752 * bits 4-7 are used for "per vn group attention" */
10753 val = IS_MF(sc) ? 0xF7 : 0x7;
10754 val |= 0x10;
10755 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);
10756
10757 ecore_init_block(sc, BLOCK_NIG, init_phase);
10758
10759 if (!CHIP_IS_E1x(sc)) {
10760 /* Bit-map indicating which L2 hdrs may appear after the
10761 * basic Ethernet header
10762 */
10763 if (IS_MF_AFEX(sc)) {
10764 REG_WR(sc, SC_PORT(sc) ?
10765 NIG_REG_P1_HDRS_AFTER_BASIC :
10766 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
10767 } else {
10768 REG_WR(sc, SC_PORT(sc) ?
10769 NIG_REG_P1_HDRS_AFTER_BASIC :
10770 NIG_REG_P0_HDRS_AFTER_BASIC,
10771 IS_MF_SD(sc) ? 7 : 6);
10772 }
10773
10774 if (CHIP_IS_E3(sc)) {
10775 REG_WR(sc, SC_PORT(sc) ?
10776 NIG_REG_LLH1_MF_MODE :
10777 NIG_REG_LLH_MF_MODE, IS_MF(sc));
10778 }
10779 }
10780 if (!CHIP_IS_E3(sc)) {
10781 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
10782 }
10783
10784 /* 0x2 disable mf_ov, 0x1 enable */
10785 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
10786 (IS_MF_SD(sc) ? 0x1 : 0x2));
10787
10788 if (!CHIP_IS_E1x(sc)) {
10789 val = 0;
10790 switch (sc->devinfo.mf_info.mf_mode) {
10791 case MULTI_FUNCTION_SD:
10792 val = 1;
10793 break;
10794 case MULTI_FUNCTION_SI:
10795 case MULTI_FUNCTION_AFEX:
10796 val = 2;
10797 break;
10798 }
10799
10800 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
10801 NIG_REG_LLH0_CLS_TYPE), val);
10802 }
10803 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
10804 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
10805 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
10806
10807 /* If SPIO5 is set to generate interrupts, enable it for this port */
10808 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
10809 if (val & MISC_SPIO_SPIO5) {
10810 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10811 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
10812 val = REG_RD(sc, reg_addr);
10813 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
10814 REG_WR(sc, reg_addr, val);
10815 }
10816
10817 return 0;
10818 }
10819
10820 static uint32_t
10821 bnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,
10822 uint32_t expected, uint32_t poll_count)
10823 {
10824 uint32_t cur_cnt = poll_count;
10825 uint32_t val;
10826
10827 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
10828 DELAY(FLR_WAIT_INTERVAL);
10829 }
10830
10831 return val;
10832 }
10833
10834 static int
10835 bnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,
10836 __rte_unused const char *msg, uint32_t poll_cnt)
10837 {
10838 uint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
10839
10840 if (val != 0) {
10841 PMD_DRV_LOG(NOTICE, sc, "%s usage count=%d", msg, val);
10842 return -1;
10843 }
10844
10845 return 0;
10846 }
10847
10848 /* Common routines with VF FLR cleanup */
10849 static uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)
10850 {
10851 /* adjust polling timeout */
10852 if (CHIP_REV_IS_EMUL(sc)) {
10853 return FLR_POLL_CNT * 2000;
10854 }
10855
10856 if (CHIP_REV_IS_FPGA(sc)) {
10857 return FLR_POLL_CNT * 120;
10858 }
10859
10860 return FLR_POLL_CNT;
10861 }
10862
10863 static int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)
10864 {
10865 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
10866 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10867 CFC_REG_NUM_LCIDS_INSIDE_PF,
10868 "CFC PF usage counter timed out",
10869 poll_cnt)) {
10870 return -1;
10871 }
10872
10873 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
10874 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10875 DORQ_REG_PF_USAGE_CNT,
10876 "DQ PF usage counter timed out",
10877 poll_cnt)) {
10878 return -1;
10879 }
10880
10881 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
10882 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10883 QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),
10884 "QM PF usage counter timed out",
10885 poll_cnt)) {
10886 return -1;
10887 }
10888
10889 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
10890 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10891 TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),
10892 "Timers VNIC usage counter timed out",
10893 poll_cnt)) {
10894 return -1;
10895 }
10896
10897 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10898 TM_REG_LIN0_NUM_SCANS +
10899 4 * SC_PORT(sc),
10900 "Timers NUM_SCANS usage counter timed out",
10901 poll_cnt)) {
10902 return -1;
10903 }
10904
10905 /* Wait DMAE PF usage counter to zero */
10906 if (bnx2x_flr_clnup_poll_hw_counter(sc,
10907 dmae_reg_go_c[INIT_DMAE_C(sc)],
10908 "DMAE dommand register timed out",
10909 poll_cnt)) {
10910 return -1;
10911 }
10912
10913 return 0;
10914 }
10915
10916 #define OP_GEN_PARAM(param) \
10917 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
10918 #define OP_GEN_TYPE(type) \
10919 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
10920 #define OP_GEN_AGG_VECT(index) \
10921 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
10922
10923 static int
10924 bnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,
10925 uint32_t poll_cnt)
10926 {
10927 uint32_t op_gen_command = 0;
10928 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
10929 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
10930 int ret = 0;
10931
10932 if (REG_RD(sc, comp_addr)) {
10933 PMD_DRV_LOG(NOTICE, sc,
10934 "Cleanup complete was not 0 before sending");
10935 return -1;
10936 }
10937
10938 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
10939 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
10940 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
10941 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
10942
10943 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
10944
10945 if (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
10946 PMD_DRV_LOG(NOTICE, sc, "FW final cleanup did not succeed");
10947 PMD_DRV_LOG(DEBUG, sc, "At timeout completion address contained %x",
10948 (REG_RD(sc, comp_addr)));
10949 rte_panic("FLR cleanup failed");
10950 return -1;
10951 }
10952
10953 /* Zero completion for nxt FLR */
10954 REG_WR(sc, comp_addr, 0);
10955
10956 return ret;
10957 }
10958
10959 static void
10960 bnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,
10961 uint32_t poll_count)
10962 {
10963 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
10964 uint32_t cur_cnt = poll_count;
10965
10966 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
10967 crd = crd_start = REG_RD(sc, regs->crd);
10968 init_crd = REG_RD(sc, regs->init_crd);
10969
10970 while ((crd != init_crd) &&
10971 ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <
10972 (init_crd - crd_start))) {
10973 if (cur_cnt--) {
10974 DELAY(FLR_WAIT_INTERVAL);
10975 crd = REG_RD(sc, regs->crd);
10976 crd_freed = REG_RD(sc, regs->crd_freed);
10977 } else {
10978 break;
10979 }
10980 }
10981 }
10982
10983 static void
10984 bnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,
10985 uint32_t poll_count)
10986 {
10987 uint32_t occup, to_free, freed, freed_start;
10988 uint32_t cur_cnt = poll_count;
10989
10990 occup = to_free = REG_RD(sc, regs->lines_occup);
10991 freed = freed_start = REG_RD(sc, regs->lines_freed);
10992
10993 while (occup &&
10994 ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <
10995 to_free)) {
10996 if (cur_cnt--) {
10997 DELAY(FLR_WAIT_INTERVAL);
10998 occup = REG_RD(sc, regs->lines_occup);
10999 freed = REG_RD(sc, regs->lines_freed);
11000 } else {
11001 break;
11002 }
11003 }
11004 }
11005
11006 static void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)
11007 {
11008 struct pbf_pN_cmd_regs cmd_regs[] = {
11009 {0, (CHIP_IS_E3B0(sc)) ?
11010 PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,
11011 (CHIP_IS_E3B0(sc)) ?
11012 PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},
11013 {1, (CHIP_IS_E3B0(sc)) ?
11014 PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,
11015 (CHIP_IS_E3B0(sc)) ?
11016 PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},
11017 {4, (CHIP_IS_E3B0(sc)) ?
11018 PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,
11019 (CHIP_IS_E3B0(sc)) ?
11020 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
11021 PBF_REG_P4_TQ_LINES_FREED_CNT}
11022 };
11023
11024 struct pbf_pN_buf_regs buf_regs[] = {
11025 {0, (CHIP_IS_E3B0(sc)) ?
11026 PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,
11027 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,
11028 (CHIP_IS_E3B0(sc)) ?
11029 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
11030 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
11031 {1, (CHIP_IS_E3B0(sc)) ?
11032 PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,
11033 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,
11034 (CHIP_IS_E3B0(sc)) ?
11035 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
11036 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
11037 {4, (CHIP_IS_E3B0(sc)) ?
11038 PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,
11039 (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,
11040 (CHIP_IS_E3B0(sc)) ?
11041 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
11042 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
11043 };
11044
11045 uint32_t i;
11046
11047 /* Verify the command queues are flushed P0, P1, P4 */
11048 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
11049 bnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
11050 }
11051
11052 /* Verify the transmission buffers are flushed P0, P1, P4 */
11053 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
11054 bnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
11055 }
11056 }
11057
11058 static void bnx2x_hw_enable_status(struct bnx2x_softc *sc)
11059 {
11060 __rte_unused uint32_t val;
11061
11062 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
11063 PMD_DRV_LOG(DEBUG, sc, "CFC_REG_WEAK_ENABLE_PF is 0x%x", val);
11064
11065 val = REG_RD(sc, PBF_REG_DISABLE_PF);
11066 PMD_DRV_LOG(DEBUG, sc, "PBF_REG_DISABLE_PF is 0x%x", val);
11067
11068 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
11069 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSI_EN is 0x%x", val);
11070
11071 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
11072 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_EN is 0x%x", val);
11073
11074 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
11075 PMD_DRV_LOG(DEBUG, sc, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x", val);
11076
11077 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
11078 PMD_DRV_LOG(DEBUG, sc,
11079 "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x", val);
11080
11081 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
11082 PMD_DRV_LOG(DEBUG, sc,
11083 "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x", val);
11084
11085 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
11086 PMD_DRV_LOG(DEBUG, sc, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x",
11087 val);
11088 }
11089
11090 /**
11091 * bnx2x_pf_flr_clnup
11092 * a. re-enable target read on the PF
11093 * b. poll cfc per function usage counter
11094 * c. poll the qm perfunction usage counter
11095 * d. poll the tm per function usage counter
11096 * e. poll the tm per function scan-done indication
11097 * f. clear the dmae channel associated wit hthe PF
11098 * g. zero the igu 'trailing edge' and 'leading edge' regs (attentions)
11099 * h. call the common flr cleanup code with -1 (pf indication)
11100 */
11101 static int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)
11102 {
11103 uint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);
11104
11105 /* Re-enable PF target read access */
11106 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11107
11108 /* Poll HW usage counters */
11109 if (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {
11110 return -1;
11111 }
11112
11113 /* Zero the igu 'trailing edge' and 'leading edge' */
11114
11115 /* Send the FW cleanup command */
11116 if (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {
11117 return -1;
11118 }
11119
11120 /* ATC cleanup */
11121
11122 /* Verify TX hw is flushed */
11123 bnx2x_tx_hw_flushed(sc, poll_cnt);
11124
11125 /* Wait 100ms (not adjusted according to platform) */
11126 DELAY(100000);
11127
11128 /* Verify no pending pci transactions */
11129 if (bnx2x_is_pcie_pending(sc)) {
11130 PMD_DRV_LOG(NOTICE, sc, "PCIE Transactions still pending");
11131 }
11132
11133 /* Debug */
11134 bnx2x_hw_enable_status(sc);
11135
11136 /*
11137 * Master enable - Due to WB DMAE writes performed before this
11138 * register is re-initialized as part of the regular function init
11139 */
11140 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11141
11142 return 0;
11143 }
11144
11145 static int bnx2x_init_hw_func(struct bnx2x_softc *sc)
11146 {
11147 int port = SC_PORT(sc);
11148 int func = SC_FUNC(sc);
11149 int init_phase = PHASE_PF0 + func;
11150 struct ecore_ilt *ilt = sc->ilt;
11151 uint16_t cdu_ilt_start;
11152 uint32_t addr, val;
11153 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
11154 int main_mem_width, rc;
11155 uint32_t i;
11156
11157 PMD_DRV_LOG(DEBUG, sc, "starting func init for func %d", func);
11158
11159 /* FLR cleanup */
11160 if (!CHIP_IS_E1x(sc)) {
11161 rc = bnx2x_pf_flr_clnup(sc);
11162 if (rc) {
11163 PMD_DRV_LOG(NOTICE, sc, "FLR cleanup failed!");
11164 return rc;
11165 }
11166 }
11167
11168 /* set MSI reconfigure capability */
11169 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11170 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
11171 val = REG_RD(sc, addr);
11172 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
11173 REG_WR(sc, addr, val);
11174 }
11175
11176 ecore_init_block(sc, BLOCK_PXP, init_phase);
11177 ecore_init_block(sc, BLOCK_PXP2, init_phase);
11178
11179 ilt = sc->ilt;
11180 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
11181
11182 for (i = 0; i < L2_ILT_LINES(sc); i++) {
11183 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
11184 ilt->lines[cdu_ilt_start + i].page_mapping =
11185 (rte_iova_t)sc->context[i].vcxt_dma.paddr;
11186 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
11187 }
11188 ecore_ilt_init_op(sc, INITOP_SET);
11189
11190 REG_WR(sc, PRS_REG_NIC_MODE, 1);
11191
11192 if (!CHIP_IS_E1x(sc)) {
11193 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
11194
11195 /* Turn on a single ISR mode in IGU if driver is going to use
11196 * INT#x or MSI
11197 */
11198 if ((sc->interrupt_mode != INTR_MODE_MSIX)
11199 || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {
11200 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
11201 }
11202
11203 /*
11204 * Timers workaround bug: function init part.
11205 * Need to wait 20msec after initializing ILT,
11206 * needed to make sure there are no requests in
11207 * one of the PXP internal queues with "old" ILT addresses
11208 */
11209 DELAY(20000);
11210
11211 /*
11212 * Master enable - Due to WB DMAE writes performed before this
11213 * register is re-initialized as part of the regular function
11214 * init
11215 */
11216 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
11217 /* Enable the function in IGU */
11218 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
11219 }
11220
11221 sc->dmae_ready = 1;
11222
11223 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
11224
11225 if (!CHIP_IS_E1x(sc))
11226 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
11227
11228 ecore_init_block(sc, BLOCK_ATC, init_phase);
11229 ecore_init_block(sc, BLOCK_DMAE, init_phase);
11230 ecore_init_block(sc, BLOCK_NIG, init_phase);
11231 ecore_init_block(sc, BLOCK_SRC, init_phase);
11232 ecore_init_block(sc, BLOCK_MISC, init_phase);
11233 ecore_init_block(sc, BLOCK_TCM, init_phase);
11234 ecore_init_block(sc, BLOCK_UCM, init_phase);
11235 ecore_init_block(sc, BLOCK_CCM, init_phase);
11236 ecore_init_block(sc, BLOCK_XCM, init_phase);
11237 ecore_init_block(sc, BLOCK_TSEM, init_phase);
11238 ecore_init_block(sc, BLOCK_USEM, init_phase);
11239 ecore_init_block(sc, BLOCK_CSEM, init_phase);
11240 ecore_init_block(sc, BLOCK_XSEM, init_phase);
11241
11242 if (!CHIP_IS_E1x(sc))
11243 REG_WR(sc, QM_REG_PF_EN, 1);
11244
11245 if (!CHIP_IS_E1x(sc)) {
11246 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11247 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11248 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11249 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
11250 }
11251 ecore_init_block(sc, BLOCK_QM, init_phase);
11252
11253 ecore_init_block(sc, BLOCK_TM, init_phase);
11254 ecore_init_block(sc, BLOCK_DORQ, init_phase);
11255
11256 ecore_init_block(sc, BLOCK_BRB1, init_phase);
11257 ecore_init_block(sc, BLOCK_PRS, init_phase);
11258 ecore_init_block(sc, BLOCK_TSDM, init_phase);
11259 ecore_init_block(sc, BLOCK_CSDM, init_phase);
11260 ecore_init_block(sc, BLOCK_USDM, init_phase);
11261 ecore_init_block(sc, BLOCK_XSDM, init_phase);
11262 ecore_init_block(sc, BLOCK_UPB, init_phase);
11263 ecore_init_block(sc, BLOCK_XPB, init_phase);
11264 ecore_init_block(sc, BLOCK_PBF, init_phase);
11265 if (!CHIP_IS_E1x(sc))
11266 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
11267
11268 ecore_init_block(sc, BLOCK_CDU, init_phase);
11269
11270 ecore_init_block(sc, BLOCK_CFC, init_phase);
11271
11272 if (!CHIP_IS_E1x(sc))
11273 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
11274
11275 if (IS_MF(sc)) {
11276 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
11277 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));
11278 }
11279
11280 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
11281
11282 /* HC init per function */
11283 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11284 if (CHIP_IS_E1H(sc)) {
11285 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11286
11287 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11288 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11289 }
11290 ecore_init_block(sc, BLOCK_HC, init_phase);
11291
11292 } else {
11293 uint32_t num_segs, sb_idx, prod_offset;
11294
11295 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
11296
11297 if (!CHIP_IS_E1x(sc)) {
11298 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11299 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11300 }
11301
11302 ecore_init_block(sc, BLOCK_IGU, init_phase);
11303
11304 if (!CHIP_IS_E1x(sc)) {
11305 int dsb_idx = 0;
11306 /**
11307 * Producer memory:
11308 * E2 mode: address 0-135 match to the mapping memory;
11309 * 136 - PF0 default prod; 137 - PF1 default prod;
11310 * 138 - PF2 default prod; 139 - PF3 default prod;
11311 * 140 - PF0 attn prod; 141 - PF1 attn prod;
11312 * 142 - PF2 attn prod; 143 - PF3 attn prod;
11313 * 144-147 reserved.
11314 *
11315 * E1.5 mode - In backward compatible mode;
11316 * for non default SB; each even line in the memory
11317 * holds the U producer and each odd line hold
11318 * the C producer. The first 128 producers are for
11319 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
11320 * producers are for the DSB for each PF.
11321 * Each PF has five segments: (the order inside each
11322 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
11323 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
11324 * 144-147 attn prods;
11325 */
11326 /* non-default-status-blocks */
11327 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11328 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
11329 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
11330 prod_offset = (sc->igu_base_sb + sb_idx) *
11331 num_segs;
11332
11333 for (i = 0; i < num_segs; i++) {
11334 addr = IGU_REG_PROD_CONS_MEMORY +
11335 (prod_offset + i) * 4;
11336 REG_WR(sc, addr, 0);
11337 }
11338 /* send consumer update with value 0 */
11339 bnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,
11340 USTORM_ID, 0, IGU_INT_NOP, 1);
11341 bnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
11342 }
11343
11344 /* default-status-blocks */
11345 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
11346 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
11347
11348 if (CHIP_IS_MODE_4_PORT(sc))
11349 dsb_idx = SC_FUNC(sc);
11350 else
11351 dsb_idx = SC_VN(sc);
11352
11353 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
11354 IGU_BC_BASE_DSB_PROD + dsb_idx :
11355 IGU_NORM_BASE_DSB_PROD + dsb_idx);
11356
11357 /*
11358 * igu prods come in chunks of E1HVN_MAX (4) -
11359 * does not matters what is the current chip mode
11360 */
11361 for (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {
11362 addr = IGU_REG_PROD_CONS_MEMORY +
11363 (prod_offset + i) * 4;
11364 REG_WR(sc, addr, 0);
11365 }
11366 /* send consumer update with 0 */
11367 if (CHIP_INT_MODE_IS_BC(sc)) {
11368 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11369 USTORM_ID, 0, IGU_INT_NOP, 1);
11370 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11371 CSTORM_ID, 0, IGU_INT_NOP, 1);
11372 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11373 XSTORM_ID, 0, IGU_INT_NOP, 1);
11374 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11375 TSTORM_ID, 0, IGU_INT_NOP, 1);
11376 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11377 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11378 } else {
11379 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11380 USTORM_ID, 0, IGU_INT_NOP, 1);
11381 bnx2x_ack_sb(sc, sc->igu_dsb_id,
11382 ATTENTION_ID, 0, IGU_INT_NOP, 1);
11383 }
11384 bnx2x_igu_clear_sb(sc, sc->igu_dsb_id);
11385
11386 /* !!! these should become driver const once
11387 rf-tool supports split-68 const */
11388 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
11389 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
11390 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
11391 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
11392 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
11393 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
11394 }
11395 }
11396
11397 /* Reset PCIE errors for debug */
11398 REG_WR(sc, 0x2114, 0xffffffff);
11399 REG_WR(sc, 0x2120, 0xffffffff);
11400
11401 if (CHIP_IS_E1x(sc)) {
11402 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords */
11403 main_mem_base = HC_REG_MAIN_MEMORY +
11404 SC_PORT(sc) * (main_mem_size * 4);
11405 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
11406 main_mem_width = 8;
11407
11408 val = REG_RD(sc, main_mem_prty_clr);
11409 if (val) {
11410 PMD_DRV_LOG(DEBUG, sc,
11411 "Parity errors in HC block during function init (0x%x)!",
11412 val);
11413 }
11414
11415 /* Clear "false" parity errors in MSI-X table */
11416 for (i = main_mem_base;
11417 i < main_mem_base + main_mem_size * 4;
11418 i += main_mem_width) {
11419 bnx2x_read_dmae(sc, i, main_mem_width / 4);
11420 bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),
11421 i, main_mem_width / 4);
11422 }
11423 /* Clear HC parity attention */
11424 REG_RD(sc, main_mem_prty_clr);
11425 }
11426
11427 /* Enable STORMs SP logging */
11428 REG_WR8(sc, BAR_USTRORM_INTMEM +
11429 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11430 REG_WR8(sc, BAR_TSTRORM_INTMEM +
11431 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11432 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11433 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11434 REG_WR8(sc, BAR_XSTRORM_INTMEM +
11435 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
11436
11437 elink_phy_probe(&sc->link_params);
11438
11439 return 0;
11440 }
11441
11442 static void bnx2x_link_reset(struct bnx2x_softc *sc)
11443 {
11444 if (!BNX2X_NOMCP(sc)) {
11445 bnx2x_acquire_phy_lock(sc);
11446 elink_lfa_reset(&sc->link_params, &sc->link_vars);
11447 bnx2x_release_phy_lock(sc);
11448 } else {
11449 if (!CHIP_REV_IS_SLOW(sc)) {
11450 PMD_DRV_LOG(WARNING, sc,
11451 "Bootcode is missing - cannot reset link");
11452 }
11453 }
11454 }
11455
11456 static void bnx2x_reset_port(struct bnx2x_softc *sc)
11457 {
11458 int port = SC_PORT(sc);
11459 uint32_t val;
11460
11461 /* reset physical Link */
11462 bnx2x_link_reset(sc);
11463
11464 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
11465
11466 /* Do not rcv packets to BRB */
11467 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
11468 /* Do not direct rcv packets that are not for MCP to the BRB */
11469 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
11470 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
11471
11472 /* Configure AEU */
11473 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
11474
11475 DELAY(100000);
11476
11477 /* Check for BRB port occupancy */
11478 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
11479 if (val) {
11480 PMD_DRV_LOG(DEBUG, sc,
11481 "BRB1 is not empty, %d blocks are occupied", val);
11482 }
11483 }
11484
11485 static void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, rte_iova_t addr)
11486 {
11487 int reg;
11488 uint32_t wb_write[2];
11489
11490 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
11491
11492 wb_write[0] = ONCHIP_ADDR1(addr);
11493 wb_write[1] = ONCHIP_ADDR2(addr);
11494 REG_WR_DMAE(sc, reg, wb_write, 2);
11495 }
11496
11497 static void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)
11498 {
11499 uint32_t i, base = FUNC_ILT_BASE(func);
11500 for (i = base; i < base + ILT_PER_FUNC; i++) {
11501 bnx2x_ilt_wr(sc, i, 0);
11502 }
11503 }
11504
11505 static void bnx2x_reset_func(struct bnx2x_softc *sc)
11506 {
11507 struct bnx2x_fastpath *fp;
11508 int port = SC_PORT(sc);
11509 int func = SC_FUNC(sc);
11510 int i;
11511
11512 /* Disable the function in the FW */
11513 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
11514 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
11515 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
11516 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
11517
11518 /* FP SBs */
11519 FOR_EACH_ETH_QUEUE(sc, i) {
11520 fp = &sc->fp[i];
11521 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11522 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
11523 SB_DISABLED);
11524 }
11525
11526 /* SP SB */
11527 REG_WR8(sc, BAR_CSTRORM_INTMEM +
11528 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);
11529
11530 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
11531 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
11532 0);
11533 }
11534
11535 /* Configure IGU */
11536 if (sc->devinfo.int_block == INT_BLOCK_HC) {
11537 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
11538 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
11539 } else {
11540 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
11541 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
11542 }
11543
11544 if (CNIC_LOADED(sc)) {
11545 /* Disable Timer scan */
11546 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);
11547 /*
11548 * Wait for at least 10ms and up to 2 second for the timers
11549 * scan to complete
11550 */
11551 for (i = 0; i < 200; i++) {
11552 DELAY(10000);
11553 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))
11554 break;
11555 }
11556 }
11557
11558 /* Clear ILT */
11559 bnx2x_clear_func_ilt(sc, func);
11560
11561 /*
11562 * Timers workaround bug for E2: if this is vnic-3,
11563 * we need to set the entire ilt range for this timers.
11564 */
11565 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
11566 struct ilt_client_info ilt_cli;
11567 /* use dummy TM client */
11568 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
11569 ilt_cli.start = 0;
11570 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
11571 ilt_cli.client_num = ILT_CLIENT_TM;
11572
11573 ecore_ilt_boundary_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
11574 }
11575
11576 /* this assumes that reset_port() called before reset_func() */
11577 if (!CHIP_IS_E1x(sc)) {
11578 bnx2x_pf_disable(sc);
11579 }
11580
11581 sc->dmae_ready = 0;
11582 }
11583
11584 static void bnx2x_release_firmware(struct bnx2x_softc *sc)
11585 {
11586 rte_free(sc->init_ops);
11587 rte_free(sc->init_ops_offsets);
11588 rte_free(sc->init_data);
11589 rte_free(sc->iro_array);
11590 }
11591
11592 static int bnx2x_init_firmware(struct bnx2x_softc *sc)
11593 {
11594 uint32_t len, i;
11595 uint8_t *p = sc->firmware;
11596 uint32_t off[24];
11597
11598 for (i = 0; i < 24; ++i)
11599 off[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));
11600
11601 len = off[0];
11602 sc->init_ops = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11603 if (!sc->init_ops)
11604 goto alloc_failed;
11605 bnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);
11606
11607 len = off[2];
11608 sc->init_ops_offsets = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11609 if (!sc->init_ops_offsets)
11610 goto alloc_failed;
11611 bnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);
11612
11613 len = off[4];
11614 sc->init_data = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11615 if (!sc->init_data)
11616 goto alloc_failed;
11617 bnx2x_data_to_init_data(p + off[5], sc->init_data, len);
11618
11619 sc->tsem_int_table_data = p + off[7];
11620 sc->tsem_pram_data = p + off[9];
11621 sc->usem_int_table_data = p + off[11];
11622 sc->usem_pram_data = p + off[13];
11623 sc->csem_int_table_data = p + off[15];
11624 sc->csem_pram_data = p + off[17];
11625 sc->xsem_int_table_data = p + off[19];
11626 sc->xsem_pram_data = p + off[21];
11627
11628 len = off[22];
11629 sc->iro_array = rte_zmalloc("", len, RTE_CACHE_LINE_SIZE);
11630 if (!sc->iro_array)
11631 goto alloc_failed;
11632 bnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);
11633
11634 return 0;
11635
11636 alloc_failed:
11637 bnx2x_release_firmware(sc);
11638 return -1;
11639 }
11640
11641 static int cut_gzip_prefix(const uint8_t * zbuf, int len)
11642 {
11643 #define MIN_PREFIX_SIZE (10)
11644
11645 int n = MIN_PREFIX_SIZE;
11646 uint16_t xlen;
11647
11648 if (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||
11649 len <= MIN_PREFIX_SIZE) {
11650 return -1;
11651 }
11652
11653 /* optional extra fields are present */
11654 if (zbuf[3] & 0x4) {
11655 xlen = zbuf[13];
11656 xlen <<= 8;
11657 xlen += zbuf[12];
11658
11659 n += xlen;
11660 }
11661 /* file name is present */
11662 if (zbuf[3] & 0x8) {
11663 while ((zbuf[n++] != 0) && (n < len)) ;
11664 }
11665
11666 return n;
11667 }
11668
11669 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)
11670 {
11671 int ret;
11672 int data_begin = cut_gzip_prefix(zbuf, len);
11673
11674 PMD_DRV_LOG(DEBUG, sc, "ecore_gunzip %d", len);
11675
11676 if (data_begin <= 0) {
11677 PMD_DRV_LOG(NOTICE, sc, "bad gzip prefix");
11678 return -1;
11679 }
11680
11681 memset(&zlib_stream, 0, sizeof(zlib_stream));
11682 zlib_stream.next_in = zbuf + data_begin;
11683 zlib_stream.avail_in = len - data_begin;
11684 zlib_stream.next_out = sc->gz_buf;
11685 zlib_stream.avail_out = FW_BUF_SIZE;
11686
11687 ret = inflateInit2(&zlib_stream, -MAX_WBITS);
11688 if (ret != Z_OK) {
11689 PMD_DRV_LOG(NOTICE, sc, "zlib inflateInit2 error");
11690 return ret;
11691 }
11692
11693 ret = inflate(&zlib_stream, Z_FINISH);
11694 if ((ret != Z_STREAM_END) && (ret != Z_OK)) {
11695 PMD_DRV_LOG(NOTICE, sc, "zlib inflate error: %d %s", ret,
11696 zlib_stream.msg);
11697 }
11698
11699 sc->gz_outlen = zlib_stream.total_out;
11700 if (sc->gz_outlen & 0x3) {
11701 PMD_DRV_LOG(NOTICE, sc, "firmware is not aligned. gz_outlen == %d",
11702 sc->gz_outlen);
11703 }
11704 sc->gz_outlen >>= 2;
11705
11706 inflateEnd(&zlib_stream);
11707
11708 if (ret == Z_STREAM_END)
11709 return 0;
11710
11711 return ret;
11712 }
11713
11714 static void
11715 ecore_write_dmae_phys_len(struct bnx2x_softc *sc, rte_iova_t phys_addr,
11716 uint32_t addr, uint32_t len)
11717 {
11718 bnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);
11719 }
11720
11721 void
11722 ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,
11723 uint32_t * data)
11724 {
11725 uint8_t i;
11726 for (i = 0; i < size / 4; i++) {
11727 REG_WR(sc, addr + (i * 4), data[i]);
11728 }
11729 }
11730
11731 static const char *get_ext_phy_type(uint32_t ext_phy_type)
11732 {
11733 uint32_t phy_type_idx = ext_phy_type >> 8;
11734 static const char *types[] =
11735 { "DIRECT", "BNX2X-8071", "BNX2X-8072", "BNX2X-8073",
11736 "BNX2X-8705", "BNX2X-8706", "BNX2X-8726", "BNX2X-8481", "SFX-7101",
11737 "BNX2X-8727",
11738 "BNX2X-8727-NOC", "BNX2X-84823", "NOT_CONN", "FAILURE"
11739 };
11740
11741 if (phy_type_idx < 12)
11742 return types[phy_type_idx];
11743 else if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)
11744 return types[12];
11745 else
11746 return types[13];
11747 }
11748
11749 static const char *get_state(uint32_t state)
11750 {
11751 uint32_t state_idx = state >> 12;
11752 static const char *states[] = { "CLOSED", "OPENING_WAIT4_LOAD",
11753 "OPENING_WAIT4_PORT", "OPEN", "CLOSING_WAIT4_HALT",
11754 "CLOSING_WAIT4_DELETE", "CLOSING_WAIT4_UNLOAD",
11755 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
11756 "UNKNOWN", "DISABLED", "DIAG", "ERROR", "UNDEFINED"
11757 };
11758
11759 if (state_idx <= 0xF)
11760 return states[state_idx];
11761 else
11762 return states[0x10];
11763 }
11764
11765 static const char *get_recovery_state(uint32_t state)
11766 {
11767 static const char *states[] = { "NONE", "DONE", "INIT",
11768 "WAIT", "FAILED", "NIC_LOADING"
11769 };
11770 return states[state];
11771 }
11772
11773 static const char *get_rx_mode(uint32_t mode)
11774 {
11775 static const char *modes[] = { "NONE", "NORMAL", "ALLMULTI",
11776 "PROMISC", "MAX_MULTICAST", "ERROR"
11777 };
11778
11779 if (mode < 0x4)
11780 return modes[mode];
11781 else if (BNX2X_MAX_MULTICAST == mode)
11782 return modes[4];
11783 else
11784 return modes[5];
11785 }
11786
11787 #define BNX2X_INFO_STR_MAX 256
11788 static const char *get_bnx2x_flags(uint32_t flags)
11789 {
11790 int i;
11791 static const char *flag[] = { "ONE_PORT ", "NO_ISCSI ",
11792 "NO_FCOE ", "NO_WOL ", "USING_DAC ", "USING_MSIX ",
11793 "USING_MSI ", "DISABLE_MSI ", "UNKNOWN ", "NO_MCP ",
11794 "SAFC_TX_FLAG ", "MF_FUNC_DIS ", "TX_SWITCHING "
11795 };
11796 static char flag_str[BNX2X_INFO_STR_MAX];
11797 memset(flag_str, 0, BNX2X_INFO_STR_MAX);
11798
11799 for (i = 0; i < 5; i++)
11800 if (flags & (1 << i)) {
11801 strlcat(flag_str, flag[i], sizeof(flag_str));
11802 flags ^= (1 << i);
11803 }
11804 if (flags) {
11805 static char unknown[BNX2X_INFO_STR_MAX];
11806 snprintf(unknown, 32, "Unknown flag mask %x", flags);
11807 strlcat(flag_str, unknown, sizeof(flag_str));
11808 }
11809 return flag_str;
11810 }
11811
11812 /* Prints useful adapter info. */
11813 void bnx2x_print_adapter_info(struct bnx2x_softc *sc)
11814 {
11815 int i = 0;
11816
11817 PMD_DRV_LOG(INFO, sc, "========================================");
11818 /* DPDK and Driver versions */
11819 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DPDK",
11820 rte_version());
11821 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Driver",
11822 bnx2x_pmd_version());
11823 /* Firmware versions. */
11824 PMD_DRV_LOG(INFO, sc, "%12s : %d.%d.%d",
11825 "Firmware",
11826 BNX2X_5710_FW_MAJOR_VERSION,
11827 BNX2X_5710_FW_MINOR_VERSION,
11828 BNX2X_5710_FW_REVISION_VERSION);
11829 PMD_DRV_LOG(INFO, sc, "%12s : %s",
11830 "Bootcode", sc->devinfo.bc_ver_str);
11831 /* Hardware chip info. */
11832 PMD_DRV_LOG(INFO, sc, "%12s : %#08x", "ASIC", sc->devinfo.chip_id);
11833 PMD_DRV_LOG(INFO, sc, "%12s : %c%d", "Rev", (CHIP_REV(sc) >> 12) + 'A',
11834 (CHIP_METAL(sc) >> 4));
11835 /* Bus PCIe info. */
11836 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Vendor Id",
11837 sc->devinfo.vendor_id);
11838 PMD_DRV_LOG(INFO, sc, "%12s : 0x%x", "Device Id",
11839 sc->devinfo.device_id);
11840 PMD_DRV_LOG(INFO, sc, "%12s : width x%d, ", "Bus PCIe",
11841 sc->devinfo.pcie_link_width);
11842 switch (sc->devinfo.pcie_link_speed) {
11843 case 1:
11844 PMD_DRV_LOG(INFO, sc, "%23s", "2.5 Gbps");
11845 break;
11846 case 2:
11847 PMD_DRV_LOG(INFO, sc, "%21s", "5 Gbps");
11848 break;
11849 case 4:
11850 PMD_DRV_LOG(INFO, sc, "%21s", "8 Gbps");
11851 break;
11852 default:
11853 PMD_DRV_LOG(INFO, sc, "%33s", "Unknown link speed");
11854 }
11855 /* Device features. */
11856 PMD_DRV_LOG(INFO, sc, "%12s : ", "Flags");
11857 /* Miscellaneous flags. */
11858 if (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {
11859 PMD_DRV_LOG(INFO, sc, "%18s", "MSI");
11860 i++;
11861 }
11862 if (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {
11863 if (i > 0)
11864 PMD_DRV_LOG(INFO, sc, "|");
11865 PMD_DRV_LOG(INFO, sc, "%20s", "MSI-X");
11866 i++;
11867 }
11868 PMD_DRV_LOG(INFO, sc, "%12s : %s", "OVLAN", (OVLAN(sc) ? "YES" : "NO"));
11869 PMD_DRV_LOG(INFO, sc, "%12s : %s", "MF", (IS_MF(sc) ? "YES" : "NO"));
11870 PMD_DRV_LOG(INFO, sc, "========================================");
11871 }
11872
11873 /* Prints useful device info. */
11874 void bnx2x_print_device_info(struct bnx2x_softc *sc)
11875 {
11876 __rte_unused uint32_t ext_phy_type;
11877 uint32_t offset, reg_val;
11878
11879 PMD_INIT_FUNC_TRACE(sc);
11880 offset = offsetof(struct shmem_region,
11881 dev_info.port_hw_config[0].external_phy_config);
11882 reg_val = REG_RD(sc, sc->devinfo.shmem_base + offset);
11883 if (sc->link_vars.phy_flags & PHY_XGXS_FLAG)
11884 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(reg_val);
11885 else
11886 ext_phy_type = ELINK_SERDES_EXT_PHY_TYPE(reg_val);
11887
11888 /* Device features. */
11889 PMD_DRV_LOG(INFO, sc, "%12s : %u", "Bnx2x Func", sc->pcie_func);
11890 PMD_DRV_LOG(INFO, sc,
11891 "%12s : %s", "Bnx2x Flags", get_bnx2x_flags(sc->flags));
11892 PMD_DRV_LOG(INFO, sc, "%12s : %s", "DMAE Is",
11893 (sc->dmae_ready ? "Ready" : "Not Ready"));
11894 PMD_DRV_LOG(INFO, sc, "%12s : %u", "MTU", sc->mtu);
11895 PMD_DRV_LOG(INFO, sc,
11896 "%12s : %s", "PHY Type", get_ext_phy_type(ext_phy_type));
11897 PMD_DRV_LOG(INFO, sc, "%12s : " RTE_ETHER_ADDR_PRT_FMT, "MAC Addr",
11898 sc->link_params.mac_addr[0],
11899 sc->link_params.mac_addr[1],
11900 sc->link_params.mac_addr[2],
11901 sc->link_params.mac_addr[3],
11902 sc->link_params.mac_addr[4],
11903 sc->link_params.mac_addr[5]);
11904 PMD_DRV_LOG(INFO, sc, "%12s : %s", "RX Mode", get_rx_mode(sc->rx_mode));
11905 PMD_DRV_LOG(INFO, sc, "%12s : %s", "State", get_state(sc->state));
11906 if (sc->recovery_state)
11907 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Recovery",
11908 get_recovery_state(sc->recovery_state));
11909 /* Queue info. */
11910 if (IS_PF(sc)) {
11911 switch (sc->sp->rss_rdata.rss_mode) {
11912 case ETH_RSS_MODE_DISABLED:
11913 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - None");
11914 break;
11915 case ETH_RSS_MODE_REGULAR:
11916 PMD_DRV_LOG(INFO, sc, "%12s : %s,", "Queues", "RSS mode - Regular");
11917 PMD_DRV_LOG(INFO, sc, "%16d", sc->num_queues);
11918 break;
11919 default:
11920 PMD_DRV_LOG(INFO, sc, "%12s : %s", "Queues", "RSS mode - Unknown");
11921 break;
11922 }
11923 }
11924 PMD_DRV_LOG(INFO, sc, "%12s : CQ = %lx, EQ = %lx", "SPQ Left",
11925 sc->cq_spq_left, sc->eq_spq_left);
11926
11927 PMD_DRV_LOG(INFO, sc,
11928 "%12s : %x", "Switch", sc->link_params.switch_cfg);
11929 PMD_DRV_LOG(INFO, sc, "pcie_bus=%d, pcie_device=%d",
11930 sc->pcie_bus, sc->pcie_device);
11931 PMD_DRV_LOG(INFO, sc, "bar0.addr=%p, bar1.addr=%p",
11932 sc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);
11933 PMD_DRV_LOG(INFO, sc, "port=%d, path=%d, vnic=%d, func=%d",
11934 PORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));
11935 }
11936